1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 struct hdmi_spec_per_cvt { 42 hda_nid_t cvt_nid; 43 int assigned; 44 unsigned int channels_min; 45 unsigned int channels_max; 46 u32 rates; 47 u64 formats; 48 unsigned int maxbps; 49 }; 50 51 /* max. connections to a widget */ 52 #define HDA_MAX_CONNECTIONS 32 53 54 struct hdmi_spec_per_pin { 55 hda_nid_t pin_nid; 56 int dev_id; 57 /* pin idx, different device entries on the same pin use the same idx */ 58 int pin_nid_idx; 59 int num_mux_nids; 60 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 61 int mux_idx; 62 hda_nid_t cvt_nid; 63 64 struct hda_codec *codec; 65 struct hdmi_eld sink_eld; 66 struct mutex lock; 67 struct delayed_work work; 68 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 69 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 70 int repoll_count; 71 bool setup; /* the stream has been set up by prepare callback */ 72 int channels; /* current number of channels */ 73 bool non_pcm; 74 bool chmap_set; /* channel-map override by ALSA API? */ 75 unsigned char chmap[8]; /* ALSA API channel-map */ 76 #ifdef CONFIG_SND_PROC_FS 77 struct snd_info_entry *proc_entry; 78 #endif 79 }; 80 81 /* operations used by generic code that can be overridden by patches */ 82 struct hdmi_ops { 83 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 84 int dev_id, unsigned char *buf, int *eld_size); 85 86 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 87 int dev_id, 88 int ca, int active_channels, int conn_type); 89 90 /* enable/disable HBR (HD passthrough) */ 91 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 92 int dev_id, bool hbr); 93 94 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 95 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 96 int format); 97 98 void (*pin_cvt_fixup)(struct hda_codec *codec, 99 struct hdmi_spec_per_pin *per_pin, 100 hda_nid_t cvt_nid); 101 }; 102 103 struct hdmi_pcm { 104 struct hda_pcm *pcm; 105 struct snd_jack *jack; 106 struct snd_kcontrol *eld_ctl; 107 }; 108 109 struct hdmi_spec { 110 struct hda_codec *codec; 111 int num_cvts; 112 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 113 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 114 115 /* 116 * num_pins is the number of virtual pins 117 * for example, there are 3 pins, and each pin 118 * has 4 device entries, then the num_pins is 12 119 */ 120 int num_pins; 121 /* 122 * num_nids is the number of real pins 123 * In the above example, num_nids is 3 124 */ 125 int num_nids; 126 /* 127 * dev_num is the number of device entries 128 * on each pin. 129 * In the above example, dev_num is 4 130 */ 131 int dev_num; 132 struct snd_array pins; /* struct hdmi_spec_per_pin */ 133 struct hdmi_pcm pcm_rec[16]; 134 struct mutex pcm_lock; 135 struct mutex bind_lock; /* for audio component binding */ 136 /* pcm_bitmap means which pcms have been assigned to pins*/ 137 unsigned long pcm_bitmap; 138 int pcm_used; /* counter of pcm_rec[] */ 139 /* bitmap shows whether the pcm is opened in user space 140 * bit 0 means the first playback PCM (PCM3); 141 * bit 1 means the second playback PCM, and so on. 142 */ 143 unsigned long pcm_in_use; 144 145 struct hdmi_eld temp_eld; 146 struct hdmi_ops ops; 147 148 bool dyn_pin_out; 149 bool dyn_pcm_assign; 150 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 151 /* 152 * Non-generic VIA/NVIDIA specific 153 */ 154 struct hda_multi_out multiout; 155 struct hda_pcm_stream pcm_playback; 156 157 bool use_jack_detect; /* jack detection enabled */ 158 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 159 bool acomp_registered; /* audio component registered in this driver */ 160 struct drm_audio_component_audio_ops drm_audio_ops; 161 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 162 163 struct hdac_chmap chmap; 164 hda_nid_t vendor_nid; 165 const int *port_map; 166 int port_num; 167 }; 168 169 #ifdef CONFIG_SND_HDA_COMPONENT 170 static inline bool codec_has_acomp(struct hda_codec *codec) 171 { 172 struct hdmi_spec *spec = codec->spec; 173 return spec->use_acomp_notifier; 174 } 175 #else 176 #define codec_has_acomp(codec) false 177 #endif 178 179 struct hdmi_audio_infoframe { 180 u8 type; /* 0x84 */ 181 u8 ver; /* 0x01 */ 182 u8 len; /* 0x0a */ 183 184 u8 checksum; 185 186 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 187 u8 SS01_SF24; 188 u8 CXT04; 189 u8 CA; 190 u8 LFEPBL01_LSV36_DM_INH7; 191 }; 192 193 struct dp_audio_infoframe { 194 u8 type; /* 0x84 */ 195 u8 len; /* 0x1b */ 196 u8 ver; /* 0x11 << 2 */ 197 198 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 199 u8 SS01_SF24; 200 u8 CXT04; 201 u8 CA; 202 u8 LFEPBL01_LSV36_DM_INH7; 203 }; 204 205 union audio_infoframe { 206 struct hdmi_audio_infoframe hdmi; 207 struct dp_audio_infoframe dp; 208 u8 bytes[0]; 209 }; 210 211 /* 212 * HDMI routines 213 */ 214 215 #define get_pin(spec, idx) \ 216 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 217 #define get_cvt(spec, idx) \ 218 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 219 /* obtain hdmi_pcm object assigned to idx */ 220 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 221 /* obtain hda_pcm object assigned to idx */ 222 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 223 224 static int pin_id_to_pin_index(struct hda_codec *codec, 225 hda_nid_t pin_nid, int dev_id) 226 { 227 struct hdmi_spec *spec = codec->spec; 228 int pin_idx; 229 struct hdmi_spec_per_pin *per_pin; 230 231 /* 232 * (dev_id == -1) means it is NON-MST pin 233 * return the first virtual pin on this port 234 */ 235 if (dev_id == -1) 236 dev_id = 0; 237 238 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 239 per_pin = get_pin(spec, pin_idx); 240 if ((per_pin->pin_nid == pin_nid) && 241 (per_pin->dev_id == dev_id)) 242 return pin_idx; 243 } 244 245 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 246 return -EINVAL; 247 } 248 249 static int hinfo_to_pcm_index(struct hda_codec *codec, 250 struct hda_pcm_stream *hinfo) 251 { 252 struct hdmi_spec *spec = codec->spec; 253 int pcm_idx; 254 255 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 256 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 257 return pcm_idx; 258 259 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); 260 return -EINVAL; 261 } 262 263 static int hinfo_to_pin_index(struct hda_codec *codec, 264 struct hda_pcm_stream *hinfo) 265 { 266 struct hdmi_spec *spec = codec->spec; 267 struct hdmi_spec_per_pin *per_pin; 268 int pin_idx; 269 270 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 271 per_pin = get_pin(spec, pin_idx); 272 if (per_pin->pcm && 273 per_pin->pcm->pcm->stream == hinfo) 274 return pin_idx; 275 } 276 277 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); 278 return -EINVAL; 279 } 280 281 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 282 int pcm_idx) 283 { 284 int i; 285 struct hdmi_spec_per_pin *per_pin; 286 287 for (i = 0; i < spec->num_pins; i++) { 288 per_pin = get_pin(spec, i); 289 if (per_pin->pcm_idx == pcm_idx) 290 return per_pin; 291 } 292 return NULL; 293 } 294 295 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 296 { 297 struct hdmi_spec *spec = codec->spec; 298 int cvt_idx; 299 300 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 301 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 302 return cvt_idx; 303 304 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 305 return -EINVAL; 306 } 307 308 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 309 struct snd_ctl_elem_info *uinfo) 310 { 311 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 312 struct hdmi_spec *spec = codec->spec; 313 struct hdmi_spec_per_pin *per_pin; 314 struct hdmi_eld *eld; 315 int pcm_idx; 316 317 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 318 319 pcm_idx = kcontrol->private_value; 320 mutex_lock(&spec->pcm_lock); 321 per_pin = pcm_idx_to_pin(spec, pcm_idx); 322 if (!per_pin) { 323 /* no pin is bound to the pcm */ 324 uinfo->count = 0; 325 goto unlock; 326 } 327 eld = &per_pin->sink_eld; 328 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 329 330 unlock: 331 mutex_unlock(&spec->pcm_lock); 332 return 0; 333 } 334 335 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 336 struct snd_ctl_elem_value *ucontrol) 337 { 338 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 339 struct hdmi_spec *spec = codec->spec; 340 struct hdmi_spec_per_pin *per_pin; 341 struct hdmi_eld *eld; 342 int pcm_idx; 343 int err = 0; 344 345 pcm_idx = kcontrol->private_value; 346 mutex_lock(&spec->pcm_lock); 347 per_pin = pcm_idx_to_pin(spec, pcm_idx); 348 if (!per_pin) { 349 /* no pin is bound to the pcm */ 350 memset(ucontrol->value.bytes.data, 0, 351 ARRAY_SIZE(ucontrol->value.bytes.data)); 352 goto unlock; 353 } 354 355 eld = &per_pin->sink_eld; 356 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 357 eld->eld_size > ELD_MAX_SIZE) { 358 snd_BUG(); 359 err = -EINVAL; 360 goto unlock; 361 } 362 363 memset(ucontrol->value.bytes.data, 0, 364 ARRAY_SIZE(ucontrol->value.bytes.data)); 365 if (eld->eld_valid) 366 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 367 eld->eld_size); 368 369 unlock: 370 mutex_unlock(&spec->pcm_lock); 371 return err; 372 } 373 374 static const struct snd_kcontrol_new eld_bytes_ctl = { 375 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | 376 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, 377 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 378 .name = "ELD", 379 .info = hdmi_eld_ctl_info, 380 .get = hdmi_eld_ctl_get, 381 }; 382 383 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 384 int device) 385 { 386 struct snd_kcontrol *kctl; 387 struct hdmi_spec *spec = codec->spec; 388 int err; 389 390 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 391 if (!kctl) 392 return -ENOMEM; 393 kctl->private_value = pcm_idx; 394 kctl->id.device = device; 395 396 /* no pin nid is associated with the kctl now 397 * tbd: associate pin nid to eld ctl later 398 */ 399 err = snd_hda_ctl_add(codec, 0, kctl); 400 if (err < 0) 401 return err; 402 403 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 404 return 0; 405 } 406 407 #ifdef BE_PARANOID 408 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 409 int *packet_index, int *byte_index) 410 { 411 int val; 412 413 val = snd_hda_codec_read(codec, pin_nid, 0, 414 AC_VERB_GET_HDMI_DIP_INDEX, 0); 415 416 *packet_index = val >> 5; 417 *byte_index = val & 0x1f; 418 } 419 #endif 420 421 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 422 int packet_index, int byte_index) 423 { 424 int val; 425 426 val = (packet_index << 5) | (byte_index & 0x1f); 427 428 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 429 } 430 431 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 432 unsigned char val) 433 { 434 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 435 } 436 437 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 438 { 439 struct hdmi_spec *spec = codec->spec; 440 int pin_out; 441 442 /* Unmute */ 443 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 444 snd_hda_codec_write(codec, pin_nid, 0, 445 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 446 447 if (spec->dyn_pin_out) 448 /* Disable pin out until stream is active */ 449 pin_out = 0; 450 else 451 /* Enable pin out: some machines with GM965 gets broken output 452 * when the pin is disabled or changed while using with HDMI 453 */ 454 pin_out = PIN_OUT; 455 456 snd_hda_codec_write(codec, pin_nid, 0, 457 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 458 } 459 460 /* 461 * ELD proc files 462 */ 463 464 #ifdef CONFIG_SND_PROC_FS 465 static void print_eld_info(struct snd_info_entry *entry, 466 struct snd_info_buffer *buffer) 467 { 468 struct hdmi_spec_per_pin *per_pin = entry->private_data; 469 470 mutex_lock(&per_pin->lock); 471 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 472 mutex_unlock(&per_pin->lock); 473 } 474 475 static void write_eld_info(struct snd_info_entry *entry, 476 struct snd_info_buffer *buffer) 477 { 478 struct hdmi_spec_per_pin *per_pin = entry->private_data; 479 480 mutex_lock(&per_pin->lock); 481 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 482 mutex_unlock(&per_pin->lock); 483 } 484 485 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 486 { 487 char name[32]; 488 struct hda_codec *codec = per_pin->codec; 489 struct snd_info_entry *entry; 490 int err; 491 492 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 493 err = snd_card_proc_new(codec->card, name, &entry); 494 if (err < 0) 495 return err; 496 497 snd_info_set_text_ops(entry, per_pin, print_eld_info); 498 entry->c.text.write = write_eld_info; 499 entry->mode |= 0200; 500 per_pin->proc_entry = entry; 501 502 return 0; 503 } 504 505 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 506 { 507 if (!per_pin->codec->bus->shutdown) { 508 snd_info_free_entry(per_pin->proc_entry); 509 per_pin->proc_entry = NULL; 510 } 511 } 512 #else 513 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 514 int index) 515 { 516 return 0; 517 } 518 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 519 { 520 } 521 #endif 522 523 /* 524 * Audio InfoFrame routines 525 */ 526 527 /* 528 * Enable Audio InfoFrame Transmission 529 */ 530 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 531 hda_nid_t pin_nid) 532 { 533 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 534 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 535 AC_DIPXMIT_BEST); 536 } 537 538 /* 539 * Disable Audio InfoFrame Transmission 540 */ 541 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 542 hda_nid_t pin_nid) 543 { 544 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 545 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 546 AC_DIPXMIT_DISABLE); 547 } 548 549 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 550 { 551 #ifdef CONFIG_SND_DEBUG_VERBOSE 552 int i; 553 int size; 554 555 size = snd_hdmi_get_eld_size(codec, pin_nid); 556 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 557 558 for (i = 0; i < 8; i++) { 559 size = snd_hda_codec_read(codec, pin_nid, 0, 560 AC_VERB_GET_HDMI_DIP_SIZE, i); 561 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 562 } 563 #endif 564 } 565 566 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 567 { 568 #ifdef BE_PARANOID 569 int i, j; 570 int size; 571 int pi, bi; 572 for (i = 0; i < 8; i++) { 573 size = snd_hda_codec_read(codec, pin_nid, 0, 574 AC_VERB_GET_HDMI_DIP_SIZE, i); 575 if (size == 0) 576 continue; 577 578 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 579 for (j = 1; j < 1000; j++) { 580 hdmi_write_dip_byte(codec, pin_nid, 0x0); 581 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 582 if (pi != i) 583 codec_dbg(codec, "dip index %d: %d != %d\n", 584 bi, pi, i); 585 if (bi == 0) /* byte index wrapped around */ 586 break; 587 } 588 codec_dbg(codec, 589 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 590 i, size, j); 591 } 592 #endif 593 } 594 595 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 596 { 597 u8 *bytes = (u8 *)hdmi_ai; 598 u8 sum = 0; 599 int i; 600 601 hdmi_ai->checksum = 0; 602 603 for (i = 0; i < sizeof(*hdmi_ai); i++) 604 sum += bytes[i]; 605 606 hdmi_ai->checksum = -sum; 607 } 608 609 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 610 hda_nid_t pin_nid, 611 u8 *dip, int size) 612 { 613 int i; 614 615 hdmi_debug_dip_size(codec, pin_nid); 616 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 617 618 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 619 for (i = 0; i < size; i++) 620 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 621 } 622 623 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 624 u8 *dip, int size) 625 { 626 u8 val; 627 int i; 628 629 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 630 != AC_DIPXMIT_BEST) 631 return false; 632 633 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 634 for (i = 0; i < size; i++) { 635 val = snd_hda_codec_read(codec, pin_nid, 0, 636 AC_VERB_GET_HDMI_DIP_DATA, 0); 637 if (val != dip[i]) 638 return false; 639 } 640 641 return true; 642 } 643 644 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 645 int dev_id, unsigned char *buf, int *eld_size) 646 { 647 snd_hda_set_dev_select(codec, nid, dev_id); 648 649 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 650 } 651 652 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 653 hda_nid_t pin_nid, int dev_id, 654 int ca, int active_channels, 655 int conn_type) 656 { 657 union audio_infoframe ai; 658 659 memset(&ai, 0, sizeof(ai)); 660 if (conn_type == 0) { /* HDMI */ 661 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 662 663 hdmi_ai->type = 0x84; 664 hdmi_ai->ver = 0x01; 665 hdmi_ai->len = 0x0a; 666 hdmi_ai->CC02_CT47 = active_channels - 1; 667 hdmi_ai->CA = ca; 668 hdmi_checksum_audio_infoframe(hdmi_ai); 669 } else if (conn_type == 1) { /* DisplayPort */ 670 struct dp_audio_infoframe *dp_ai = &ai.dp; 671 672 dp_ai->type = 0x84; 673 dp_ai->len = 0x1b; 674 dp_ai->ver = 0x11 << 2; 675 dp_ai->CC02_CT47 = active_channels - 1; 676 dp_ai->CA = ca; 677 } else { 678 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 679 pin_nid); 680 return; 681 } 682 683 snd_hda_set_dev_select(codec, pin_nid, dev_id); 684 685 /* 686 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 687 * sizeof(*dp_ai) to avoid partial match/update problems when 688 * the user switches between HDMI/DP monitors. 689 */ 690 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 691 sizeof(ai))) { 692 codec_dbg(codec, 693 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 694 pin_nid, 695 active_channels, ca); 696 hdmi_stop_infoframe_trans(codec, pin_nid); 697 hdmi_fill_audio_infoframe(codec, pin_nid, 698 ai.bytes, sizeof(ai)); 699 hdmi_start_infoframe_trans(codec, pin_nid); 700 } 701 } 702 703 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 704 struct hdmi_spec_per_pin *per_pin, 705 bool non_pcm) 706 { 707 struct hdmi_spec *spec = codec->spec; 708 struct hdac_chmap *chmap = &spec->chmap; 709 hda_nid_t pin_nid = per_pin->pin_nid; 710 int dev_id = per_pin->dev_id; 711 int channels = per_pin->channels; 712 int active_channels; 713 struct hdmi_eld *eld; 714 int ca; 715 716 if (!channels) 717 return; 718 719 snd_hda_set_dev_select(codec, pin_nid, dev_id); 720 721 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 722 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 723 snd_hda_codec_write(codec, pin_nid, 0, 724 AC_VERB_SET_AMP_GAIN_MUTE, 725 AMP_OUT_UNMUTE); 726 727 eld = &per_pin->sink_eld; 728 729 ca = snd_hdac_channel_allocation(&codec->core, 730 eld->info.spk_alloc, channels, 731 per_pin->chmap_set, non_pcm, per_pin->chmap); 732 733 active_channels = snd_hdac_get_active_channels(ca); 734 735 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 736 active_channels); 737 738 /* 739 * always configure channel mapping, it may have been changed by the 740 * user in the meantime 741 */ 742 snd_hdac_setup_channel_mapping(&spec->chmap, 743 pin_nid, non_pcm, ca, channels, 744 per_pin->chmap, per_pin->chmap_set); 745 746 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 747 ca, active_channels, eld->info.conn_type); 748 749 per_pin->non_pcm = non_pcm; 750 } 751 752 /* 753 * Unsolicited events 754 */ 755 756 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 757 758 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 759 int dev_id) 760 { 761 struct hdmi_spec *spec = codec->spec; 762 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 763 764 if (pin_idx < 0) 765 return; 766 mutex_lock(&spec->pcm_lock); 767 if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) 768 snd_hda_jack_report_sync(codec); 769 mutex_unlock(&spec->pcm_lock); 770 } 771 772 static void jack_callback(struct hda_codec *codec, 773 struct hda_jack_callback *jack) 774 { 775 /* stop polling when notification is enabled */ 776 if (codec_has_acomp(codec)) 777 return; 778 779 check_presence_and_report(codec, jack->nid, jack->dev_id); 780 } 781 782 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) 783 { 784 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 785 struct hda_jack_tbl *jack; 786 787 if (codec->dp_mst) { 788 int dev_entry = 789 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 790 791 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 792 } else { 793 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 794 } 795 if (!jack) 796 return; 797 jack->jack_dirty = 1; 798 799 codec_dbg(codec, 800 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 801 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 802 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 803 804 check_presence_and_report(codec, jack->nid, jack->dev_id); 805 } 806 807 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 808 { 809 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 810 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 811 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 812 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 813 814 codec_info(codec, 815 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 816 codec->addr, 817 tag, 818 subtag, 819 cp_state, 820 cp_ready); 821 822 /* TODO */ 823 if (cp_state) { 824 ; 825 } 826 if (cp_ready) { 827 ; 828 } 829 } 830 831 832 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 833 { 834 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 835 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 836 struct hda_jack_tbl *jack; 837 838 if (codec_has_acomp(codec)) 839 return; 840 841 if (codec->dp_mst) { 842 int dev_entry = 843 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 844 845 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 846 } else { 847 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 848 } 849 850 if (!jack) { 851 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 852 return; 853 } 854 855 if (subtag == 0) 856 hdmi_intrinsic_event(codec, res); 857 else 858 hdmi_non_intrinsic_event(codec, res); 859 } 860 861 static void haswell_verify_D0(struct hda_codec *codec, 862 hda_nid_t cvt_nid, hda_nid_t nid) 863 { 864 int pwr; 865 866 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 867 * thus pins could only choose converter 0 for use. Make sure the 868 * converters are in correct power state */ 869 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 870 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 871 872 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 873 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 874 AC_PWRST_D0); 875 msleep(40); 876 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 877 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 878 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 879 } 880 } 881 882 /* 883 * Callbacks 884 */ 885 886 /* HBR should be Non-PCM, 8 channels */ 887 #define is_hbr_format(format) \ 888 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 889 890 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 891 int dev_id, bool hbr) 892 { 893 int pinctl, new_pinctl; 894 895 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 896 snd_hda_set_dev_select(codec, pin_nid, dev_id); 897 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 898 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 899 900 if (pinctl < 0) 901 return hbr ? -EINVAL : 0; 902 903 new_pinctl = pinctl & ~AC_PINCTL_EPT; 904 if (hbr) 905 new_pinctl |= AC_PINCTL_EPT_HBR; 906 else 907 new_pinctl |= AC_PINCTL_EPT_NATIVE; 908 909 codec_dbg(codec, 910 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 911 pin_nid, 912 pinctl == new_pinctl ? "" : "new-", 913 new_pinctl); 914 915 if (pinctl != new_pinctl) 916 snd_hda_codec_write(codec, pin_nid, 0, 917 AC_VERB_SET_PIN_WIDGET_CONTROL, 918 new_pinctl); 919 } else if (hbr) 920 return -EINVAL; 921 922 return 0; 923 } 924 925 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 926 hda_nid_t pin_nid, int dev_id, 927 u32 stream_tag, int format) 928 { 929 struct hdmi_spec *spec = codec->spec; 930 unsigned int param; 931 int err; 932 933 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 934 is_hbr_format(format)); 935 936 if (err) { 937 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 938 return err; 939 } 940 941 if (spec->intel_hsw_fixup) { 942 943 /* 944 * on recent platforms IEC Coding Type is required for HBR 945 * support, read current Digital Converter settings and set 946 * ICT bitfield if needed. 947 */ 948 param = snd_hda_codec_read(codec, cvt_nid, 0, 949 AC_VERB_GET_DIGI_CONVERT_1, 0); 950 951 param = (param >> 16) & ~(AC_DIG3_ICT); 952 953 /* on recent platforms ICT mode is required for HBR support */ 954 if (is_hbr_format(format)) 955 param |= 0x1; 956 957 snd_hda_codec_write(codec, cvt_nid, 0, 958 AC_VERB_SET_DIGI_CONVERT_3, param); 959 } 960 961 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 962 return 0; 963 } 964 965 /* Try to find an available converter 966 * If pin_idx is less then zero, just try to find an available converter. 967 * Otherwise, try to find an available converter and get the cvt mux index 968 * of the pin. 969 */ 970 static int hdmi_choose_cvt(struct hda_codec *codec, 971 int pin_idx, int *cvt_id) 972 { 973 struct hdmi_spec *spec = codec->spec; 974 struct hdmi_spec_per_pin *per_pin; 975 struct hdmi_spec_per_cvt *per_cvt = NULL; 976 int cvt_idx, mux_idx = 0; 977 978 /* pin_idx < 0 means no pin will be bound to the converter */ 979 if (pin_idx < 0) 980 per_pin = NULL; 981 else 982 per_pin = get_pin(spec, pin_idx); 983 984 /* Dynamically assign converter to stream */ 985 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 986 per_cvt = get_cvt(spec, cvt_idx); 987 988 /* Must not already be assigned */ 989 if (per_cvt->assigned) 990 continue; 991 if (per_pin == NULL) 992 break; 993 /* Must be in pin's mux's list of converters */ 994 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 995 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 996 break; 997 /* Not in mux list */ 998 if (mux_idx == per_pin->num_mux_nids) 999 continue; 1000 break; 1001 } 1002 1003 /* No free converters */ 1004 if (cvt_idx == spec->num_cvts) 1005 return -EBUSY; 1006 1007 if (per_pin != NULL) 1008 per_pin->mux_idx = mux_idx; 1009 1010 if (cvt_id) 1011 *cvt_id = cvt_idx; 1012 1013 return 0; 1014 } 1015 1016 /* Assure the pin select the right convetor */ 1017 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1018 struct hdmi_spec_per_pin *per_pin) 1019 { 1020 hda_nid_t pin_nid = per_pin->pin_nid; 1021 int mux_idx, curr; 1022 1023 mux_idx = per_pin->mux_idx; 1024 curr = snd_hda_codec_read(codec, pin_nid, 0, 1025 AC_VERB_GET_CONNECT_SEL, 0); 1026 if (curr != mux_idx) 1027 snd_hda_codec_write_cache(codec, pin_nid, 0, 1028 AC_VERB_SET_CONNECT_SEL, 1029 mux_idx); 1030 } 1031 1032 /* get the mux index for the converter of the pins 1033 * converter's mux index is the same for all pins on Intel platform 1034 */ 1035 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1036 hda_nid_t cvt_nid) 1037 { 1038 int i; 1039 1040 for (i = 0; i < spec->num_cvts; i++) 1041 if (spec->cvt_nids[i] == cvt_nid) 1042 return i; 1043 return -EINVAL; 1044 } 1045 1046 /* Intel HDMI workaround to fix audio routing issue: 1047 * For some Intel display codecs, pins share the same connection list. 1048 * So a conveter can be selected by multiple pins and playback on any of these 1049 * pins will generate sound on the external display, because audio flows from 1050 * the same converter to the display pipeline. Also muting one pin may make 1051 * other pins have no sound output. 1052 * So this function assures that an assigned converter for a pin is not selected 1053 * by any other pins. 1054 */ 1055 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1056 hda_nid_t pin_nid, 1057 int dev_id, int mux_idx) 1058 { 1059 struct hdmi_spec *spec = codec->spec; 1060 hda_nid_t nid; 1061 int cvt_idx, curr; 1062 struct hdmi_spec_per_cvt *per_cvt; 1063 struct hdmi_spec_per_pin *per_pin; 1064 int pin_idx; 1065 1066 /* configure the pins connections */ 1067 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1068 int dev_id_saved; 1069 int dev_num; 1070 1071 per_pin = get_pin(spec, pin_idx); 1072 /* 1073 * pin not connected to monitor 1074 * no need to operate on it 1075 */ 1076 if (!per_pin->pcm) 1077 continue; 1078 1079 if ((per_pin->pin_nid == pin_nid) && 1080 (per_pin->dev_id == dev_id)) 1081 continue; 1082 1083 /* 1084 * if per_pin->dev_id >= dev_num, 1085 * snd_hda_get_dev_select() will fail, 1086 * and the following operation is unpredictable. 1087 * So skip this situation. 1088 */ 1089 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1090 if (per_pin->dev_id >= dev_num) 1091 continue; 1092 1093 nid = per_pin->pin_nid; 1094 1095 /* 1096 * Calling this function should not impact 1097 * on the device entry selection 1098 * So let's save the dev id for each pin, 1099 * and restore it when return 1100 */ 1101 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1102 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1103 curr = snd_hda_codec_read(codec, nid, 0, 1104 AC_VERB_GET_CONNECT_SEL, 0); 1105 if (curr != mux_idx) { 1106 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1107 continue; 1108 } 1109 1110 1111 /* choose an unassigned converter. The conveters in the 1112 * connection list are in the same order as in the codec. 1113 */ 1114 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1115 per_cvt = get_cvt(spec, cvt_idx); 1116 if (!per_cvt->assigned) { 1117 codec_dbg(codec, 1118 "choose cvt %d for pin nid %d\n", 1119 cvt_idx, nid); 1120 snd_hda_codec_write_cache(codec, nid, 0, 1121 AC_VERB_SET_CONNECT_SEL, 1122 cvt_idx); 1123 break; 1124 } 1125 } 1126 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1127 } 1128 } 1129 1130 /* A wrapper of intel_not_share_asigned_cvt() */ 1131 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1132 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1133 { 1134 int mux_idx; 1135 struct hdmi_spec *spec = codec->spec; 1136 1137 /* On Intel platform, the mapping of converter nid to 1138 * mux index of the pins are always the same. 1139 * The pin nid may be 0, this means all pins will not 1140 * share the converter. 1141 */ 1142 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1143 if (mux_idx >= 0) 1144 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1145 } 1146 1147 /* skeleton caller of pin_cvt_fixup ops */ 1148 static void pin_cvt_fixup(struct hda_codec *codec, 1149 struct hdmi_spec_per_pin *per_pin, 1150 hda_nid_t cvt_nid) 1151 { 1152 struct hdmi_spec *spec = codec->spec; 1153 1154 if (spec->ops.pin_cvt_fixup) 1155 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1156 } 1157 1158 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1159 * in dyn_pcm_assign mode. 1160 */ 1161 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1162 struct hda_codec *codec, 1163 struct snd_pcm_substream *substream) 1164 { 1165 struct hdmi_spec *spec = codec->spec; 1166 struct snd_pcm_runtime *runtime = substream->runtime; 1167 int cvt_idx, pcm_idx; 1168 struct hdmi_spec_per_cvt *per_cvt = NULL; 1169 int err; 1170 1171 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1172 if (pcm_idx < 0) 1173 return -EINVAL; 1174 1175 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1176 if (err) 1177 return err; 1178 1179 per_cvt = get_cvt(spec, cvt_idx); 1180 per_cvt->assigned = 1; 1181 hinfo->nid = per_cvt->cvt_nid; 1182 1183 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1184 1185 set_bit(pcm_idx, &spec->pcm_in_use); 1186 /* todo: setup spdif ctls assign */ 1187 1188 /* Initially set the converter's capabilities */ 1189 hinfo->channels_min = per_cvt->channels_min; 1190 hinfo->channels_max = per_cvt->channels_max; 1191 hinfo->rates = per_cvt->rates; 1192 hinfo->formats = per_cvt->formats; 1193 hinfo->maxbps = per_cvt->maxbps; 1194 1195 /* Store the updated parameters */ 1196 runtime->hw.channels_min = hinfo->channels_min; 1197 runtime->hw.channels_max = hinfo->channels_max; 1198 runtime->hw.formats = hinfo->formats; 1199 runtime->hw.rates = hinfo->rates; 1200 1201 snd_pcm_hw_constraint_step(substream->runtime, 0, 1202 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1203 return 0; 1204 } 1205 1206 /* 1207 * HDA PCM callbacks 1208 */ 1209 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1210 struct hda_codec *codec, 1211 struct snd_pcm_substream *substream) 1212 { 1213 struct hdmi_spec *spec = codec->spec; 1214 struct snd_pcm_runtime *runtime = substream->runtime; 1215 int pin_idx, cvt_idx, pcm_idx; 1216 struct hdmi_spec_per_pin *per_pin; 1217 struct hdmi_eld *eld; 1218 struct hdmi_spec_per_cvt *per_cvt = NULL; 1219 int err; 1220 1221 /* Validate hinfo */ 1222 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1223 if (pcm_idx < 0) 1224 return -EINVAL; 1225 1226 mutex_lock(&spec->pcm_lock); 1227 pin_idx = hinfo_to_pin_index(codec, hinfo); 1228 if (!spec->dyn_pcm_assign) { 1229 if (snd_BUG_ON(pin_idx < 0)) { 1230 err = -EINVAL; 1231 goto unlock; 1232 } 1233 } else { 1234 /* no pin is assigned to the PCM 1235 * PA need pcm open successfully when probe 1236 */ 1237 if (pin_idx < 0) { 1238 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1239 goto unlock; 1240 } 1241 } 1242 1243 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1244 if (err < 0) 1245 goto unlock; 1246 1247 per_cvt = get_cvt(spec, cvt_idx); 1248 /* Claim converter */ 1249 per_cvt->assigned = 1; 1250 1251 set_bit(pcm_idx, &spec->pcm_in_use); 1252 per_pin = get_pin(spec, pin_idx); 1253 per_pin->cvt_nid = per_cvt->cvt_nid; 1254 hinfo->nid = per_cvt->cvt_nid; 1255 1256 /* flip stripe flag for the assigned stream if supported */ 1257 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1258 azx_stream(get_azx_dev(substream))->stripe = 1; 1259 1260 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1261 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1262 AC_VERB_SET_CONNECT_SEL, 1263 per_pin->mux_idx); 1264 1265 /* configure unused pins to choose other converters */ 1266 pin_cvt_fixup(codec, per_pin, 0); 1267 1268 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1269 1270 /* Initially set the converter's capabilities */ 1271 hinfo->channels_min = per_cvt->channels_min; 1272 hinfo->channels_max = per_cvt->channels_max; 1273 hinfo->rates = per_cvt->rates; 1274 hinfo->formats = per_cvt->formats; 1275 hinfo->maxbps = per_cvt->maxbps; 1276 1277 eld = &per_pin->sink_eld; 1278 /* Restrict capabilities by ELD if this isn't disabled */ 1279 if (!static_hdmi_pcm && eld->eld_valid) { 1280 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1281 if (hinfo->channels_min > hinfo->channels_max || 1282 !hinfo->rates || !hinfo->formats) { 1283 per_cvt->assigned = 0; 1284 hinfo->nid = 0; 1285 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1286 err = -ENODEV; 1287 goto unlock; 1288 } 1289 } 1290 1291 /* Store the updated parameters */ 1292 runtime->hw.channels_min = hinfo->channels_min; 1293 runtime->hw.channels_max = hinfo->channels_max; 1294 runtime->hw.formats = hinfo->formats; 1295 runtime->hw.rates = hinfo->rates; 1296 1297 snd_pcm_hw_constraint_step(substream->runtime, 0, 1298 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1299 unlock: 1300 mutex_unlock(&spec->pcm_lock); 1301 return err; 1302 } 1303 1304 /* 1305 * HDA/HDMI auto parsing 1306 */ 1307 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1308 { 1309 struct hdmi_spec *spec = codec->spec; 1310 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1311 hda_nid_t pin_nid = per_pin->pin_nid; 1312 int dev_id = per_pin->dev_id; 1313 int conns; 1314 1315 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1316 codec_warn(codec, 1317 "HDMI: pin %d wcaps %#x does not support connection list\n", 1318 pin_nid, get_wcaps(codec, pin_nid)); 1319 return -EINVAL; 1320 } 1321 1322 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1323 1324 if (spec->intel_hsw_fixup) { 1325 conns = spec->num_cvts; 1326 memcpy(per_pin->mux_nids, spec->cvt_nids, 1327 sizeof(hda_nid_t) * conns); 1328 } else { 1329 conns = snd_hda_get_raw_connections(codec, pin_nid, 1330 per_pin->mux_nids, 1331 HDA_MAX_CONNECTIONS); 1332 } 1333 1334 /* all the device entries on the same pin have the same conn list */ 1335 per_pin->num_mux_nids = conns; 1336 1337 return 0; 1338 } 1339 1340 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1341 struct hdmi_spec_per_pin *per_pin) 1342 { 1343 int i; 1344 1345 /* 1346 * generic_hdmi_build_pcms() may allocate extra PCMs on some 1347 * platforms (with maximum of 'num_nids + dev_num - 1') 1348 * 1349 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n 1350 * if m==0. This guarantees that dynamic pcm assignments are compatible 1351 * with the legacy static per_pin-pcm assignment that existed in the 1352 * days before DP-MST. 1353 * 1354 * Intel DP-MST prefers this legacy behavior for compatibility, too. 1355 * 1356 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)). 1357 */ 1358 1359 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) { 1360 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1361 return per_pin->pin_nid_idx; 1362 } else { 1363 i = spec->num_nids + (per_pin->dev_id - 1); 1364 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap))) 1365 return i; 1366 } 1367 1368 /* have a second try; check the area over num_nids */ 1369 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1370 if (!test_bit(i, &spec->pcm_bitmap)) 1371 return i; 1372 } 1373 1374 /* the last try; check the empty slots in pins */ 1375 for (i = 0; i < spec->num_nids; i++) { 1376 if (!test_bit(i, &spec->pcm_bitmap)) 1377 return i; 1378 } 1379 return -EBUSY; 1380 } 1381 1382 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1383 struct hdmi_spec_per_pin *per_pin) 1384 { 1385 int idx; 1386 1387 /* pcm already be attached to the pin */ 1388 if (per_pin->pcm) 1389 return; 1390 idx = hdmi_find_pcm_slot(spec, per_pin); 1391 if (idx == -EBUSY) 1392 return; 1393 per_pin->pcm_idx = idx; 1394 per_pin->pcm = get_hdmi_pcm(spec, idx); 1395 set_bit(idx, &spec->pcm_bitmap); 1396 } 1397 1398 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1399 struct hdmi_spec_per_pin *per_pin) 1400 { 1401 int idx; 1402 1403 /* pcm already be detached from the pin */ 1404 if (!per_pin->pcm) 1405 return; 1406 idx = per_pin->pcm_idx; 1407 per_pin->pcm_idx = -1; 1408 per_pin->pcm = NULL; 1409 if (idx >= 0 && idx < spec->pcm_used) 1410 clear_bit(idx, &spec->pcm_bitmap); 1411 } 1412 1413 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1414 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1415 { 1416 int mux_idx; 1417 1418 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1419 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1420 break; 1421 return mux_idx; 1422 } 1423 1424 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1425 1426 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1427 struct hdmi_spec_per_pin *per_pin) 1428 { 1429 struct hda_codec *codec = per_pin->codec; 1430 struct hda_pcm *pcm; 1431 struct hda_pcm_stream *hinfo; 1432 struct snd_pcm_substream *substream; 1433 int mux_idx; 1434 bool non_pcm; 1435 1436 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1437 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1438 else 1439 return; 1440 if (!pcm->pcm) 1441 return; 1442 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1443 return; 1444 1445 /* hdmi audio only uses playback and one substream */ 1446 hinfo = pcm->stream; 1447 substream = pcm->pcm->streams[0].substream; 1448 1449 per_pin->cvt_nid = hinfo->nid; 1450 1451 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1452 if (mux_idx < per_pin->num_mux_nids) { 1453 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1454 per_pin->dev_id); 1455 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1456 AC_VERB_SET_CONNECT_SEL, 1457 mux_idx); 1458 } 1459 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1460 1461 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1462 if (substream->runtime) 1463 per_pin->channels = substream->runtime->channels; 1464 per_pin->setup = true; 1465 per_pin->mux_idx = mux_idx; 1466 1467 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1468 } 1469 1470 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1471 struct hdmi_spec_per_pin *per_pin) 1472 { 1473 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1474 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1475 1476 per_pin->chmap_set = false; 1477 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1478 1479 per_pin->setup = false; 1480 per_pin->channels = 0; 1481 } 1482 1483 /* update per_pin ELD from the given new ELD; 1484 * setup info frame and notification accordingly 1485 */ 1486 static bool update_eld(struct hda_codec *codec, 1487 struct hdmi_spec_per_pin *per_pin, 1488 struct hdmi_eld *eld) 1489 { 1490 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1491 struct hdmi_spec *spec = codec->spec; 1492 bool old_eld_valid = pin_eld->eld_valid; 1493 bool eld_changed; 1494 int pcm_idx; 1495 1496 /* for monitor disconnection, save pcm_idx firstly */ 1497 pcm_idx = per_pin->pcm_idx; 1498 if (spec->dyn_pcm_assign) { 1499 if (eld->eld_valid) { 1500 hdmi_attach_hda_pcm(spec, per_pin); 1501 hdmi_pcm_setup_pin(spec, per_pin); 1502 } else { 1503 hdmi_pcm_reset_pin(spec, per_pin); 1504 hdmi_detach_hda_pcm(spec, per_pin); 1505 } 1506 } 1507 /* if pcm_idx == -1, it means this is in monitor connection event 1508 * we can get the correct pcm_idx now. 1509 */ 1510 if (pcm_idx == -1) 1511 pcm_idx = per_pin->pcm_idx; 1512 1513 if (eld->eld_valid) 1514 snd_hdmi_show_eld(codec, &eld->info); 1515 1516 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1517 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1518 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1519 if (pin_eld->eld_size != eld->eld_size || 1520 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1521 eld->eld_size) != 0) 1522 eld_changed = true; 1523 1524 if (eld_changed) { 1525 pin_eld->monitor_present = eld->monitor_present; 1526 pin_eld->eld_valid = eld->eld_valid; 1527 pin_eld->eld_size = eld->eld_size; 1528 if (eld->eld_valid) 1529 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1530 eld->eld_size); 1531 pin_eld->info = eld->info; 1532 } 1533 1534 /* 1535 * Re-setup pin and infoframe. This is needed e.g. when 1536 * - sink is first plugged-in 1537 * - transcoder can change during stream playback on Haswell 1538 * and this can make HW reset converter selection on a pin. 1539 */ 1540 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1541 pin_cvt_fixup(codec, per_pin, 0); 1542 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1543 } 1544 1545 if (eld_changed && pcm_idx >= 0) 1546 snd_ctl_notify(codec->card, 1547 SNDRV_CTL_EVENT_MASK_VALUE | 1548 SNDRV_CTL_EVENT_MASK_INFO, 1549 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1550 return eld_changed; 1551 } 1552 1553 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, 1554 struct hdmi_spec_per_pin *per_pin) 1555 { 1556 struct hdmi_spec *spec = codec->spec; 1557 struct snd_jack *jack = NULL; 1558 struct hda_jack_tbl *jack_tbl; 1559 1560 /* if !dyn_pcm_assign, get jack from hda_jack_tbl 1561 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not 1562 * NULL even after snd_hda_jack_tbl_clear() is called to 1563 * free snd_jack. This may cause access invalid memory 1564 * when calling snd_jack_report 1565 */ 1566 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign) { 1567 jack = spec->pcm_rec[per_pin->pcm_idx].jack; 1568 } else if (!spec->dyn_pcm_assign) { 1569 /* 1570 * jack tbl doesn't support DP MST 1571 * DP MST will use dyn_pcm_assign, 1572 * so DP MST will never come here 1573 */ 1574 jack_tbl = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1575 per_pin->dev_id); 1576 if (jack_tbl) 1577 jack = jack_tbl->jack; 1578 } 1579 return jack; 1580 } 1581 /* update ELD and jack state via HD-audio verbs */ 1582 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1583 int repoll) 1584 { 1585 struct hda_jack_tbl *jack; 1586 struct hda_codec *codec = per_pin->codec; 1587 struct hdmi_spec *spec = codec->spec; 1588 struct hdmi_eld *eld = &spec->temp_eld; 1589 hda_nid_t pin_nid = per_pin->pin_nid; 1590 int dev_id = per_pin->dev_id; 1591 /* 1592 * Always execute a GetPinSense verb here, even when called from 1593 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1594 * response's PD bit is not the real PD value, but indicates that 1595 * the real PD value changed. An older version of the HD-audio 1596 * specification worked this way. Hence, we just ignore the data in 1597 * the unsolicited response to avoid custom WARs. 1598 */ 1599 int present; 1600 bool ret; 1601 bool do_repoll = false; 1602 struct snd_jack *pcm_jack = NULL; 1603 1604 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1605 1606 mutex_lock(&per_pin->lock); 1607 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1608 if (eld->monitor_present) 1609 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1610 else 1611 eld->eld_valid = false; 1612 1613 codec_dbg(codec, 1614 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1615 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1616 1617 if (eld->eld_valid) { 1618 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1619 eld->eld_buffer, &eld->eld_size) < 0) 1620 eld->eld_valid = false; 1621 else { 1622 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1623 eld->eld_size) < 0) 1624 eld->eld_valid = false; 1625 } 1626 if (!eld->eld_valid && repoll) 1627 do_repoll = true; 1628 } 1629 1630 if (do_repoll) { 1631 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); 1632 } else { 1633 /* 1634 * pcm_idx >=0 before update_eld() means it is in monitor 1635 * disconnected event. Jack must be fetched before 1636 * update_eld(). 1637 */ 1638 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1639 update_eld(codec, per_pin, eld); 1640 if (!pcm_jack) 1641 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1642 } 1643 1644 ret = !repoll || !eld->monitor_present || eld->eld_valid; 1645 1646 jack = snd_hda_jack_tbl_get_mst(codec, pin_nid, per_pin->dev_id); 1647 if (jack) { 1648 jack->block_report = !ret; 1649 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ? 1650 AC_PINSENSE_PRESENCE : 0; 1651 1652 if (spec->dyn_pcm_assign && pcm_jack && !do_repoll) { 1653 int state = 0; 1654 1655 if (jack->pin_sense & AC_PINSENSE_PRESENCE) 1656 state = SND_JACK_AVOUT; 1657 snd_jack_report(pcm_jack, state); 1658 } 1659 1660 /* 1661 * snd_hda_jack_pin_sense() call at the beginning of this 1662 * function, updates jack->pins_sense and clears 1663 * jack->jack_dirty, therefore snd_hda_jack_report_sync() will 1664 * not override the jack->pin_sense. 1665 * 1666 * snd_hda_jack_report_sync() is superfluous for dyn_pcm_assign 1667 * case. The jack->pin_sense update was already performed, and 1668 * hda_jack->jack is NULL for dyn_pcm_assign. 1669 * 1670 * Don't call snd_hda_jack_report_sync() for 1671 * dyn_pcm_assign. 1672 */ 1673 ret = ret && !spec->dyn_pcm_assign; 1674 } 1675 mutex_unlock(&per_pin->lock); 1676 return ret; 1677 } 1678 1679 /* update ELD and jack state via audio component */ 1680 static void sync_eld_via_acomp(struct hda_codec *codec, 1681 struct hdmi_spec_per_pin *per_pin) 1682 { 1683 struct hdmi_spec *spec = codec->spec; 1684 struct hdmi_eld *eld = &spec->temp_eld; 1685 struct snd_jack *jack = NULL; 1686 bool changed; 1687 int size; 1688 1689 mutex_lock(&per_pin->lock); 1690 eld->monitor_present = false; 1691 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1692 per_pin->dev_id, &eld->monitor_present, 1693 eld->eld_buffer, ELD_MAX_SIZE); 1694 if (size > 0) { 1695 size = min(size, ELD_MAX_SIZE); 1696 if (snd_hdmi_parse_eld(codec, &eld->info, 1697 eld->eld_buffer, size) < 0) 1698 size = -EINVAL; 1699 } 1700 1701 if (size > 0) { 1702 eld->eld_valid = true; 1703 eld->eld_size = size; 1704 } else { 1705 eld->eld_valid = false; 1706 eld->eld_size = 0; 1707 } 1708 1709 /* pcm_idx >=0 before update_eld() means it is in monitor 1710 * disconnected event. Jack must be fetched before update_eld() 1711 */ 1712 jack = pin_idx_to_pcm_jack(codec, per_pin); 1713 changed = update_eld(codec, per_pin, eld); 1714 if (jack == NULL) 1715 jack = pin_idx_to_pcm_jack(codec, per_pin); 1716 if (changed && jack) 1717 snd_jack_report(jack, 1718 (eld->monitor_present && eld->eld_valid) ? 1719 SND_JACK_AVOUT : 0); 1720 mutex_unlock(&per_pin->lock); 1721 } 1722 1723 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1724 { 1725 struct hda_codec *codec = per_pin->codec; 1726 int ret; 1727 1728 /* no temporary power up/down needed for component notifier */ 1729 if (!codec_has_acomp(codec)) { 1730 ret = snd_hda_power_up_pm(codec); 1731 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) { 1732 snd_hda_power_down_pm(codec); 1733 return false; 1734 } 1735 ret = hdmi_present_sense_via_verbs(per_pin, repoll); 1736 snd_hda_power_down_pm(codec); 1737 } else { 1738 sync_eld_via_acomp(codec, per_pin); 1739 ret = false; /* don't call snd_hda_jack_report_sync() */ 1740 } 1741 1742 return ret; 1743 } 1744 1745 static void hdmi_repoll_eld(struct work_struct *work) 1746 { 1747 struct hdmi_spec_per_pin *per_pin = 1748 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1749 struct hda_codec *codec = per_pin->codec; 1750 struct hdmi_spec *spec = codec->spec; 1751 struct hda_jack_tbl *jack; 1752 1753 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1754 per_pin->dev_id); 1755 if (jack) 1756 jack->jack_dirty = 1; 1757 1758 if (per_pin->repoll_count++ > 6) 1759 per_pin->repoll_count = 0; 1760 1761 mutex_lock(&spec->pcm_lock); 1762 if (hdmi_present_sense(per_pin, per_pin->repoll_count)) 1763 snd_hda_jack_report_sync(per_pin->codec); 1764 mutex_unlock(&spec->pcm_lock); 1765 } 1766 1767 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1768 { 1769 struct hdmi_spec *spec = codec->spec; 1770 unsigned int caps, config; 1771 int pin_idx; 1772 struct hdmi_spec_per_pin *per_pin; 1773 int err; 1774 int dev_num, i; 1775 1776 caps = snd_hda_query_pin_caps(codec, pin_nid); 1777 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1778 return 0; 1779 1780 /* 1781 * For DP MST audio, Configuration Default is the same for 1782 * all device entries on the same pin 1783 */ 1784 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1785 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1786 return 0; 1787 1788 /* 1789 * To simplify the implementation, malloc all 1790 * the virtual pins in the initialization statically 1791 */ 1792 if (spec->intel_hsw_fixup) { 1793 /* 1794 * On Intel platforms, device entries number is 1795 * changed dynamically. If there is a DP MST 1796 * hub connected, the device entries number is 3. 1797 * Otherwise, it is 1. 1798 * Here we manually set dev_num to 3, so that 1799 * we can initialize all the device entries when 1800 * bootup statically. 1801 */ 1802 dev_num = 3; 1803 spec->dev_num = 3; 1804 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1805 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1806 /* 1807 * spec->dev_num is the maxinum number of device entries 1808 * among all the pins 1809 */ 1810 spec->dev_num = (spec->dev_num > dev_num) ? 1811 spec->dev_num : dev_num; 1812 } else { 1813 /* 1814 * If the platform doesn't support DP MST, 1815 * manually set dev_num to 1. This means 1816 * the pin has only one device entry. 1817 */ 1818 dev_num = 1; 1819 spec->dev_num = 1; 1820 } 1821 1822 for (i = 0; i < dev_num; i++) { 1823 pin_idx = spec->num_pins; 1824 per_pin = snd_array_new(&spec->pins); 1825 1826 if (!per_pin) 1827 return -ENOMEM; 1828 1829 if (spec->dyn_pcm_assign) { 1830 per_pin->pcm = NULL; 1831 per_pin->pcm_idx = -1; 1832 } else { 1833 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1834 per_pin->pcm_idx = pin_idx; 1835 } 1836 per_pin->pin_nid = pin_nid; 1837 per_pin->pin_nid_idx = spec->num_nids; 1838 per_pin->dev_id = i; 1839 per_pin->non_pcm = false; 1840 snd_hda_set_dev_select(codec, pin_nid, i); 1841 err = hdmi_read_pin_conn(codec, pin_idx); 1842 if (err < 0) 1843 return err; 1844 spec->num_pins++; 1845 } 1846 spec->num_nids++; 1847 1848 return 0; 1849 } 1850 1851 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1852 { 1853 struct hdmi_spec *spec = codec->spec; 1854 struct hdmi_spec_per_cvt *per_cvt; 1855 unsigned int chans; 1856 int err; 1857 1858 chans = get_wcaps(codec, cvt_nid); 1859 chans = get_wcaps_channels(chans); 1860 1861 per_cvt = snd_array_new(&spec->cvts); 1862 if (!per_cvt) 1863 return -ENOMEM; 1864 1865 per_cvt->cvt_nid = cvt_nid; 1866 per_cvt->channels_min = 2; 1867 if (chans <= 16) { 1868 per_cvt->channels_max = chans; 1869 if (chans > spec->chmap.channels_max) 1870 spec->chmap.channels_max = chans; 1871 } 1872 1873 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1874 &per_cvt->rates, 1875 &per_cvt->formats, 1876 &per_cvt->maxbps); 1877 if (err < 0) 1878 return err; 1879 1880 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1881 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1882 spec->num_cvts++; 1883 1884 return 0; 1885 } 1886 1887 static int hdmi_parse_codec(struct hda_codec *codec) 1888 { 1889 hda_nid_t nid; 1890 int i, nodes; 1891 1892 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); 1893 if (!nid || nodes < 0) { 1894 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1895 return -EINVAL; 1896 } 1897 1898 for (i = 0; i < nodes; i++, nid++) { 1899 unsigned int caps; 1900 unsigned int type; 1901 1902 caps = get_wcaps(codec, nid); 1903 type = get_wcaps_type(caps); 1904 1905 if (!(caps & AC_WCAP_DIGITAL)) 1906 continue; 1907 1908 switch (type) { 1909 case AC_WID_AUD_OUT: 1910 hdmi_add_cvt(codec, nid); 1911 break; 1912 case AC_WID_PIN: 1913 hdmi_add_pin(codec, nid); 1914 break; 1915 } 1916 } 1917 1918 return 0; 1919 } 1920 1921 /* 1922 */ 1923 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1924 { 1925 struct hda_spdif_out *spdif; 1926 bool non_pcm; 1927 1928 mutex_lock(&codec->spdif_mutex); 1929 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1930 /* Add sanity check to pass klockwork check. 1931 * This should never happen. 1932 */ 1933 if (WARN_ON(spdif == NULL)) 1934 return true; 1935 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1936 mutex_unlock(&codec->spdif_mutex); 1937 return non_pcm; 1938 } 1939 1940 /* 1941 * HDMI callbacks 1942 */ 1943 1944 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1945 struct hda_codec *codec, 1946 unsigned int stream_tag, 1947 unsigned int format, 1948 struct snd_pcm_substream *substream) 1949 { 1950 hda_nid_t cvt_nid = hinfo->nid; 1951 struct hdmi_spec *spec = codec->spec; 1952 int pin_idx; 1953 struct hdmi_spec_per_pin *per_pin; 1954 struct snd_pcm_runtime *runtime = substream->runtime; 1955 bool non_pcm; 1956 int pinctl, stripe; 1957 int err = 0; 1958 1959 mutex_lock(&spec->pcm_lock); 1960 pin_idx = hinfo_to_pin_index(codec, hinfo); 1961 if (spec->dyn_pcm_assign && pin_idx < 0) { 1962 /* when dyn_pcm_assign and pcm is not bound to a pin 1963 * skip pin setup and return 0 to make audio playback 1964 * be ongoing 1965 */ 1966 pin_cvt_fixup(codec, NULL, cvt_nid); 1967 snd_hda_codec_setup_stream(codec, cvt_nid, 1968 stream_tag, 0, format); 1969 goto unlock; 1970 } 1971 1972 if (snd_BUG_ON(pin_idx < 0)) { 1973 err = -EINVAL; 1974 goto unlock; 1975 } 1976 per_pin = get_pin(spec, pin_idx); 1977 1978 /* Verify pin:cvt selections to avoid silent audio after S3. 1979 * After S3, the audio driver restores pin:cvt selections 1980 * but this can happen before gfx is ready and such selection 1981 * is overlooked by HW. Thus multiple pins can share a same 1982 * default convertor and mute control will affect each other, 1983 * which can cause a resumed audio playback become silent 1984 * after S3. 1985 */ 1986 pin_cvt_fixup(codec, per_pin, 0); 1987 1988 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 1989 /* Todo: add DP1.2 MST audio support later */ 1990 if (codec_has_acomp(codec)) 1991 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1992 per_pin->dev_id, runtime->rate); 1993 1994 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1995 mutex_lock(&per_pin->lock); 1996 per_pin->channels = substream->runtime->channels; 1997 per_pin->setup = true; 1998 1999 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 2000 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 2001 substream); 2002 snd_hda_codec_write(codec, cvt_nid, 0, 2003 AC_VERB_SET_STRIPE_CONTROL, 2004 stripe); 2005 } 2006 2007 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 2008 mutex_unlock(&per_pin->lock); 2009 if (spec->dyn_pin_out) { 2010 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2011 per_pin->dev_id); 2012 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2013 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2014 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2015 AC_VERB_SET_PIN_WIDGET_CONTROL, 2016 pinctl | PIN_OUT); 2017 } 2018 2019 /* snd_hda_set_dev_select() has been called before */ 2020 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 2021 per_pin->dev_id, stream_tag, format); 2022 unlock: 2023 mutex_unlock(&spec->pcm_lock); 2024 return err; 2025 } 2026 2027 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2028 struct hda_codec *codec, 2029 struct snd_pcm_substream *substream) 2030 { 2031 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 2032 return 0; 2033 } 2034 2035 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2036 struct hda_codec *codec, 2037 struct snd_pcm_substream *substream) 2038 { 2039 struct hdmi_spec *spec = codec->spec; 2040 int cvt_idx, pin_idx, pcm_idx; 2041 struct hdmi_spec_per_cvt *per_cvt; 2042 struct hdmi_spec_per_pin *per_pin; 2043 int pinctl; 2044 int err = 0; 2045 2046 if (hinfo->nid) { 2047 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2048 if (snd_BUG_ON(pcm_idx < 0)) 2049 return -EINVAL; 2050 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2051 if (snd_BUG_ON(cvt_idx < 0)) 2052 return -EINVAL; 2053 per_cvt = get_cvt(spec, cvt_idx); 2054 2055 snd_BUG_ON(!per_cvt->assigned); 2056 per_cvt->assigned = 0; 2057 hinfo->nid = 0; 2058 2059 azx_stream(get_azx_dev(substream))->stripe = 0; 2060 2061 mutex_lock(&spec->pcm_lock); 2062 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2063 clear_bit(pcm_idx, &spec->pcm_in_use); 2064 pin_idx = hinfo_to_pin_index(codec, hinfo); 2065 if (spec->dyn_pcm_assign && pin_idx < 0) 2066 goto unlock; 2067 2068 if (snd_BUG_ON(pin_idx < 0)) { 2069 err = -EINVAL; 2070 goto unlock; 2071 } 2072 per_pin = get_pin(spec, pin_idx); 2073 2074 if (spec->dyn_pin_out) { 2075 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2076 per_pin->dev_id); 2077 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2078 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2079 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2080 AC_VERB_SET_PIN_WIDGET_CONTROL, 2081 pinctl & ~PIN_OUT); 2082 } 2083 2084 mutex_lock(&per_pin->lock); 2085 per_pin->chmap_set = false; 2086 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2087 2088 per_pin->setup = false; 2089 per_pin->channels = 0; 2090 mutex_unlock(&per_pin->lock); 2091 unlock: 2092 mutex_unlock(&spec->pcm_lock); 2093 } 2094 2095 return err; 2096 } 2097 2098 static const struct hda_pcm_ops generic_ops = { 2099 .open = hdmi_pcm_open, 2100 .close = hdmi_pcm_close, 2101 .prepare = generic_hdmi_playback_pcm_prepare, 2102 .cleanup = generic_hdmi_playback_pcm_cleanup, 2103 }; 2104 2105 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2106 { 2107 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2108 struct hdmi_spec *spec = codec->spec; 2109 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2110 2111 if (!per_pin) 2112 return 0; 2113 2114 return per_pin->sink_eld.info.spk_alloc; 2115 } 2116 2117 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2118 unsigned char *chmap) 2119 { 2120 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2121 struct hdmi_spec *spec = codec->spec; 2122 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2123 2124 /* chmap is already set to 0 in caller */ 2125 if (!per_pin) 2126 return; 2127 2128 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2129 } 2130 2131 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2132 unsigned char *chmap, int prepared) 2133 { 2134 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2135 struct hdmi_spec *spec = codec->spec; 2136 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2137 2138 if (!per_pin) 2139 return; 2140 mutex_lock(&per_pin->lock); 2141 per_pin->chmap_set = true; 2142 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2143 if (prepared) 2144 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2145 mutex_unlock(&per_pin->lock); 2146 } 2147 2148 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2149 { 2150 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2151 struct hdmi_spec *spec = codec->spec; 2152 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2153 2154 return per_pin ? true:false; 2155 } 2156 2157 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2158 { 2159 struct hdmi_spec *spec = codec->spec; 2160 int idx, pcm_num; 2161 2162 /* 2163 * for non-mst mode, pcm number is the same as before 2164 * for DP MST mode without extra PCM, pcm number is same 2165 * for DP MST mode with extra PCMs, pcm number is 2166 * (nid number + dev_num - 1) 2167 * dev_num is the device entry number in a pin 2168 */ 2169 2170 if (codec->mst_no_extra_pcms) 2171 pcm_num = spec->num_nids; 2172 else 2173 pcm_num = spec->num_nids + spec->dev_num - 1; 2174 2175 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2176 2177 for (idx = 0; idx < pcm_num; idx++) { 2178 struct hda_pcm *info; 2179 struct hda_pcm_stream *pstr; 2180 2181 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2182 if (!info) 2183 return -ENOMEM; 2184 2185 spec->pcm_rec[idx].pcm = info; 2186 spec->pcm_used++; 2187 info->pcm_type = HDA_PCM_TYPE_HDMI; 2188 info->own_chmap = true; 2189 2190 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2191 pstr->substreams = 1; 2192 pstr->ops = generic_ops; 2193 /* pcm number is less than 16 */ 2194 if (spec->pcm_used >= 16) 2195 break; 2196 /* other pstr fields are set in open */ 2197 } 2198 2199 return 0; 2200 } 2201 2202 static void free_hdmi_jack_priv(struct snd_jack *jack) 2203 { 2204 struct hdmi_pcm *pcm = jack->private_data; 2205 2206 pcm->jack = NULL; 2207 } 2208 2209 static int add_hdmi_jack_kctl(struct hda_codec *codec, 2210 struct hdmi_spec *spec, 2211 int pcm_idx, 2212 const char *name) 2213 { 2214 struct snd_jack *jack; 2215 int err; 2216 2217 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack, 2218 true, false); 2219 if (err < 0) 2220 return err; 2221 2222 spec->pcm_rec[pcm_idx].jack = jack; 2223 jack->private_data = &spec->pcm_rec[pcm_idx]; 2224 jack->private_free = free_hdmi_jack_priv; 2225 return 0; 2226 } 2227 2228 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2229 { 2230 char hdmi_str[32] = "HDMI/DP"; 2231 struct hdmi_spec *spec = codec->spec; 2232 struct hdmi_spec_per_pin *per_pin; 2233 struct hda_jack_tbl *jack; 2234 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2235 bool phantom_jack; 2236 int ret; 2237 2238 if (pcmdev > 0) 2239 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2240 2241 if (spec->dyn_pcm_assign) 2242 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str); 2243 2244 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */ 2245 /* if !dyn_pcm_assign, it must be non-MST mode. 2246 * This means pcms and pins are statically mapped. 2247 * And pcm_idx is pin_idx. 2248 */ 2249 per_pin = get_pin(spec, pcm_idx); 2250 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); 2251 if (phantom_jack) 2252 strncat(hdmi_str, " Phantom", 2253 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2254 ret = snd_hda_jack_add_kctl_mst(codec, per_pin->pin_nid, 2255 per_pin->dev_id, hdmi_str, phantom_jack, 2256 0, NULL); 2257 if (ret < 0) 2258 return ret; 2259 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 2260 per_pin->dev_id); 2261 if (jack == NULL) 2262 return 0; 2263 /* assign jack->jack to pcm_rec[].jack to 2264 * align with dyn_pcm_assign mode 2265 */ 2266 spec->pcm_rec[pcm_idx].jack = jack->jack; 2267 return 0; 2268 } 2269 2270 static int generic_hdmi_build_controls(struct hda_codec *codec) 2271 { 2272 struct hdmi_spec *spec = codec->spec; 2273 int dev, err; 2274 int pin_idx, pcm_idx; 2275 2276 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2277 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2278 /* no PCM: mark this for skipping permanently */ 2279 set_bit(pcm_idx, &spec->pcm_bitmap); 2280 continue; 2281 } 2282 2283 err = generic_hdmi_build_jack(codec, pcm_idx); 2284 if (err < 0) 2285 return err; 2286 2287 /* create the spdif for each pcm 2288 * pin will be bound when monitor is connected 2289 */ 2290 if (spec->dyn_pcm_assign) 2291 err = snd_hda_create_dig_out_ctls(codec, 2292 0, spec->cvt_nids[0], 2293 HDA_PCM_TYPE_HDMI); 2294 else { 2295 struct hdmi_spec_per_pin *per_pin = 2296 get_pin(spec, pcm_idx); 2297 err = snd_hda_create_dig_out_ctls(codec, 2298 per_pin->pin_nid, 2299 per_pin->mux_nids[0], 2300 HDA_PCM_TYPE_HDMI); 2301 } 2302 if (err < 0) 2303 return err; 2304 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2305 2306 dev = get_pcm_rec(spec, pcm_idx)->device; 2307 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2308 /* add control for ELD Bytes */ 2309 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2310 if (err < 0) 2311 return err; 2312 } 2313 } 2314 2315 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2316 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2317 2318 hdmi_present_sense(per_pin, 0); 2319 } 2320 2321 /* add channel maps */ 2322 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2323 struct hda_pcm *pcm; 2324 2325 pcm = get_pcm_rec(spec, pcm_idx); 2326 if (!pcm || !pcm->pcm) 2327 break; 2328 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2329 if (err < 0) 2330 return err; 2331 } 2332 2333 return 0; 2334 } 2335 2336 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2337 { 2338 struct hdmi_spec *spec = codec->spec; 2339 int pin_idx; 2340 2341 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2342 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2343 2344 per_pin->codec = codec; 2345 mutex_init(&per_pin->lock); 2346 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2347 eld_proc_new(per_pin, pin_idx); 2348 } 2349 return 0; 2350 } 2351 2352 static int generic_hdmi_init(struct hda_codec *codec) 2353 { 2354 struct hdmi_spec *spec = codec->spec; 2355 int pin_idx; 2356 2357 mutex_lock(&spec->bind_lock); 2358 spec->use_jack_detect = !codec->jackpoll_interval; 2359 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2360 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2361 hda_nid_t pin_nid = per_pin->pin_nid; 2362 int dev_id = per_pin->dev_id; 2363 2364 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2365 hdmi_init_pin(codec, pin_nid); 2366 if (codec_has_acomp(codec)) 2367 continue; 2368 if (spec->use_jack_detect) 2369 snd_hda_jack_detect_enable(codec, pin_nid, dev_id); 2370 else 2371 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, 2372 dev_id, 2373 jack_callback); 2374 } 2375 mutex_unlock(&spec->bind_lock); 2376 return 0; 2377 } 2378 2379 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2380 { 2381 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2382 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2383 } 2384 2385 static void hdmi_array_free(struct hdmi_spec *spec) 2386 { 2387 snd_array_free(&spec->pins); 2388 snd_array_free(&spec->cvts); 2389 } 2390 2391 static void generic_spec_free(struct hda_codec *codec) 2392 { 2393 struct hdmi_spec *spec = codec->spec; 2394 2395 if (spec) { 2396 hdmi_array_free(spec); 2397 kfree(spec); 2398 codec->spec = NULL; 2399 } 2400 codec->dp_mst = false; 2401 } 2402 2403 static void generic_hdmi_free(struct hda_codec *codec) 2404 { 2405 struct hdmi_spec *spec = codec->spec; 2406 int pin_idx, pcm_idx; 2407 2408 if (spec->acomp_registered) { 2409 snd_hdac_acomp_exit(&codec->bus->core); 2410 } else if (codec_has_acomp(codec)) { 2411 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2412 } 2413 codec->relaxed_resume = 0; 2414 2415 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2416 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2417 cancel_delayed_work_sync(&per_pin->work); 2418 eld_proc_free(per_pin); 2419 } 2420 2421 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2422 if (spec->pcm_rec[pcm_idx].jack == NULL) 2423 continue; 2424 if (spec->dyn_pcm_assign) 2425 snd_device_free(codec->card, 2426 spec->pcm_rec[pcm_idx].jack); 2427 else 2428 spec->pcm_rec[pcm_idx].jack = NULL; 2429 } 2430 2431 generic_spec_free(codec); 2432 } 2433 2434 #ifdef CONFIG_PM 2435 static int generic_hdmi_resume(struct hda_codec *codec) 2436 { 2437 struct hdmi_spec *spec = codec->spec; 2438 int pin_idx; 2439 2440 codec->patch_ops.init(codec); 2441 snd_hda_regmap_sync(codec); 2442 2443 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2444 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2445 hdmi_present_sense(per_pin, 1); 2446 } 2447 return 0; 2448 } 2449 #endif 2450 2451 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2452 .init = generic_hdmi_init, 2453 .free = generic_hdmi_free, 2454 .build_pcms = generic_hdmi_build_pcms, 2455 .build_controls = generic_hdmi_build_controls, 2456 .unsol_event = hdmi_unsol_event, 2457 #ifdef CONFIG_PM 2458 .resume = generic_hdmi_resume, 2459 #endif 2460 }; 2461 2462 static const struct hdmi_ops generic_standard_hdmi_ops = { 2463 .pin_get_eld = hdmi_pin_get_eld, 2464 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2465 .pin_hbr_setup = hdmi_pin_hbr_setup, 2466 .setup_stream = hdmi_setup_stream, 2467 }; 2468 2469 /* allocate codec->spec and assign/initialize generic parser ops */ 2470 static int alloc_generic_hdmi(struct hda_codec *codec) 2471 { 2472 struct hdmi_spec *spec; 2473 2474 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2475 if (!spec) 2476 return -ENOMEM; 2477 2478 spec->codec = codec; 2479 spec->ops = generic_standard_hdmi_ops; 2480 spec->dev_num = 1; /* initialize to 1 */ 2481 mutex_init(&spec->pcm_lock); 2482 mutex_init(&spec->bind_lock); 2483 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2484 2485 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2486 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2487 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2488 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, 2489 2490 codec->spec = spec; 2491 hdmi_array_init(spec, 4); 2492 2493 codec->patch_ops = generic_hdmi_patch_ops; 2494 2495 return 0; 2496 } 2497 2498 /* generic HDMI parser */ 2499 static int patch_generic_hdmi(struct hda_codec *codec) 2500 { 2501 int err; 2502 2503 err = alloc_generic_hdmi(codec); 2504 if (err < 0) 2505 return err; 2506 2507 err = hdmi_parse_codec(codec); 2508 if (err < 0) { 2509 generic_spec_free(codec); 2510 return err; 2511 } 2512 2513 generic_hdmi_init_per_pins(codec); 2514 return 0; 2515 } 2516 2517 /* 2518 * generic audio component binding 2519 */ 2520 2521 /* turn on / off the unsol event jack detection dynamically */ 2522 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2523 int dev_id, bool use_acomp) 2524 { 2525 struct hda_jack_tbl *tbl; 2526 2527 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2528 if (tbl) { 2529 /* clear unsol even if component notifier is used, or re-enable 2530 * if notifier is cleared 2531 */ 2532 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2533 snd_hda_codec_write_cache(codec, nid, 0, 2534 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2535 } else { 2536 /* if no jack entry was defined beforehand, create a new one 2537 * at need (i.e. only when notifier is cleared) 2538 */ 2539 if (!use_acomp) 2540 snd_hda_jack_detect_enable(codec, nid, dev_id); 2541 } 2542 } 2543 2544 /* set up / clear component notifier dynamically */ 2545 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2546 bool use_acomp) 2547 { 2548 struct hdmi_spec *spec; 2549 int i; 2550 2551 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2552 mutex_lock(&spec->bind_lock); 2553 spec->use_acomp_notifier = use_acomp; 2554 spec->codec->relaxed_resume = use_acomp; 2555 /* reprogram each jack detection logic depending on the notifier */ 2556 if (spec->use_jack_detect) { 2557 for (i = 0; i < spec->num_pins; i++) 2558 reprogram_jack_detect(spec->codec, 2559 get_pin(spec, i)->pin_nid, 2560 get_pin(spec, i)->dev_id, 2561 use_acomp); 2562 } 2563 mutex_unlock(&spec->bind_lock); 2564 } 2565 2566 /* enable / disable the notifier via master bind / unbind */ 2567 static int generic_acomp_master_bind(struct device *dev, 2568 struct drm_audio_component *acomp) 2569 { 2570 generic_acomp_notifier_set(acomp, true); 2571 return 0; 2572 } 2573 2574 static void generic_acomp_master_unbind(struct device *dev, 2575 struct drm_audio_component *acomp) 2576 { 2577 generic_acomp_notifier_set(acomp, false); 2578 } 2579 2580 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2581 static int match_bound_vga(struct device *dev, int subtype, void *data) 2582 { 2583 struct hdac_bus *bus = data; 2584 struct pci_dev *pci, *master; 2585 2586 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2587 return 0; 2588 master = to_pci_dev(bus->dev); 2589 pci = to_pci_dev(dev); 2590 return master->bus == pci->bus; 2591 } 2592 2593 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2594 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2595 { 2596 struct hda_codec *codec = audio_ptr; 2597 struct hdmi_spec *spec = codec->spec; 2598 hda_nid_t pin_nid = spec->port2pin(codec, port); 2599 2600 if (!pin_nid) 2601 return; 2602 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2603 return; 2604 /* skip notification during system suspend (but not in runtime PM); 2605 * the state will be updated at resume 2606 */ 2607 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2608 return; 2609 /* ditto during suspend/resume process itself */ 2610 if (snd_hdac_is_in_pm(&codec->core)) 2611 return; 2612 2613 check_presence_and_report(codec, pin_nid, dev_id); 2614 } 2615 2616 /* set up the private drm_audio_ops from the template */ 2617 static void setup_drm_audio_ops(struct hda_codec *codec, 2618 const struct drm_audio_component_audio_ops *ops) 2619 { 2620 struct hdmi_spec *spec = codec->spec; 2621 2622 spec->drm_audio_ops.audio_ptr = codec; 2623 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2624 * will call pin_eld_notify with using audio_ptr pointer 2625 * We need make sure audio_ptr is really setup 2626 */ 2627 wmb(); 2628 spec->drm_audio_ops.pin2port = ops->pin2port; 2629 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2630 spec->drm_audio_ops.master_bind = ops->master_bind; 2631 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2632 } 2633 2634 /* initialize the generic HDMI audio component */ 2635 static void generic_acomp_init(struct hda_codec *codec, 2636 const struct drm_audio_component_audio_ops *ops, 2637 int (*port2pin)(struct hda_codec *, int)) 2638 { 2639 struct hdmi_spec *spec = codec->spec; 2640 2641 spec->port2pin = port2pin; 2642 setup_drm_audio_ops(codec, ops); 2643 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2644 match_bound_vga, 0)) { 2645 spec->acomp_registered = true; 2646 codec->bus->keep_power = 0; 2647 } 2648 } 2649 2650 /* 2651 * Intel codec parsers and helpers 2652 */ 2653 2654 #define INTEL_GET_VENDOR_VERB 0xf81 2655 #define INTEL_SET_VENDOR_VERB 0x781 2656 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2657 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2658 2659 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2660 bool update_tree) 2661 { 2662 unsigned int vendor_param; 2663 struct hdmi_spec *spec = codec->spec; 2664 2665 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2666 INTEL_GET_VENDOR_VERB, 0); 2667 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2668 return; 2669 2670 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2671 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2672 INTEL_SET_VENDOR_VERB, vendor_param); 2673 if (vendor_param == -1) 2674 return; 2675 2676 if (update_tree) 2677 snd_hda_codec_update_widgets(codec); 2678 } 2679 2680 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2681 { 2682 unsigned int vendor_param; 2683 struct hdmi_spec *spec = codec->spec; 2684 2685 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2686 INTEL_GET_VENDOR_VERB, 0); 2687 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2688 return; 2689 2690 /* enable DP1.2 mode */ 2691 vendor_param |= INTEL_EN_DP12; 2692 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2693 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2694 INTEL_SET_VENDOR_VERB, vendor_param); 2695 } 2696 2697 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2698 * Otherwise you may get severe h/w communication errors. 2699 */ 2700 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2701 unsigned int power_state) 2702 { 2703 if (power_state == AC_PWRST_D0) { 2704 intel_haswell_enable_all_pins(codec, false); 2705 intel_haswell_fixup_enable_dp12(codec); 2706 } 2707 2708 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2709 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2710 } 2711 2712 /* There is a fixed mapping between audio pin node and display port. 2713 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2714 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2715 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2716 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2717 * 2718 * on VLV, ILK: 2719 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2720 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2721 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2722 */ 2723 static int intel_base_nid(struct hda_codec *codec) 2724 { 2725 switch (codec->core.vendor_id) { 2726 case 0x80860054: /* ILK */ 2727 case 0x80862804: /* ILK */ 2728 case 0x80862882: /* VLV */ 2729 return 4; 2730 default: 2731 return 5; 2732 } 2733 } 2734 2735 static int intel_pin2port(void *audio_ptr, int pin_nid) 2736 { 2737 struct hda_codec *codec = audio_ptr; 2738 struct hdmi_spec *spec = codec->spec; 2739 int base_nid, i; 2740 2741 if (!spec->port_num) { 2742 base_nid = intel_base_nid(codec); 2743 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2744 return -1; 2745 return pin_nid - base_nid + 1; 2746 } 2747 2748 /* 2749 * looking for the pin number in the mapping table and return 2750 * the index which indicate the port number 2751 */ 2752 for (i = 0; i < spec->port_num; i++) { 2753 if (pin_nid == spec->port_map[i]) 2754 return i; 2755 } 2756 2757 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid); 2758 return -1; 2759 } 2760 2761 static int intel_port2pin(struct hda_codec *codec, int port) 2762 { 2763 struct hdmi_spec *spec = codec->spec; 2764 2765 if (!spec->port_num) { 2766 /* we assume only from port-B to port-D */ 2767 if (port < 1 || port > 3) 2768 return 0; 2769 return port + intel_base_nid(codec) - 1; 2770 } 2771 2772 if (port < 0 || port >= spec->port_num) 2773 return 0; 2774 return spec->port_map[port]; 2775 } 2776 2777 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2778 { 2779 struct hda_codec *codec = audio_ptr; 2780 int pin_nid; 2781 int dev_id = pipe; 2782 2783 pin_nid = intel_port2pin(codec, port); 2784 if (!pin_nid) 2785 return; 2786 /* skip notification during system suspend (but not in runtime PM); 2787 * the state will be updated at resume 2788 */ 2789 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2790 return; 2791 /* ditto during suspend/resume process itself */ 2792 if (snd_hdac_is_in_pm(&codec->core)) 2793 return; 2794 2795 snd_hdac_i915_set_bclk(&codec->bus->core); 2796 check_presence_and_report(codec, pin_nid, dev_id); 2797 } 2798 2799 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2800 .pin2port = intel_pin2port, 2801 .pin_eld_notify = intel_pin_eld_notify, 2802 }; 2803 2804 /* register i915 component pin_eld_notify callback */ 2805 static void register_i915_notifier(struct hda_codec *codec) 2806 { 2807 struct hdmi_spec *spec = codec->spec; 2808 2809 spec->use_acomp_notifier = true; 2810 spec->port2pin = intel_port2pin; 2811 setup_drm_audio_ops(codec, &intel_audio_ops); 2812 snd_hdac_acomp_register_notifier(&codec->bus->core, 2813 &spec->drm_audio_ops); 2814 /* no need for forcible resume for jack check thanks to notifier */ 2815 codec->relaxed_resume = 1; 2816 } 2817 2818 /* setup_stream ops override for HSW+ */ 2819 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2820 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2821 int format) 2822 { 2823 haswell_verify_D0(codec, cvt_nid, pin_nid); 2824 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2825 stream_tag, format); 2826 } 2827 2828 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2829 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2830 struct hdmi_spec_per_pin *per_pin, 2831 hda_nid_t cvt_nid) 2832 { 2833 if (per_pin) { 2834 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2835 per_pin->dev_id); 2836 intel_verify_pin_cvt_connect(codec, per_pin); 2837 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2838 per_pin->dev_id, per_pin->mux_idx); 2839 } else { 2840 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2841 } 2842 } 2843 2844 /* precondition and allocation for Intel codecs */ 2845 static int alloc_intel_hdmi(struct hda_codec *codec) 2846 { 2847 int err; 2848 2849 /* requires i915 binding */ 2850 if (!codec->bus->core.audio_component) { 2851 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2852 /* set probe_id here to prevent generic fallback binding */ 2853 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2854 return -ENODEV; 2855 } 2856 2857 err = alloc_generic_hdmi(codec); 2858 if (err < 0) 2859 return err; 2860 /* no need to handle unsol events */ 2861 codec->patch_ops.unsol_event = NULL; 2862 return 0; 2863 } 2864 2865 /* parse and post-process for Intel codecs */ 2866 static int parse_intel_hdmi(struct hda_codec *codec) 2867 { 2868 int err, retries = 3; 2869 2870 do { 2871 err = hdmi_parse_codec(codec); 2872 } while (err < 0 && retries--); 2873 2874 if (err < 0) { 2875 generic_spec_free(codec); 2876 return err; 2877 } 2878 2879 generic_hdmi_init_per_pins(codec); 2880 register_i915_notifier(codec); 2881 return 0; 2882 } 2883 2884 /* Intel Haswell and onwards; audio component with eld notifier */ 2885 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 2886 const int *port_map, int port_num) 2887 { 2888 struct hdmi_spec *spec; 2889 int err; 2890 2891 err = alloc_intel_hdmi(codec); 2892 if (err < 0) 2893 return err; 2894 spec = codec->spec; 2895 codec->dp_mst = true; 2896 spec->dyn_pcm_assign = true; 2897 spec->vendor_nid = vendor_nid; 2898 spec->port_map = port_map; 2899 spec->port_num = port_num; 2900 spec->intel_hsw_fixup = true; 2901 2902 intel_haswell_enable_all_pins(codec, true); 2903 intel_haswell_fixup_enable_dp12(codec); 2904 2905 codec->display_power_control = 1; 2906 2907 codec->patch_ops.set_power_state = haswell_set_power_state; 2908 codec->depop_delay = 0; 2909 codec->auto_runtime_pm = 1; 2910 2911 spec->ops.setup_stream = i915_hsw_setup_stream; 2912 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2913 2914 return parse_intel_hdmi(codec); 2915 } 2916 2917 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2918 { 2919 return intel_hsw_common_init(codec, 0x08, NULL, 0); 2920 } 2921 2922 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2923 { 2924 return intel_hsw_common_init(codec, 0x0b, NULL, 0); 2925 } 2926 2927 static int patch_i915_icl_hdmi(struct hda_codec *codec) 2928 { 2929 /* 2930 * pin to port mapping table where the value indicate the pin number and 2931 * the index indicate the port number. 2932 */ 2933 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 2934 2935 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2936 } 2937 2938 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 2939 { 2940 /* 2941 * pin to port mapping table where the value indicate the pin number and 2942 * the index indicate the port number. 2943 */ 2944 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 2945 2946 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2947 } 2948 2949 /* Intel Baytrail and Braswell; with eld notifier */ 2950 static int patch_i915_byt_hdmi(struct hda_codec *codec) 2951 { 2952 struct hdmi_spec *spec; 2953 int err; 2954 2955 err = alloc_intel_hdmi(codec); 2956 if (err < 0) 2957 return err; 2958 spec = codec->spec; 2959 2960 /* For Valleyview/Cherryview, only the display codec is in the display 2961 * power well and can use link_power ops to request/release the power. 2962 */ 2963 codec->display_power_control = 1; 2964 2965 codec->depop_delay = 0; 2966 codec->auto_runtime_pm = 1; 2967 2968 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2969 2970 return parse_intel_hdmi(codec); 2971 } 2972 2973 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 2974 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 2975 { 2976 int err; 2977 2978 err = alloc_intel_hdmi(codec); 2979 if (err < 0) 2980 return err; 2981 return parse_intel_hdmi(codec); 2982 } 2983 2984 /* 2985 * Shared non-generic implementations 2986 */ 2987 2988 static int simple_playback_build_pcms(struct hda_codec *codec) 2989 { 2990 struct hdmi_spec *spec = codec->spec; 2991 struct hda_pcm *info; 2992 unsigned int chans; 2993 struct hda_pcm_stream *pstr; 2994 struct hdmi_spec_per_cvt *per_cvt; 2995 2996 per_cvt = get_cvt(spec, 0); 2997 chans = get_wcaps(codec, per_cvt->cvt_nid); 2998 chans = get_wcaps_channels(chans); 2999 3000 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 3001 if (!info) 3002 return -ENOMEM; 3003 spec->pcm_rec[0].pcm = info; 3004 info->pcm_type = HDA_PCM_TYPE_HDMI; 3005 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3006 *pstr = spec->pcm_playback; 3007 pstr->nid = per_cvt->cvt_nid; 3008 if (pstr->channels_max <= 2 && chans && chans <= 16) 3009 pstr->channels_max = chans; 3010 3011 return 0; 3012 } 3013 3014 /* unsolicited event for jack sensing */ 3015 static void simple_hdmi_unsol_event(struct hda_codec *codec, 3016 unsigned int res) 3017 { 3018 snd_hda_jack_set_dirty_all(codec); 3019 snd_hda_jack_report_sync(codec); 3020 } 3021 3022 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 3023 * as long as spec->pins[] is set correctly 3024 */ 3025 #define simple_hdmi_build_jack generic_hdmi_build_jack 3026 3027 static int simple_playback_build_controls(struct hda_codec *codec) 3028 { 3029 struct hdmi_spec *spec = codec->spec; 3030 struct hdmi_spec_per_cvt *per_cvt; 3031 int err; 3032 3033 per_cvt = get_cvt(spec, 0); 3034 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 3035 per_cvt->cvt_nid, 3036 HDA_PCM_TYPE_HDMI); 3037 if (err < 0) 3038 return err; 3039 return simple_hdmi_build_jack(codec, 0); 3040 } 3041 3042 static int simple_playback_init(struct hda_codec *codec) 3043 { 3044 struct hdmi_spec *spec = codec->spec; 3045 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 3046 hda_nid_t pin = per_pin->pin_nid; 3047 3048 snd_hda_codec_write(codec, pin, 0, 3049 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 3050 /* some codecs require to unmute the pin */ 3051 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 3052 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 3053 AMP_OUT_UNMUTE); 3054 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 3055 return 0; 3056 } 3057 3058 static void simple_playback_free(struct hda_codec *codec) 3059 { 3060 struct hdmi_spec *spec = codec->spec; 3061 3062 hdmi_array_free(spec); 3063 kfree(spec); 3064 } 3065 3066 /* 3067 * Nvidia specific implementations 3068 */ 3069 3070 #define Nv_VERB_SET_Channel_Allocation 0xF79 3071 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3072 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3073 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3074 3075 #define nvhdmi_master_con_nid_7x 0x04 3076 #define nvhdmi_master_pin_nid_7x 0x05 3077 3078 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3079 /*front, rear, clfe, rear_surr */ 3080 0x6, 0x8, 0xa, 0xc, 3081 }; 3082 3083 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3084 /* set audio protect on */ 3085 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3086 /* enable digital output on pin widget */ 3087 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3088 {} /* terminator */ 3089 }; 3090 3091 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3092 /* set audio protect on */ 3093 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3094 /* enable digital output on pin widget */ 3095 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3096 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3097 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3098 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3099 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3100 {} /* terminator */ 3101 }; 3102 3103 #ifdef LIMITED_RATE_FMT_SUPPORT 3104 /* support only the safe format and rate */ 3105 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3106 #define SUPPORTED_MAXBPS 16 3107 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3108 #else 3109 /* support all rates and formats */ 3110 #define SUPPORTED_RATES \ 3111 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3112 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3113 SNDRV_PCM_RATE_192000) 3114 #define SUPPORTED_MAXBPS 24 3115 #define SUPPORTED_FORMATS \ 3116 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3117 #endif 3118 3119 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3120 { 3121 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3122 return 0; 3123 } 3124 3125 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3126 { 3127 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3128 return 0; 3129 } 3130 3131 static const unsigned int channels_2_6_8[] = { 3132 2, 6, 8 3133 }; 3134 3135 static const unsigned int channels_2_8[] = { 3136 2, 8 3137 }; 3138 3139 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3140 .count = ARRAY_SIZE(channels_2_6_8), 3141 .list = channels_2_6_8, 3142 .mask = 0, 3143 }; 3144 3145 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3146 .count = ARRAY_SIZE(channels_2_8), 3147 .list = channels_2_8, 3148 .mask = 0, 3149 }; 3150 3151 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3152 struct hda_codec *codec, 3153 struct snd_pcm_substream *substream) 3154 { 3155 struct hdmi_spec *spec = codec->spec; 3156 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3157 3158 switch (codec->preset->vendor_id) { 3159 case 0x10de0002: 3160 case 0x10de0003: 3161 case 0x10de0005: 3162 case 0x10de0006: 3163 hw_constraints_channels = &hw_constraints_2_8_channels; 3164 break; 3165 case 0x10de0007: 3166 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3167 break; 3168 default: 3169 break; 3170 } 3171 3172 if (hw_constraints_channels != NULL) { 3173 snd_pcm_hw_constraint_list(substream->runtime, 0, 3174 SNDRV_PCM_HW_PARAM_CHANNELS, 3175 hw_constraints_channels); 3176 } else { 3177 snd_pcm_hw_constraint_step(substream->runtime, 0, 3178 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3179 } 3180 3181 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3182 } 3183 3184 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3185 struct hda_codec *codec, 3186 struct snd_pcm_substream *substream) 3187 { 3188 struct hdmi_spec *spec = codec->spec; 3189 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3190 } 3191 3192 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3193 struct hda_codec *codec, 3194 unsigned int stream_tag, 3195 unsigned int format, 3196 struct snd_pcm_substream *substream) 3197 { 3198 struct hdmi_spec *spec = codec->spec; 3199 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3200 stream_tag, format, substream); 3201 } 3202 3203 static const struct hda_pcm_stream simple_pcm_playback = { 3204 .substreams = 1, 3205 .channels_min = 2, 3206 .channels_max = 2, 3207 .ops = { 3208 .open = simple_playback_pcm_open, 3209 .close = simple_playback_pcm_close, 3210 .prepare = simple_playback_pcm_prepare 3211 }, 3212 }; 3213 3214 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3215 .build_controls = simple_playback_build_controls, 3216 .build_pcms = simple_playback_build_pcms, 3217 .init = simple_playback_init, 3218 .free = simple_playback_free, 3219 .unsol_event = simple_hdmi_unsol_event, 3220 }; 3221 3222 static int patch_simple_hdmi(struct hda_codec *codec, 3223 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3224 { 3225 struct hdmi_spec *spec; 3226 struct hdmi_spec_per_cvt *per_cvt; 3227 struct hdmi_spec_per_pin *per_pin; 3228 3229 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3230 if (!spec) 3231 return -ENOMEM; 3232 3233 spec->codec = codec; 3234 codec->spec = spec; 3235 hdmi_array_init(spec, 1); 3236 3237 spec->multiout.num_dacs = 0; /* no analog */ 3238 spec->multiout.max_channels = 2; 3239 spec->multiout.dig_out_nid = cvt_nid; 3240 spec->num_cvts = 1; 3241 spec->num_pins = 1; 3242 per_pin = snd_array_new(&spec->pins); 3243 per_cvt = snd_array_new(&spec->cvts); 3244 if (!per_pin || !per_cvt) { 3245 simple_playback_free(codec); 3246 return -ENOMEM; 3247 } 3248 per_cvt->cvt_nid = cvt_nid; 3249 per_pin->pin_nid = pin_nid; 3250 spec->pcm_playback = simple_pcm_playback; 3251 3252 codec->patch_ops = simple_hdmi_patch_ops; 3253 3254 return 0; 3255 } 3256 3257 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3258 int channels) 3259 { 3260 unsigned int chanmask; 3261 int chan = channels ? (channels - 1) : 1; 3262 3263 switch (channels) { 3264 default: 3265 case 0: 3266 case 2: 3267 chanmask = 0x00; 3268 break; 3269 case 4: 3270 chanmask = 0x08; 3271 break; 3272 case 6: 3273 chanmask = 0x0b; 3274 break; 3275 case 8: 3276 chanmask = 0x13; 3277 break; 3278 } 3279 3280 /* Set the audio infoframe channel allocation and checksum fields. The 3281 * channel count is computed implicitly by the hardware. */ 3282 snd_hda_codec_write(codec, 0x1, 0, 3283 Nv_VERB_SET_Channel_Allocation, chanmask); 3284 3285 snd_hda_codec_write(codec, 0x1, 0, 3286 Nv_VERB_SET_Info_Frame_Checksum, 3287 (0x71 - chan - chanmask)); 3288 } 3289 3290 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3291 struct hda_codec *codec, 3292 struct snd_pcm_substream *substream) 3293 { 3294 struct hdmi_spec *spec = codec->spec; 3295 int i; 3296 3297 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3298 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3299 for (i = 0; i < 4; i++) { 3300 /* set the stream id */ 3301 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3302 AC_VERB_SET_CHANNEL_STREAMID, 0); 3303 /* set the stream format */ 3304 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3305 AC_VERB_SET_STREAM_FORMAT, 0); 3306 } 3307 3308 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3309 * streams are disabled. */ 3310 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3311 3312 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3313 } 3314 3315 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3316 struct hda_codec *codec, 3317 unsigned int stream_tag, 3318 unsigned int format, 3319 struct snd_pcm_substream *substream) 3320 { 3321 int chs; 3322 unsigned int dataDCC2, channel_id; 3323 int i; 3324 struct hdmi_spec *spec = codec->spec; 3325 struct hda_spdif_out *spdif; 3326 struct hdmi_spec_per_cvt *per_cvt; 3327 3328 mutex_lock(&codec->spdif_mutex); 3329 per_cvt = get_cvt(spec, 0); 3330 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3331 3332 chs = substream->runtime->channels; 3333 3334 dataDCC2 = 0x2; 3335 3336 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3337 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3338 snd_hda_codec_write(codec, 3339 nvhdmi_master_con_nid_7x, 3340 0, 3341 AC_VERB_SET_DIGI_CONVERT_1, 3342 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3343 3344 /* set the stream id */ 3345 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3346 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3347 3348 /* set the stream format */ 3349 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3350 AC_VERB_SET_STREAM_FORMAT, format); 3351 3352 /* turn on again (if needed) */ 3353 /* enable and set the channel status audio/data flag */ 3354 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3355 snd_hda_codec_write(codec, 3356 nvhdmi_master_con_nid_7x, 3357 0, 3358 AC_VERB_SET_DIGI_CONVERT_1, 3359 spdif->ctls & 0xff); 3360 snd_hda_codec_write(codec, 3361 nvhdmi_master_con_nid_7x, 3362 0, 3363 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3364 } 3365 3366 for (i = 0; i < 4; i++) { 3367 if (chs == 2) 3368 channel_id = 0; 3369 else 3370 channel_id = i * 2; 3371 3372 /* turn off SPDIF once; 3373 *otherwise the IEC958 bits won't be updated 3374 */ 3375 if (codec->spdif_status_reset && 3376 (spdif->ctls & AC_DIG1_ENABLE)) 3377 snd_hda_codec_write(codec, 3378 nvhdmi_con_nids_7x[i], 3379 0, 3380 AC_VERB_SET_DIGI_CONVERT_1, 3381 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3382 /* set the stream id */ 3383 snd_hda_codec_write(codec, 3384 nvhdmi_con_nids_7x[i], 3385 0, 3386 AC_VERB_SET_CHANNEL_STREAMID, 3387 (stream_tag << 4) | channel_id); 3388 /* set the stream format */ 3389 snd_hda_codec_write(codec, 3390 nvhdmi_con_nids_7x[i], 3391 0, 3392 AC_VERB_SET_STREAM_FORMAT, 3393 format); 3394 /* turn on again (if needed) */ 3395 /* enable and set the channel status audio/data flag */ 3396 if (codec->spdif_status_reset && 3397 (spdif->ctls & AC_DIG1_ENABLE)) { 3398 snd_hda_codec_write(codec, 3399 nvhdmi_con_nids_7x[i], 3400 0, 3401 AC_VERB_SET_DIGI_CONVERT_1, 3402 spdif->ctls & 0xff); 3403 snd_hda_codec_write(codec, 3404 nvhdmi_con_nids_7x[i], 3405 0, 3406 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3407 } 3408 } 3409 3410 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3411 3412 mutex_unlock(&codec->spdif_mutex); 3413 return 0; 3414 } 3415 3416 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3417 .substreams = 1, 3418 .channels_min = 2, 3419 .channels_max = 8, 3420 .nid = nvhdmi_master_con_nid_7x, 3421 .rates = SUPPORTED_RATES, 3422 .maxbps = SUPPORTED_MAXBPS, 3423 .formats = SUPPORTED_FORMATS, 3424 .ops = { 3425 .open = simple_playback_pcm_open, 3426 .close = nvhdmi_8ch_7x_pcm_close, 3427 .prepare = nvhdmi_8ch_7x_pcm_prepare 3428 }, 3429 }; 3430 3431 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3432 { 3433 struct hdmi_spec *spec; 3434 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3435 nvhdmi_master_pin_nid_7x); 3436 if (err < 0) 3437 return err; 3438 3439 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3440 /* override the PCM rates, etc, as the codec doesn't give full list */ 3441 spec = codec->spec; 3442 spec->pcm_playback.rates = SUPPORTED_RATES; 3443 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3444 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3445 return 0; 3446 } 3447 3448 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3449 { 3450 struct hdmi_spec *spec = codec->spec; 3451 int err = simple_playback_build_pcms(codec); 3452 if (!err) { 3453 struct hda_pcm *info = get_pcm_rec(spec, 0); 3454 info->own_chmap = true; 3455 } 3456 return err; 3457 } 3458 3459 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3460 { 3461 struct hdmi_spec *spec = codec->spec; 3462 struct hda_pcm *info; 3463 struct snd_pcm_chmap *chmap; 3464 int err; 3465 3466 err = simple_playback_build_controls(codec); 3467 if (err < 0) 3468 return err; 3469 3470 /* add channel maps */ 3471 info = get_pcm_rec(spec, 0); 3472 err = snd_pcm_add_chmap_ctls(info->pcm, 3473 SNDRV_PCM_STREAM_PLAYBACK, 3474 snd_pcm_alt_chmaps, 8, 0, &chmap); 3475 if (err < 0) 3476 return err; 3477 switch (codec->preset->vendor_id) { 3478 case 0x10de0002: 3479 case 0x10de0003: 3480 case 0x10de0005: 3481 case 0x10de0006: 3482 chmap->channel_mask = (1U << 2) | (1U << 8); 3483 break; 3484 case 0x10de0007: 3485 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3486 } 3487 return 0; 3488 } 3489 3490 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3491 { 3492 struct hdmi_spec *spec; 3493 int err = patch_nvhdmi_2ch(codec); 3494 if (err < 0) 3495 return err; 3496 spec = codec->spec; 3497 spec->multiout.max_channels = 8; 3498 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3499 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3500 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3501 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3502 3503 /* Initialize the audio infoframe channel mask and checksum to something 3504 * valid */ 3505 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3506 3507 return 0; 3508 } 3509 3510 /* 3511 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3512 * - 0x10de0015 3513 * - 0x10de0040 3514 */ 3515 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3516 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3517 { 3518 if (cap->ca_index == 0x00 && channels == 2) 3519 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3520 3521 /* If the speaker allocation matches the channel count, it is OK. */ 3522 if (cap->channels != channels) 3523 return -1; 3524 3525 /* all channels are remappable freely */ 3526 return SNDRV_CTL_TLVT_CHMAP_VAR; 3527 } 3528 3529 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3530 int ca, int chs, unsigned char *map) 3531 { 3532 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3533 return -EINVAL; 3534 3535 return 0; 3536 } 3537 3538 /* map from pin NID to port; port is 0-based */ 3539 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3540 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3541 { 3542 return pin_nid - 4; 3543 } 3544 3545 /* reverse-map from port to pin NID: see above */ 3546 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3547 { 3548 return port + 4; 3549 } 3550 3551 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3552 .pin2port = nvhdmi_pin2port, 3553 .pin_eld_notify = generic_acomp_pin_eld_notify, 3554 .master_bind = generic_acomp_master_bind, 3555 .master_unbind = generic_acomp_master_unbind, 3556 }; 3557 3558 static int patch_nvhdmi(struct hda_codec *codec) 3559 { 3560 struct hdmi_spec *spec; 3561 int err; 3562 3563 err = alloc_generic_hdmi(codec); 3564 if (err < 0) 3565 return err; 3566 codec->dp_mst = true; 3567 3568 spec = codec->spec; 3569 spec->dyn_pcm_assign = true; 3570 3571 err = hdmi_parse_codec(codec); 3572 if (err < 0) { 3573 generic_spec_free(codec); 3574 return err; 3575 } 3576 3577 generic_hdmi_init_per_pins(codec); 3578 3579 spec->dyn_pin_out = true; 3580 3581 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3582 nvhdmi_chmap_cea_alloc_validate_get_type; 3583 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3584 3585 codec->link_down_at_suspend = 1; 3586 3587 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3588 3589 return 0; 3590 } 3591 3592 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3593 { 3594 struct hdmi_spec *spec; 3595 int err; 3596 3597 err = patch_generic_hdmi(codec); 3598 if (err) 3599 return err; 3600 3601 spec = codec->spec; 3602 spec->dyn_pin_out = true; 3603 3604 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3605 nvhdmi_chmap_cea_alloc_validate_get_type; 3606 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3607 3608 codec->link_down_at_suspend = 1; 3609 3610 return 0; 3611 } 3612 3613 /* 3614 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3615 * accessed using vendor-defined verbs. These registers can be used for 3616 * interoperability between the HDA and HDMI drivers. 3617 */ 3618 3619 /* Audio Function Group node */ 3620 #define NVIDIA_AFG_NID 0x01 3621 3622 /* 3623 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3624 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3625 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3626 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3627 * additional bit (at position 30) to signal the validity of the format. 3628 * 3629 * | 31 | 30 | 29 16 | 15 0 | 3630 * +---------+-------+--------+--------+ 3631 * | TRIGGER | VALID | UNUSED | FORMAT | 3632 * +-----------------------------------| 3633 * 3634 * Note that for the trigger bit to take effect it needs to change value 3635 * (i.e. it needs to be toggled). 3636 */ 3637 #define NVIDIA_GET_SCRATCH0 0xfa6 3638 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3639 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3640 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3641 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3642 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3643 #define NVIDIA_SCRATCH_VALID (1 << 6) 3644 3645 #define NVIDIA_GET_SCRATCH1 0xfab 3646 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3647 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3648 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3649 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3650 3651 /* 3652 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3653 * the format is invalidated so that the HDMI codec can be disabled. 3654 */ 3655 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3656 { 3657 unsigned int value; 3658 3659 /* bits [31:30] contain the trigger and valid bits */ 3660 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3661 NVIDIA_GET_SCRATCH0, 0); 3662 value = (value >> 24) & 0xff; 3663 3664 /* bits [15:0] are used to store the HDA format */ 3665 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3666 NVIDIA_SET_SCRATCH0_BYTE0, 3667 (format >> 0) & 0xff); 3668 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3669 NVIDIA_SET_SCRATCH0_BYTE1, 3670 (format >> 8) & 0xff); 3671 3672 /* bits [16:24] are unused */ 3673 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3674 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3675 3676 /* 3677 * Bit 30 signals that the data is valid and hence that HDMI audio can 3678 * be enabled. 3679 */ 3680 if (format == 0) 3681 value &= ~NVIDIA_SCRATCH_VALID; 3682 else 3683 value |= NVIDIA_SCRATCH_VALID; 3684 3685 /* 3686 * Whenever the trigger bit is toggled, an interrupt is raised in the 3687 * HDMI codec. The HDMI driver will use that as trigger to update its 3688 * configuration. 3689 */ 3690 value ^= NVIDIA_SCRATCH_TRIGGER; 3691 3692 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3693 NVIDIA_SET_SCRATCH0_BYTE3, value); 3694 } 3695 3696 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3697 struct hda_codec *codec, 3698 unsigned int stream_tag, 3699 unsigned int format, 3700 struct snd_pcm_substream *substream) 3701 { 3702 int err; 3703 3704 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3705 format, substream); 3706 if (err < 0) 3707 return err; 3708 3709 /* notify the HDMI codec of the format change */ 3710 tegra_hdmi_set_format(codec, format); 3711 3712 return 0; 3713 } 3714 3715 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3716 struct hda_codec *codec, 3717 struct snd_pcm_substream *substream) 3718 { 3719 /* invalidate the format in the HDMI codec */ 3720 tegra_hdmi_set_format(codec, 0); 3721 3722 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3723 } 3724 3725 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3726 { 3727 struct hdmi_spec *spec = codec->spec; 3728 unsigned int i; 3729 3730 for (i = 0; i < spec->num_pins; i++) { 3731 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3732 3733 if (pcm->pcm_type == type) 3734 return pcm; 3735 } 3736 3737 return NULL; 3738 } 3739 3740 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3741 { 3742 struct hda_pcm_stream *stream; 3743 struct hda_pcm *pcm; 3744 int err; 3745 3746 err = generic_hdmi_build_pcms(codec); 3747 if (err < 0) 3748 return err; 3749 3750 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3751 if (!pcm) 3752 return -ENODEV; 3753 3754 /* 3755 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3756 * codec about format changes. 3757 */ 3758 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3759 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3760 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3761 3762 return 0; 3763 } 3764 3765 static int patch_tegra_hdmi(struct hda_codec *codec) 3766 { 3767 int err; 3768 3769 err = patch_generic_hdmi(codec); 3770 if (err) 3771 return err; 3772 3773 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3774 3775 return 0; 3776 } 3777 3778 /* 3779 * ATI/AMD-specific implementations 3780 */ 3781 3782 #define is_amdhdmi_rev3_or_later(codec) \ 3783 ((codec)->core.vendor_id == 0x1002aa01 && \ 3784 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3785 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3786 3787 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3788 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3789 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3790 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3791 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3792 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3793 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3794 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3795 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3796 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3797 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3798 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3799 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3800 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3801 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3802 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3803 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3804 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3805 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3806 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3807 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3808 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3809 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3810 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3811 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3812 3813 /* AMD specific HDA cvt verbs */ 3814 #define ATI_VERB_SET_RAMP_RATE 0x770 3815 #define ATI_VERB_GET_RAMP_RATE 0xf70 3816 3817 #define ATI_OUT_ENABLE 0x1 3818 3819 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3820 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3821 3822 #define ATI_HBR_CAPABLE 0x01 3823 #define ATI_HBR_ENABLE 0x10 3824 3825 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3826 int dev_id, unsigned char *buf, int *eld_size) 3827 { 3828 WARN_ON(dev_id != 0); 3829 /* call hda_eld.c ATI/AMD-specific function */ 3830 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3831 is_amdhdmi_rev3_or_later(codec)); 3832 } 3833 3834 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 3835 hda_nid_t pin_nid, int dev_id, int ca, 3836 int active_channels, int conn_type) 3837 { 3838 WARN_ON(dev_id != 0); 3839 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3840 } 3841 3842 static int atihdmi_paired_swap_fc_lfe(int pos) 3843 { 3844 /* 3845 * ATI/AMD have automatic FC/LFE swap built-in 3846 * when in pairwise mapping mode. 3847 */ 3848 3849 switch (pos) { 3850 /* see channel_allocations[].speakers[] */ 3851 case 2: return 3; 3852 case 3: return 2; 3853 default: break; 3854 } 3855 3856 return pos; 3857 } 3858 3859 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3860 int ca, int chs, unsigned char *map) 3861 { 3862 struct hdac_cea_channel_speaker_allocation *cap; 3863 int i, j; 3864 3865 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3866 3867 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3868 for (i = 0; i < chs; ++i) { 3869 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3870 bool ok = false; 3871 bool companion_ok = false; 3872 3873 if (!mask) 3874 continue; 3875 3876 for (j = 0 + i % 2; j < 8; j += 2) { 3877 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3878 if (cap->speakers[chan_idx] == mask) { 3879 /* channel is in a supported position */ 3880 ok = true; 3881 3882 if (i % 2 == 0 && i + 1 < chs) { 3883 /* even channel, check the odd companion */ 3884 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3885 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3886 int comp_mask_act = cap->speakers[comp_chan_idx]; 3887 3888 if (comp_mask_req == comp_mask_act) 3889 companion_ok = true; 3890 else 3891 return -EINVAL; 3892 } 3893 break; 3894 } 3895 } 3896 3897 if (!ok) 3898 return -EINVAL; 3899 3900 if (companion_ok) 3901 i++; /* companion channel already checked */ 3902 } 3903 3904 return 0; 3905 } 3906 3907 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 3908 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 3909 { 3910 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3911 int verb; 3912 int ati_channel_setup = 0; 3913 3914 if (hdmi_slot > 7) 3915 return -EINVAL; 3916 3917 if (!has_amd_full_remap_support(codec)) { 3918 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3919 3920 /* In case this is an odd slot but without stream channel, do not 3921 * disable the slot since the corresponding even slot could have a 3922 * channel. In case neither have a channel, the slot pair will be 3923 * disabled when this function is called for the even slot. */ 3924 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3925 return 0; 3926 3927 hdmi_slot -= hdmi_slot % 2; 3928 3929 if (stream_channel != 0xf) 3930 stream_channel -= stream_channel % 2; 3931 } 3932 3933 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3934 3935 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3936 3937 if (stream_channel != 0xf) 3938 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3939 3940 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3941 } 3942 3943 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 3944 hda_nid_t pin_nid, int asp_slot) 3945 { 3946 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3947 bool was_odd = false; 3948 int ati_asp_slot = asp_slot; 3949 int verb; 3950 int ati_channel_setup; 3951 3952 if (asp_slot > 7) 3953 return -EINVAL; 3954 3955 if (!has_amd_full_remap_support(codec)) { 3956 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3957 if (ati_asp_slot % 2 != 0) { 3958 ati_asp_slot -= 1; 3959 was_odd = true; 3960 } 3961 } 3962 3963 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3964 3965 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3966 3967 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3968 return 0xf; 3969 3970 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3971 } 3972 3973 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 3974 struct hdac_chmap *chmap, 3975 struct hdac_cea_channel_speaker_allocation *cap, 3976 int channels) 3977 { 3978 int c; 3979 3980 /* 3981 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3982 * we need to take that into account (a single channel may take 2 3983 * channel slots if we need to carry a silent channel next to it). 3984 * On Rev3+ AMD codecs this function is not used. 3985 */ 3986 int chanpairs = 0; 3987 3988 /* We only produce even-numbered channel count TLVs */ 3989 if ((channels % 2) != 0) 3990 return -1; 3991 3992 for (c = 0; c < 7; c += 2) { 3993 if (cap->speakers[c] || cap->speakers[c+1]) 3994 chanpairs++; 3995 } 3996 3997 if (chanpairs * 2 != channels) 3998 return -1; 3999 4000 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 4001 } 4002 4003 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 4004 struct hdac_cea_channel_speaker_allocation *cap, 4005 unsigned int *chmap, int channels) 4006 { 4007 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 4008 int count = 0; 4009 int c; 4010 4011 for (c = 7; c >= 0; c--) { 4012 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 4013 int spk = cap->speakers[chan]; 4014 if (!spk) { 4015 /* add N/A channel if the companion channel is occupied */ 4016 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 4017 chmap[count++] = SNDRV_CHMAP_NA; 4018 4019 continue; 4020 } 4021 4022 chmap[count++] = snd_hdac_spk_to_chmap(spk); 4023 } 4024 4025 WARN_ON(count != channels); 4026 } 4027 4028 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 4029 int dev_id, bool hbr) 4030 { 4031 int hbr_ctl, hbr_ctl_new; 4032 4033 WARN_ON(dev_id != 0); 4034 4035 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 4036 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 4037 if (hbr) 4038 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 4039 else 4040 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 4041 4042 codec_dbg(codec, 4043 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 4044 pin_nid, 4045 hbr_ctl == hbr_ctl_new ? "" : "new-", 4046 hbr_ctl_new); 4047 4048 if (hbr_ctl != hbr_ctl_new) 4049 snd_hda_codec_write(codec, pin_nid, 0, 4050 ATI_VERB_SET_HBR_CONTROL, 4051 hbr_ctl_new); 4052 4053 } else if (hbr) 4054 return -EINVAL; 4055 4056 return 0; 4057 } 4058 4059 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4060 hda_nid_t pin_nid, int dev_id, 4061 u32 stream_tag, int format) 4062 { 4063 if (is_amdhdmi_rev3_or_later(codec)) { 4064 int ramp_rate = 180; /* default as per AMD spec */ 4065 /* disable ramp-up/down for non-pcm as per AMD spec */ 4066 if (format & AC_FMT_TYPE_NON_PCM) 4067 ramp_rate = 0; 4068 4069 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4070 } 4071 4072 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4073 stream_tag, format); 4074 } 4075 4076 4077 static int atihdmi_init(struct hda_codec *codec) 4078 { 4079 struct hdmi_spec *spec = codec->spec; 4080 int pin_idx, err; 4081 4082 err = generic_hdmi_init(codec); 4083 4084 if (err) 4085 return err; 4086 4087 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4088 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4089 4090 /* make sure downmix information in infoframe is zero */ 4091 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4092 4093 /* enable channel-wise remap mode if supported */ 4094 if (has_amd_full_remap_support(codec)) 4095 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4096 ATI_VERB_SET_MULTICHANNEL_MODE, 4097 ATI_MULTICHANNEL_MODE_SINGLE); 4098 } 4099 codec->auto_runtime_pm = 1; 4100 4101 return 0; 4102 } 4103 4104 /* map from pin NID to port; port is 0-based */ 4105 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4106 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4107 { 4108 return pin_nid / 2 - 1; 4109 } 4110 4111 /* reverse-map from port to pin NID: see above */ 4112 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4113 { 4114 return port * 2 + 3; 4115 } 4116 4117 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4118 .pin2port = atihdmi_pin2port, 4119 .pin_eld_notify = generic_acomp_pin_eld_notify, 4120 .master_bind = generic_acomp_master_bind, 4121 .master_unbind = generic_acomp_master_unbind, 4122 }; 4123 4124 static int patch_atihdmi(struct hda_codec *codec) 4125 { 4126 struct hdmi_spec *spec; 4127 struct hdmi_spec_per_cvt *per_cvt; 4128 int err, cvt_idx; 4129 4130 err = patch_generic_hdmi(codec); 4131 4132 if (err) 4133 return err; 4134 4135 codec->patch_ops.init = atihdmi_init; 4136 4137 spec = codec->spec; 4138 4139 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4140 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4141 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4142 spec->ops.setup_stream = atihdmi_setup_stream; 4143 4144 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4145 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4146 4147 if (!has_amd_full_remap_support(codec)) { 4148 /* override to ATI/AMD-specific versions with pairwise mapping */ 4149 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4150 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4151 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4152 atihdmi_paired_cea_alloc_to_tlv_chmap; 4153 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4154 } 4155 4156 /* ATI/AMD converters do not advertise all of their capabilities */ 4157 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4158 per_cvt = get_cvt(spec, cvt_idx); 4159 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4160 per_cvt->rates |= SUPPORTED_RATES; 4161 per_cvt->formats |= SUPPORTED_FORMATS; 4162 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4163 } 4164 4165 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4166 4167 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4168 * the link-down as is. Tell the core to allow it. 4169 */ 4170 codec->link_down_at_suspend = 1; 4171 4172 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4173 4174 return 0; 4175 } 4176 4177 /* VIA HDMI Implementation */ 4178 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4179 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4180 4181 static int patch_via_hdmi(struct hda_codec *codec) 4182 { 4183 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4184 } 4185 4186 /* 4187 * patch entries 4188 */ 4189 static const struct hda_device_id snd_hda_id_hdmi[] = { 4190 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4191 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4192 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4193 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4194 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4195 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4196 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4197 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4198 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4199 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4200 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4201 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4202 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4203 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4204 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4205 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4206 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4207 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4208 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4209 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4210 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4211 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4212 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4213 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4214 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4215 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4216 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4217 /* 17 is known to be absent */ 4218 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4219 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4220 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4221 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4222 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4223 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4224 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4225 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4226 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4227 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4228 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4229 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4230 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4231 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4232 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4233 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4234 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4235 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4236 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4237 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4238 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4239 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4240 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4241 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4242 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4243 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4244 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4245 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4246 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4247 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4248 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4249 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4250 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4251 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4252 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4253 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4254 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4255 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4256 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4257 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4258 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4259 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4260 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4261 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4262 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4263 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4264 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4265 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4266 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4267 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4268 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4269 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4270 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4271 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4272 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4273 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4274 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4275 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4276 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4277 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4278 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4279 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4280 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4281 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4282 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4283 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4284 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4285 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4286 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4287 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4288 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4289 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4290 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4291 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), 4292 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4293 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4294 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4295 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4296 /* special ID for generic HDMI */ 4297 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4298 {} /* terminator */ 4299 }; 4300 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4301 4302 MODULE_LICENSE("GPL"); 4303 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4304 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4305 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4306 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4307 4308 static struct hda_codec_driver hdmi_driver = { 4309 .id = snd_hda_id_hdmi, 4310 }; 4311 4312 module_hda_codec_driver(hdmi_driver); 4313