1 /* 2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "gf100.h" 24 #include "ctxgf100.h" 25 26 #include <subdev/acr.h> 27 28 #include <nvif/class.h> 29 30 #include <nvfw/flcn.h> 31 32 static const struct nvkm_acr_lsf_func 33 gp10b_gr_gpccs_acr = { 34 .flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD, 35 .bld_size = sizeof(struct flcn_bl_dmem_desc), 36 .bld_write = gm20b_gr_acr_bld_write, 37 .bld_patch = gm20b_gr_acr_bld_patch, 38 }; 39 40 static const struct gf100_gr_func 41 gp10b_gr = { 42 .oneinit_tiles = gm200_gr_oneinit_tiles, 43 .oneinit_sm_id = gm200_gr_oneinit_sm_id, 44 .init = gf100_gr_init, 45 .init_gpc_mmu = gm200_gr_init_gpc_mmu, 46 .init_vsc_stream_master = gk104_gr_init_vsc_stream_master, 47 .init_zcull = gf117_gr_init_zcull, 48 .init_num_active_ltcs = gf100_gr_init_num_active_ltcs, 49 .init_rop_active_fbps = gp100_gr_init_rop_active_fbps, 50 .init_fecs_exceptions = gp100_gr_init_fecs_exceptions, 51 .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2, 52 .init_sked_hww_esr = gk104_gr_init_sked_hww_esr, 53 .init_419cc0 = gf100_gr_init_419cc0, 54 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, 55 .init_tex_hww_esr = gf100_gr_init_tex_hww_esr, 56 .init_504430 = gm107_gr_init_504430, 57 .init_shader_exceptions = gp100_gr_init_shader_exceptions, 58 .trap_mp = gf100_gr_trap_mp, 59 .rops = gm200_gr_rops, 60 .gpc_nr = 1, 61 .tpc_nr = 2, 62 .ppc_nr = 1, 63 .grctx = &gp100_grctx, 64 .zbc = &gp100_gr_zbc, 65 .sclass = { 66 { -1, -1, FERMI_TWOD_A }, 67 { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, 68 { -1, -1, PASCAL_A, &gf100_fermi }, 69 { -1, -1, PASCAL_COMPUTE_A }, 70 {} 71 } 72 }; 73 74 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) 75 MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_bl.bin"); 76 MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_inst.bin"); 77 MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_data.bin"); 78 MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_sig.bin"); 79 MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_bl.bin"); 80 MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_inst.bin"); 81 MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_data.bin"); 82 MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_sig.bin"); 83 MODULE_FIRMWARE("nvidia/gp10b/gr/sw_ctx.bin"); 84 MODULE_FIRMWARE("nvidia/gp10b/gr/sw_nonctx.bin"); 85 MODULE_FIRMWARE("nvidia/gp10b/gr/sw_bundle_init.bin"); 86 MODULE_FIRMWARE("nvidia/gp10b/gr/sw_method_init.bin"); 87 #endif 88 89 static const struct gf100_gr_fwif 90 gp10b_gr_fwif[] = { 91 { 0, gm200_gr_load, &gp10b_gr, &gm20b_gr_fecs_acr, &gp10b_gr_gpccs_acr }, 92 {} 93 }; 94 95 int 96 gp10b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) 97 { 98 return gf100_gr_new_(gp10b_gr_fwif, device, index, pgr); 99 } 100