1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Motorola/Freescale IMX serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Author: Sascha Hauer <sascha@saschahauer.de> 8 * Copyright (C) 2004 Pengutronix 9 */ 10 11 #include <linux/module.h> 12 #include <linux/ioport.h> 13 #include <linux/init.h> 14 #include <linux/console.h> 15 #include <linux/sysrq.h> 16 #include <linux/platform_device.h> 17 #include <linux/tty.h> 18 #include <linux/tty_flip.h> 19 #include <linux/serial_core.h> 20 #include <linux/serial.h> 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/rational.h> 25 #include <linux/slab.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/io.h> 29 #include <linux/dma-mapping.h> 30 31 #include <asm/irq.h> 32 #include <linux/platform_data/serial-imx.h> 33 #include <linux/platform_data/dma-imx.h> 34 35 #include "serial_mctrl_gpio.h" 36 37 /* Register definitions */ 38 #define URXD0 0x0 /* Receiver Register */ 39 #define URTX0 0x40 /* Transmitter Register */ 40 #define UCR1 0x80 /* Control Register 1 */ 41 #define UCR2 0x84 /* Control Register 2 */ 42 #define UCR3 0x88 /* Control Register 3 */ 43 #define UCR4 0x8c /* Control Register 4 */ 44 #define UFCR 0x90 /* FIFO Control Register */ 45 #define USR1 0x94 /* Status Register 1 */ 46 #define USR2 0x98 /* Status Register 2 */ 47 #define UESC 0x9c /* Escape Character Register */ 48 #define UTIM 0xa0 /* Escape Timer Register */ 49 #define UBIR 0xa4 /* BRM Incremental Register */ 50 #define UBMR 0xa8 /* BRM Modulator Register */ 51 #define UBRC 0xac /* Baud Rate Count Register */ 52 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 53 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 54 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 55 56 /* UART Control Register Bit Fields.*/ 57 #define URXD_DUMMY_READ (1<<16) 58 #define URXD_CHARRDY (1<<15) 59 #define URXD_ERR (1<<14) 60 #define URXD_OVRRUN (1<<13) 61 #define URXD_FRMERR (1<<12) 62 #define URXD_BRK (1<<11) 63 #define URXD_PRERR (1<<10) 64 #define URXD_RX_DATA (0xFF<<0) 65 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 66 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 67 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 68 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 69 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 70 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 71 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 72 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 73 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 74 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 75 #define UCR1_SNDBRK (1<<4) /* Send break */ 76 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 77 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 78 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 79 #define UCR1_DOZE (1<<1) /* Doze */ 80 #define UCR1_UARTEN (1<<0) /* UART enabled */ 81 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 82 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 83 #define UCR2_CTSC (1<<13) /* CTS pin control */ 84 #define UCR2_CTS (1<<12) /* Clear to send */ 85 #define UCR2_ESCEN (1<<11) /* Escape enable */ 86 #define UCR2_PREN (1<<8) /* Parity enable */ 87 #define UCR2_PROE (1<<7) /* Parity odd/even */ 88 #define UCR2_STPB (1<<6) /* Stop */ 89 #define UCR2_WS (1<<5) /* Word size */ 90 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 91 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 92 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 93 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 94 #define UCR2_SRST (1<<0) /* SW reset */ 95 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 96 #define UCR3_PARERREN (1<<12) /* Parity enable */ 97 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 98 #define UCR3_DSR (1<<10) /* Data set ready */ 99 #define UCR3_DCD (1<<9) /* Data carrier detect */ 100 #define UCR3_RI (1<<8) /* Ring indicator */ 101 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 102 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 103 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 104 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 105 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 106 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 107 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 108 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 109 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 110 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 111 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 112 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 113 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 114 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 115 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 116 #define UCR4_IRSC (1<<5) /* IR special case */ 117 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 118 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 119 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 120 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 121 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 122 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 123 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 124 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 125 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 126 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 127 #define USR1_RTSS (1<<14) /* RTS pin status */ 128 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 129 #define USR1_RTSD (1<<12) /* RTS delta */ 130 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 131 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 132 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 133 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 134 #define USR1_DTRD (1<<7) /* DTR Delta */ 135 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 136 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 137 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 138 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 139 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 140 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 141 #define USR2_IDLE (1<<12) /* Idle condition */ 142 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 143 #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 144 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 145 #define USR2_WAKE (1<<7) /* Wake */ 146 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 147 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 148 #define USR2_TXDC (1<<3) /* Transmitter complete */ 149 #define USR2_BRCD (1<<2) /* Break condition */ 150 #define USR2_ORE (1<<1) /* Overrun error */ 151 #define USR2_RDR (1<<0) /* Recv data ready */ 152 #define UTS_FRCPERR (1<<13) /* Force parity error */ 153 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 154 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 155 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 156 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 157 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 158 #define UTS_SOFTRST (1<<0) /* Software reset */ 159 160 /* We've been assigned a range on the "Low-density serial ports" major */ 161 #define SERIAL_IMX_MAJOR 207 162 #define MINOR_START 16 163 #define DEV_NAME "ttymxc" 164 165 /* 166 * This determines how often we check the modem status signals 167 * for any change. They generally aren't connected to an IRQ 168 * so we have to poll them. We also check immediately before 169 * filling the TX fifo incase CTS has been dropped. 170 */ 171 #define MCTRL_TIMEOUT (250*HZ/1000) 172 173 #define DRIVER_NAME "IMX-uart" 174 175 #define UART_NR 8 176 177 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 178 enum imx_uart_type { 179 IMX1_UART, 180 IMX21_UART, 181 IMX53_UART, 182 IMX6Q_UART, 183 }; 184 185 /* device type dependent stuff */ 186 struct imx_uart_data { 187 unsigned uts_reg; 188 enum imx_uart_type devtype; 189 }; 190 191 struct imx_port { 192 struct uart_port port; 193 struct timer_list timer; 194 unsigned int old_status; 195 unsigned int have_rtscts:1; 196 unsigned int have_rtsgpio:1; 197 unsigned int dte_mode:1; 198 struct clk *clk_ipg; 199 struct clk *clk_per; 200 const struct imx_uart_data *devdata; 201 202 struct mctrl_gpios *gpios; 203 204 /* shadow registers */ 205 unsigned int ucr1; 206 unsigned int ucr2; 207 unsigned int ucr3; 208 unsigned int ucr4; 209 unsigned int ufcr; 210 211 /* DMA fields */ 212 unsigned int dma_is_enabled:1; 213 unsigned int dma_is_rxing:1; 214 unsigned int dma_is_txing:1; 215 struct dma_chan *dma_chan_rx, *dma_chan_tx; 216 struct scatterlist rx_sgl, tx_sgl[2]; 217 void *rx_buf; 218 struct circ_buf rx_ring; 219 unsigned int rx_periods; 220 dma_cookie_t rx_cookie; 221 unsigned int tx_bytes; 222 unsigned int dma_tx_nents; 223 unsigned int saved_reg[10]; 224 bool context_saved; 225 }; 226 227 struct imx_port_ucrs { 228 unsigned int ucr1; 229 unsigned int ucr2; 230 unsigned int ucr3; 231 }; 232 233 static struct imx_uart_data imx_uart_devdata[] = { 234 [IMX1_UART] = { 235 .uts_reg = IMX1_UTS, 236 .devtype = IMX1_UART, 237 }, 238 [IMX21_UART] = { 239 .uts_reg = IMX21_UTS, 240 .devtype = IMX21_UART, 241 }, 242 [IMX53_UART] = { 243 .uts_reg = IMX21_UTS, 244 .devtype = IMX53_UART, 245 }, 246 [IMX6Q_UART] = { 247 .uts_reg = IMX21_UTS, 248 .devtype = IMX6Q_UART, 249 }, 250 }; 251 252 static const struct platform_device_id imx_uart_devtype[] = { 253 { 254 .name = "imx1-uart", 255 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 256 }, { 257 .name = "imx21-uart", 258 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 259 }, { 260 .name = "imx53-uart", 261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 262 }, { 263 .name = "imx6q-uart", 264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 265 }, { 266 /* sentinel */ 267 } 268 }; 269 MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 270 271 static const struct of_device_id imx_uart_dt_ids[] = { 272 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 273 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 274 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 275 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 276 { /* sentinel */ } 277 }; 278 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 279 280 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 281 { 282 switch (offset) { 283 case UCR1: 284 sport->ucr1 = val; 285 break; 286 case UCR2: 287 sport->ucr2 = val; 288 break; 289 case UCR3: 290 sport->ucr3 = val; 291 break; 292 case UCR4: 293 sport->ucr4 = val; 294 break; 295 case UFCR: 296 sport->ufcr = val; 297 break; 298 default: 299 break; 300 } 301 writel(val, sport->port.membase + offset); 302 } 303 304 static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 305 { 306 switch (offset) { 307 case UCR1: 308 return sport->ucr1; 309 break; 310 case UCR2: 311 /* 312 * UCR2_SRST is the only bit in the cached registers that might 313 * differ from the value that was last written. As it only 314 * automatically becomes one after being cleared, reread 315 * conditionally. 316 */ 317 if (!(sport->ucr2 & UCR2_SRST)) 318 sport->ucr2 = readl(sport->port.membase + offset); 319 return sport->ucr2; 320 break; 321 case UCR3: 322 return sport->ucr3; 323 break; 324 case UCR4: 325 return sport->ucr4; 326 break; 327 case UFCR: 328 return sport->ufcr; 329 break; 330 default: 331 return readl(sport->port.membase + offset); 332 } 333 } 334 335 static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 336 { 337 return sport->devdata->uts_reg; 338 } 339 340 static inline int imx_uart_is_imx1(struct imx_port *sport) 341 { 342 return sport->devdata->devtype == IMX1_UART; 343 } 344 345 static inline int imx_uart_is_imx21(struct imx_port *sport) 346 { 347 return sport->devdata->devtype == IMX21_UART; 348 } 349 350 static inline int imx_uart_is_imx53(struct imx_port *sport) 351 { 352 return sport->devdata->devtype == IMX53_UART; 353 } 354 355 static inline int imx_uart_is_imx6q(struct imx_port *sport) 356 { 357 return sport->devdata->devtype == IMX6Q_UART; 358 } 359 /* 360 * Save and restore functions for UCR1, UCR2 and UCR3 registers 361 */ 362 #if defined(CONFIG_SERIAL_IMX_CONSOLE) 363 static void imx_uart_ucrs_save(struct imx_port *sport, 364 struct imx_port_ucrs *ucr) 365 { 366 /* save control registers */ 367 ucr->ucr1 = imx_uart_readl(sport, UCR1); 368 ucr->ucr2 = imx_uart_readl(sport, UCR2); 369 ucr->ucr3 = imx_uart_readl(sport, UCR3); 370 } 371 372 static void imx_uart_ucrs_restore(struct imx_port *sport, 373 struct imx_port_ucrs *ucr) 374 { 375 /* restore control registers */ 376 imx_uart_writel(sport, ucr->ucr1, UCR1); 377 imx_uart_writel(sport, ucr->ucr2, UCR2); 378 imx_uart_writel(sport, ucr->ucr3, UCR3); 379 } 380 #endif 381 382 /* called with port.lock taken and irqs caller dependent */ 383 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 384 { 385 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 386 387 sport->port.mctrl |= TIOCM_RTS; 388 mctrl_gpio_set(sport->gpios, sport->port.mctrl); 389 } 390 391 /* called with port.lock taken and irqs caller dependent */ 392 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 393 { 394 *ucr2 &= ~UCR2_CTSC; 395 *ucr2 |= UCR2_CTS; 396 397 sport->port.mctrl &= ~TIOCM_RTS; 398 mctrl_gpio_set(sport->gpios, sport->port.mctrl); 399 } 400 401 /* called with port.lock taken and irqs off */ 402 static void imx_uart_start_rx(struct uart_port *port) 403 { 404 struct imx_port *sport = (struct imx_port *)port; 405 unsigned int ucr1, ucr2; 406 407 ucr1 = imx_uart_readl(sport, UCR1); 408 ucr2 = imx_uart_readl(sport, UCR2); 409 410 ucr2 |= UCR2_RXEN; 411 412 if (sport->dma_is_enabled) { 413 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 414 } else { 415 ucr1 |= UCR1_RRDYEN; 416 ucr2 |= UCR2_ATEN; 417 } 418 419 /* Write UCR2 first as it includes RXEN */ 420 imx_uart_writel(sport, ucr2, UCR2); 421 imx_uart_writel(sport, ucr1, UCR1); 422 } 423 424 /* called with port.lock taken and irqs off */ 425 static void imx_uart_stop_tx(struct uart_port *port) 426 { 427 struct imx_port *sport = (struct imx_port *)port; 428 u32 ucr1; 429 430 /* 431 * We are maybe in the SMP context, so if the DMA TX thread is running 432 * on other cpu, we have to wait for it to finish. 433 */ 434 if (sport->dma_is_txing) 435 return; 436 437 ucr1 = imx_uart_readl(sport, UCR1); 438 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); 439 440 /* in rs485 mode disable transmitter if shifter is empty */ 441 if (port->rs485.flags & SER_RS485_ENABLED && 442 imx_uart_readl(sport, USR2) & USR2_TXDC) { 443 u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4; 444 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 445 imx_uart_rts_active(sport, &ucr2); 446 else 447 imx_uart_rts_inactive(sport, &ucr2); 448 imx_uart_writel(sport, ucr2, UCR2); 449 450 imx_uart_start_rx(port); 451 452 ucr4 = imx_uart_readl(sport, UCR4); 453 ucr4 &= ~UCR4_TCEN; 454 imx_uart_writel(sport, ucr4, UCR4); 455 } 456 } 457 458 /* called with port.lock taken and irqs off */ 459 static void imx_uart_stop_rx(struct uart_port *port) 460 { 461 struct imx_port *sport = (struct imx_port *)port; 462 u32 ucr1, ucr2; 463 464 ucr1 = imx_uart_readl(sport, UCR1); 465 ucr2 = imx_uart_readl(sport, UCR2); 466 467 if (sport->dma_is_enabled) { 468 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 469 } else { 470 ucr1 &= ~UCR1_RRDYEN; 471 ucr2 &= ~UCR2_ATEN; 472 } 473 imx_uart_writel(sport, ucr1, UCR1); 474 475 ucr2 &= ~UCR2_RXEN; 476 imx_uart_writel(sport, ucr2, UCR2); 477 } 478 479 /* called with port.lock taken and irqs off */ 480 static void imx_uart_enable_ms(struct uart_port *port) 481 { 482 struct imx_port *sport = (struct imx_port *)port; 483 484 mod_timer(&sport->timer, jiffies); 485 486 mctrl_gpio_enable_ms(sport->gpios); 487 } 488 489 static void imx_uart_dma_tx(struct imx_port *sport); 490 491 /* called with port.lock taken and irqs off */ 492 static inline void imx_uart_transmit_buffer(struct imx_port *sport) 493 { 494 struct circ_buf *xmit = &sport->port.state->xmit; 495 496 if (sport->port.x_char) { 497 /* Send next char */ 498 imx_uart_writel(sport, sport->port.x_char, URTX0); 499 sport->port.icount.tx++; 500 sport->port.x_char = 0; 501 return; 502 } 503 504 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 505 imx_uart_stop_tx(&sport->port); 506 return; 507 } 508 509 if (sport->dma_is_enabled) { 510 u32 ucr1; 511 /* 512 * We've just sent a X-char Ensure the TX DMA is enabled 513 * and the TX IRQ is disabled. 514 **/ 515 ucr1 = imx_uart_readl(sport, UCR1); 516 ucr1 &= ~UCR1_TRDYEN; 517 if (sport->dma_is_txing) { 518 ucr1 |= UCR1_TXDMAEN; 519 imx_uart_writel(sport, ucr1, UCR1); 520 } else { 521 imx_uart_writel(sport, ucr1, UCR1); 522 imx_uart_dma_tx(sport); 523 } 524 525 return; 526 } 527 528 while (!uart_circ_empty(xmit) && 529 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 530 /* send xmit->buf[xmit->tail] 531 * out the port here */ 532 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 533 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 534 sport->port.icount.tx++; 535 } 536 537 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 538 uart_write_wakeup(&sport->port); 539 540 if (uart_circ_empty(xmit)) 541 imx_uart_stop_tx(&sport->port); 542 } 543 544 static void imx_uart_dma_tx_callback(void *data) 545 { 546 struct imx_port *sport = data; 547 struct scatterlist *sgl = &sport->tx_sgl[0]; 548 struct circ_buf *xmit = &sport->port.state->xmit; 549 unsigned long flags; 550 u32 ucr1; 551 552 spin_lock_irqsave(&sport->port.lock, flags); 553 554 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 555 556 ucr1 = imx_uart_readl(sport, UCR1); 557 ucr1 &= ~UCR1_TXDMAEN; 558 imx_uart_writel(sport, ucr1, UCR1); 559 560 /* update the stat */ 561 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 562 sport->port.icount.tx += sport->tx_bytes; 563 564 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 565 566 sport->dma_is_txing = 0; 567 568 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 569 uart_write_wakeup(&sport->port); 570 571 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 572 imx_uart_dma_tx(sport); 573 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 574 u32 ucr4 = imx_uart_readl(sport, UCR4); 575 ucr4 |= UCR4_TCEN; 576 imx_uart_writel(sport, ucr4, UCR4); 577 } 578 579 spin_unlock_irqrestore(&sport->port.lock, flags); 580 } 581 582 /* called with port.lock taken and irqs off */ 583 static void imx_uart_dma_tx(struct imx_port *sport) 584 { 585 struct circ_buf *xmit = &sport->port.state->xmit; 586 struct scatterlist *sgl = sport->tx_sgl; 587 struct dma_async_tx_descriptor *desc; 588 struct dma_chan *chan = sport->dma_chan_tx; 589 struct device *dev = sport->port.dev; 590 u32 ucr1, ucr4; 591 int ret; 592 593 if (sport->dma_is_txing) 594 return; 595 596 ucr4 = imx_uart_readl(sport, UCR4); 597 ucr4 &= ~UCR4_TCEN; 598 imx_uart_writel(sport, ucr4, UCR4); 599 600 sport->tx_bytes = uart_circ_chars_pending(xmit); 601 602 if (xmit->tail < xmit->head) { 603 sport->dma_tx_nents = 1; 604 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 605 } else { 606 sport->dma_tx_nents = 2; 607 sg_init_table(sgl, 2); 608 sg_set_buf(sgl, xmit->buf + xmit->tail, 609 UART_XMIT_SIZE - xmit->tail); 610 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 611 } 612 613 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 614 if (ret == 0) { 615 dev_err(dev, "DMA mapping error for TX.\n"); 616 return; 617 } 618 desc = dmaengine_prep_slave_sg(chan, sgl, ret, 619 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 620 if (!desc) { 621 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 622 DMA_TO_DEVICE); 623 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 624 return; 625 } 626 desc->callback = imx_uart_dma_tx_callback; 627 desc->callback_param = sport; 628 629 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 630 uart_circ_chars_pending(xmit)); 631 632 ucr1 = imx_uart_readl(sport, UCR1); 633 ucr1 |= UCR1_TXDMAEN; 634 imx_uart_writel(sport, ucr1, UCR1); 635 636 /* fire it */ 637 sport->dma_is_txing = 1; 638 dmaengine_submit(desc); 639 dma_async_issue_pending(chan); 640 return; 641 } 642 643 /* called with port.lock taken and irqs off */ 644 static void imx_uart_start_tx(struct uart_port *port) 645 { 646 struct imx_port *sport = (struct imx_port *)port; 647 u32 ucr1; 648 649 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 650 return; 651 652 if (port->rs485.flags & SER_RS485_ENABLED) { 653 u32 ucr2; 654 655 ucr2 = imx_uart_readl(sport, UCR2); 656 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 657 imx_uart_rts_active(sport, &ucr2); 658 else 659 imx_uart_rts_inactive(sport, &ucr2); 660 imx_uart_writel(sport, ucr2, UCR2); 661 662 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 663 imx_uart_stop_rx(port); 664 665 /* 666 * Enable transmitter and shifter empty irq only if DMA is off. 667 * In the DMA case this is done in the tx-callback. 668 */ 669 if (!sport->dma_is_enabled) { 670 u32 ucr4 = imx_uart_readl(sport, UCR4); 671 ucr4 |= UCR4_TCEN; 672 imx_uart_writel(sport, ucr4, UCR4); 673 } 674 } 675 676 if (!sport->dma_is_enabled) { 677 ucr1 = imx_uart_readl(sport, UCR1); 678 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); 679 } 680 681 if (sport->dma_is_enabled) { 682 if (sport->port.x_char) { 683 /* We have X-char to send, so enable TX IRQ and 684 * disable TX DMA to let TX interrupt to send X-char */ 685 ucr1 = imx_uart_readl(sport, UCR1); 686 ucr1 &= ~UCR1_TXDMAEN; 687 ucr1 |= UCR1_TRDYEN; 688 imx_uart_writel(sport, ucr1, UCR1); 689 return; 690 } 691 692 if (!uart_circ_empty(&port->state->xmit) && 693 !uart_tx_stopped(port)) 694 imx_uart_dma_tx(sport); 695 return; 696 } 697 } 698 699 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id) 700 { 701 struct imx_port *sport = dev_id; 702 u32 usr1; 703 704 imx_uart_writel(sport, USR1_RTSD, USR1); 705 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 706 uart_handle_cts_change(&sport->port, !!usr1); 707 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 708 709 return IRQ_HANDLED; 710 } 711 712 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 713 { 714 struct imx_port *sport = dev_id; 715 irqreturn_t ret; 716 717 spin_lock(&sport->port.lock); 718 719 ret = __imx_uart_rtsint(irq, dev_id); 720 721 spin_unlock(&sport->port.lock); 722 723 return ret; 724 } 725 726 static irqreturn_t imx_uart_txint(int irq, void *dev_id) 727 { 728 struct imx_port *sport = dev_id; 729 730 spin_lock(&sport->port.lock); 731 imx_uart_transmit_buffer(sport); 732 spin_unlock(&sport->port.lock); 733 return IRQ_HANDLED; 734 } 735 736 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) 737 { 738 struct imx_port *sport = dev_id; 739 unsigned int rx, flg, ignored = 0; 740 struct tty_port *port = &sport->port.state->port; 741 742 while (imx_uart_readl(sport, USR2) & USR2_RDR) { 743 u32 usr2; 744 745 flg = TTY_NORMAL; 746 sport->port.icount.rx++; 747 748 rx = imx_uart_readl(sport, URXD0); 749 750 usr2 = imx_uart_readl(sport, USR2); 751 if (usr2 & USR2_BRCD) { 752 imx_uart_writel(sport, USR2_BRCD, USR2); 753 if (uart_handle_break(&sport->port)) 754 continue; 755 } 756 757 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 758 continue; 759 760 if (unlikely(rx & URXD_ERR)) { 761 if (rx & URXD_BRK) 762 sport->port.icount.brk++; 763 else if (rx & URXD_PRERR) 764 sport->port.icount.parity++; 765 else if (rx & URXD_FRMERR) 766 sport->port.icount.frame++; 767 if (rx & URXD_OVRRUN) 768 sport->port.icount.overrun++; 769 770 if (rx & sport->port.ignore_status_mask) { 771 if (++ignored > 100) 772 goto out; 773 continue; 774 } 775 776 rx &= (sport->port.read_status_mask | 0xFF); 777 778 if (rx & URXD_BRK) 779 flg = TTY_BREAK; 780 else if (rx & URXD_PRERR) 781 flg = TTY_PARITY; 782 else if (rx & URXD_FRMERR) 783 flg = TTY_FRAME; 784 if (rx & URXD_OVRRUN) 785 flg = TTY_OVERRUN; 786 787 sport->port.sysrq = 0; 788 } 789 790 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 791 goto out; 792 793 if (tty_insert_flip_char(port, rx, flg) == 0) 794 sport->port.icount.buf_overrun++; 795 } 796 797 out: 798 tty_flip_buffer_push(port); 799 800 return IRQ_HANDLED; 801 } 802 803 static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 804 { 805 struct imx_port *sport = dev_id; 806 irqreturn_t ret; 807 808 spin_lock(&sport->port.lock); 809 810 ret = __imx_uart_rxint(irq, dev_id); 811 812 spin_unlock(&sport->port.lock); 813 814 return ret; 815 } 816 817 static void imx_uart_clear_rx_errors(struct imx_port *sport); 818 819 /* 820 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 821 */ 822 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 823 { 824 unsigned int tmp = TIOCM_DSR; 825 unsigned usr1 = imx_uart_readl(sport, USR1); 826 unsigned usr2 = imx_uart_readl(sport, USR2); 827 828 if (usr1 & USR1_RTSS) 829 tmp |= TIOCM_CTS; 830 831 /* in DCE mode DCDIN is always 0 */ 832 if (!(usr2 & USR2_DCDIN)) 833 tmp |= TIOCM_CAR; 834 835 if (sport->dte_mode) 836 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 837 tmp |= TIOCM_RI; 838 839 return tmp; 840 } 841 842 /* 843 * Handle any change of modem status signal since we were last called. 844 */ 845 static void imx_uart_mctrl_check(struct imx_port *sport) 846 { 847 unsigned int status, changed; 848 849 status = imx_uart_get_hwmctrl(sport); 850 changed = status ^ sport->old_status; 851 852 if (changed == 0) 853 return; 854 855 sport->old_status = status; 856 857 if (changed & TIOCM_RI && status & TIOCM_RI) 858 sport->port.icount.rng++; 859 if (changed & TIOCM_DSR) 860 sport->port.icount.dsr++; 861 if (changed & TIOCM_CAR) 862 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 863 if (changed & TIOCM_CTS) 864 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 865 866 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 867 } 868 869 static irqreturn_t imx_uart_int(int irq, void *dev_id) 870 { 871 struct imx_port *sport = dev_id; 872 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 873 irqreturn_t ret = IRQ_NONE; 874 875 spin_lock(&sport->port.lock); 876 877 usr1 = imx_uart_readl(sport, USR1); 878 usr2 = imx_uart_readl(sport, USR2); 879 ucr1 = imx_uart_readl(sport, UCR1); 880 ucr2 = imx_uart_readl(sport, UCR2); 881 ucr3 = imx_uart_readl(sport, UCR3); 882 ucr4 = imx_uart_readl(sport, UCR4); 883 884 /* 885 * Even if a condition is true that can trigger an irq only handle it if 886 * the respective irq source is enabled. This prevents some undesired 887 * actions, for example if a character that sits in the RX FIFO and that 888 * should be fetched via DMA is tried to be fetched using PIO. Or the 889 * receiver is currently off and so reading from URXD0 results in an 890 * exception. So just mask the (raw) status bits for disabled irqs. 891 */ 892 if ((ucr1 & UCR1_RRDYEN) == 0) 893 usr1 &= ~USR1_RRDY; 894 if ((ucr2 & UCR2_ATEN) == 0) 895 usr1 &= ~USR1_AGTIM; 896 if ((ucr1 & UCR1_TRDYEN) == 0) 897 usr1 &= ~USR1_TRDY; 898 if ((ucr4 & UCR4_TCEN) == 0) 899 usr2 &= ~USR2_TXDC; 900 if ((ucr3 & UCR3_DTRDEN) == 0) 901 usr1 &= ~USR1_DTRD; 902 if ((ucr1 & UCR1_RTSDEN) == 0) 903 usr1 &= ~USR1_RTSD; 904 if ((ucr3 & UCR3_AWAKEN) == 0) 905 usr1 &= ~USR1_AWAKE; 906 if ((ucr4 & UCR4_OREN) == 0) 907 usr2 &= ~USR2_ORE; 908 909 if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 910 __imx_uart_rxint(irq, dev_id); 911 ret = IRQ_HANDLED; 912 } 913 914 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 915 imx_uart_transmit_buffer(sport); 916 ret = IRQ_HANDLED; 917 } 918 919 if (usr1 & USR1_DTRD) { 920 imx_uart_writel(sport, USR1_DTRD, USR1); 921 922 imx_uart_mctrl_check(sport); 923 924 ret = IRQ_HANDLED; 925 } 926 927 if (usr1 & USR1_RTSD) { 928 __imx_uart_rtsint(irq, dev_id); 929 ret = IRQ_HANDLED; 930 } 931 932 if (usr1 & USR1_AWAKE) { 933 imx_uart_writel(sport, USR1_AWAKE, USR1); 934 ret = IRQ_HANDLED; 935 } 936 937 if (usr2 & USR2_ORE) { 938 sport->port.icount.overrun++; 939 imx_uart_writel(sport, USR2_ORE, USR2); 940 ret = IRQ_HANDLED; 941 } 942 943 spin_unlock(&sport->port.lock); 944 945 return ret; 946 } 947 948 /* 949 * Return TIOCSER_TEMT when transmitter is not busy. 950 */ 951 static unsigned int imx_uart_tx_empty(struct uart_port *port) 952 { 953 struct imx_port *sport = (struct imx_port *)port; 954 unsigned int ret; 955 956 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 957 958 /* If the TX DMA is working, return 0. */ 959 if (sport->dma_is_txing) 960 ret = 0; 961 962 return ret; 963 } 964 965 /* called with port.lock taken and irqs off */ 966 static unsigned int imx_uart_get_mctrl(struct uart_port *port) 967 { 968 struct imx_port *sport = (struct imx_port *)port; 969 unsigned int ret = imx_uart_get_hwmctrl(sport); 970 971 mctrl_gpio_get(sport->gpios, &ret); 972 973 return ret; 974 } 975 976 /* called with port.lock taken and irqs off */ 977 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 978 { 979 struct imx_port *sport = (struct imx_port *)port; 980 u32 ucr3, uts; 981 982 if (!(port->rs485.flags & SER_RS485_ENABLED)) { 983 u32 ucr2; 984 985 /* 986 * Turn off autoRTS if RTS is lowered and restore autoRTS 987 * setting if RTS is raised. 988 */ 989 ucr2 = imx_uart_readl(sport, UCR2); 990 ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 991 if (mctrl & TIOCM_RTS) { 992 ucr2 |= UCR2_CTS; 993 /* 994 * UCR2_IRTS is unset if and only if the port is 995 * configured for CRTSCTS, so we use inverted UCR2_IRTS 996 * to get the state to restore to. 997 */ 998 if (!(ucr2 & UCR2_IRTS)) 999 ucr2 |= UCR2_CTSC; 1000 } 1001 imx_uart_writel(sport, ucr2, UCR2); 1002 } 1003 1004 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 1005 if (!(mctrl & TIOCM_DTR)) 1006 ucr3 |= UCR3_DSR; 1007 imx_uart_writel(sport, ucr3, UCR3); 1008 1009 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 1010 if (mctrl & TIOCM_LOOP) 1011 uts |= UTS_LOOP; 1012 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 1013 1014 mctrl_gpio_set(sport->gpios, mctrl); 1015 } 1016 1017 /* 1018 * Interrupts always disabled. 1019 */ 1020 static void imx_uart_break_ctl(struct uart_port *port, int break_state) 1021 { 1022 struct imx_port *sport = (struct imx_port *)port; 1023 unsigned long flags; 1024 u32 ucr1; 1025 1026 spin_lock_irqsave(&sport->port.lock, flags); 1027 1028 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1029 1030 if (break_state != 0) 1031 ucr1 |= UCR1_SNDBRK; 1032 1033 imx_uart_writel(sport, ucr1, UCR1); 1034 1035 spin_unlock_irqrestore(&sport->port.lock, flags); 1036 } 1037 1038 /* 1039 * This is our per-port timeout handler, for checking the 1040 * modem status signals. 1041 */ 1042 static void imx_uart_timeout(struct timer_list *t) 1043 { 1044 struct imx_port *sport = from_timer(sport, t, timer); 1045 unsigned long flags; 1046 1047 if (sport->port.state) { 1048 spin_lock_irqsave(&sport->port.lock, flags); 1049 imx_uart_mctrl_check(sport); 1050 spin_unlock_irqrestore(&sport->port.lock, flags); 1051 1052 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1053 } 1054 } 1055 1056 /* 1057 * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1058 * [1] the RX DMA buffer is full. 1059 * [2] the aging timer expires 1060 * 1061 * Condition [2] is triggered when a character has been sitting in the FIFO 1062 * for at least 8 byte durations. 1063 */ 1064 static void imx_uart_dma_rx_callback(void *data) 1065 { 1066 struct imx_port *sport = data; 1067 struct dma_chan *chan = sport->dma_chan_rx; 1068 struct scatterlist *sgl = &sport->rx_sgl; 1069 struct tty_port *port = &sport->port.state->port; 1070 struct dma_tx_state state; 1071 struct circ_buf *rx_ring = &sport->rx_ring; 1072 enum dma_status status; 1073 unsigned int w_bytes = 0; 1074 unsigned int r_bytes; 1075 unsigned int bd_size; 1076 1077 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1078 1079 if (status == DMA_ERROR) { 1080 imx_uart_clear_rx_errors(sport); 1081 return; 1082 } 1083 1084 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1085 1086 /* 1087 * The state-residue variable represents the empty space 1088 * relative to the entire buffer. Taking this in consideration 1089 * the head is always calculated base on the buffer total 1090 * length - DMA transaction residue. The UART script from the 1091 * SDMA firmware will jump to the next buffer descriptor, 1092 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 1093 * Taking this in consideration the tail is always at the 1094 * beginning of the buffer descriptor that contains the head. 1095 */ 1096 1097 /* Calculate the head */ 1098 rx_ring->head = sg_dma_len(sgl) - state.residue; 1099 1100 /* Calculate the tail. */ 1101 bd_size = sg_dma_len(sgl) / sport->rx_periods; 1102 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 1103 1104 if (rx_ring->head <= sg_dma_len(sgl) && 1105 rx_ring->head > rx_ring->tail) { 1106 1107 /* Move data from tail to head */ 1108 r_bytes = rx_ring->head - rx_ring->tail; 1109 1110 /* CPU claims ownership of RX DMA buffer */ 1111 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 1112 DMA_FROM_DEVICE); 1113 1114 w_bytes = tty_insert_flip_string(port, 1115 sport->rx_buf + rx_ring->tail, r_bytes); 1116 1117 /* UART retrieves ownership of RX DMA buffer */ 1118 dma_sync_sg_for_device(sport->port.dev, sgl, 1, 1119 DMA_FROM_DEVICE); 1120 1121 if (w_bytes != r_bytes) 1122 sport->port.icount.buf_overrun++; 1123 1124 sport->port.icount.rx += w_bytes; 1125 } else { 1126 WARN_ON(rx_ring->head > sg_dma_len(sgl)); 1127 WARN_ON(rx_ring->head <= rx_ring->tail); 1128 } 1129 } 1130 1131 if (w_bytes) { 1132 tty_flip_buffer_push(port); 1133 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 1134 } 1135 } 1136 1137 /* RX DMA buffer periods */ 1138 #define RX_DMA_PERIODS 16 1139 #define RX_BUF_SIZE (RX_DMA_PERIODS * PAGE_SIZE / 4) 1140 1141 static int imx_uart_start_rx_dma(struct imx_port *sport) 1142 { 1143 struct scatterlist *sgl = &sport->rx_sgl; 1144 struct dma_chan *chan = sport->dma_chan_rx; 1145 struct device *dev = sport->port.dev; 1146 struct dma_async_tx_descriptor *desc; 1147 int ret; 1148 1149 sport->rx_ring.head = 0; 1150 sport->rx_ring.tail = 0; 1151 sport->rx_periods = RX_DMA_PERIODS; 1152 1153 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1154 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1155 if (ret == 0) { 1156 dev_err(dev, "DMA mapping error for RX.\n"); 1157 return -EINVAL; 1158 } 1159 1160 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 1161 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 1162 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1163 1164 if (!desc) { 1165 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1166 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1167 return -EINVAL; 1168 } 1169 desc->callback = imx_uart_dma_rx_callback; 1170 desc->callback_param = sport; 1171 1172 dev_dbg(dev, "RX: prepare for the DMA.\n"); 1173 sport->dma_is_rxing = 1; 1174 sport->rx_cookie = dmaengine_submit(desc); 1175 dma_async_issue_pending(chan); 1176 return 0; 1177 } 1178 1179 static void imx_uart_clear_rx_errors(struct imx_port *sport) 1180 { 1181 struct tty_port *port = &sport->port.state->port; 1182 u32 usr1, usr2; 1183 1184 usr1 = imx_uart_readl(sport, USR1); 1185 usr2 = imx_uart_readl(sport, USR2); 1186 1187 if (usr2 & USR2_BRCD) { 1188 sport->port.icount.brk++; 1189 imx_uart_writel(sport, USR2_BRCD, USR2); 1190 uart_handle_break(&sport->port); 1191 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 1192 sport->port.icount.buf_overrun++; 1193 tty_flip_buffer_push(port); 1194 } else { 1195 if (usr1 & USR1_FRAMERR) { 1196 sport->port.icount.frame++; 1197 imx_uart_writel(sport, USR1_FRAMERR, USR1); 1198 } else if (usr1 & USR1_PARITYERR) { 1199 sport->port.icount.parity++; 1200 imx_uart_writel(sport, USR1_PARITYERR, USR1); 1201 } 1202 } 1203 1204 if (usr2 & USR2_ORE) { 1205 sport->port.icount.overrun++; 1206 imx_uart_writel(sport, USR2_ORE, USR2); 1207 } 1208 1209 } 1210 1211 #define TXTL_DEFAULT 2 /* reset default */ 1212 #define RXTL_DEFAULT 1 /* reset default */ 1213 #define TXTL_DMA 8 /* DMA burst setting */ 1214 #define RXTL_DMA 9 /* DMA burst setting */ 1215 1216 static void imx_uart_setup_ufcr(struct imx_port *sport, 1217 unsigned char txwl, unsigned char rxwl) 1218 { 1219 unsigned int val; 1220 1221 /* set receiver / transmitter trigger level */ 1222 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1223 val |= txwl << UFCR_TXTL_SHF | rxwl; 1224 imx_uart_writel(sport, val, UFCR); 1225 } 1226 1227 static void imx_uart_dma_exit(struct imx_port *sport) 1228 { 1229 if (sport->dma_chan_rx) { 1230 dmaengine_terminate_sync(sport->dma_chan_rx); 1231 dma_release_channel(sport->dma_chan_rx); 1232 sport->dma_chan_rx = NULL; 1233 sport->rx_cookie = -EINVAL; 1234 kfree(sport->rx_buf); 1235 sport->rx_buf = NULL; 1236 } 1237 1238 if (sport->dma_chan_tx) { 1239 dmaengine_terminate_sync(sport->dma_chan_tx); 1240 dma_release_channel(sport->dma_chan_tx); 1241 sport->dma_chan_tx = NULL; 1242 } 1243 } 1244 1245 static int imx_uart_dma_init(struct imx_port *sport) 1246 { 1247 struct dma_slave_config slave_config = {}; 1248 struct device *dev = sport->port.dev; 1249 int ret; 1250 1251 /* Prepare for RX : */ 1252 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1253 if (!sport->dma_chan_rx) { 1254 dev_dbg(dev, "cannot get the DMA channel.\n"); 1255 ret = -EINVAL; 1256 goto err; 1257 } 1258 1259 slave_config.direction = DMA_DEV_TO_MEM; 1260 slave_config.src_addr = sport->port.mapbase + URXD0; 1261 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1262 /* one byte less than the watermark level to enable the aging timer */ 1263 slave_config.src_maxburst = RXTL_DMA - 1; 1264 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1265 if (ret) { 1266 dev_err(dev, "error in RX dma configuration.\n"); 1267 goto err; 1268 } 1269 1270 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1271 if (!sport->rx_buf) { 1272 ret = -ENOMEM; 1273 goto err; 1274 } 1275 sport->rx_ring.buf = sport->rx_buf; 1276 1277 /* Prepare for TX : */ 1278 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1279 if (!sport->dma_chan_tx) { 1280 dev_err(dev, "cannot get the TX DMA channel!\n"); 1281 ret = -EINVAL; 1282 goto err; 1283 } 1284 1285 slave_config.direction = DMA_MEM_TO_DEV; 1286 slave_config.dst_addr = sport->port.mapbase + URTX0; 1287 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1288 slave_config.dst_maxburst = TXTL_DMA; 1289 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1290 if (ret) { 1291 dev_err(dev, "error in TX dma configuration."); 1292 goto err; 1293 } 1294 1295 return 0; 1296 err: 1297 imx_uart_dma_exit(sport); 1298 return ret; 1299 } 1300 1301 static void imx_uart_enable_dma(struct imx_port *sport) 1302 { 1303 u32 ucr1; 1304 1305 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1306 1307 /* set UCR1 */ 1308 ucr1 = imx_uart_readl(sport, UCR1); 1309 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 1310 imx_uart_writel(sport, ucr1, UCR1); 1311 1312 sport->dma_is_enabled = 1; 1313 } 1314 1315 static void imx_uart_disable_dma(struct imx_port *sport) 1316 { 1317 u32 ucr1; 1318 1319 /* clear UCR1 */ 1320 ucr1 = imx_uart_readl(sport, UCR1); 1321 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 1322 imx_uart_writel(sport, ucr1, UCR1); 1323 1324 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1325 1326 sport->dma_is_enabled = 0; 1327 } 1328 1329 /* half the RX buffer size */ 1330 #define CTSTL 16 1331 1332 static int imx_uart_startup(struct uart_port *port) 1333 { 1334 struct imx_port *sport = (struct imx_port *)port; 1335 int retval, i; 1336 unsigned long flags; 1337 int dma_is_inited = 0; 1338 u32 ucr1, ucr2, ucr4; 1339 1340 retval = clk_prepare_enable(sport->clk_per); 1341 if (retval) 1342 return retval; 1343 retval = clk_prepare_enable(sport->clk_ipg); 1344 if (retval) { 1345 clk_disable_unprepare(sport->clk_per); 1346 return retval; 1347 } 1348 1349 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1350 1351 /* disable the DREN bit (Data Ready interrupt enable) before 1352 * requesting IRQs 1353 */ 1354 ucr4 = imx_uart_readl(sport, UCR4); 1355 1356 /* set the trigger level for CTS */ 1357 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1358 ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1359 1360 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1361 1362 /* Can we enable the DMA support? */ 1363 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 1364 dma_is_inited = 1; 1365 1366 spin_lock_irqsave(&sport->port.lock, flags); 1367 /* Reset fifo's and state machines */ 1368 i = 100; 1369 1370 ucr2 = imx_uart_readl(sport, UCR2); 1371 ucr2 &= ~UCR2_SRST; 1372 imx_uart_writel(sport, ucr2, UCR2); 1373 1374 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1375 udelay(1); 1376 1377 /* 1378 * Finally, clear and enable interrupts 1379 */ 1380 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 1381 imx_uart_writel(sport, USR2_ORE, USR2); 1382 1383 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 1384 ucr1 |= UCR1_UARTEN; 1385 if (sport->have_rtscts) 1386 ucr1 |= UCR1_RTSDEN; 1387 1388 imx_uart_writel(sport, ucr1, UCR1); 1389 1390 ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN; 1391 if (!sport->dma_is_enabled) 1392 ucr4 |= UCR4_OREN; 1393 imx_uart_writel(sport, ucr4, UCR4); 1394 1395 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 1396 ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1397 if (!sport->have_rtscts) 1398 ucr2 |= UCR2_IRTS; 1399 /* 1400 * make sure the edge sensitive RTS-irq is disabled, 1401 * we're using RTSD instead. 1402 */ 1403 if (!imx_uart_is_imx1(sport)) 1404 ucr2 &= ~UCR2_RTSEN; 1405 imx_uart_writel(sport, ucr2, UCR2); 1406 1407 if (!imx_uart_is_imx1(sport)) { 1408 u32 ucr3; 1409 1410 ucr3 = imx_uart_readl(sport, UCR3); 1411 1412 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 1413 1414 if (sport->dte_mode) 1415 /* disable broken interrupts */ 1416 ucr3 &= ~(UCR3_RI | UCR3_DCD); 1417 1418 imx_uart_writel(sport, ucr3, UCR3); 1419 } 1420 1421 /* 1422 * Enable modem status interrupts 1423 */ 1424 imx_uart_enable_ms(&sport->port); 1425 1426 if (dma_is_inited) { 1427 imx_uart_enable_dma(sport); 1428 imx_uart_start_rx_dma(sport); 1429 } else { 1430 ucr1 = imx_uart_readl(sport, UCR1); 1431 ucr1 |= UCR1_RRDYEN; 1432 imx_uart_writel(sport, ucr1, UCR1); 1433 1434 ucr2 = imx_uart_readl(sport, UCR2); 1435 ucr2 |= UCR2_ATEN; 1436 imx_uart_writel(sport, ucr2, UCR2); 1437 } 1438 1439 spin_unlock_irqrestore(&sport->port.lock, flags); 1440 1441 return 0; 1442 } 1443 1444 static void imx_uart_shutdown(struct uart_port *port) 1445 { 1446 struct imx_port *sport = (struct imx_port *)port; 1447 unsigned long flags; 1448 u32 ucr1, ucr2, ucr4; 1449 1450 if (sport->dma_is_enabled) { 1451 dmaengine_terminate_sync(sport->dma_chan_tx); 1452 if (sport->dma_is_txing) { 1453 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 1454 sport->dma_tx_nents, DMA_TO_DEVICE); 1455 sport->dma_is_txing = 0; 1456 } 1457 dmaengine_terminate_sync(sport->dma_chan_rx); 1458 if (sport->dma_is_rxing) { 1459 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1460 1, DMA_FROM_DEVICE); 1461 sport->dma_is_rxing = 0; 1462 } 1463 1464 spin_lock_irqsave(&sport->port.lock, flags); 1465 imx_uart_stop_tx(port); 1466 imx_uart_stop_rx(port); 1467 imx_uart_disable_dma(sport); 1468 spin_unlock_irqrestore(&sport->port.lock, flags); 1469 imx_uart_dma_exit(sport); 1470 } 1471 1472 mctrl_gpio_disable_ms(sport->gpios); 1473 1474 spin_lock_irqsave(&sport->port.lock, flags); 1475 ucr2 = imx_uart_readl(sport, UCR2); 1476 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 1477 imx_uart_writel(sport, ucr2, UCR2); 1478 1479 ucr4 = imx_uart_readl(sport, UCR4); 1480 ucr4 &= ~UCR4_OREN; 1481 imx_uart_writel(sport, ucr4, UCR4); 1482 spin_unlock_irqrestore(&sport->port.lock, flags); 1483 1484 /* 1485 * Stop our timer. 1486 */ 1487 del_timer_sync(&sport->timer); 1488 1489 /* 1490 * Disable all interrupts, port and break condition. 1491 */ 1492 1493 spin_lock_irqsave(&sport->port.lock, flags); 1494 ucr1 = imx_uart_readl(sport, UCR1); 1495 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 1496 1497 imx_uart_writel(sport, ucr1, UCR1); 1498 spin_unlock_irqrestore(&sport->port.lock, flags); 1499 1500 clk_disable_unprepare(sport->clk_per); 1501 clk_disable_unprepare(sport->clk_ipg); 1502 } 1503 1504 /* called with port.lock taken and irqs off */ 1505 static void imx_uart_flush_buffer(struct uart_port *port) 1506 { 1507 struct imx_port *sport = (struct imx_port *)port; 1508 struct scatterlist *sgl = &sport->tx_sgl[0]; 1509 u32 ucr2; 1510 int i = 100, ubir, ubmr, uts; 1511 1512 if (!sport->dma_chan_tx) 1513 return; 1514 1515 sport->tx_bytes = 0; 1516 dmaengine_terminate_all(sport->dma_chan_tx); 1517 if (sport->dma_is_txing) { 1518 u32 ucr1; 1519 1520 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 1521 DMA_TO_DEVICE); 1522 ucr1 = imx_uart_readl(sport, UCR1); 1523 ucr1 &= ~UCR1_TXDMAEN; 1524 imx_uart_writel(sport, ucr1, UCR1); 1525 sport->dma_is_txing = 0; 1526 } 1527 1528 /* 1529 * According to the Reference Manual description of the UART SRST bit: 1530 * 1531 * "Reset the transmit and receive state machines, 1532 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1533 * and UTS[6-3]". 1534 * 1535 * We don't need to restore the old values from USR1, USR2, URXD and 1536 * UTXD. UBRC is read only, so only save/restore the other three 1537 * registers. 1538 */ 1539 ubir = imx_uart_readl(sport, UBIR); 1540 ubmr = imx_uart_readl(sport, UBMR); 1541 uts = imx_uart_readl(sport, IMX21_UTS); 1542 1543 ucr2 = imx_uart_readl(sport, UCR2); 1544 ucr2 &= ~UCR2_SRST; 1545 imx_uart_writel(sport, ucr2, UCR2); 1546 1547 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1548 udelay(1); 1549 1550 /* Restore the registers */ 1551 imx_uart_writel(sport, ubir, UBIR); 1552 imx_uart_writel(sport, ubmr, UBMR); 1553 imx_uart_writel(sport, uts, IMX21_UTS); 1554 } 1555 1556 static void 1557 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1558 struct ktermios *old) 1559 { 1560 struct imx_port *sport = (struct imx_port *)port; 1561 unsigned long flags; 1562 u32 ucr2, old_ucr2, ufcr; 1563 unsigned int baud, quot; 1564 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1565 unsigned long div; 1566 unsigned long num, denom, old_ubir, old_ubmr; 1567 uint64_t tdiv64; 1568 1569 /* 1570 * We only support CS7 and CS8. 1571 */ 1572 while ((termios->c_cflag & CSIZE) != CS7 && 1573 (termios->c_cflag & CSIZE) != CS8) { 1574 termios->c_cflag &= ~CSIZE; 1575 termios->c_cflag |= old_csize; 1576 old_csize = CS8; 1577 } 1578 1579 del_timer_sync(&sport->timer); 1580 1581 /* 1582 * Ask the core to calculate the divisor for us. 1583 */ 1584 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1585 quot = uart_get_divisor(port, baud); 1586 1587 spin_lock_irqsave(&sport->port.lock, flags); 1588 1589 /* 1590 * Read current UCR2 and save it for future use, then clear all the bits 1591 * except those we will or may need to preserve. 1592 */ 1593 old_ucr2 = imx_uart_readl(sport, UCR2); 1594 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS); 1595 1596 ucr2 |= UCR2_SRST | UCR2_IRTS; 1597 if ((termios->c_cflag & CSIZE) == CS8) 1598 ucr2 |= UCR2_WS; 1599 1600 if (!sport->have_rtscts) 1601 termios->c_cflag &= ~CRTSCTS; 1602 1603 if (port->rs485.flags & SER_RS485_ENABLED) { 1604 /* 1605 * RTS is mandatory for rs485 operation, so keep 1606 * it under manual control and keep transmitter 1607 * disabled. 1608 */ 1609 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1610 imx_uart_rts_active(sport, &ucr2); 1611 else 1612 imx_uart_rts_inactive(sport, &ucr2); 1613 1614 } else if (termios->c_cflag & CRTSCTS) { 1615 /* 1616 * Only let receiver control RTS output if we were not requested 1617 * to have RTS inactive (which then should take precedence). 1618 */ 1619 if (ucr2 & UCR2_CTS) 1620 ucr2 |= UCR2_CTSC; 1621 } 1622 1623 if (termios->c_cflag & CRTSCTS) 1624 ucr2 &= ~UCR2_IRTS; 1625 1626 if (termios->c_cflag & CSTOPB) 1627 ucr2 |= UCR2_STPB; 1628 if (termios->c_cflag & PARENB) { 1629 ucr2 |= UCR2_PREN; 1630 if (termios->c_cflag & PARODD) 1631 ucr2 |= UCR2_PROE; 1632 } 1633 1634 sport->port.read_status_mask = 0; 1635 if (termios->c_iflag & INPCK) 1636 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1637 if (termios->c_iflag & (BRKINT | PARMRK)) 1638 sport->port.read_status_mask |= URXD_BRK; 1639 1640 /* 1641 * Characters to ignore 1642 */ 1643 sport->port.ignore_status_mask = 0; 1644 if (termios->c_iflag & IGNPAR) 1645 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1646 if (termios->c_iflag & IGNBRK) { 1647 sport->port.ignore_status_mask |= URXD_BRK; 1648 /* 1649 * If we're ignoring parity and break indicators, 1650 * ignore overruns too (for real raw support). 1651 */ 1652 if (termios->c_iflag & IGNPAR) 1653 sport->port.ignore_status_mask |= URXD_OVRRUN; 1654 } 1655 1656 if ((termios->c_cflag & CREAD) == 0) 1657 sport->port.ignore_status_mask |= URXD_DUMMY_READ; 1658 1659 /* 1660 * Update the per-port timeout. 1661 */ 1662 uart_update_timeout(port, termios->c_cflag, baud); 1663 1664 /* custom-baudrate handling */ 1665 div = sport->port.uartclk / (baud * 16); 1666 if (baud == 38400 && quot != div) 1667 baud = sport->port.uartclk / (quot * 16); 1668 1669 div = sport->port.uartclk / (baud * 16); 1670 if (div > 7) 1671 div = 7; 1672 if (!div) 1673 div = 1; 1674 1675 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1676 1 << 16, 1 << 16, &num, &denom); 1677 1678 tdiv64 = sport->port.uartclk; 1679 tdiv64 *= num; 1680 do_div(tdiv64, denom * 16 * div); 1681 tty_termios_encode_baud_rate(termios, 1682 (speed_t)tdiv64, (speed_t)tdiv64); 1683 1684 num -= 1; 1685 denom -= 1; 1686 1687 ufcr = imx_uart_readl(sport, UFCR); 1688 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1689 imx_uart_writel(sport, ufcr, UFCR); 1690 1691 /* 1692 * Two registers below should always be written both and in this 1693 * particular order. One consequence is that we need to check if any of 1694 * them changes and then update both. We do need the check for change 1695 * as even writing the same values seem to "restart" 1696 * transmission/receiving logic in the hardware, that leads to data 1697 * breakage even when rate doesn't in fact change. E.g., user switches 1698 * RTS/CTS handshake and suddenly gets broken bytes. 1699 */ 1700 old_ubir = imx_uart_readl(sport, UBIR); 1701 old_ubmr = imx_uart_readl(sport, UBMR); 1702 if (old_ubir != num || old_ubmr != denom) { 1703 imx_uart_writel(sport, num, UBIR); 1704 imx_uart_writel(sport, denom, UBMR); 1705 } 1706 1707 if (!imx_uart_is_imx1(sport)) 1708 imx_uart_writel(sport, sport->port.uartclk / div / 1000, 1709 IMX21_ONEMS); 1710 1711 imx_uart_writel(sport, ucr2, UCR2); 1712 1713 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1714 imx_uart_enable_ms(&sport->port); 1715 1716 spin_unlock_irqrestore(&sport->port.lock, flags); 1717 } 1718 1719 static const char *imx_uart_type(struct uart_port *port) 1720 { 1721 struct imx_port *sport = (struct imx_port *)port; 1722 1723 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1724 } 1725 1726 /* 1727 * Configure/autoconfigure the port. 1728 */ 1729 static void imx_uart_config_port(struct uart_port *port, int flags) 1730 { 1731 struct imx_port *sport = (struct imx_port *)port; 1732 1733 if (flags & UART_CONFIG_TYPE) 1734 sport->port.type = PORT_IMX; 1735 } 1736 1737 /* 1738 * Verify the new serial_struct (for TIOCSSERIAL). 1739 * The only change we allow are to the flags and type, and 1740 * even then only between PORT_IMX and PORT_UNKNOWN 1741 */ 1742 static int 1743 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1744 { 1745 struct imx_port *sport = (struct imx_port *)port; 1746 int ret = 0; 1747 1748 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1749 ret = -EINVAL; 1750 if (sport->port.irq != ser->irq) 1751 ret = -EINVAL; 1752 if (ser->io_type != UPIO_MEM) 1753 ret = -EINVAL; 1754 if (sport->port.uartclk / 16 != ser->baud_base) 1755 ret = -EINVAL; 1756 if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1757 ret = -EINVAL; 1758 if (sport->port.iobase != ser->port) 1759 ret = -EINVAL; 1760 if (ser->hub6 != 0) 1761 ret = -EINVAL; 1762 return ret; 1763 } 1764 1765 #if defined(CONFIG_CONSOLE_POLL) 1766 1767 static int imx_uart_poll_init(struct uart_port *port) 1768 { 1769 struct imx_port *sport = (struct imx_port *)port; 1770 unsigned long flags; 1771 u32 ucr1, ucr2; 1772 int retval; 1773 1774 retval = clk_prepare_enable(sport->clk_ipg); 1775 if (retval) 1776 return retval; 1777 retval = clk_prepare_enable(sport->clk_per); 1778 if (retval) 1779 clk_disable_unprepare(sport->clk_ipg); 1780 1781 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1782 1783 spin_lock_irqsave(&sport->port.lock, flags); 1784 1785 /* 1786 * Be careful about the order of enabling bits here. First enable the 1787 * receiver (UARTEN + RXEN) and only then the corresponding irqs. 1788 * This prevents that a character that already sits in the RX fifo is 1789 * triggering an irq but the try to fetch it from there results in an 1790 * exception because UARTEN or RXEN is still off. 1791 */ 1792 ucr1 = imx_uart_readl(sport, UCR1); 1793 ucr2 = imx_uart_readl(sport, UCR2); 1794 1795 if (imx_uart_is_imx1(sport)) 1796 ucr1 |= IMX1_UCR1_UARTCLKEN; 1797 1798 ucr1 |= UCR1_UARTEN; 1799 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); 1800 1801 ucr2 |= UCR2_RXEN; 1802 ucr2 &= ~UCR2_ATEN; 1803 1804 imx_uart_writel(sport, ucr1, UCR1); 1805 imx_uart_writel(sport, ucr2, UCR2); 1806 1807 /* now enable irqs */ 1808 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 1809 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 1810 1811 spin_unlock_irqrestore(&sport->port.lock, flags); 1812 1813 return 0; 1814 } 1815 1816 static int imx_uart_poll_get_char(struct uart_port *port) 1817 { 1818 struct imx_port *sport = (struct imx_port *)port; 1819 if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 1820 return NO_POLL_CHAR; 1821 1822 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 1823 } 1824 1825 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 1826 { 1827 struct imx_port *sport = (struct imx_port *)port; 1828 unsigned int status; 1829 1830 /* drain */ 1831 do { 1832 status = imx_uart_readl(sport, USR1); 1833 } while (~status & USR1_TRDY); 1834 1835 /* write */ 1836 imx_uart_writel(sport, c, URTX0); 1837 1838 /* flush */ 1839 do { 1840 status = imx_uart_readl(sport, USR2); 1841 } while (~status & USR2_TXDC); 1842 } 1843 #endif 1844 1845 /* called with port.lock taken and irqs off or from .probe without locking */ 1846 static int imx_uart_rs485_config(struct uart_port *port, 1847 struct serial_rs485 *rs485conf) 1848 { 1849 struct imx_port *sport = (struct imx_port *)port; 1850 u32 ucr2; 1851 1852 /* unimplemented */ 1853 rs485conf->delay_rts_before_send = 0; 1854 rs485conf->delay_rts_after_send = 0; 1855 1856 /* RTS is required to control the transmitter */ 1857 if (!sport->have_rtscts && !sport->have_rtsgpio) 1858 rs485conf->flags &= ~SER_RS485_ENABLED; 1859 1860 if (rs485conf->flags & SER_RS485_ENABLED) { 1861 /* Enable receiver if low-active RTS signal is requested */ 1862 if (sport->have_rtscts && !sport->have_rtsgpio && 1863 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 1864 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1865 1866 /* disable transmitter */ 1867 ucr2 = imx_uart_readl(sport, UCR2); 1868 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 1869 imx_uart_rts_active(sport, &ucr2); 1870 else 1871 imx_uart_rts_inactive(sport, &ucr2); 1872 imx_uart_writel(sport, ucr2, UCR2); 1873 } 1874 1875 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 1876 if (!(rs485conf->flags & SER_RS485_ENABLED) || 1877 rs485conf->flags & SER_RS485_RX_DURING_TX) 1878 imx_uart_start_rx(port); 1879 1880 port->rs485 = *rs485conf; 1881 1882 return 0; 1883 } 1884 1885 static const struct uart_ops imx_uart_pops = { 1886 .tx_empty = imx_uart_tx_empty, 1887 .set_mctrl = imx_uart_set_mctrl, 1888 .get_mctrl = imx_uart_get_mctrl, 1889 .stop_tx = imx_uart_stop_tx, 1890 .start_tx = imx_uart_start_tx, 1891 .stop_rx = imx_uart_stop_rx, 1892 .enable_ms = imx_uart_enable_ms, 1893 .break_ctl = imx_uart_break_ctl, 1894 .startup = imx_uart_startup, 1895 .shutdown = imx_uart_shutdown, 1896 .flush_buffer = imx_uart_flush_buffer, 1897 .set_termios = imx_uart_set_termios, 1898 .type = imx_uart_type, 1899 .config_port = imx_uart_config_port, 1900 .verify_port = imx_uart_verify_port, 1901 #if defined(CONFIG_CONSOLE_POLL) 1902 .poll_init = imx_uart_poll_init, 1903 .poll_get_char = imx_uart_poll_get_char, 1904 .poll_put_char = imx_uart_poll_put_char, 1905 #endif 1906 }; 1907 1908 static struct imx_port *imx_uart_ports[UART_NR]; 1909 1910 #ifdef CONFIG_SERIAL_IMX_CONSOLE 1911 static void imx_uart_console_putchar(struct uart_port *port, int ch) 1912 { 1913 struct imx_port *sport = (struct imx_port *)port; 1914 1915 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1916 barrier(); 1917 1918 imx_uart_writel(sport, ch, URTX0); 1919 } 1920 1921 /* 1922 * Interrupts are disabled on entering 1923 */ 1924 static void 1925 imx_uart_console_write(struct console *co, const char *s, unsigned int count) 1926 { 1927 struct imx_port *sport = imx_uart_ports[co->index]; 1928 struct imx_port_ucrs old_ucr; 1929 unsigned int ucr1; 1930 unsigned long flags = 0; 1931 int locked = 1; 1932 int retval; 1933 1934 retval = clk_enable(sport->clk_per); 1935 if (retval) 1936 return; 1937 retval = clk_enable(sport->clk_ipg); 1938 if (retval) { 1939 clk_disable(sport->clk_per); 1940 return; 1941 } 1942 1943 if (sport->port.sysrq) 1944 locked = 0; 1945 else if (oops_in_progress) 1946 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1947 else 1948 spin_lock_irqsave(&sport->port.lock, flags); 1949 1950 /* 1951 * First, save UCR1/2/3 and then disable interrupts 1952 */ 1953 imx_uart_ucrs_save(sport, &old_ucr); 1954 ucr1 = old_ucr.ucr1; 1955 1956 if (imx_uart_is_imx1(sport)) 1957 ucr1 |= IMX1_UCR1_UARTCLKEN; 1958 ucr1 |= UCR1_UARTEN; 1959 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1960 1961 imx_uart_writel(sport, ucr1, UCR1); 1962 1963 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 1964 1965 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 1966 1967 /* 1968 * Finally, wait for transmitter to become empty 1969 * and restore UCR1/2/3 1970 */ 1971 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 1972 1973 imx_uart_ucrs_restore(sport, &old_ucr); 1974 1975 if (locked) 1976 spin_unlock_irqrestore(&sport->port.lock, flags); 1977 1978 clk_disable(sport->clk_ipg); 1979 clk_disable(sport->clk_per); 1980 } 1981 1982 /* 1983 * If the port was already initialised (eg, by a boot loader), 1984 * try to determine the current setup. 1985 */ 1986 static void __init 1987 imx_uart_console_get_options(struct imx_port *sport, int *baud, 1988 int *parity, int *bits) 1989 { 1990 1991 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 1992 /* ok, the port was enabled */ 1993 unsigned int ucr2, ubir, ubmr, uartclk; 1994 unsigned int baud_raw; 1995 unsigned int ucfr_rfdiv; 1996 1997 ucr2 = imx_uart_readl(sport, UCR2); 1998 1999 *parity = 'n'; 2000 if (ucr2 & UCR2_PREN) { 2001 if (ucr2 & UCR2_PROE) 2002 *parity = 'o'; 2003 else 2004 *parity = 'e'; 2005 } 2006 2007 if (ucr2 & UCR2_WS) 2008 *bits = 8; 2009 else 2010 *bits = 7; 2011 2012 ubir = imx_uart_readl(sport, UBIR) & 0xffff; 2013 ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 2014 2015 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 2016 if (ucfr_rfdiv == 6) 2017 ucfr_rfdiv = 7; 2018 else 2019 ucfr_rfdiv = 6 - ucfr_rfdiv; 2020 2021 uartclk = clk_get_rate(sport->clk_per); 2022 uartclk /= ucfr_rfdiv; 2023 2024 { /* 2025 * The next code provides exact computation of 2026 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2027 * without need of float support or long long division, 2028 * which would be required to prevent 32bit arithmetic overflow 2029 */ 2030 unsigned int mul = ubir + 1; 2031 unsigned int div = 16 * (ubmr + 1); 2032 unsigned int rem = uartclk % div; 2033 2034 baud_raw = (uartclk / div) * mul; 2035 baud_raw += (rem * mul + div / 2) / div; 2036 *baud = (baud_raw + 50) / 100 * 100; 2037 } 2038 2039 if (*baud != baud_raw) 2040 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", 2041 baud_raw, *baud); 2042 } 2043 } 2044 2045 static int __init 2046 imx_uart_console_setup(struct console *co, char *options) 2047 { 2048 struct imx_port *sport; 2049 int baud = 9600; 2050 int bits = 8; 2051 int parity = 'n'; 2052 int flow = 'n'; 2053 int retval; 2054 2055 /* 2056 * Check whether an invalid uart number has been specified, and 2057 * if so, search for the first available port that does have 2058 * console support. 2059 */ 2060 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2061 co->index = 0; 2062 sport = imx_uart_ports[co->index]; 2063 if (sport == NULL) 2064 return -ENODEV; 2065 2066 /* For setting the registers, we only need to enable the ipg clock. */ 2067 retval = clk_prepare_enable(sport->clk_ipg); 2068 if (retval) 2069 goto error_console; 2070 2071 if (options) 2072 uart_parse_options(options, &baud, &parity, &bits, &flow); 2073 else 2074 imx_uart_console_get_options(sport, &baud, &parity, &bits); 2075 2076 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2077 2078 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 2079 2080 clk_disable(sport->clk_ipg); 2081 if (retval) { 2082 clk_unprepare(sport->clk_ipg); 2083 goto error_console; 2084 } 2085 2086 retval = clk_prepare(sport->clk_per); 2087 if (retval) 2088 clk_unprepare(sport->clk_ipg); 2089 2090 error_console: 2091 return retval; 2092 } 2093 2094 static struct uart_driver imx_uart_uart_driver; 2095 static struct console imx_uart_console = { 2096 .name = DEV_NAME, 2097 .write = imx_uart_console_write, 2098 .device = uart_console_device, 2099 .setup = imx_uart_console_setup, 2100 .flags = CON_PRINTBUFFER, 2101 .index = -1, 2102 .data = &imx_uart_uart_driver, 2103 }; 2104 2105 #define IMX_CONSOLE &imx_uart_console 2106 2107 #ifdef CONFIG_OF 2108 static void imx_uart_console_early_putchar(struct uart_port *port, int ch) 2109 { 2110 struct imx_port *sport = (struct imx_port *)port; 2111 2112 while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL) 2113 cpu_relax(); 2114 2115 imx_uart_writel(sport, ch, URTX0); 2116 } 2117 2118 static void imx_uart_console_early_write(struct console *con, const char *s, 2119 unsigned count) 2120 { 2121 struct earlycon_device *dev = con->data; 2122 2123 uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar); 2124 } 2125 2126 static int __init 2127 imx_console_early_setup(struct earlycon_device *dev, const char *opt) 2128 { 2129 if (!dev->port.membase) 2130 return -ENODEV; 2131 2132 dev->con->write = imx_uart_console_early_write; 2133 2134 return 0; 2135 } 2136 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 2137 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 2138 #endif 2139 2140 #else 2141 #define IMX_CONSOLE NULL 2142 #endif 2143 2144 static struct uart_driver imx_uart_uart_driver = { 2145 .owner = THIS_MODULE, 2146 .driver_name = DRIVER_NAME, 2147 .dev_name = DEV_NAME, 2148 .major = SERIAL_IMX_MAJOR, 2149 .minor = MINOR_START, 2150 .nr = ARRAY_SIZE(imx_uart_ports), 2151 .cons = IMX_CONSOLE, 2152 }; 2153 2154 #ifdef CONFIG_OF 2155 /* 2156 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 2157 * could successfully get all information from dt or a negative errno. 2158 */ 2159 static int imx_uart_probe_dt(struct imx_port *sport, 2160 struct platform_device *pdev) 2161 { 2162 struct device_node *np = pdev->dev.of_node; 2163 int ret; 2164 2165 sport->devdata = of_device_get_match_data(&pdev->dev); 2166 if (!sport->devdata) 2167 /* no device tree device */ 2168 return 1; 2169 2170 ret = of_alias_get_id(np, "serial"); 2171 if (ret < 0) { 2172 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2173 return ret; 2174 } 2175 sport->port.line = ret; 2176 2177 if (of_get_property(np, "uart-has-rtscts", NULL) || 2178 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 2179 sport->have_rtscts = 1; 2180 2181 if (of_get_property(np, "fsl,dte-mode", NULL)) 2182 sport->dte_mode = 1; 2183 2184 if (of_get_property(np, "rts-gpios", NULL)) 2185 sport->have_rtsgpio = 1; 2186 2187 return 0; 2188 } 2189 #else 2190 static inline int imx_uart_probe_dt(struct imx_port *sport, 2191 struct platform_device *pdev) 2192 { 2193 return 1; 2194 } 2195 #endif 2196 2197 static void imx_uart_probe_pdata(struct imx_port *sport, 2198 struct platform_device *pdev) 2199 { 2200 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 2201 2202 sport->port.line = pdev->id; 2203 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 2204 2205 if (!pdata) 2206 return; 2207 2208 if (pdata->flags & IMXUART_HAVE_RTSCTS) 2209 sport->have_rtscts = 1; 2210 } 2211 2212 static int imx_uart_probe(struct platform_device *pdev) 2213 { 2214 struct imx_port *sport; 2215 void __iomem *base; 2216 int ret = 0; 2217 u32 ucr1; 2218 struct resource *res; 2219 int txirq, rxirq, rtsirq; 2220 2221 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2222 if (!sport) 2223 return -ENOMEM; 2224 2225 ret = imx_uart_probe_dt(sport, pdev); 2226 if (ret > 0) 2227 imx_uart_probe_pdata(sport, pdev); 2228 else if (ret < 0) 2229 return ret; 2230 2231 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 2232 dev_err(&pdev->dev, "serial%d out of range\n", 2233 sport->port.line); 2234 return -EINVAL; 2235 } 2236 2237 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2238 base = devm_ioremap_resource(&pdev->dev, res); 2239 if (IS_ERR(base)) 2240 return PTR_ERR(base); 2241 2242 rxirq = platform_get_irq(pdev, 0); 2243 txirq = platform_get_irq_optional(pdev, 1); 2244 rtsirq = platform_get_irq_optional(pdev, 2); 2245 2246 sport->port.dev = &pdev->dev; 2247 sport->port.mapbase = res->start; 2248 sport->port.membase = base; 2249 sport->port.type = PORT_IMX, 2250 sport->port.iotype = UPIO_MEM; 2251 sport->port.irq = rxirq; 2252 sport->port.fifosize = 32; 2253 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); 2254 sport->port.ops = &imx_uart_pops; 2255 sport->port.rs485_config = imx_uart_rs485_config; 2256 sport->port.flags = UPF_BOOT_AUTOCONF; 2257 timer_setup(&sport->timer, imx_uart_timeout, 0); 2258 2259 sport->gpios = mctrl_gpio_init(&sport->port, 0); 2260 if (IS_ERR(sport->gpios)) 2261 return PTR_ERR(sport->gpios); 2262 2263 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2264 if (IS_ERR(sport->clk_ipg)) { 2265 ret = PTR_ERR(sport->clk_ipg); 2266 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 2267 return ret; 2268 } 2269 2270 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 2271 if (IS_ERR(sport->clk_per)) { 2272 ret = PTR_ERR(sport->clk_per); 2273 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 2274 return ret; 2275 } 2276 2277 sport->port.uartclk = clk_get_rate(sport->clk_per); 2278 2279 /* For register access, we only need to enable the ipg clock. */ 2280 ret = clk_prepare_enable(sport->clk_ipg); 2281 if (ret) { 2282 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 2283 return ret; 2284 } 2285 2286 /* initialize shadow register values */ 2287 sport->ucr1 = readl(sport->port.membase + UCR1); 2288 sport->ucr2 = readl(sport->port.membase + UCR2); 2289 sport->ucr3 = readl(sport->port.membase + UCR3); 2290 sport->ucr4 = readl(sport->port.membase + UCR4); 2291 sport->ufcr = readl(sport->port.membase + UFCR); 2292 2293 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2294 2295 if (sport->port.rs485.flags & SER_RS485_ENABLED && 2296 (!sport->have_rtscts && !sport->have_rtsgpio)) 2297 dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2298 2299 /* 2300 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 2301 * signal cannot be set low during transmission in case the 2302 * receiver is off (limitation of the i.MX UART IP). 2303 */ 2304 if (sport->port.rs485.flags & SER_RS485_ENABLED && 2305 sport->have_rtscts && !sport->have_rtsgpio && 2306 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 2307 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 2308 dev_err(&pdev->dev, 2309 "low-active RTS not possible when receiver is off, enabling receiver\n"); 2310 2311 imx_uart_rs485_config(&sport->port, &sport->port.rs485); 2312 2313 /* Disable interrupts before requesting them */ 2314 ucr1 = imx_uart_readl(sport, UCR1); 2315 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 2316 UCR1_TRDYEN | UCR1_RTSDEN); 2317 imx_uart_writel(sport, ucr1, UCR1); 2318 2319 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2320 /* 2321 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2322 * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2323 * and DCD (when they are outputs) or enables the respective 2324 * irqs. So set this bit early, i.e. before requesting irqs. 2325 */ 2326 u32 ufcr = imx_uart_readl(sport, UFCR); 2327 if (!(ufcr & UFCR_DCEDTE)) 2328 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2329 2330 /* 2331 * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2332 * enabled later because they cannot be cleared 2333 * (confirmed on i.MX25) which makes them unusable. 2334 */ 2335 imx_uart_writel(sport, 2336 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 2337 UCR3); 2338 2339 } else { 2340 u32 ucr3 = UCR3_DSR; 2341 u32 ufcr = imx_uart_readl(sport, UFCR); 2342 if (ufcr & UFCR_DCEDTE) 2343 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 2344 2345 if (!imx_uart_is_imx1(sport)) 2346 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 2347 imx_uart_writel(sport, ucr3, UCR3); 2348 } 2349 2350 clk_disable_unprepare(sport->clk_ipg); 2351 2352 /* 2353 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2354 * chips only have one interrupt. 2355 */ 2356 if (txirq > 0) { 2357 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2358 dev_name(&pdev->dev), sport); 2359 if (ret) { 2360 dev_err(&pdev->dev, "failed to request rx irq: %d\n", 2361 ret); 2362 return ret; 2363 } 2364 2365 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2366 dev_name(&pdev->dev), sport); 2367 if (ret) { 2368 dev_err(&pdev->dev, "failed to request tx irq: %d\n", 2369 ret); 2370 return ret; 2371 } 2372 2373 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, 2374 dev_name(&pdev->dev), sport); 2375 if (ret) { 2376 dev_err(&pdev->dev, "failed to request rts irq: %d\n", 2377 ret); 2378 return ret; 2379 } 2380 } else { 2381 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2382 dev_name(&pdev->dev), sport); 2383 if (ret) { 2384 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2385 return ret; 2386 } 2387 } 2388 2389 imx_uart_ports[sport->port.line] = sport; 2390 2391 platform_set_drvdata(pdev, sport); 2392 2393 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2394 } 2395 2396 static int imx_uart_remove(struct platform_device *pdev) 2397 { 2398 struct imx_port *sport = platform_get_drvdata(pdev); 2399 2400 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2401 } 2402 2403 static void imx_uart_restore_context(struct imx_port *sport) 2404 { 2405 unsigned long flags; 2406 2407 spin_lock_irqsave(&sport->port.lock, flags); 2408 if (!sport->context_saved) { 2409 spin_unlock_irqrestore(&sport->port.lock, flags); 2410 return; 2411 } 2412 2413 imx_uart_writel(sport, sport->saved_reg[4], UFCR); 2414 imx_uart_writel(sport, sport->saved_reg[5], UESC); 2415 imx_uart_writel(sport, sport->saved_reg[6], UTIM); 2416 imx_uart_writel(sport, sport->saved_reg[7], UBIR); 2417 imx_uart_writel(sport, sport->saved_reg[8], UBMR); 2418 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 2419 imx_uart_writel(sport, sport->saved_reg[0], UCR1); 2420 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 2421 imx_uart_writel(sport, sport->saved_reg[2], UCR3); 2422 imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2423 sport->context_saved = false; 2424 spin_unlock_irqrestore(&sport->port.lock, flags); 2425 } 2426 2427 static void imx_uart_save_context(struct imx_port *sport) 2428 { 2429 unsigned long flags; 2430 2431 /* Save necessary regs */ 2432 spin_lock_irqsave(&sport->port.lock, flags); 2433 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 2434 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 2435 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 2436 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 2437 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 2438 sport->saved_reg[5] = imx_uart_readl(sport, UESC); 2439 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 2440 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 2441 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 2442 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2443 sport->context_saved = true; 2444 spin_unlock_irqrestore(&sport->port.lock, flags); 2445 } 2446 2447 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2448 { 2449 u32 ucr3; 2450 2451 ucr3 = imx_uart_readl(sport, UCR3); 2452 if (on) { 2453 imx_uart_writel(sport, USR1_AWAKE, USR1); 2454 ucr3 |= UCR3_AWAKEN; 2455 } else { 2456 ucr3 &= ~UCR3_AWAKEN; 2457 } 2458 imx_uart_writel(sport, ucr3, UCR3); 2459 2460 if (sport->have_rtscts) { 2461 u32 ucr1 = imx_uart_readl(sport, UCR1); 2462 if (on) 2463 ucr1 |= UCR1_RTSDEN; 2464 else 2465 ucr1 &= ~UCR1_RTSDEN; 2466 imx_uart_writel(sport, ucr1, UCR1); 2467 } 2468 } 2469 2470 static int imx_uart_suspend_noirq(struct device *dev) 2471 { 2472 struct imx_port *sport = dev_get_drvdata(dev); 2473 2474 imx_uart_save_context(sport); 2475 2476 clk_disable(sport->clk_ipg); 2477 2478 pinctrl_pm_select_sleep_state(dev); 2479 2480 return 0; 2481 } 2482 2483 static int imx_uart_resume_noirq(struct device *dev) 2484 { 2485 struct imx_port *sport = dev_get_drvdata(dev); 2486 int ret; 2487 2488 pinctrl_pm_select_default_state(dev); 2489 2490 ret = clk_enable(sport->clk_ipg); 2491 if (ret) 2492 return ret; 2493 2494 imx_uart_restore_context(sport); 2495 2496 return 0; 2497 } 2498 2499 static int imx_uart_suspend(struct device *dev) 2500 { 2501 struct imx_port *sport = dev_get_drvdata(dev); 2502 int ret; 2503 2504 uart_suspend_port(&imx_uart_uart_driver, &sport->port); 2505 disable_irq(sport->port.irq); 2506 2507 ret = clk_prepare_enable(sport->clk_ipg); 2508 if (ret) 2509 return ret; 2510 2511 /* enable wakeup from i.MX UART */ 2512 imx_uart_enable_wakeup(sport, true); 2513 2514 return 0; 2515 } 2516 2517 static int imx_uart_resume(struct device *dev) 2518 { 2519 struct imx_port *sport = dev_get_drvdata(dev); 2520 2521 /* disable wakeup from i.MX UART */ 2522 imx_uart_enable_wakeup(sport, false); 2523 2524 uart_resume_port(&imx_uart_uart_driver, &sport->port); 2525 enable_irq(sport->port.irq); 2526 2527 clk_disable_unprepare(sport->clk_ipg); 2528 2529 return 0; 2530 } 2531 2532 static int imx_uart_freeze(struct device *dev) 2533 { 2534 struct imx_port *sport = dev_get_drvdata(dev); 2535 2536 uart_suspend_port(&imx_uart_uart_driver, &sport->port); 2537 2538 return clk_prepare_enable(sport->clk_ipg); 2539 } 2540 2541 static int imx_uart_thaw(struct device *dev) 2542 { 2543 struct imx_port *sport = dev_get_drvdata(dev); 2544 2545 uart_resume_port(&imx_uart_uart_driver, &sport->port); 2546 2547 clk_disable_unprepare(sport->clk_ipg); 2548 2549 return 0; 2550 } 2551 2552 static const struct dev_pm_ops imx_uart_pm_ops = { 2553 .suspend_noirq = imx_uart_suspend_noirq, 2554 .resume_noirq = imx_uart_resume_noirq, 2555 .freeze_noirq = imx_uart_suspend_noirq, 2556 .restore_noirq = imx_uart_resume_noirq, 2557 .suspend = imx_uart_suspend, 2558 .resume = imx_uart_resume, 2559 .freeze = imx_uart_freeze, 2560 .thaw = imx_uart_thaw, 2561 .restore = imx_uart_thaw, 2562 }; 2563 2564 static struct platform_driver imx_uart_platform_driver = { 2565 .probe = imx_uart_probe, 2566 .remove = imx_uart_remove, 2567 2568 .id_table = imx_uart_devtype, 2569 .driver = { 2570 .name = "imx-uart", 2571 .of_match_table = imx_uart_dt_ids, 2572 .pm = &imx_uart_pm_ops, 2573 }, 2574 }; 2575 2576 static int __init imx_uart_init(void) 2577 { 2578 int ret = uart_register_driver(&imx_uart_uart_driver); 2579 2580 if (ret) 2581 return ret; 2582 2583 ret = platform_driver_register(&imx_uart_platform_driver); 2584 if (ret != 0) 2585 uart_unregister_driver(&imx_uart_uart_driver); 2586 2587 return ret; 2588 } 2589 2590 static void __exit imx_uart_exit(void) 2591 { 2592 platform_driver_unregister(&imx_uart_platform_driver); 2593 uart_unregister_driver(&imx_uart_uart_driver); 2594 } 2595 2596 module_init(imx_uart_init); 2597 module_exit(imx_uart_exit); 2598 2599 MODULE_AUTHOR("Sascha Hauer"); 2600 MODULE_DESCRIPTION("IMX generic serial port driver"); 2601 MODULE_LICENSE("GPL"); 2602 MODULE_ALIAS("platform:imx-uart"); 2603