1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Freescale Enhanced Local Bus Controller NAND driver 3 * 4 * Copyright © 2006-2007, 2010 Freescale Semiconductor 5 * 6 * Authors: Nick Spence <nick.spence@freescale.com>, 7 * Scott Wood <scottwood@freescale.com> 8 * Jack Lan <jack.lan@freescale.com> 9 * Roy Zang <tie-fei.zang@freescale.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/types.h> 14 #include <linux/kernel.h> 15 #include <linux/string.h> 16 #include <linux/ioport.h> 17 #include <linux/of_address.h> 18 #include <linux/of_platform.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/interrupt.h> 22 23 #include <linux/mtd/mtd.h> 24 #include <linux/mtd/rawnand.h> 25 #include <linux/mtd/nand_ecc.h> 26 #include <linux/mtd/partitions.h> 27 28 #include <asm/io.h> 29 #include <asm/fsl_lbc.h> 30 31 #define MAX_BANKS 8 32 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ 33 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */ 34 35 /* mtd information per set */ 36 37 struct fsl_elbc_mtd { 38 struct nand_chip chip; 39 struct fsl_lbc_ctrl *ctrl; 40 41 struct device *dev; 42 int bank; /* Chip select bank number */ 43 u8 __iomem *vbase; /* Chip select base virtual address */ 44 int page_size; /* NAND page size (0=512, 1=2048) */ 45 unsigned int fmr; /* FCM Flash Mode Register value */ 46 }; 47 48 /* Freescale eLBC FCM controller information */ 49 50 struct fsl_elbc_fcm_ctrl { 51 struct nand_controller controller; 52 struct fsl_elbc_mtd *chips[MAX_BANKS]; 53 54 u8 __iomem *addr; /* Address of assigned FCM buffer */ 55 unsigned int page; /* Last page written to / read from */ 56 unsigned int read_bytes; /* Number of bytes read during command */ 57 unsigned int column; /* Saved column from SEQIN */ 58 unsigned int index; /* Pointer to next byte to 'read' */ 59 unsigned int status; /* status read from LTESR after last op */ 60 unsigned int mdr; /* UPM/FCM Data Register value */ 61 unsigned int use_mdr; /* Non zero if the MDR is to be set */ 62 unsigned int oob; /* Non zero if operating on OOB data */ 63 unsigned int counter; /* counter for the initializations */ 64 unsigned int max_bitflips; /* Saved during READ0 cmd */ 65 }; 66 67 /* These map to the positions used by the FCM hardware ECC generator */ 68 69 static int fsl_elbc_ooblayout_ecc(struct mtd_info *mtd, int section, 70 struct mtd_oob_region *oobregion) 71 { 72 struct nand_chip *chip = mtd_to_nand(mtd); 73 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 74 75 if (section >= chip->ecc.steps) 76 return -ERANGE; 77 78 oobregion->offset = (16 * section) + 6; 79 if (priv->fmr & FMR_ECCM) 80 oobregion->offset += 2; 81 82 oobregion->length = chip->ecc.bytes; 83 84 return 0; 85 } 86 87 static int fsl_elbc_ooblayout_free(struct mtd_info *mtd, int section, 88 struct mtd_oob_region *oobregion) 89 { 90 struct nand_chip *chip = mtd_to_nand(mtd); 91 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 92 93 if (section > chip->ecc.steps) 94 return -ERANGE; 95 96 if (!section) { 97 oobregion->offset = 0; 98 if (mtd->writesize > 512) 99 oobregion->offset++; 100 oobregion->length = (priv->fmr & FMR_ECCM) ? 7 : 5; 101 } else { 102 oobregion->offset = (16 * section) - 103 ((priv->fmr & FMR_ECCM) ? 5 : 7); 104 if (section < chip->ecc.steps) 105 oobregion->length = 13; 106 else 107 oobregion->length = mtd->oobsize - oobregion->offset; 108 } 109 110 return 0; 111 } 112 113 static const struct mtd_ooblayout_ops fsl_elbc_ooblayout_ops = { 114 .ecc = fsl_elbc_ooblayout_ecc, 115 .free = fsl_elbc_ooblayout_free, 116 }; 117 118 /* 119 * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt, 120 * interfere with ECC positions, that's why we implement our own descriptors. 121 * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0. 122 */ 123 static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; 124 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; 125 126 static struct nand_bbt_descr bbt_main_descr = { 127 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 128 NAND_BBT_2BIT | NAND_BBT_VERSION, 129 .offs = 11, 130 .len = 4, 131 .veroffs = 15, 132 .maxblocks = 4, 133 .pattern = bbt_pattern, 134 }; 135 136 static struct nand_bbt_descr bbt_mirror_descr = { 137 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 138 NAND_BBT_2BIT | NAND_BBT_VERSION, 139 .offs = 11, 140 .len = 4, 141 .veroffs = 15, 142 .maxblocks = 4, 143 .pattern = mirror_pattern, 144 }; 145 146 /*=================================*/ 147 148 /* 149 * Set up the FCM hardware block and page address fields, and the fcm 150 * structure addr field to point to the correct FCM buffer in memory 151 */ 152 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) 153 { 154 struct nand_chip *chip = mtd_to_nand(mtd); 155 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 156 struct fsl_lbc_ctrl *ctrl = priv->ctrl; 157 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; 158 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; 159 int buf_num; 160 161 elbc_fcm_ctrl->page = page_addr; 162 163 if (priv->page_size) { 164 /* 165 * large page size chip : FPAR[PI] save the lowest 6 bits, 166 * FBAR[BLK] save the other bits. 167 */ 168 out_be32(&lbc->fbar, page_addr >> 6); 169 out_be32(&lbc->fpar, 170 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | 171 (oob ? FPAR_LP_MS : 0) | column); 172 buf_num = (page_addr & 1) << 2; 173 } else { 174 /* 175 * small page size chip : FPAR[PI] save the lowest 5 bits, 176 * FBAR[BLK] save the other bits. 177 */ 178 out_be32(&lbc->fbar, page_addr >> 5); 179 out_be32(&lbc->fpar, 180 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | 181 (oob ? FPAR_SP_MS : 0) | column); 182 buf_num = page_addr & 7; 183 } 184 185 elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024; 186 elbc_fcm_ctrl->index = column; 187 188 /* for OOB data point to the second half of the buffer */ 189 if (oob) 190 elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512; 191 192 dev_vdbg(priv->dev, "set_addr: bank=%d, " 193 "elbc_fcm_ctrl->addr=0x%p (0x%p), " 194 "index %x, pes %d ps %d\n", 195 buf_num, elbc_fcm_ctrl->addr, priv->vbase, 196 elbc_fcm_ctrl->index, 197 chip->phys_erase_shift, chip->page_shift); 198 } 199 200 /* 201 * execute FCM command and wait for it to complete 202 */ 203 static int fsl_elbc_run_command(struct mtd_info *mtd) 204 { 205 struct nand_chip *chip = mtd_to_nand(mtd); 206 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 207 struct fsl_lbc_ctrl *ctrl = priv->ctrl; 208 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; 209 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; 210 211 /* Setup the FMR[OP] to execute without write protection */ 212 out_be32(&lbc->fmr, priv->fmr | 3); 213 if (elbc_fcm_ctrl->use_mdr) 214 out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr); 215 216 dev_vdbg(priv->dev, 217 "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n", 218 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); 219 dev_vdbg(priv->dev, 220 "fsl_elbc_run_command: fbar=%08x fpar=%08x " 221 "fbcr=%08x bank=%d\n", 222 in_be32(&lbc->fbar), in_be32(&lbc->fpar), 223 in_be32(&lbc->fbcr), priv->bank); 224 225 ctrl->irq_status = 0; 226 /* execute special operation */ 227 out_be32(&lbc->lsor, priv->bank); 228 229 /* wait for FCM complete flag or timeout */ 230 wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, 231 FCM_TIMEOUT_MSECS * HZ/1000); 232 elbc_fcm_ctrl->status = ctrl->irq_status; 233 /* store mdr value in case it was needed */ 234 if (elbc_fcm_ctrl->use_mdr) 235 elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr); 236 237 elbc_fcm_ctrl->use_mdr = 0; 238 239 if (elbc_fcm_ctrl->status != LTESR_CC) { 240 dev_info(priv->dev, 241 "command failed: fir %x fcr %x status %x mdr %x\n", 242 in_be32(&lbc->fir), in_be32(&lbc->fcr), 243 elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr); 244 return -EIO; 245 } 246 247 if (chip->ecc.mode != NAND_ECC_HW) 248 return 0; 249 250 elbc_fcm_ctrl->max_bitflips = 0; 251 252 if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) { 253 uint32_t lteccr = in_be32(&lbc->lteccr); 254 /* 255 * if command was a full page read and the ELBC 256 * has the LTECCR register, then bits 12-15 (ppc order) of 257 * LTECCR indicates which 512 byte sub-pages had fixed errors. 258 * bits 28-31 are uncorrectable errors, marked elsewhere. 259 * for small page nand only 1 bit is used. 260 * if the ELBC doesn't have the lteccr register it reads 0 261 * FIXME: 4 bits can be corrected on NANDs with 2k pages, so 262 * count the number of sub-pages with bitflips and update 263 * ecc_stats.corrected accordingly. 264 */ 265 if (lteccr & 0x000F000F) 266 out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */ 267 if (lteccr & 0x000F0000) { 268 mtd->ecc_stats.corrected++; 269 elbc_fcm_ctrl->max_bitflips = 1; 270 } 271 } 272 273 return 0; 274 } 275 276 static void fsl_elbc_do_read(struct nand_chip *chip, int oob) 277 { 278 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 279 struct fsl_lbc_ctrl *ctrl = priv->ctrl; 280 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; 281 282 if (priv->page_size) { 283 out_be32(&lbc->fir, 284 (FIR_OP_CM0 << FIR_OP0_SHIFT) | 285 (FIR_OP_CA << FIR_OP1_SHIFT) | 286 (FIR_OP_PA << FIR_OP2_SHIFT) | 287 (FIR_OP_CM1 << FIR_OP3_SHIFT) | 288 (FIR_OP_RBW << FIR_OP4_SHIFT)); 289 290 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | 291 (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); 292 } else { 293 out_be32(&lbc->fir, 294 (FIR_OP_CM0 << FIR_OP0_SHIFT) | 295 (FIR_OP_CA << FIR_OP1_SHIFT) | 296 (FIR_OP_PA << FIR_OP2_SHIFT) | 297 (FIR_OP_RBW << FIR_OP3_SHIFT)); 298 299 if (oob) 300 out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT); 301 else 302 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); 303 } 304 } 305 306 /* cmdfunc send commands to the FCM */ 307 static void fsl_elbc_cmdfunc(struct nand_chip *chip, unsigned int command, 308 int column, int page_addr) 309 { 310 struct mtd_info *mtd = nand_to_mtd(chip); 311 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 312 struct fsl_lbc_ctrl *ctrl = priv->ctrl; 313 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; 314 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; 315 316 elbc_fcm_ctrl->use_mdr = 0; 317 318 /* clear the read buffer */ 319 elbc_fcm_ctrl->read_bytes = 0; 320 if (command != NAND_CMD_PAGEPROG) 321 elbc_fcm_ctrl->index = 0; 322 323 switch (command) { 324 /* READ0 and READ1 read the entire buffer to use hardware ECC. */ 325 case NAND_CMD_READ1: 326 column += 256; 327 fallthrough; 328 case NAND_CMD_READ0: 329 dev_dbg(priv->dev, 330 "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:" 331 " 0x%x, column: 0x%x.\n", page_addr, column); 332 333 334 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ 335 set_addr(mtd, 0, page_addr, 0); 336 337 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; 338 elbc_fcm_ctrl->index += column; 339 340 fsl_elbc_do_read(chip, 0); 341 fsl_elbc_run_command(mtd); 342 return; 343 344 /* RNDOUT moves the pointer inside the page */ 345 case NAND_CMD_RNDOUT: 346 dev_dbg(priv->dev, 347 "fsl_elbc_cmdfunc: NAND_CMD_RNDOUT, column: 0x%x.\n", 348 column); 349 350 elbc_fcm_ctrl->index = column; 351 return; 352 353 /* READOOB reads only the OOB because no ECC is performed. */ 354 case NAND_CMD_READOOB: 355 dev_vdbg(priv->dev, 356 "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" 357 " 0x%x, column: 0x%x.\n", page_addr, column); 358 359 out_be32(&lbc->fbcr, mtd->oobsize - column); 360 set_addr(mtd, column, page_addr, 1); 361 362 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; 363 364 fsl_elbc_do_read(chip, 1); 365 fsl_elbc_run_command(mtd); 366 return; 367 368 case NAND_CMD_READID: 369 case NAND_CMD_PARAM: 370 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command); 371 372 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) | 373 (FIR_OP_UA << FIR_OP1_SHIFT) | 374 (FIR_OP_RBW << FIR_OP2_SHIFT)); 375 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT); 376 /* 377 * although currently it's 8 bytes for READID, we always read 378 * the maximum 256 bytes(for PARAM) 379 */ 380 out_be32(&lbc->fbcr, 256); 381 elbc_fcm_ctrl->read_bytes = 256; 382 elbc_fcm_ctrl->use_mdr = 1; 383 elbc_fcm_ctrl->mdr = column; 384 set_addr(mtd, 0, 0, 0); 385 fsl_elbc_run_command(mtd); 386 return; 387 388 /* ERASE1 stores the block and page address */ 389 case NAND_CMD_ERASE1: 390 dev_vdbg(priv->dev, 391 "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, " 392 "page_addr: 0x%x.\n", page_addr); 393 set_addr(mtd, 0, page_addr, 0); 394 return; 395 396 /* ERASE2 uses the block and page address from ERASE1 */ 397 case NAND_CMD_ERASE2: 398 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); 399 400 out_be32(&lbc->fir, 401 (FIR_OP_CM0 << FIR_OP0_SHIFT) | 402 (FIR_OP_PA << FIR_OP1_SHIFT) | 403 (FIR_OP_CM2 << FIR_OP2_SHIFT) | 404 (FIR_OP_CW1 << FIR_OP3_SHIFT) | 405 (FIR_OP_RS << FIR_OP4_SHIFT)); 406 407 out_be32(&lbc->fcr, 408 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | 409 (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | 410 (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT)); 411 412 out_be32(&lbc->fbcr, 0); 413 elbc_fcm_ctrl->read_bytes = 0; 414 elbc_fcm_ctrl->use_mdr = 1; 415 416 fsl_elbc_run_command(mtd); 417 return; 418 419 /* SEQIN sets up the addr buffer and all registers except the length */ 420 case NAND_CMD_SEQIN: { 421 __be32 fcr; 422 dev_vdbg(priv->dev, 423 "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, " 424 "page_addr: 0x%x, column: 0x%x.\n", 425 page_addr, column); 426 427 elbc_fcm_ctrl->column = column; 428 elbc_fcm_ctrl->use_mdr = 1; 429 430 if (column >= mtd->writesize) { 431 /* OOB area */ 432 column -= mtd->writesize; 433 elbc_fcm_ctrl->oob = 1; 434 } else { 435 WARN_ON(column != 0); 436 elbc_fcm_ctrl->oob = 0; 437 } 438 439 fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | 440 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) | 441 (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT); 442 443 if (priv->page_size) { 444 out_be32(&lbc->fir, 445 (FIR_OP_CM2 << FIR_OP0_SHIFT) | 446 (FIR_OP_CA << FIR_OP1_SHIFT) | 447 (FIR_OP_PA << FIR_OP2_SHIFT) | 448 (FIR_OP_WB << FIR_OP3_SHIFT) | 449 (FIR_OP_CM3 << FIR_OP4_SHIFT) | 450 (FIR_OP_CW1 << FIR_OP5_SHIFT) | 451 (FIR_OP_RS << FIR_OP6_SHIFT)); 452 } else { 453 out_be32(&lbc->fir, 454 (FIR_OP_CM0 << FIR_OP0_SHIFT) | 455 (FIR_OP_CM2 << FIR_OP1_SHIFT) | 456 (FIR_OP_CA << FIR_OP2_SHIFT) | 457 (FIR_OP_PA << FIR_OP3_SHIFT) | 458 (FIR_OP_WB << FIR_OP4_SHIFT) | 459 (FIR_OP_CM3 << FIR_OP5_SHIFT) | 460 (FIR_OP_CW1 << FIR_OP6_SHIFT) | 461 (FIR_OP_RS << FIR_OP7_SHIFT)); 462 463 if (elbc_fcm_ctrl->oob) 464 /* OOB area --> READOOB */ 465 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; 466 else 467 /* First 256 bytes --> READ0 */ 468 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; 469 } 470 471 out_be32(&lbc->fcr, fcr); 472 set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob); 473 return; 474 } 475 476 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ 477 case NAND_CMD_PAGEPROG: { 478 dev_vdbg(priv->dev, 479 "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG " 480 "writing %d bytes.\n", elbc_fcm_ctrl->index); 481 482 /* if the write did not start at 0 or is not a full page 483 * then set the exact length, otherwise use a full page 484 * write so the HW generates the ECC. 485 */ 486 if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 || 487 elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize) 488 out_be32(&lbc->fbcr, 489 elbc_fcm_ctrl->index - elbc_fcm_ctrl->column); 490 else 491 out_be32(&lbc->fbcr, 0); 492 493 fsl_elbc_run_command(mtd); 494 return; 495 } 496 497 /* CMD_STATUS must read the status byte while CEB is active */ 498 /* Note - it does not wait for the ready line */ 499 case NAND_CMD_STATUS: 500 out_be32(&lbc->fir, 501 (FIR_OP_CM0 << FIR_OP0_SHIFT) | 502 (FIR_OP_RBW << FIR_OP1_SHIFT)); 503 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); 504 out_be32(&lbc->fbcr, 1); 505 set_addr(mtd, 0, 0, 0); 506 elbc_fcm_ctrl->read_bytes = 1; 507 508 fsl_elbc_run_command(mtd); 509 510 /* The chip always seems to report that it is 511 * write-protected, even when it is not. 512 */ 513 setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP); 514 return; 515 516 /* RESET without waiting for the ready line */ 517 case NAND_CMD_RESET: 518 dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n"); 519 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); 520 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); 521 fsl_elbc_run_command(mtd); 522 return; 523 524 default: 525 dev_err(priv->dev, 526 "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n", 527 command); 528 } 529 } 530 531 static void fsl_elbc_select_chip(struct nand_chip *chip, int cs) 532 { 533 /* The hardware does not seem to support multiple 534 * chips per bank. 535 */ 536 } 537 538 /* 539 * Write buf to the FCM Controller Data Buffer 540 */ 541 static void fsl_elbc_write_buf(struct nand_chip *chip, const u8 *buf, int len) 542 { 543 struct mtd_info *mtd = nand_to_mtd(chip); 544 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 545 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; 546 unsigned int bufsize = mtd->writesize + mtd->oobsize; 547 548 if (len <= 0) { 549 dev_err(priv->dev, "write_buf of %d bytes", len); 550 elbc_fcm_ctrl->status = 0; 551 return; 552 } 553 554 if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) { 555 dev_err(priv->dev, 556 "write_buf beyond end of buffer " 557 "(%d requested, %u available)\n", 558 len, bufsize - elbc_fcm_ctrl->index); 559 len = bufsize - elbc_fcm_ctrl->index; 560 } 561 562 memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len); 563 /* 564 * This is workaround for the weird elbc hangs during nand write, 565 * Scott Wood says: "...perhaps difference in how long it takes a 566 * write to make it through the localbus compared to a write to IMMR 567 * is causing problems, and sync isn't helping for some reason." 568 * Reading back the last byte helps though. 569 */ 570 in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1); 571 572 elbc_fcm_ctrl->index += len; 573 } 574 575 /* 576 * read a byte from either the FCM hardware buffer if it has any data left 577 * otherwise issue a command to read a single byte. 578 */ 579 static u8 fsl_elbc_read_byte(struct nand_chip *chip) 580 { 581 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 582 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; 583 584 /* If there are still bytes in the FCM, then use the next byte. */ 585 if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes) 586 return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]); 587 588 dev_err(priv->dev, "read_byte beyond end of buffer\n"); 589 return ERR_BYTE; 590 } 591 592 /* 593 * Read from the FCM Controller Data Buffer 594 */ 595 static void fsl_elbc_read_buf(struct nand_chip *chip, u8 *buf, int len) 596 { 597 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 598 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; 599 int avail; 600 601 if (len < 0) 602 return; 603 604 avail = min((unsigned int)len, 605 elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index); 606 memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail); 607 elbc_fcm_ctrl->index += avail; 608 609 if (len > avail) 610 dev_err(priv->dev, 611 "read_buf beyond end of buffer " 612 "(%d requested, %d available)\n", 613 len, avail); 614 } 615 616 /* This function is called after Program and Erase Operations to 617 * check for success or failure. 618 */ 619 static int fsl_elbc_wait(struct nand_chip *chip) 620 { 621 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 622 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; 623 624 if (elbc_fcm_ctrl->status != LTESR_CC) 625 return NAND_STATUS_FAIL; 626 627 /* The chip always seems to report that it is 628 * write-protected, even when it is not. 629 */ 630 return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP; 631 } 632 633 static int fsl_elbc_read_page(struct nand_chip *chip, uint8_t *buf, 634 int oob_required, int page) 635 { 636 struct mtd_info *mtd = nand_to_mtd(chip); 637 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 638 struct fsl_lbc_ctrl *ctrl = priv->ctrl; 639 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; 640 641 nand_read_page_op(chip, page, 0, buf, mtd->writesize); 642 if (oob_required) 643 fsl_elbc_read_buf(chip, chip->oob_poi, mtd->oobsize); 644 645 if (fsl_elbc_wait(chip) & NAND_STATUS_FAIL) 646 mtd->ecc_stats.failed++; 647 648 return elbc_fcm_ctrl->max_bitflips; 649 } 650 651 /* ECC will be calculated automatically, and errors will be detected in 652 * waitfunc. 653 */ 654 static int fsl_elbc_write_page(struct nand_chip *chip, const uint8_t *buf, 655 int oob_required, int page) 656 { 657 struct mtd_info *mtd = nand_to_mtd(chip); 658 659 nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); 660 fsl_elbc_write_buf(chip, chip->oob_poi, mtd->oobsize); 661 662 return nand_prog_page_end_op(chip); 663 } 664 665 /* ECC will be calculated automatically, and errors will be detected in 666 * waitfunc. 667 */ 668 static int fsl_elbc_write_subpage(struct nand_chip *chip, uint32_t offset, 669 uint32_t data_len, const uint8_t *buf, 670 int oob_required, int page) 671 { 672 struct mtd_info *mtd = nand_to_mtd(chip); 673 674 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 675 fsl_elbc_write_buf(chip, buf, mtd->writesize); 676 fsl_elbc_write_buf(chip, chip->oob_poi, mtd->oobsize); 677 return nand_prog_page_end_op(chip); 678 } 679 680 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) 681 { 682 struct fsl_lbc_ctrl *ctrl = priv->ctrl; 683 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; 684 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; 685 struct nand_chip *chip = &priv->chip; 686 struct mtd_info *mtd = nand_to_mtd(chip); 687 688 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank); 689 690 /* Fill in fsl_elbc_mtd structure */ 691 mtd->dev.parent = priv->dev; 692 nand_set_flash_node(chip, priv->dev->of_node); 693 694 /* set timeout to maximum */ 695 priv->fmr = 15 << FMR_CWTO_SHIFT; 696 if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS) 697 priv->fmr |= FMR_ECCM; 698 699 /* fill in nand_chip structure */ 700 /* set up function call table */ 701 chip->legacy.read_byte = fsl_elbc_read_byte; 702 chip->legacy.write_buf = fsl_elbc_write_buf; 703 chip->legacy.read_buf = fsl_elbc_read_buf; 704 chip->legacy.select_chip = fsl_elbc_select_chip; 705 chip->legacy.cmdfunc = fsl_elbc_cmdfunc; 706 chip->legacy.waitfunc = fsl_elbc_wait; 707 chip->legacy.set_features = nand_get_set_features_notsupp; 708 chip->legacy.get_features = nand_get_set_features_notsupp; 709 710 chip->bbt_td = &bbt_main_descr; 711 chip->bbt_md = &bbt_mirror_descr; 712 713 /* set up nand options */ 714 chip->bbt_options = NAND_BBT_USE_FLASH; 715 716 chip->controller = &elbc_fcm_ctrl->controller; 717 nand_set_controller_data(chip, priv); 718 719 return 0; 720 } 721 722 static int fsl_elbc_attach_chip(struct nand_chip *chip) 723 { 724 struct mtd_info *mtd = nand_to_mtd(chip); 725 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 726 struct fsl_lbc_ctrl *ctrl = priv->ctrl; 727 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; 728 unsigned int al; 729 730 switch (chip->ecc.mode) { 731 /* 732 * if ECC was not chosen in DT, decide whether to use HW or SW ECC from 733 * CS Base Register 734 */ 735 case NAND_ECC_NONE: 736 /* If CS Base Register selects full hardware ECC then use it */ 737 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == 738 BR_DECC_CHK_GEN) { 739 chip->ecc.read_page = fsl_elbc_read_page; 740 chip->ecc.write_page = fsl_elbc_write_page; 741 chip->ecc.write_subpage = fsl_elbc_write_subpage; 742 743 chip->ecc.mode = NAND_ECC_HW; 744 mtd_set_ooblayout(mtd, &fsl_elbc_ooblayout_ops); 745 chip->ecc.size = 512; 746 chip->ecc.bytes = 3; 747 chip->ecc.strength = 1; 748 } else { 749 /* otherwise fall back to default software ECC */ 750 chip->ecc.mode = NAND_ECC_SOFT; 751 chip->ecc.algo = NAND_ECC_HAMMING; 752 } 753 break; 754 755 /* if SW ECC was chosen in DT, we do not need to set anything here */ 756 case NAND_ECC_SOFT: 757 break; 758 759 /* should we also implement NAND_ECC_HW to do as the code above? */ 760 default: 761 return -EINVAL; 762 } 763 764 /* calculate FMR Address Length field */ 765 al = 0; 766 if (chip->pagemask & 0xffff0000) 767 al++; 768 if (chip->pagemask & 0xff000000) 769 al++; 770 771 priv->fmr |= al << FMR_AL_SHIFT; 772 773 dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n", 774 nanddev_ntargets(&chip->base)); 775 dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n", 776 nanddev_target_size(&chip->base)); 777 dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n", 778 chip->pagemask); 779 dev_dbg(priv->dev, "fsl_elbc_init: nand->legacy.chip_delay = %d\n", 780 chip->legacy.chip_delay); 781 dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n", 782 chip->badblockpos); 783 dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n", 784 chip->chip_shift); 785 dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n", 786 chip->page_shift); 787 dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n", 788 chip->phys_erase_shift); 789 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n", 790 chip->ecc.mode); 791 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n", 792 chip->ecc.steps); 793 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n", 794 chip->ecc.bytes); 795 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n", 796 chip->ecc.total); 797 dev_dbg(priv->dev, "fsl_elbc_init: mtd->ooblayout = %p\n", 798 mtd->ooblayout); 799 dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags); 800 dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size); 801 dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n", 802 mtd->erasesize); 803 dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n", 804 mtd->writesize); 805 dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n", 806 mtd->oobsize); 807 808 /* adjust Option Register and ECC to match Flash page size */ 809 if (mtd->writesize == 512) { 810 priv->page_size = 0; 811 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); 812 } else if (mtd->writesize == 2048) { 813 priv->page_size = 1; 814 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); 815 } else { 816 dev_err(priv->dev, 817 "fsl_elbc_init: page size %d is not supported\n", 818 mtd->writesize); 819 return -ENOTSUPP; 820 } 821 822 return 0; 823 } 824 825 static const struct nand_controller_ops fsl_elbc_controller_ops = { 826 .attach_chip = fsl_elbc_attach_chip, 827 }; 828 829 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv) 830 { 831 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; 832 struct mtd_info *mtd = nand_to_mtd(&priv->chip); 833 834 kfree(mtd->name); 835 836 if (priv->vbase) 837 iounmap(priv->vbase); 838 839 elbc_fcm_ctrl->chips[priv->bank] = NULL; 840 kfree(priv); 841 return 0; 842 } 843 844 static DEFINE_MUTEX(fsl_elbc_nand_mutex); 845 846 static int fsl_elbc_nand_probe(struct platform_device *pdev) 847 { 848 struct fsl_lbc_regs __iomem *lbc; 849 struct fsl_elbc_mtd *priv; 850 struct resource res; 851 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl; 852 static const char *part_probe_types[] 853 = { "cmdlinepart", "RedBoot", "ofpart", NULL }; 854 int ret; 855 int bank; 856 struct device *dev; 857 struct device_node *node = pdev->dev.of_node; 858 struct mtd_info *mtd; 859 860 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) 861 return -ENODEV; 862 lbc = fsl_lbc_ctrl_dev->regs; 863 dev = fsl_lbc_ctrl_dev->dev; 864 865 /* get, allocate and map the memory resource */ 866 ret = of_address_to_resource(node, 0, &res); 867 if (ret) { 868 dev_err(dev, "failed to get resource\n"); 869 return ret; 870 } 871 872 /* find which chip select it is connected to */ 873 for (bank = 0; bank < MAX_BANKS; bank++) 874 if ((in_be32(&lbc->bank[bank].br) & BR_V) && 875 (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM && 876 (in_be32(&lbc->bank[bank].br) & 877 in_be32(&lbc->bank[bank].or) & BR_BA) 878 == fsl_lbc_addr(res.start)) 879 break; 880 881 if (bank >= MAX_BANKS) { 882 dev_err(dev, "address did not match any chip selects\n"); 883 return -ENODEV; 884 } 885 886 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 887 if (!priv) 888 return -ENOMEM; 889 890 mutex_lock(&fsl_elbc_nand_mutex); 891 if (!fsl_lbc_ctrl_dev->nand) { 892 elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL); 893 if (!elbc_fcm_ctrl) { 894 mutex_unlock(&fsl_elbc_nand_mutex); 895 ret = -ENOMEM; 896 goto err; 897 } 898 elbc_fcm_ctrl->counter++; 899 900 nand_controller_init(&elbc_fcm_ctrl->controller); 901 fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl; 902 } else { 903 elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; 904 } 905 mutex_unlock(&fsl_elbc_nand_mutex); 906 907 elbc_fcm_ctrl->chips[bank] = priv; 908 priv->bank = bank; 909 priv->ctrl = fsl_lbc_ctrl_dev; 910 priv->dev = &pdev->dev; 911 dev_set_drvdata(priv->dev, priv); 912 913 priv->vbase = ioremap(res.start, resource_size(&res)); 914 if (!priv->vbase) { 915 dev_err(dev, "failed to map chip region\n"); 916 ret = -ENOMEM; 917 goto err; 918 } 919 920 mtd = nand_to_mtd(&priv->chip); 921 mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start); 922 if (!nand_to_mtd(&priv->chip)->name) { 923 ret = -ENOMEM; 924 goto err; 925 } 926 927 ret = fsl_elbc_chip_init(priv); 928 if (ret) 929 goto err; 930 931 priv->chip.controller->ops = &fsl_elbc_controller_ops; 932 ret = nand_scan(&priv->chip, 1); 933 if (ret) 934 goto err; 935 936 /* First look for RedBoot table or partitions on the command 937 * line, these take precedence over device tree information */ 938 ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0); 939 if (ret) 940 goto cleanup_nand; 941 942 pr_info("eLBC NAND device at 0x%llx, bank %d\n", 943 (unsigned long long)res.start, priv->bank); 944 945 return 0; 946 947 cleanup_nand: 948 nand_cleanup(&priv->chip); 949 err: 950 fsl_elbc_chip_remove(priv); 951 952 return ret; 953 } 954 955 static int fsl_elbc_nand_remove(struct platform_device *pdev) 956 { 957 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; 958 struct fsl_elbc_mtd *priv = dev_get_drvdata(&pdev->dev); 959 960 nand_release(&priv->chip); 961 fsl_elbc_chip_remove(priv); 962 963 mutex_lock(&fsl_elbc_nand_mutex); 964 elbc_fcm_ctrl->counter--; 965 if (!elbc_fcm_ctrl->counter) { 966 fsl_lbc_ctrl_dev->nand = NULL; 967 kfree(elbc_fcm_ctrl); 968 } 969 mutex_unlock(&fsl_elbc_nand_mutex); 970 971 return 0; 972 973 } 974 975 static const struct of_device_id fsl_elbc_nand_match[] = { 976 { .compatible = "fsl,elbc-fcm-nand", }, 977 {} 978 }; 979 MODULE_DEVICE_TABLE(of, fsl_elbc_nand_match); 980 981 static struct platform_driver fsl_elbc_nand_driver = { 982 .driver = { 983 .name = "fsl,elbc-fcm-nand", 984 .of_match_table = fsl_elbc_nand_match, 985 }, 986 .probe = fsl_elbc_nand_probe, 987 .remove = fsl_elbc_nand_remove, 988 }; 989 990 module_platform_driver(fsl_elbc_nand_driver); 991 992 MODULE_LICENSE("GPL"); 993 MODULE_AUTHOR("Freescale"); 994 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver"); 995