1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 Endless Mobile, Inc. 4 * Author: Carlo Caione <carlo@endlessm.com> 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Jerome Brunet <jbrunet@baylibre.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/irqchip.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 19 #define NUM_CHANNEL 8 20 #define MAX_INPUT_MUX 256 21 22 #define REG_EDGE_POL 0x00 23 #define REG_PIN_03_SEL 0x04 24 #define REG_PIN_47_SEL 0x08 25 #define REG_FILTER_SEL 0x0c 26 27 /* use for A1 like chips */ 28 #define REG_PIN_A1_SEL 0x04 29 30 /* 31 * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by 32 * bits 24 to 31. Tests on the actual HW show that these bits are 33 * stuck at 0. Bits 8 to 15 are responsive and have the expected 34 * effect. 35 */ 36 #define REG_EDGE_POL_EDGE(params, x) BIT((params)->edge_single_offset + (x)) 37 #define REG_EDGE_POL_LOW(params, x) BIT((params)->pol_low_offset + (x)) 38 #define REG_BOTH_EDGE(params, x) BIT((params)->edge_both_offset + (x)) 39 #define REG_EDGE_POL_MASK(params, x) ( \ 40 REG_EDGE_POL_EDGE(params, x) | \ 41 REG_EDGE_POL_LOW(params, x) | \ 42 REG_BOTH_EDGE(params, x)) 43 #define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8) 44 #define REG_FILTER_SEL_SHIFT(x) ((x) * 4) 45 46 struct meson_gpio_irq_controller; 47 static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, 48 unsigned int channel, unsigned long hwirq); 49 static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl); 50 static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, 51 unsigned int channel, 52 unsigned long hwirq); 53 static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl); 54 55 struct irq_ctl_ops { 56 void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl, 57 unsigned int channel, unsigned long hwirq); 58 void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl); 59 }; 60 61 struct meson_gpio_irq_params { 62 unsigned int nr_hwirq; 63 bool support_edge_both; 64 unsigned int edge_both_offset; 65 unsigned int edge_single_offset; 66 unsigned int pol_low_offset; 67 unsigned int pin_sel_mask; 68 struct irq_ctl_ops ops; 69 }; 70 71 #define INIT_MESON_COMMON(irqs, init, sel) \ 72 .nr_hwirq = irqs, \ 73 .ops = { \ 74 .gpio_irq_init = init, \ 75 .gpio_irq_sel_pin = sel, \ 76 }, 77 78 #define INIT_MESON8_COMMON_DATA(irqs) \ 79 INIT_MESON_COMMON(irqs, meson_gpio_irq_init_dummy, \ 80 meson8_gpio_irq_sel_pin) \ 81 .edge_single_offset = 0, \ 82 .pol_low_offset = 16, \ 83 .pin_sel_mask = 0xff, \ 84 85 #define INIT_MESON_A1_COMMON_DATA(irqs) \ 86 INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ 87 meson_a1_gpio_irq_sel_pin) \ 88 .support_edge_both = true, \ 89 .edge_both_offset = 16, \ 90 .edge_single_offset = 8, \ 91 .pol_low_offset = 0, \ 92 .pin_sel_mask = 0x7f, \ 93 94 static const struct meson_gpio_irq_params meson8_params = { 95 INIT_MESON8_COMMON_DATA(134) 96 }; 97 98 static const struct meson_gpio_irq_params meson8b_params = { 99 INIT_MESON8_COMMON_DATA(119) 100 }; 101 102 static const struct meson_gpio_irq_params gxbb_params = { 103 INIT_MESON8_COMMON_DATA(133) 104 }; 105 106 static const struct meson_gpio_irq_params gxl_params = { 107 INIT_MESON8_COMMON_DATA(110) 108 }; 109 110 static const struct meson_gpio_irq_params axg_params = { 111 INIT_MESON8_COMMON_DATA(100) 112 }; 113 114 static const struct meson_gpio_irq_params sm1_params = { 115 INIT_MESON8_COMMON_DATA(100) 116 .support_edge_both = true, 117 .edge_both_offset = 8, 118 }; 119 120 static const struct meson_gpio_irq_params a1_params = { 121 INIT_MESON_A1_COMMON_DATA(62) 122 }; 123 124 static const struct of_device_id meson_irq_gpio_matches[] = { 125 { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params }, 126 { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params }, 127 { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params }, 128 { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params }, 129 { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params }, 130 { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params }, 131 { .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params }, 132 { .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params }, 133 { } 134 }; 135 136 struct meson_gpio_irq_controller { 137 const struct meson_gpio_irq_params *params; 138 void __iomem *base; 139 u32 channel_irqs[NUM_CHANNEL]; 140 DECLARE_BITMAP(channel_map, NUM_CHANNEL); 141 spinlock_t lock; 142 }; 143 144 static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl, 145 unsigned int reg, u32 mask, u32 val) 146 { 147 u32 tmp; 148 149 tmp = readl_relaxed(ctl->base + reg); 150 tmp &= ~mask; 151 tmp |= val; 152 writel_relaxed(tmp, ctl->base + reg); 153 } 154 155 static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl) 156 { 157 } 158 159 static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, 160 unsigned int channel, unsigned long hwirq) 161 { 162 unsigned int reg_offset; 163 unsigned int bit_offset; 164 165 reg_offset = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL; 166 bit_offset = REG_PIN_SEL_SHIFT(channel); 167 168 meson_gpio_irq_update_bits(ctl, reg_offset, 169 ctl->params->pin_sel_mask << bit_offset, 170 hwirq << bit_offset); 171 } 172 173 static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, 174 unsigned int channel, 175 unsigned long hwirq) 176 { 177 unsigned int reg_offset; 178 unsigned int bit_offset; 179 180 bit_offset = ((channel % 2) == 0) ? 0 : 16; 181 reg_offset = REG_PIN_A1_SEL + ((channel / 2) << 2); 182 183 meson_gpio_irq_update_bits(ctl, reg_offset, 184 ctl->params->pin_sel_mask << bit_offset, 185 hwirq << bit_offset); 186 } 187 188 /* For a1 or later chips like a1 there is a switch to enable/disable irq */ 189 static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl) 190 { 191 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31)); 192 } 193 194 static int 195 meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl, 196 unsigned long hwirq, 197 u32 **channel_hwirq) 198 { 199 unsigned int idx; 200 201 spin_lock(&ctl->lock); 202 203 /* Find a free channel */ 204 idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL); 205 if (idx >= NUM_CHANNEL) { 206 spin_unlock(&ctl->lock); 207 pr_err("No channel available\n"); 208 return -ENOSPC; 209 } 210 211 /* Mark the channel as used */ 212 set_bit(idx, ctl->channel_map); 213 214 /* 215 * Setup the mux of the channel to route the signal of the pad 216 * to the appropriate input of the GIC 217 */ 218 ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq); 219 220 /* 221 * Get the hwirq number assigned to this channel through 222 * a pointer the channel_irq table. The added benifit of this 223 * method is that we can also retrieve the channel index with 224 * it, using the table base. 225 */ 226 *channel_hwirq = &(ctl->channel_irqs[idx]); 227 228 spin_unlock(&ctl->lock); 229 230 pr_debug("hwirq %lu assigned to channel %d - irq %u\n", 231 hwirq, idx, **channel_hwirq); 232 233 return 0; 234 } 235 236 static unsigned int 237 meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl, 238 u32 *channel_hwirq) 239 { 240 return channel_hwirq - ctl->channel_irqs; 241 } 242 243 static void 244 meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl, 245 u32 *channel_hwirq) 246 { 247 unsigned int idx; 248 249 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); 250 clear_bit(idx, ctl->channel_map); 251 } 252 253 static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl, 254 unsigned int type, 255 u32 *channel_hwirq) 256 { 257 u32 val = 0; 258 unsigned int idx; 259 const struct meson_gpio_irq_params *params; 260 261 params = ctl->params; 262 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); 263 264 /* 265 * The controller has a filter block to operate in either LEVEL or 266 * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and 267 * EDGE_FALLING support (which the GIC does not support), the filter 268 * block is also able to invert the input signal it gets before 269 * providing it to the GIC. 270 */ 271 type &= IRQ_TYPE_SENSE_MASK; 272 273 /* 274 * New controller support EDGE_BOTH trigger. This setting takes 275 * precedence over the other edge/polarity settings 276 */ 277 if (type == IRQ_TYPE_EDGE_BOTH) { 278 if (!params->support_edge_both) 279 return -EINVAL; 280 281 val |= REG_BOTH_EDGE(params, idx); 282 } else { 283 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) 284 val |= REG_EDGE_POL_EDGE(params, idx); 285 286 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) 287 val |= REG_EDGE_POL_LOW(params, idx); 288 } 289 290 spin_lock(&ctl->lock); 291 292 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, 293 REG_EDGE_POL_MASK(params, idx), val); 294 295 spin_unlock(&ctl->lock); 296 297 return 0; 298 } 299 300 static unsigned int meson_gpio_irq_type_output(unsigned int type) 301 { 302 unsigned int sense = type & IRQ_TYPE_SENSE_MASK; 303 304 type &= ~IRQ_TYPE_SENSE_MASK; 305 306 /* 307 * The polarity of the signal provided to the GIC should always 308 * be high. 309 */ 310 if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 311 type |= IRQ_TYPE_LEVEL_HIGH; 312 else 313 type |= IRQ_TYPE_EDGE_RISING; 314 315 return type; 316 } 317 318 static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type) 319 { 320 struct meson_gpio_irq_controller *ctl = data->domain->host_data; 321 u32 *channel_hwirq = irq_data_get_irq_chip_data(data); 322 int ret; 323 324 ret = meson_gpio_irq_type_setup(ctl, type, channel_hwirq); 325 if (ret) 326 return ret; 327 328 return irq_chip_set_type_parent(data, 329 meson_gpio_irq_type_output(type)); 330 } 331 332 static struct irq_chip meson_gpio_irq_chip = { 333 .name = "meson-gpio-irqchip", 334 .irq_mask = irq_chip_mask_parent, 335 .irq_unmask = irq_chip_unmask_parent, 336 .irq_eoi = irq_chip_eoi_parent, 337 .irq_set_type = meson_gpio_irq_set_type, 338 .irq_retrigger = irq_chip_retrigger_hierarchy, 339 #ifdef CONFIG_SMP 340 .irq_set_affinity = irq_chip_set_affinity_parent, 341 #endif 342 .flags = IRQCHIP_SET_TYPE_MASKED, 343 }; 344 345 static int meson_gpio_irq_domain_translate(struct irq_domain *domain, 346 struct irq_fwspec *fwspec, 347 unsigned long *hwirq, 348 unsigned int *type) 349 { 350 if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) { 351 *hwirq = fwspec->param[0]; 352 *type = fwspec->param[1]; 353 return 0; 354 } 355 356 return -EINVAL; 357 } 358 359 static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain, 360 unsigned int virq, 361 u32 hwirq, 362 unsigned int type) 363 { 364 struct irq_fwspec fwspec; 365 366 fwspec.fwnode = domain->parent->fwnode; 367 fwspec.param_count = 3; 368 fwspec.param[0] = 0; /* SPI */ 369 fwspec.param[1] = hwirq; 370 fwspec.param[2] = meson_gpio_irq_type_output(type); 371 372 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); 373 } 374 375 static int meson_gpio_irq_domain_alloc(struct irq_domain *domain, 376 unsigned int virq, 377 unsigned int nr_irqs, 378 void *data) 379 { 380 struct irq_fwspec *fwspec = data; 381 struct meson_gpio_irq_controller *ctl = domain->host_data; 382 unsigned long hwirq; 383 u32 *channel_hwirq; 384 unsigned int type; 385 int ret; 386 387 if (WARN_ON(nr_irqs != 1)) 388 return -EINVAL; 389 390 ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type); 391 if (ret) 392 return ret; 393 394 ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq); 395 if (ret) 396 return ret; 397 398 ret = meson_gpio_irq_allocate_gic_irq(domain, virq, 399 *channel_hwirq, type); 400 if (ret < 0) { 401 pr_err("failed to allocate gic irq %u\n", *channel_hwirq); 402 meson_gpio_irq_release_channel(ctl, channel_hwirq); 403 return ret; 404 } 405 406 irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 407 &meson_gpio_irq_chip, channel_hwirq); 408 409 return 0; 410 } 411 412 static void meson_gpio_irq_domain_free(struct irq_domain *domain, 413 unsigned int virq, 414 unsigned int nr_irqs) 415 { 416 struct meson_gpio_irq_controller *ctl = domain->host_data; 417 struct irq_data *irq_data; 418 u32 *channel_hwirq; 419 420 if (WARN_ON(nr_irqs != 1)) 421 return; 422 423 irq_domain_free_irqs_parent(domain, virq, 1); 424 425 irq_data = irq_domain_get_irq_data(domain, virq); 426 channel_hwirq = irq_data_get_irq_chip_data(irq_data); 427 428 meson_gpio_irq_release_channel(ctl, channel_hwirq); 429 } 430 431 static const struct irq_domain_ops meson_gpio_irq_domain_ops = { 432 .alloc = meson_gpio_irq_domain_alloc, 433 .free = meson_gpio_irq_domain_free, 434 .translate = meson_gpio_irq_domain_translate, 435 }; 436 437 static int __init meson_gpio_irq_parse_dt(struct device_node *node, 438 struct meson_gpio_irq_controller *ctl) 439 { 440 const struct of_device_id *match; 441 int ret; 442 443 match = of_match_node(meson_irq_gpio_matches, node); 444 if (!match) 445 return -ENODEV; 446 447 ctl->params = match->data; 448 449 ret = of_property_read_variable_u32_array(node, 450 "amlogic,channel-interrupts", 451 ctl->channel_irqs, 452 NUM_CHANNEL, 453 NUM_CHANNEL); 454 if (ret < 0) { 455 pr_err("can't get %d channel interrupts\n", NUM_CHANNEL); 456 return ret; 457 } 458 459 ctl->params->ops.gpio_irq_init(ctl); 460 461 return 0; 462 } 463 464 static int __init meson_gpio_irq_of_init(struct device_node *node, 465 struct device_node *parent) 466 { 467 struct irq_domain *domain, *parent_domain; 468 struct meson_gpio_irq_controller *ctl; 469 int ret; 470 471 if (!parent) { 472 pr_err("missing parent interrupt node\n"); 473 return -ENODEV; 474 } 475 476 parent_domain = irq_find_host(parent); 477 if (!parent_domain) { 478 pr_err("unable to obtain parent domain\n"); 479 return -ENXIO; 480 } 481 482 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); 483 if (!ctl) 484 return -ENOMEM; 485 486 spin_lock_init(&ctl->lock); 487 488 ctl->base = of_iomap(node, 0); 489 if (!ctl->base) { 490 ret = -ENOMEM; 491 goto free_ctl; 492 } 493 494 ret = meson_gpio_irq_parse_dt(node, ctl); 495 if (ret) 496 goto free_channel_irqs; 497 498 domain = irq_domain_create_hierarchy(parent_domain, 0, 499 ctl->params->nr_hwirq, 500 of_node_to_fwnode(node), 501 &meson_gpio_irq_domain_ops, 502 ctl); 503 if (!domain) { 504 pr_err("failed to add domain\n"); 505 ret = -ENODEV; 506 goto free_channel_irqs; 507 } 508 509 pr_info("%d to %d gpio interrupt mux initialized\n", 510 ctl->params->nr_hwirq, NUM_CHANNEL); 511 512 return 0; 513 514 free_channel_irqs: 515 iounmap(ctl->base); 516 free_ctl: 517 kfree(ctl); 518 519 return ret; 520 } 521 522 IRQCHIP_DECLARE(meson_gpio_intc, "amlogic,meson-gpio-intc", 523 meson_gpio_irq_of_init); 524