1 /* 2 ******************************************************************************* 3 ** O.S : Linux 4 ** FILE NAME : arcmsr_hba.c 5 ** BY : Nick Cheng, C.L. Huang 6 ** Description: SCSI RAID Device Driver for Areca RAID Controller 7 ******************************************************************************* 8 ** Copyright (C) 2002 - 2014, Areca Technology Corporation All rights reserved 9 ** 10 ** Web site: www.areca.com.tw 11 ** E-mail: support@areca.com.tw 12 ** 13 ** This program is free software; you can redistribute it and/or modify 14 ** it under the terms of the GNU General Public License version 2 as 15 ** published by the Free Software Foundation. 16 ** This program is distributed in the hope that it will be useful, 17 ** but WITHOUT ANY WARRANTY; without even the implied warranty of 18 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 ** GNU General Public License for more details. 20 ******************************************************************************* 21 ** Redistribution and use in source and binary forms, with or without 22 ** modification, are permitted provided that the following conditions 23 ** are met: 24 ** 1. Redistributions of source code must retain the above copyright 25 ** notice, this list of conditions and the following disclaimer. 26 ** 2. Redistributions in binary form must reproduce the above copyright 27 ** notice, this list of conditions and the following disclaimer in the 28 ** documentation and/or other materials provided with the distribution. 29 ** 3. The name of the author may not be used to endorse or promote products 30 ** derived from this software without specific prior written permission. 31 ** 32 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 33 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 34 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 35 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 36 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 37 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 39 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 41 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 ******************************************************************************* 43 ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr 44 ** Firmware Specification, see Documentation/scsi/arcmsr_spec.rst 45 ******************************************************************************* 46 */ 47 #include <linux/module.h> 48 #include <linux/reboot.h> 49 #include <linux/spinlock.h> 50 #include <linux/pci_ids.h> 51 #include <linux/interrupt.h> 52 #include <linux/moduleparam.h> 53 #include <linux/errno.h> 54 #include <linux/types.h> 55 #include <linux/delay.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/timer.h> 58 #include <linux/slab.h> 59 #include <linux/pci.h> 60 #include <linux/aer.h> 61 #include <linux/circ_buf.h> 62 #include <asm/dma.h> 63 #include <asm/io.h> 64 #include <linux/uaccess.h> 65 #include <scsi/scsi_host.h> 66 #include <scsi/scsi.h> 67 #include <scsi/scsi_cmnd.h> 68 #include <scsi/scsi_tcq.h> 69 #include <scsi/scsi_device.h> 70 #include <scsi/scsi_transport.h> 71 #include <scsi/scsicam.h> 72 #include "arcmsr.h" 73 MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>"); 74 MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver"); 75 MODULE_LICENSE("Dual BSD/GPL"); 76 MODULE_VERSION(ARCMSR_DRIVER_VERSION); 77 78 static int msix_enable = 1; 79 module_param(msix_enable, int, S_IRUGO); 80 MODULE_PARM_DESC(msix_enable, "Enable MSI-X interrupt(0 ~ 1), msix_enable=1(enable), =0(disable)"); 81 82 static int msi_enable = 1; 83 module_param(msi_enable, int, S_IRUGO); 84 MODULE_PARM_DESC(msi_enable, "Enable MSI interrupt(0 ~ 1), msi_enable=1(enable), =0(disable)"); 85 86 static int host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD; 87 module_param(host_can_queue, int, S_IRUGO); 88 MODULE_PARM_DESC(host_can_queue, " adapter queue depth(32 ~ 1024), default is 128"); 89 90 static int cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN; 91 module_param(cmd_per_lun, int, S_IRUGO); 92 MODULE_PARM_DESC(cmd_per_lun, " device queue depth(1 ~ 128), default is 32"); 93 94 static int dma_mask_64 = 0; 95 module_param(dma_mask_64, int, S_IRUGO); 96 MODULE_PARM_DESC(dma_mask_64, " set DMA mask to 64 bits(0 ~ 1), dma_mask_64=1(64 bits), =0(32 bits)"); 97 98 static int set_date_time = 0; 99 module_param(set_date_time, int, S_IRUGO); 100 MODULE_PARM_DESC(set_date_time, " send date, time to iop(0 ~ 1), set_date_time=1(enable), default(=0) is disable"); 101 102 #define ARCMSR_SLEEPTIME 10 103 #define ARCMSR_RETRYCOUNT 12 104 105 static wait_queue_head_t wait_q; 106 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, 107 struct scsi_cmnd *cmd); 108 static int arcmsr_iop_confirm(struct AdapterControlBlock *acb); 109 static int arcmsr_abort(struct scsi_cmnd *); 110 static int arcmsr_bus_reset(struct scsi_cmnd *); 111 static int arcmsr_bios_param(struct scsi_device *sdev, 112 struct block_device *bdev, sector_t capacity, int *info); 113 static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd); 114 static int arcmsr_probe(struct pci_dev *pdev, 115 const struct pci_device_id *id); 116 static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state); 117 static int arcmsr_resume(struct pci_dev *pdev); 118 static void arcmsr_remove(struct pci_dev *pdev); 119 static void arcmsr_shutdown(struct pci_dev *pdev); 120 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 121 static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb); 122 static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb); 123 static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb, 124 u32 intmask_org); 125 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 126 static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb); 127 static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb); 128 static void arcmsr_request_device_map(struct timer_list *t); 129 static void arcmsr_message_isr_bh_fn(struct work_struct *work); 130 static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb); 131 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 132 static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB); 133 static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb); 134 static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb); 135 static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb); 136 static void arcmsr_hardware_reset(struct AdapterControlBlock *acb); 137 static const char *arcmsr_info(struct Scsi_Host *); 138 static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb); 139 static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *); 140 static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb); 141 static void arcmsr_set_iop_datetime(struct timer_list *); 142 static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth) 143 { 144 if (queue_depth > ARCMSR_MAX_CMD_PERLUN) 145 queue_depth = ARCMSR_MAX_CMD_PERLUN; 146 return scsi_change_queue_depth(sdev, queue_depth); 147 } 148 149 static struct scsi_host_template arcmsr_scsi_host_template = { 150 .module = THIS_MODULE, 151 .name = "Areca SAS/SATA RAID driver", 152 .info = arcmsr_info, 153 .queuecommand = arcmsr_queue_command, 154 .eh_abort_handler = arcmsr_abort, 155 .eh_bus_reset_handler = arcmsr_bus_reset, 156 .bios_param = arcmsr_bios_param, 157 .change_queue_depth = arcmsr_adjust_disk_queue_depth, 158 .can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD, 159 .this_id = ARCMSR_SCSI_INITIATOR_ID, 160 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES, 161 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C, 162 .cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN, 163 .shost_attrs = arcmsr_host_attrs, 164 .no_write_same = 1, 165 }; 166 167 static struct pci_device_id arcmsr_device_id_table[] = { 168 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110), 169 .driver_data = ACB_ADAPTER_TYPE_A}, 170 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120), 171 .driver_data = ACB_ADAPTER_TYPE_A}, 172 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130), 173 .driver_data = ACB_ADAPTER_TYPE_A}, 174 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160), 175 .driver_data = ACB_ADAPTER_TYPE_A}, 176 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170), 177 .driver_data = ACB_ADAPTER_TYPE_A}, 178 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200), 179 .driver_data = ACB_ADAPTER_TYPE_B}, 180 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201), 181 .driver_data = ACB_ADAPTER_TYPE_B}, 182 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202), 183 .driver_data = ACB_ADAPTER_TYPE_B}, 184 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1203), 185 .driver_data = ACB_ADAPTER_TYPE_B}, 186 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210), 187 .driver_data = ACB_ADAPTER_TYPE_A}, 188 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214), 189 .driver_data = ACB_ADAPTER_TYPE_D}, 190 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220), 191 .driver_data = ACB_ADAPTER_TYPE_A}, 192 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230), 193 .driver_data = ACB_ADAPTER_TYPE_A}, 194 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260), 195 .driver_data = ACB_ADAPTER_TYPE_A}, 196 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270), 197 .driver_data = ACB_ADAPTER_TYPE_A}, 198 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280), 199 .driver_data = ACB_ADAPTER_TYPE_A}, 200 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380), 201 .driver_data = ACB_ADAPTER_TYPE_A}, 202 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381), 203 .driver_data = ACB_ADAPTER_TYPE_A}, 204 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680), 205 .driver_data = ACB_ADAPTER_TYPE_A}, 206 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681), 207 .driver_data = ACB_ADAPTER_TYPE_A}, 208 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880), 209 .driver_data = ACB_ADAPTER_TYPE_C}, 210 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1884), 211 .driver_data = ACB_ADAPTER_TYPE_E}, 212 {0, 0}, /* Terminating entry */ 213 }; 214 MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table); 215 216 static struct pci_driver arcmsr_pci_driver = { 217 .name = "arcmsr", 218 .id_table = arcmsr_device_id_table, 219 .probe = arcmsr_probe, 220 .remove = arcmsr_remove, 221 .suspend = arcmsr_suspend, 222 .resume = arcmsr_resume, 223 .shutdown = arcmsr_shutdown, 224 }; 225 /* 226 **************************************************************************** 227 **************************************************************************** 228 */ 229 230 static void arcmsr_free_io_queue(struct AdapterControlBlock *acb) 231 { 232 switch (acb->adapter_type) { 233 case ACB_ADAPTER_TYPE_B: 234 case ACB_ADAPTER_TYPE_D: 235 case ACB_ADAPTER_TYPE_E: { 236 dma_free_coherent(&acb->pdev->dev, acb->ioqueue_size, 237 acb->dma_coherent2, acb->dma_coherent_handle2); 238 break; 239 } 240 } 241 } 242 243 static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb) 244 { 245 struct pci_dev *pdev = acb->pdev; 246 switch (acb->adapter_type){ 247 case ACB_ADAPTER_TYPE_A:{ 248 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0)); 249 if (!acb->pmuA) { 250 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 251 return false; 252 } 253 break; 254 } 255 case ACB_ADAPTER_TYPE_B:{ 256 void __iomem *mem_base0, *mem_base1; 257 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0)); 258 if (!mem_base0) { 259 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 260 return false; 261 } 262 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2)); 263 if (!mem_base1) { 264 iounmap(mem_base0); 265 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 266 return false; 267 } 268 acb->mem_base0 = mem_base0; 269 acb->mem_base1 = mem_base1; 270 break; 271 } 272 case ACB_ADAPTER_TYPE_C:{ 273 acb->pmuC = ioremap(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1)); 274 if (!acb->pmuC) { 275 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 276 return false; 277 } 278 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 279 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/ 280 return true; 281 } 282 break; 283 } 284 case ACB_ADAPTER_TYPE_D: { 285 void __iomem *mem_base0; 286 unsigned long addr, range, flags; 287 288 addr = (unsigned long)pci_resource_start(pdev, 0); 289 range = pci_resource_len(pdev, 0); 290 flags = pci_resource_flags(pdev, 0); 291 mem_base0 = ioremap(addr, range); 292 if (!mem_base0) { 293 pr_notice("arcmsr%d: memory mapping region fail\n", 294 acb->host->host_no); 295 return false; 296 } 297 acb->mem_base0 = mem_base0; 298 break; 299 } 300 case ACB_ADAPTER_TYPE_E: { 301 acb->pmuE = ioremap(pci_resource_start(pdev, 1), 302 pci_resource_len(pdev, 1)); 303 if (!acb->pmuE) { 304 pr_notice("arcmsr%d: memory mapping region fail \n", 305 acb->host->host_no); 306 return false; 307 } 308 writel(0, &acb->pmuE->host_int_status); /*clear interrupt*/ 309 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell); /* synchronize doorbell to 0 */ 310 acb->in_doorbell = 0; 311 acb->out_doorbell = 0; 312 break; 313 } 314 } 315 return true; 316 } 317 318 static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb) 319 { 320 switch (acb->adapter_type) { 321 case ACB_ADAPTER_TYPE_A:{ 322 iounmap(acb->pmuA); 323 } 324 break; 325 case ACB_ADAPTER_TYPE_B:{ 326 iounmap(acb->mem_base0); 327 iounmap(acb->mem_base1); 328 } 329 330 break; 331 case ACB_ADAPTER_TYPE_C:{ 332 iounmap(acb->pmuC); 333 } 334 break; 335 case ACB_ADAPTER_TYPE_D: 336 iounmap(acb->mem_base0); 337 break; 338 case ACB_ADAPTER_TYPE_E: 339 iounmap(acb->pmuE); 340 break; 341 } 342 } 343 344 static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id) 345 { 346 irqreturn_t handle_state; 347 struct AdapterControlBlock *acb = dev_id; 348 349 handle_state = arcmsr_interrupt(acb); 350 return handle_state; 351 } 352 353 static int arcmsr_bios_param(struct scsi_device *sdev, 354 struct block_device *bdev, sector_t capacity, int *geom) 355 { 356 int heads, sectors, cylinders, total_capacity; 357 358 if (scsi_partsize(bdev, capacity, geom)) 359 return 0; 360 361 total_capacity = capacity; 362 heads = 64; 363 sectors = 32; 364 cylinders = total_capacity / (heads * sectors); 365 if (cylinders > 1024) { 366 heads = 255; 367 sectors = 63; 368 cylinders = total_capacity / (heads * sectors); 369 } 370 geom[0] = heads; 371 geom[1] = sectors; 372 geom[2] = cylinders; 373 return 0; 374 } 375 376 static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb) 377 { 378 struct MessageUnit_A __iomem *reg = acb->pmuA; 379 int i; 380 381 for (i = 0; i < 2000; i++) { 382 if (readl(®->outbound_intstatus) & 383 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 384 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, 385 ®->outbound_intstatus); 386 return true; 387 } 388 msleep(10); 389 } /* max 20 seconds */ 390 391 return false; 392 } 393 394 static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb) 395 { 396 struct MessageUnit_B *reg = acb->pmuB; 397 int i; 398 399 for (i = 0; i < 2000; i++) { 400 if (readl(reg->iop2drv_doorbell) 401 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 402 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, 403 reg->iop2drv_doorbell); 404 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, 405 reg->drv2iop_doorbell); 406 return true; 407 } 408 msleep(10); 409 } /* max 20 seconds */ 410 411 return false; 412 } 413 414 static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB) 415 { 416 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC; 417 int i; 418 419 for (i = 0; i < 2000; i++) { 420 if (readl(&phbcmu->outbound_doorbell) 421 & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 422 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, 423 &phbcmu->outbound_doorbell_clear); /*clear interrupt*/ 424 return true; 425 } 426 msleep(10); 427 } /* max 20 seconds */ 428 429 return false; 430 } 431 432 static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB) 433 { 434 struct MessageUnit_D *reg = pACB->pmuD; 435 int i; 436 437 for (i = 0; i < 2000; i++) { 438 if (readl(reg->outbound_doorbell) 439 & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) { 440 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, 441 reg->outbound_doorbell); 442 return true; 443 } 444 msleep(10); 445 } /* max 20 seconds */ 446 return false; 447 } 448 449 static bool arcmsr_hbaE_wait_msgint_ready(struct AdapterControlBlock *pACB) 450 { 451 int i; 452 uint32_t read_doorbell; 453 struct MessageUnit_E __iomem *phbcmu = pACB->pmuE; 454 455 for (i = 0; i < 2000; i++) { 456 read_doorbell = readl(&phbcmu->iobound_doorbell); 457 if ((read_doorbell ^ pACB->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 458 writel(0, &phbcmu->host_int_status); /*clear interrupt*/ 459 pACB->in_doorbell = read_doorbell; 460 return true; 461 } 462 msleep(10); 463 } /* max 20 seconds */ 464 return false; 465 } 466 467 static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb) 468 { 469 struct MessageUnit_A __iomem *reg = acb->pmuA; 470 int retry_count = 30; 471 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); 472 do { 473 if (arcmsr_hbaA_wait_msgint_ready(acb)) 474 break; 475 else { 476 retry_count--; 477 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \ 478 timeout, retry count down = %d \n", acb->host->host_no, retry_count); 479 } 480 } while (retry_count != 0); 481 } 482 483 static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb) 484 { 485 struct MessageUnit_B *reg = acb->pmuB; 486 int retry_count = 30; 487 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell); 488 do { 489 if (arcmsr_hbaB_wait_msgint_ready(acb)) 490 break; 491 else { 492 retry_count--; 493 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \ 494 timeout,retry count down = %d \n", acb->host->host_no, retry_count); 495 } 496 } while (retry_count != 0); 497 } 498 499 static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB) 500 { 501 struct MessageUnit_C __iomem *reg = pACB->pmuC; 502 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 503 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); 504 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 505 do { 506 if (arcmsr_hbaC_wait_msgint_ready(pACB)) { 507 break; 508 } else { 509 retry_count--; 510 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \ 511 timeout,retry count down = %d \n", pACB->host->host_no, retry_count); 512 } 513 } while (retry_count != 0); 514 return; 515 } 516 517 static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB) 518 { 519 int retry_count = 15; 520 struct MessageUnit_D *reg = pACB->pmuD; 521 522 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0); 523 do { 524 if (arcmsr_hbaD_wait_msgint_ready(pACB)) 525 break; 526 527 retry_count--; 528 pr_notice("arcmsr%d: wait 'flush adapter " 529 "cache' timeout, retry count down = %d\n", 530 pACB->host->host_no, retry_count); 531 } while (retry_count != 0); 532 } 533 534 static void arcmsr_hbaE_flush_cache(struct AdapterControlBlock *pACB) 535 { 536 int retry_count = 30; 537 struct MessageUnit_E __iomem *reg = pACB->pmuE; 538 539 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); 540 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 541 writel(pACB->out_doorbell, ®->iobound_doorbell); 542 do { 543 if (arcmsr_hbaE_wait_msgint_ready(pACB)) 544 break; 545 retry_count--; 546 pr_notice("arcmsr%d: wait 'flush adapter " 547 "cache' timeout, retry count down = %d\n", 548 pACB->host->host_no, retry_count); 549 } while (retry_count != 0); 550 } 551 552 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 553 { 554 switch (acb->adapter_type) { 555 556 case ACB_ADAPTER_TYPE_A: { 557 arcmsr_hbaA_flush_cache(acb); 558 } 559 break; 560 561 case ACB_ADAPTER_TYPE_B: { 562 arcmsr_hbaB_flush_cache(acb); 563 } 564 break; 565 case ACB_ADAPTER_TYPE_C: { 566 arcmsr_hbaC_flush_cache(acb); 567 } 568 break; 569 case ACB_ADAPTER_TYPE_D: 570 arcmsr_hbaD_flush_cache(acb); 571 break; 572 case ACB_ADAPTER_TYPE_E: 573 arcmsr_hbaE_flush_cache(acb); 574 break; 575 } 576 } 577 578 static void arcmsr_hbaB_assign_regAddr(struct AdapterControlBlock *acb) 579 { 580 struct MessageUnit_B *reg = acb->pmuB; 581 582 if (acb->pdev->device == PCI_DEVICE_ID_ARECA_1203) { 583 reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203); 584 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203); 585 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203); 586 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203); 587 } else { 588 reg->drv2iop_doorbell= MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL); 589 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK); 590 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL); 591 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK); 592 } 593 reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER); 594 reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER); 595 reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER); 596 } 597 598 static void arcmsr_hbaD_assign_regAddr(struct AdapterControlBlock *acb) 599 { 600 struct MessageUnit_D *reg = acb->pmuD; 601 602 reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID); 603 reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION); 604 reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK); 605 reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET); 606 reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST); 607 reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS); 608 reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE); 609 reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0); 610 reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1); 611 reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0); 612 reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1); 613 reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL); 614 reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL); 615 reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE); 616 reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW); 617 reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH); 618 reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER); 619 reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW); 620 reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH); 621 reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER); 622 reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER); 623 reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE); 624 reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE); 625 reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER); 626 reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER); 627 reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER); 628 } 629 630 static bool arcmsr_alloc_io_queue(struct AdapterControlBlock *acb) 631 { 632 bool rtn = true; 633 void *dma_coherent; 634 dma_addr_t dma_coherent_handle; 635 struct pci_dev *pdev = acb->pdev; 636 637 switch (acb->adapter_type) { 638 case ACB_ADAPTER_TYPE_B: { 639 acb->ioqueue_size = roundup(sizeof(struct MessageUnit_B), 32); 640 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size, 641 &dma_coherent_handle, GFP_KERNEL); 642 if (!dma_coherent) { 643 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no); 644 return false; 645 } 646 acb->dma_coherent_handle2 = dma_coherent_handle; 647 acb->dma_coherent2 = dma_coherent; 648 acb->pmuB = (struct MessageUnit_B *)dma_coherent; 649 arcmsr_hbaB_assign_regAddr(acb); 650 } 651 break; 652 case ACB_ADAPTER_TYPE_D: { 653 acb->ioqueue_size = roundup(sizeof(struct MessageUnit_D), 32); 654 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size, 655 &dma_coherent_handle, GFP_KERNEL); 656 if (!dma_coherent) { 657 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no); 658 return false; 659 } 660 acb->dma_coherent_handle2 = dma_coherent_handle; 661 acb->dma_coherent2 = dma_coherent; 662 acb->pmuD = (struct MessageUnit_D *)dma_coherent; 663 arcmsr_hbaD_assign_regAddr(acb); 664 } 665 break; 666 case ACB_ADAPTER_TYPE_E: { 667 uint32_t completeQ_size; 668 completeQ_size = sizeof(struct deliver_completeQ) * ARCMSR_MAX_HBE_DONEQUEUE + 128; 669 acb->ioqueue_size = roundup(completeQ_size, 32); 670 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size, 671 &dma_coherent_handle, GFP_KERNEL); 672 if (!dma_coherent){ 673 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no); 674 return false; 675 } 676 acb->dma_coherent_handle2 = dma_coherent_handle; 677 acb->dma_coherent2 = dma_coherent; 678 acb->pCompletionQ = dma_coherent; 679 acb->completionQ_entry = acb->ioqueue_size / sizeof(struct deliver_completeQ); 680 acb->doneq_index = 0; 681 } 682 break; 683 default: 684 break; 685 } 686 return rtn; 687 } 688 689 static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb) 690 { 691 struct pci_dev *pdev = acb->pdev; 692 void *dma_coherent; 693 dma_addr_t dma_coherent_handle; 694 struct CommandControlBlock *ccb_tmp; 695 int i = 0, j = 0; 696 unsigned long cdb_phyaddr, next_ccb_phy; 697 unsigned long roundup_ccbsize; 698 unsigned long max_xfer_len; 699 unsigned long max_sg_entrys; 700 uint32_t firm_config_version, curr_phy_upper32; 701 702 for (i = 0; i < ARCMSR_MAX_TARGETID; i++) 703 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++) 704 acb->devstate[i][j] = ARECA_RAID_GONE; 705 706 max_xfer_len = ARCMSR_MAX_XFER_LEN; 707 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES; 708 firm_config_version = acb->firm_cfg_version; 709 if((firm_config_version & 0xFF) >= 3){ 710 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */ 711 max_sg_entrys = (max_xfer_len/4096); 712 } 713 acb->host->max_sectors = max_xfer_len/512; 714 acb->host->sg_tablesize = max_sg_entrys; 715 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32); 716 acb->uncache_size = roundup_ccbsize * acb->maxFreeCCB; 717 acb->uncache_size += acb->ioqueue_size; 718 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL); 719 if(!dma_coherent){ 720 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no); 721 return -ENOMEM; 722 } 723 acb->dma_coherent = dma_coherent; 724 acb->dma_coherent_handle = dma_coherent_handle; 725 memset(dma_coherent, 0, acb->uncache_size); 726 acb->ccbsize = roundup_ccbsize; 727 ccb_tmp = dma_coherent; 728 curr_phy_upper32 = upper_32_bits(dma_coherent_handle); 729 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle; 730 for(i = 0; i < acb->maxFreeCCB; i++){ 731 cdb_phyaddr = (unsigned long)dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb); 732 switch (acb->adapter_type) { 733 case ACB_ADAPTER_TYPE_A: 734 case ACB_ADAPTER_TYPE_B: 735 ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5; 736 break; 737 case ACB_ADAPTER_TYPE_C: 738 case ACB_ADAPTER_TYPE_D: 739 case ACB_ADAPTER_TYPE_E: 740 ccb_tmp->cdb_phyaddr = cdb_phyaddr; 741 break; 742 } 743 acb->pccb_pool[i] = ccb_tmp; 744 ccb_tmp->acb = acb; 745 ccb_tmp->smid = (u32)i << 16; 746 INIT_LIST_HEAD(&ccb_tmp->list); 747 next_ccb_phy = dma_coherent_handle + roundup_ccbsize; 748 if (upper_32_bits(next_ccb_phy) != curr_phy_upper32) { 749 acb->maxFreeCCB = i; 750 acb->host->can_queue = i; 751 break; 752 } 753 else 754 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list); 755 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize); 756 dma_coherent_handle = next_ccb_phy; 757 } 758 acb->dma_coherent_handle2 = dma_coherent_handle; 759 acb->dma_coherent2 = ccb_tmp; 760 switch (acb->adapter_type) { 761 case ACB_ADAPTER_TYPE_B: 762 acb->pmuB = (struct MessageUnit_B *)acb->dma_coherent2; 763 arcmsr_hbaB_assign_regAddr(acb); 764 break; 765 case ACB_ADAPTER_TYPE_D: 766 acb->pmuD = (struct MessageUnit_D *)acb->dma_coherent2; 767 arcmsr_hbaD_assign_regAddr(acb); 768 break; 769 case ACB_ADAPTER_TYPE_E: 770 acb->pCompletionQ = acb->dma_coherent2; 771 acb->completionQ_entry = acb->ioqueue_size / sizeof(struct deliver_completeQ); 772 acb->doneq_index = 0; 773 break; 774 } 775 return 0; 776 } 777 778 static void arcmsr_message_isr_bh_fn(struct work_struct *work) 779 { 780 struct AdapterControlBlock *acb = container_of(work, 781 struct AdapterControlBlock, arcmsr_do_message_isr_bh); 782 char *acb_dev_map = (char *)acb->device_map; 783 uint32_t __iomem *signature = NULL; 784 char __iomem *devicemap = NULL; 785 int target, lun; 786 struct scsi_device *psdev; 787 char diff, temp; 788 789 acb->acb_flags &= ~ACB_F_MSG_GET_CONFIG; 790 switch (acb->adapter_type) { 791 case ACB_ADAPTER_TYPE_A: { 792 struct MessageUnit_A __iomem *reg = acb->pmuA; 793 794 signature = (uint32_t __iomem *)(®->message_rwbuffer[0]); 795 devicemap = (char __iomem *)(®->message_rwbuffer[21]); 796 break; 797 } 798 case ACB_ADAPTER_TYPE_B: { 799 struct MessageUnit_B *reg = acb->pmuB; 800 801 signature = (uint32_t __iomem *)(®->message_rwbuffer[0]); 802 devicemap = (char __iomem *)(®->message_rwbuffer[21]); 803 break; 804 } 805 case ACB_ADAPTER_TYPE_C: { 806 struct MessageUnit_C __iomem *reg = acb->pmuC; 807 808 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); 809 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); 810 break; 811 } 812 case ACB_ADAPTER_TYPE_D: { 813 struct MessageUnit_D *reg = acb->pmuD; 814 815 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); 816 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); 817 break; 818 } 819 case ACB_ADAPTER_TYPE_E: { 820 struct MessageUnit_E __iomem *reg = acb->pmuE; 821 822 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); 823 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); 824 break; 825 } 826 } 827 atomic_inc(&acb->rq_map_token); 828 if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG) 829 return; 830 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; 831 target++) { 832 temp = readb(devicemap); 833 diff = (*acb_dev_map) ^ temp; 834 if (diff != 0) { 835 *acb_dev_map = temp; 836 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; 837 lun++) { 838 if ((diff & 0x01) == 1 && 839 (temp & 0x01) == 1) { 840 scsi_add_device(acb->host, 841 0, target, lun); 842 } else if ((diff & 0x01) == 1 843 && (temp & 0x01) == 0) { 844 psdev = scsi_device_lookup(acb->host, 845 0, target, lun); 846 if (psdev != NULL) { 847 scsi_remove_device(psdev); 848 scsi_device_put(psdev); 849 } 850 } 851 temp >>= 1; 852 diff >>= 1; 853 } 854 } 855 devicemap++; 856 acb_dev_map++; 857 } 858 } 859 860 static int 861 arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb) 862 { 863 unsigned long flags; 864 int nvec, i; 865 866 if (msix_enable == 0) 867 goto msi_int0; 868 nvec = pci_alloc_irq_vectors(pdev, 1, ARCMST_NUM_MSIX_VECTORS, 869 PCI_IRQ_MSIX); 870 if (nvec > 0) { 871 pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no); 872 flags = 0; 873 } else { 874 msi_int0: 875 if (msi_enable == 1) { 876 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 877 if (nvec == 1) { 878 dev_info(&pdev->dev, "msi enabled\n"); 879 goto msi_int1; 880 } 881 } 882 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY); 883 if (nvec < 1) 884 return FAILED; 885 msi_int1: 886 flags = IRQF_SHARED; 887 } 888 889 acb->vector_count = nvec; 890 for (i = 0; i < nvec; i++) { 891 if (request_irq(pci_irq_vector(pdev, i), arcmsr_do_interrupt, 892 flags, "arcmsr", acb)) { 893 pr_warn("arcmsr%d: request_irq =%d failed!\n", 894 acb->host->host_no, pci_irq_vector(pdev, i)); 895 goto out_free_irq; 896 } 897 } 898 899 return SUCCESS; 900 out_free_irq: 901 while (--i >= 0) 902 free_irq(pci_irq_vector(pdev, i), acb); 903 pci_free_irq_vectors(pdev); 904 return FAILED; 905 } 906 907 static void arcmsr_init_get_devmap_timer(struct AdapterControlBlock *pacb) 908 { 909 INIT_WORK(&pacb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn); 910 atomic_set(&pacb->rq_map_token, 16); 911 atomic_set(&pacb->ante_token_value, 16); 912 pacb->fw_flag = FW_NORMAL; 913 timer_setup(&pacb->eternal_timer, arcmsr_request_device_map, 0); 914 pacb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ); 915 add_timer(&pacb->eternal_timer); 916 } 917 918 static void arcmsr_init_set_datetime_timer(struct AdapterControlBlock *pacb) 919 { 920 timer_setup(&pacb->refresh_timer, arcmsr_set_iop_datetime, 0); 921 pacb->refresh_timer.expires = jiffies + msecs_to_jiffies(60 * 1000); 922 add_timer(&pacb->refresh_timer); 923 } 924 925 static int arcmsr_set_dma_mask(struct AdapterControlBlock *acb) 926 { 927 struct pci_dev *pcidev = acb->pdev; 928 929 if (IS_DMA64) { 930 if (((acb->adapter_type == ACB_ADAPTER_TYPE_A) && !dma_mask_64) || 931 dma_set_mask(&pcidev->dev, DMA_BIT_MASK(64))) 932 goto dma32; 933 if (dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(64)) || 934 dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64))) { 935 printk("arcmsr: set DMA 64 mask failed\n"); 936 return -ENXIO; 937 } 938 } else { 939 dma32: 940 if (dma_set_mask(&pcidev->dev, DMA_BIT_MASK(32)) || 941 dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(32)) || 942 dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32))) { 943 printk("arcmsr: set DMA 32-bit mask failed\n"); 944 return -ENXIO; 945 } 946 } 947 return 0; 948 } 949 950 static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id) 951 { 952 struct Scsi_Host *host; 953 struct AdapterControlBlock *acb; 954 uint8_t bus,dev_fun; 955 int error; 956 error = pci_enable_device(pdev); 957 if(error){ 958 return -ENODEV; 959 } 960 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock)); 961 if(!host){ 962 goto pci_disable_dev; 963 } 964 init_waitqueue_head(&wait_q); 965 bus = pdev->bus->number; 966 dev_fun = pdev->devfn; 967 acb = (struct AdapterControlBlock *) host->hostdata; 968 memset(acb,0,sizeof(struct AdapterControlBlock)); 969 acb->pdev = pdev; 970 acb->adapter_type = id->driver_data; 971 if (arcmsr_set_dma_mask(acb)) 972 goto scsi_host_release; 973 acb->host = host; 974 host->max_lun = ARCMSR_MAX_TARGETLUN; 975 host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/ 976 host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/ 977 if ((host_can_queue < ARCMSR_MIN_OUTSTANDING_CMD) || (host_can_queue > ARCMSR_MAX_OUTSTANDING_CMD)) 978 host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD; 979 host->can_queue = host_can_queue; /* max simultaneous cmds */ 980 if ((cmd_per_lun < ARCMSR_MIN_CMD_PERLUN) || (cmd_per_lun > ARCMSR_MAX_CMD_PERLUN)) 981 cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN; 982 host->cmd_per_lun = cmd_per_lun; 983 host->this_id = ARCMSR_SCSI_INITIATOR_ID; 984 host->unique_id = (bus << 8) | dev_fun; 985 pci_set_drvdata(pdev, host); 986 pci_set_master(pdev); 987 error = pci_request_regions(pdev, "arcmsr"); 988 if(error){ 989 goto scsi_host_release; 990 } 991 spin_lock_init(&acb->eh_lock); 992 spin_lock_init(&acb->ccblist_lock); 993 spin_lock_init(&acb->postq_lock); 994 spin_lock_init(&acb->doneq_lock); 995 spin_lock_init(&acb->rqbuffer_lock); 996 spin_lock_init(&acb->wqbuffer_lock); 997 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 998 ACB_F_MESSAGE_RQBUFFER_CLEARED | 999 ACB_F_MESSAGE_WQBUFFER_READED); 1000 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 1001 INIT_LIST_HEAD(&acb->ccb_free_list); 1002 error = arcmsr_remap_pciregion(acb); 1003 if(!error){ 1004 goto pci_release_regs; 1005 } 1006 error = arcmsr_alloc_io_queue(acb); 1007 if (!error) 1008 goto unmap_pci_region; 1009 error = arcmsr_get_firmware_spec(acb); 1010 if(!error){ 1011 goto free_hbb_mu; 1012 } 1013 arcmsr_free_io_queue(acb); 1014 error = arcmsr_alloc_ccb_pool(acb); 1015 if(error){ 1016 goto unmap_pci_region; 1017 } 1018 error = scsi_add_host(host, &pdev->dev); 1019 if(error){ 1020 goto free_ccb_pool; 1021 } 1022 if (arcmsr_request_irq(pdev, acb) == FAILED) 1023 goto scsi_host_remove; 1024 arcmsr_iop_init(acb); 1025 arcmsr_init_get_devmap_timer(acb); 1026 if (set_date_time) 1027 arcmsr_init_set_datetime_timer(acb); 1028 if(arcmsr_alloc_sysfs_attr(acb)) 1029 goto out_free_sysfs; 1030 scsi_scan_host(host); 1031 return 0; 1032 out_free_sysfs: 1033 if (set_date_time) 1034 del_timer_sync(&acb->refresh_timer); 1035 del_timer_sync(&acb->eternal_timer); 1036 flush_work(&acb->arcmsr_do_message_isr_bh); 1037 arcmsr_stop_adapter_bgrb(acb); 1038 arcmsr_flush_adapter_cache(acb); 1039 arcmsr_free_irq(pdev, acb); 1040 scsi_host_remove: 1041 scsi_remove_host(host); 1042 free_ccb_pool: 1043 arcmsr_free_ccb_pool(acb); 1044 goto unmap_pci_region; 1045 free_hbb_mu: 1046 arcmsr_free_io_queue(acb); 1047 unmap_pci_region: 1048 arcmsr_unmap_pciregion(acb); 1049 pci_release_regs: 1050 pci_release_regions(pdev); 1051 scsi_host_release: 1052 scsi_host_put(host); 1053 pci_disable_dev: 1054 pci_disable_device(pdev); 1055 return -ENODEV; 1056 } 1057 1058 static void arcmsr_free_irq(struct pci_dev *pdev, 1059 struct AdapterControlBlock *acb) 1060 { 1061 int i; 1062 1063 for (i = 0; i < acb->vector_count; i++) 1064 free_irq(pci_irq_vector(pdev, i), acb); 1065 pci_free_irq_vectors(pdev); 1066 } 1067 1068 static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state) 1069 { 1070 uint32_t intmask_org; 1071 struct Scsi_Host *host = pci_get_drvdata(pdev); 1072 struct AdapterControlBlock *acb = 1073 (struct AdapterControlBlock *)host->hostdata; 1074 1075 intmask_org = arcmsr_disable_outbound_ints(acb); 1076 arcmsr_free_irq(pdev, acb); 1077 del_timer_sync(&acb->eternal_timer); 1078 if (set_date_time) 1079 del_timer_sync(&acb->refresh_timer); 1080 flush_work(&acb->arcmsr_do_message_isr_bh); 1081 arcmsr_stop_adapter_bgrb(acb); 1082 arcmsr_flush_adapter_cache(acb); 1083 pci_set_drvdata(pdev, host); 1084 pci_save_state(pdev); 1085 pci_disable_device(pdev); 1086 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1087 return 0; 1088 } 1089 1090 static int arcmsr_resume(struct pci_dev *pdev) 1091 { 1092 struct Scsi_Host *host = pci_get_drvdata(pdev); 1093 struct AdapterControlBlock *acb = 1094 (struct AdapterControlBlock *)host->hostdata; 1095 1096 pci_set_power_state(pdev, PCI_D0); 1097 pci_enable_wake(pdev, PCI_D0, 0); 1098 pci_restore_state(pdev); 1099 if (pci_enable_device(pdev)) { 1100 pr_warn("%s: pci_enable_device error\n", __func__); 1101 return -ENODEV; 1102 } 1103 if (arcmsr_set_dma_mask(acb)) 1104 goto controller_unregister; 1105 pci_set_master(pdev); 1106 if (arcmsr_request_irq(pdev, acb) == FAILED) 1107 goto controller_stop; 1108 switch (acb->adapter_type) { 1109 case ACB_ADAPTER_TYPE_B: { 1110 struct MessageUnit_B *reg = acb->pmuB; 1111 uint32_t i; 1112 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 1113 reg->post_qbuffer[i] = 0; 1114 reg->done_qbuffer[i] = 0; 1115 } 1116 reg->postq_index = 0; 1117 reg->doneq_index = 0; 1118 break; 1119 } 1120 case ACB_ADAPTER_TYPE_E: 1121 writel(0, &acb->pmuE->host_int_status); 1122 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell); 1123 acb->in_doorbell = 0; 1124 acb->out_doorbell = 0; 1125 acb->doneq_index = 0; 1126 break; 1127 } 1128 arcmsr_iop_init(acb); 1129 arcmsr_init_get_devmap_timer(acb); 1130 if (set_date_time) 1131 arcmsr_init_set_datetime_timer(acb); 1132 return 0; 1133 controller_stop: 1134 arcmsr_stop_adapter_bgrb(acb); 1135 arcmsr_flush_adapter_cache(acb); 1136 controller_unregister: 1137 scsi_remove_host(host); 1138 arcmsr_free_ccb_pool(acb); 1139 arcmsr_unmap_pciregion(acb); 1140 pci_release_regions(pdev); 1141 scsi_host_put(host); 1142 pci_disable_device(pdev); 1143 return -ENODEV; 1144 } 1145 1146 static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb) 1147 { 1148 struct MessageUnit_A __iomem *reg = acb->pmuA; 1149 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); 1150 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 1151 printk(KERN_NOTICE 1152 "arcmsr%d: wait 'abort all outstanding command' timeout\n" 1153 , acb->host->host_no); 1154 return false; 1155 } 1156 return true; 1157 } 1158 1159 static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb) 1160 { 1161 struct MessageUnit_B *reg = acb->pmuB; 1162 1163 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell); 1164 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 1165 printk(KERN_NOTICE 1166 "arcmsr%d: wait 'abort all outstanding command' timeout\n" 1167 , acb->host->host_no); 1168 return false; 1169 } 1170 return true; 1171 } 1172 static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB) 1173 { 1174 struct MessageUnit_C __iomem *reg = pACB->pmuC; 1175 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); 1176 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 1177 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 1178 printk(KERN_NOTICE 1179 "arcmsr%d: wait 'abort all outstanding command' timeout\n" 1180 , pACB->host->host_no); 1181 return false; 1182 } 1183 return true; 1184 } 1185 1186 static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB) 1187 { 1188 struct MessageUnit_D *reg = pACB->pmuD; 1189 1190 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0); 1191 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) { 1192 pr_notice("arcmsr%d: wait 'abort all outstanding " 1193 "command' timeout\n", pACB->host->host_no); 1194 return false; 1195 } 1196 return true; 1197 } 1198 1199 static uint8_t arcmsr_hbaE_abort_allcmd(struct AdapterControlBlock *pACB) 1200 { 1201 struct MessageUnit_E __iomem *reg = pACB->pmuE; 1202 1203 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); 1204 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1205 writel(pACB->out_doorbell, ®->iobound_doorbell); 1206 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 1207 pr_notice("arcmsr%d: wait 'abort all outstanding " 1208 "command' timeout\n", pACB->host->host_no); 1209 return false; 1210 } 1211 return true; 1212 } 1213 1214 static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 1215 { 1216 uint8_t rtnval = 0; 1217 switch (acb->adapter_type) { 1218 case ACB_ADAPTER_TYPE_A: { 1219 rtnval = arcmsr_hbaA_abort_allcmd(acb); 1220 } 1221 break; 1222 1223 case ACB_ADAPTER_TYPE_B: { 1224 rtnval = arcmsr_hbaB_abort_allcmd(acb); 1225 } 1226 break; 1227 1228 case ACB_ADAPTER_TYPE_C: { 1229 rtnval = arcmsr_hbaC_abort_allcmd(acb); 1230 } 1231 break; 1232 1233 case ACB_ADAPTER_TYPE_D: 1234 rtnval = arcmsr_hbaD_abort_allcmd(acb); 1235 break; 1236 case ACB_ADAPTER_TYPE_E: 1237 rtnval = arcmsr_hbaE_abort_allcmd(acb); 1238 break; 1239 } 1240 return rtnval; 1241 } 1242 1243 static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb) 1244 { 1245 struct scsi_cmnd *pcmd = ccb->pcmd; 1246 1247 scsi_dma_unmap(pcmd); 1248 } 1249 1250 static void arcmsr_ccb_complete(struct CommandControlBlock *ccb) 1251 { 1252 struct AdapterControlBlock *acb = ccb->acb; 1253 struct scsi_cmnd *pcmd = ccb->pcmd; 1254 unsigned long flags; 1255 atomic_dec(&acb->ccboutstandingcount); 1256 arcmsr_pci_unmap_dma(ccb); 1257 ccb->startdone = ARCMSR_CCB_DONE; 1258 spin_lock_irqsave(&acb->ccblist_lock, flags); 1259 list_add_tail(&ccb->list, &acb->ccb_free_list); 1260 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 1261 pcmd->scsi_done(pcmd); 1262 } 1263 1264 static void arcmsr_report_sense_info(struct CommandControlBlock *ccb) 1265 { 1266 1267 struct scsi_cmnd *pcmd = ccb->pcmd; 1268 struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer; 1269 pcmd->result = (DID_OK << 16) | (CHECK_CONDITION << 1); 1270 if (sensebuffer) { 1271 int sense_data_length = 1272 sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE 1273 ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE; 1274 memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE); 1275 memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length); 1276 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS; 1277 sensebuffer->Valid = 1; 1278 pcmd->result |= (DRIVER_SENSE << 24); 1279 } 1280 } 1281 1282 static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb) 1283 { 1284 u32 orig_mask = 0; 1285 switch (acb->adapter_type) { 1286 case ACB_ADAPTER_TYPE_A : { 1287 struct MessageUnit_A __iomem *reg = acb->pmuA; 1288 orig_mask = readl(®->outbound_intmask); 1289 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \ 1290 ®->outbound_intmask); 1291 } 1292 break; 1293 case ACB_ADAPTER_TYPE_B : { 1294 struct MessageUnit_B *reg = acb->pmuB; 1295 orig_mask = readl(reg->iop2drv_doorbell_mask); 1296 writel(0, reg->iop2drv_doorbell_mask); 1297 } 1298 break; 1299 case ACB_ADAPTER_TYPE_C:{ 1300 struct MessageUnit_C __iomem *reg = acb->pmuC; 1301 /* disable all outbound interrupt */ 1302 orig_mask = readl(®->host_int_mask); /* disable outbound message0 int */ 1303 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask); 1304 } 1305 break; 1306 case ACB_ADAPTER_TYPE_D: { 1307 struct MessageUnit_D *reg = acb->pmuD; 1308 /* disable all outbound interrupt */ 1309 writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable); 1310 } 1311 break; 1312 case ACB_ADAPTER_TYPE_E: { 1313 struct MessageUnit_E __iomem *reg = acb->pmuE; 1314 orig_mask = readl(®->host_int_mask); 1315 writel(orig_mask | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, ®->host_int_mask); 1316 readl(®->host_int_mask); /* Dummy readl to force pci flush */ 1317 } 1318 break; 1319 } 1320 return orig_mask; 1321 } 1322 1323 static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb, 1324 struct CommandControlBlock *ccb, bool error) 1325 { 1326 uint8_t id, lun; 1327 id = ccb->pcmd->device->id; 1328 lun = ccb->pcmd->device->lun; 1329 if (!error) { 1330 if (acb->devstate[id][lun] == ARECA_RAID_GONE) 1331 acb->devstate[id][lun] = ARECA_RAID_GOOD; 1332 ccb->pcmd->result = DID_OK << 16; 1333 arcmsr_ccb_complete(ccb); 1334 }else{ 1335 switch (ccb->arcmsr_cdb.DeviceStatus) { 1336 case ARCMSR_DEV_SELECT_TIMEOUT: { 1337 acb->devstate[id][lun] = ARECA_RAID_GONE; 1338 ccb->pcmd->result = DID_NO_CONNECT << 16; 1339 arcmsr_ccb_complete(ccb); 1340 } 1341 break; 1342 1343 case ARCMSR_DEV_ABORTED: 1344 1345 case ARCMSR_DEV_INIT_FAIL: { 1346 acb->devstate[id][lun] = ARECA_RAID_GONE; 1347 ccb->pcmd->result = DID_BAD_TARGET << 16; 1348 arcmsr_ccb_complete(ccb); 1349 } 1350 break; 1351 1352 case ARCMSR_DEV_CHECK_CONDITION: { 1353 acb->devstate[id][lun] = ARECA_RAID_GOOD; 1354 arcmsr_report_sense_info(ccb); 1355 arcmsr_ccb_complete(ccb); 1356 } 1357 break; 1358 1359 default: 1360 printk(KERN_NOTICE 1361 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \ 1362 but got unknown DeviceStatus = 0x%x \n" 1363 , acb->host->host_no 1364 , id 1365 , lun 1366 , ccb->arcmsr_cdb.DeviceStatus); 1367 acb->devstate[id][lun] = ARECA_RAID_GONE; 1368 ccb->pcmd->result = DID_NO_CONNECT << 16; 1369 arcmsr_ccb_complete(ccb); 1370 break; 1371 } 1372 } 1373 } 1374 1375 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error) 1376 { 1377 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) { 1378 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 1379 struct scsi_cmnd *abortcmd = pCCB->pcmd; 1380 if (abortcmd) { 1381 abortcmd->result |= DID_ABORT << 16; 1382 arcmsr_ccb_complete(pCCB); 1383 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n", 1384 acb->host->host_no, pCCB); 1385 } 1386 return; 1387 } 1388 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \ 1389 done acb = '0x%p'" 1390 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x" 1391 " ccboutstandingcount = %d \n" 1392 , acb->host->host_no 1393 , acb 1394 , pCCB 1395 , pCCB->acb 1396 , pCCB->startdone 1397 , atomic_read(&acb->ccboutstandingcount)); 1398 return; 1399 } 1400 arcmsr_report_ccb_state(acb, pCCB, error); 1401 } 1402 1403 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 1404 { 1405 int i = 0; 1406 uint32_t flag_ccb; 1407 struct ARCMSR_CDB *pARCMSR_CDB; 1408 bool error; 1409 struct CommandControlBlock *pCCB; 1410 unsigned long ccb_cdb_phy, cdb_phy_hipart; 1411 1412 switch (acb->adapter_type) { 1413 1414 case ACB_ADAPTER_TYPE_A: { 1415 struct MessageUnit_A __iomem *reg = acb->pmuA; 1416 uint32_t outbound_intstatus; 1417 outbound_intstatus = readl(®->outbound_intstatus) & 1418 acb->outbound_int_enable; 1419 /*clear and abort all outbound posted Q*/ 1420 writel(outbound_intstatus, ®->outbound_intstatus);/*clear interrupt*/ 1421 while(((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF) 1422 && (i++ < acb->maxOutstanding)) { 1423 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff; 1424 if (acb->cdb_phyadd_hipart) 1425 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 1426 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy); 1427 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 1428 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 1429 arcmsr_drain_donequeue(acb, pCCB, error); 1430 } 1431 } 1432 break; 1433 1434 case ACB_ADAPTER_TYPE_B: { 1435 struct MessageUnit_B *reg = acb->pmuB; 1436 /*clear all outbound posted Q*/ 1437 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */ 1438 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 1439 flag_ccb = reg->done_qbuffer[i]; 1440 if (flag_ccb != 0) { 1441 reg->done_qbuffer[i] = 0; 1442 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff; 1443 if (acb->cdb_phyadd_hipart) 1444 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 1445 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy); 1446 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 1447 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 1448 arcmsr_drain_donequeue(acb, pCCB, error); 1449 } 1450 reg->post_qbuffer[i] = 0; 1451 } 1452 reg->doneq_index = 0; 1453 reg->postq_index = 0; 1454 } 1455 break; 1456 case ACB_ADAPTER_TYPE_C: { 1457 struct MessageUnit_C __iomem *reg = acb->pmuC; 1458 while ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < acb->maxOutstanding)) { 1459 /*need to do*/ 1460 flag_ccb = readl(®->outbound_queueport_low); 1461 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 1462 if (acb->cdb_phyadd_hipart) 1463 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 1464 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy); 1465 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 1466 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 1467 arcmsr_drain_donequeue(acb, pCCB, error); 1468 } 1469 } 1470 break; 1471 case ACB_ADAPTER_TYPE_D: { 1472 struct MessageUnit_D *pmu = acb->pmuD; 1473 uint32_t outbound_write_pointer; 1474 uint32_t doneq_index, index_stripped, addressLow, residual, toggle; 1475 unsigned long flags; 1476 1477 residual = atomic_read(&acb->ccboutstandingcount); 1478 for (i = 0; i < residual; i++) { 1479 spin_lock_irqsave(&acb->doneq_lock, flags); 1480 outbound_write_pointer = 1481 pmu->done_qbuffer[0].addressLow + 1; 1482 doneq_index = pmu->doneq_index; 1483 if ((doneq_index & 0xFFF) != 1484 (outbound_write_pointer & 0xFFF)) { 1485 toggle = doneq_index & 0x4000; 1486 index_stripped = (doneq_index & 0xFFF) + 1; 1487 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE; 1488 pmu->doneq_index = index_stripped ? (index_stripped | toggle) : 1489 ((toggle ^ 0x4000) + 1); 1490 doneq_index = pmu->doneq_index; 1491 spin_unlock_irqrestore(&acb->doneq_lock, flags); 1492 cdb_phy_hipart = pmu->done_qbuffer[doneq_index & 1493 0xFFF].addressHigh; 1494 addressLow = pmu->done_qbuffer[doneq_index & 1495 0xFFF].addressLow; 1496 ccb_cdb_phy = (addressLow & 0xFFFFFFF0); 1497 if (acb->cdb_phyadd_hipart) 1498 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 1499 pARCMSR_CDB = (struct ARCMSR_CDB *) 1500 (acb->vir2phy_offset + ccb_cdb_phy); 1501 pCCB = container_of(pARCMSR_CDB, 1502 struct CommandControlBlock, arcmsr_cdb); 1503 error = (addressLow & 1504 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? 1505 true : false; 1506 arcmsr_drain_donequeue(acb, pCCB, error); 1507 writel(doneq_index, 1508 pmu->outboundlist_read_pointer); 1509 } else { 1510 spin_unlock_irqrestore(&acb->doneq_lock, flags); 1511 mdelay(10); 1512 } 1513 } 1514 pmu->postq_index = 0; 1515 pmu->doneq_index = 0x40FF; 1516 } 1517 break; 1518 case ACB_ADAPTER_TYPE_E: 1519 arcmsr_hbaE_postqueue_isr(acb); 1520 break; 1521 } 1522 } 1523 1524 static void arcmsr_remove_scsi_devices(struct AdapterControlBlock *acb) 1525 { 1526 char *acb_dev_map = (char *)acb->device_map; 1527 int target, lun, i; 1528 struct scsi_device *psdev; 1529 struct CommandControlBlock *ccb; 1530 char temp; 1531 1532 for (i = 0; i < acb->maxFreeCCB; i++) { 1533 ccb = acb->pccb_pool[i]; 1534 if (ccb->startdone == ARCMSR_CCB_START) { 1535 ccb->pcmd->result = DID_NO_CONNECT << 16; 1536 arcmsr_pci_unmap_dma(ccb); 1537 ccb->pcmd->scsi_done(ccb->pcmd); 1538 } 1539 } 1540 for (target = 0; target < ARCMSR_MAX_TARGETID; target++) { 1541 temp = *acb_dev_map; 1542 if (temp) { 1543 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) { 1544 if (temp & 1) { 1545 psdev = scsi_device_lookup(acb->host, 1546 0, target, lun); 1547 if (psdev != NULL) { 1548 scsi_remove_device(psdev); 1549 scsi_device_put(psdev); 1550 } 1551 } 1552 temp >>= 1; 1553 } 1554 *acb_dev_map = 0; 1555 } 1556 acb_dev_map++; 1557 } 1558 } 1559 1560 static void arcmsr_free_pcidev(struct AdapterControlBlock *acb) 1561 { 1562 struct pci_dev *pdev; 1563 struct Scsi_Host *host; 1564 1565 host = acb->host; 1566 arcmsr_free_sysfs_attr(acb); 1567 scsi_remove_host(host); 1568 flush_work(&acb->arcmsr_do_message_isr_bh); 1569 del_timer_sync(&acb->eternal_timer); 1570 if (set_date_time) 1571 del_timer_sync(&acb->refresh_timer); 1572 pdev = acb->pdev; 1573 arcmsr_free_irq(pdev, acb); 1574 arcmsr_free_ccb_pool(acb); 1575 arcmsr_unmap_pciregion(acb); 1576 pci_release_regions(pdev); 1577 scsi_host_put(host); 1578 pci_disable_device(pdev); 1579 } 1580 1581 static void arcmsr_remove(struct pci_dev *pdev) 1582 { 1583 struct Scsi_Host *host = pci_get_drvdata(pdev); 1584 struct AdapterControlBlock *acb = 1585 (struct AdapterControlBlock *) host->hostdata; 1586 int poll_count = 0; 1587 uint16_t dev_id; 1588 1589 pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id); 1590 if (dev_id == 0xffff) { 1591 acb->acb_flags &= ~ACB_F_IOP_INITED; 1592 acb->acb_flags |= ACB_F_ADAPTER_REMOVED; 1593 arcmsr_remove_scsi_devices(acb); 1594 arcmsr_free_pcidev(acb); 1595 return; 1596 } 1597 arcmsr_free_sysfs_attr(acb); 1598 scsi_remove_host(host); 1599 flush_work(&acb->arcmsr_do_message_isr_bh); 1600 del_timer_sync(&acb->eternal_timer); 1601 if (set_date_time) 1602 del_timer_sync(&acb->refresh_timer); 1603 arcmsr_disable_outbound_ints(acb); 1604 arcmsr_stop_adapter_bgrb(acb); 1605 arcmsr_flush_adapter_cache(acb); 1606 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 1607 acb->acb_flags &= ~ACB_F_IOP_INITED; 1608 1609 for (poll_count = 0; poll_count < acb->maxOutstanding; poll_count++){ 1610 if (!atomic_read(&acb->ccboutstandingcount)) 1611 break; 1612 arcmsr_interrupt(acb);/* FIXME: need spinlock */ 1613 msleep(25); 1614 } 1615 1616 if (atomic_read(&acb->ccboutstandingcount)) { 1617 int i; 1618 1619 arcmsr_abort_allcmd(acb); 1620 arcmsr_done4abort_postqueue(acb); 1621 for (i = 0; i < acb->maxFreeCCB; i++) { 1622 struct CommandControlBlock *ccb = acb->pccb_pool[i]; 1623 if (ccb->startdone == ARCMSR_CCB_START) { 1624 ccb->startdone = ARCMSR_CCB_ABORTED; 1625 ccb->pcmd->result = DID_ABORT << 16; 1626 arcmsr_ccb_complete(ccb); 1627 } 1628 } 1629 } 1630 arcmsr_free_irq(pdev, acb); 1631 arcmsr_free_ccb_pool(acb); 1632 arcmsr_unmap_pciregion(acb); 1633 pci_release_regions(pdev); 1634 scsi_host_put(host); 1635 pci_disable_device(pdev); 1636 } 1637 1638 static void arcmsr_shutdown(struct pci_dev *pdev) 1639 { 1640 struct Scsi_Host *host = pci_get_drvdata(pdev); 1641 struct AdapterControlBlock *acb = 1642 (struct AdapterControlBlock *)host->hostdata; 1643 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) 1644 return; 1645 del_timer_sync(&acb->eternal_timer); 1646 if (set_date_time) 1647 del_timer_sync(&acb->refresh_timer); 1648 arcmsr_disable_outbound_ints(acb); 1649 arcmsr_free_irq(pdev, acb); 1650 flush_work(&acb->arcmsr_do_message_isr_bh); 1651 arcmsr_stop_adapter_bgrb(acb); 1652 arcmsr_flush_adapter_cache(acb); 1653 } 1654 1655 static int arcmsr_module_init(void) 1656 { 1657 int error = 0; 1658 error = pci_register_driver(&arcmsr_pci_driver); 1659 return error; 1660 } 1661 1662 static void arcmsr_module_exit(void) 1663 { 1664 pci_unregister_driver(&arcmsr_pci_driver); 1665 } 1666 module_init(arcmsr_module_init); 1667 module_exit(arcmsr_module_exit); 1668 1669 static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb, 1670 u32 intmask_org) 1671 { 1672 u32 mask; 1673 switch (acb->adapter_type) { 1674 1675 case ACB_ADAPTER_TYPE_A: { 1676 struct MessageUnit_A __iomem *reg = acb->pmuA; 1677 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE | 1678 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE| 1679 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 1680 writel(mask, ®->outbound_intmask); 1681 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 1682 } 1683 break; 1684 1685 case ACB_ADAPTER_TYPE_B: { 1686 struct MessageUnit_B *reg = acb->pmuB; 1687 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK | 1688 ARCMSR_IOP2DRV_DATA_READ_OK | 1689 ARCMSR_IOP2DRV_CDB_DONE | 1690 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 1691 writel(mask, reg->iop2drv_doorbell_mask); 1692 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 1693 } 1694 break; 1695 case ACB_ADAPTER_TYPE_C: { 1696 struct MessageUnit_C __iomem *reg = acb->pmuC; 1697 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 1698 writel(intmask_org & mask, ®->host_int_mask); 1699 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 1700 } 1701 break; 1702 case ACB_ADAPTER_TYPE_D: { 1703 struct MessageUnit_D *reg = acb->pmuD; 1704 1705 mask = ARCMSR_ARC1214_ALL_INT_ENABLE; 1706 writel(intmask_org | mask, reg->pcief0_int_enable); 1707 break; 1708 } 1709 case ACB_ADAPTER_TYPE_E: { 1710 struct MessageUnit_E __iomem *reg = acb->pmuE; 1711 1712 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR); 1713 writel(intmask_org & mask, ®->host_int_mask); 1714 break; 1715 } 1716 } 1717 } 1718 1719 static int arcmsr_build_ccb(struct AdapterControlBlock *acb, 1720 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd) 1721 { 1722 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb; 1723 int8_t *psge = (int8_t *)&arcmsr_cdb->u; 1724 __le32 address_lo, address_hi; 1725 int arccdbsize = 0x30; 1726 __le32 length = 0; 1727 int i; 1728 struct scatterlist *sg; 1729 int nseg; 1730 ccb->pcmd = pcmd; 1731 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 1732 arcmsr_cdb->TargetID = pcmd->device->id; 1733 arcmsr_cdb->LUN = pcmd->device->lun; 1734 arcmsr_cdb->Function = 1; 1735 arcmsr_cdb->msgContext = 0; 1736 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len); 1737 1738 nseg = scsi_dma_map(pcmd); 1739 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0)) 1740 return FAILED; 1741 scsi_for_each_sg(pcmd, sg, nseg, i) { 1742 /* Get the physical address of the current data pointer */ 1743 length = cpu_to_le32(sg_dma_len(sg)); 1744 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg))); 1745 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg))); 1746 if (address_hi == 0) { 1747 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1748 1749 pdma_sg->address = address_lo; 1750 pdma_sg->length = length; 1751 psge += sizeof (struct SG32ENTRY); 1752 arccdbsize += sizeof (struct SG32ENTRY); 1753 } else { 1754 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1755 1756 pdma_sg->addresshigh = address_hi; 1757 pdma_sg->address = address_lo; 1758 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR); 1759 psge += sizeof (struct SG64ENTRY); 1760 arccdbsize += sizeof (struct SG64ENTRY); 1761 } 1762 } 1763 arcmsr_cdb->sgcount = (uint8_t)nseg; 1764 arcmsr_cdb->DataLength = scsi_bufflen(pcmd); 1765 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0); 1766 if ( arccdbsize > 256) 1767 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1768 if (pcmd->sc_data_direction == DMA_TO_DEVICE) 1769 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1770 ccb->arc_cdb_size = arccdbsize; 1771 return SUCCESS; 1772 } 1773 1774 static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb) 1775 { 1776 uint32_t cdb_phyaddr = ccb->cdb_phyaddr; 1777 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb; 1778 atomic_inc(&acb->ccboutstandingcount); 1779 ccb->startdone = ARCMSR_CCB_START; 1780 switch (acb->adapter_type) { 1781 case ACB_ADAPTER_TYPE_A: { 1782 struct MessageUnit_A __iomem *reg = acb->pmuA; 1783 1784 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) 1785 writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE, 1786 ®->inbound_queueport); 1787 else 1788 writel(cdb_phyaddr, ®->inbound_queueport); 1789 break; 1790 } 1791 1792 case ACB_ADAPTER_TYPE_B: { 1793 struct MessageUnit_B *reg = acb->pmuB; 1794 uint32_t ending_index, index = reg->postq_index; 1795 1796 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE); 1797 reg->post_qbuffer[ending_index] = 0; 1798 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1799 reg->post_qbuffer[index] = 1800 cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE; 1801 } else { 1802 reg->post_qbuffer[index] = cdb_phyaddr; 1803 } 1804 index++; 1805 index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */ 1806 reg->postq_index = index; 1807 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell); 1808 } 1809 break; 1810 case ACB_ADAPTER_TYPE_C: { 1811 struct MessageUnit_C __iomem *phbcmu = acb->pmuC; 1812 uint32_t ccb_post_stamp, arc_cdb_size; 1813 1814 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size; 1815 ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1); 1816 writel(upper_32_bits(ccb->cdb_phyaddr), &phbcmu->inbound_queueport_high); 1817 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low); 1818 } 1819 break; 1820 case ACB_ADAPTER_TYPE_D: { 1821 struct MessageUnit_D *pmu = acb->pmuD; 1822 u16 index_stripped; 1823 u16 postq_index, toggle; 1824 unsigned long flags; 1825 struct InBound_SRB *pinbound_srb; 1826 1827 spin_lock_irqsave(&acb->postq_lock, flags); 1828 postq_index = pmu->postq_index; 1829 pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]); 1830 pinbound_srb->addressHigh = upper_32_bits(ccb->cdb_phyaddr); 1831 pinbound_srb->addressLow = cdb_phyaddr; 1832 pinbound_srb->length = ccb->arc_cdb_size >> 2; 1833 arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr); 1834 toggle = postq_index & 0x4000; 1835 index_stripped = postq_index + 1; 1836 index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1); 1837 pmu->postq_index = index_stripped ? (index_stripped | toggle) : 1838 (toggle ^ 0x4000); 1839 writel(postq_index, pmu->inboundlist_write_pointer); 1840 spin_unlock_irqrestore(&acb->postq_lock, flags); 1841 break; 1842 } 1843 case ACB_ADAPTER_TYPE_E: { 1844 struct MessageUnit_E __iomem *pmu = acb->pmuE; 1845 u32 ccb_post_stamp, arc_cdb_size; 1846 1847 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size; 1848 ccb_post_stamp = (ccb->smid | ((arc_cdb_size - 1) >> 6)); 1849 writel(0, &pmu->inbound_queueport_high); 1850 writel(ccb_post_stamp, &pmu->inbound_queueport_low); 1851 break; 1852 } 1853 } 1854 } 1855 1856 static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb) 1857 { 1858 struct MessageUnit_A __iomem *reg = acb->pmuA; 1859 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1860 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); 1861 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 1862 printk(KERN_NOTICE 1863 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n" 1864 , acb->host->host_no); 1865 } 1866 } 1867 1868 static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb) 1869 { 1870 struct MessageUnit_B *reg = acb->pmuB; 1871 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1872 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell); 1873 1874 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 1875 printk(KERN_NOTICE 1876 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n" 1877 , acb->host->host_no); 1878 } 1879 } 1880 1881 static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB) 1882 { 1883 struct MessageUnit_C __iomem *reg = pACB->pmuC; 1884 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB; 1885 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); 1886 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 1887 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 1888 printk(KERN_NOTICE 1889 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n" 1890 , pACB->host->host_no); 1891 } 1892 return; 1893 } 1894 1895 static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB) 1896 { 1897 struct MessageUnit_D *reg = pACB->pmuD; 1898 1899 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB; 1900 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0); 1901 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) 1902 pr_notice("arcmsr%d: wait 'stop adapter background rebuild' " 1903 "timeout\n", pACB->host->host_no); 1904 } 1905 1906 static void arcmsr_hbaE_stop_bgrb(struct AdapterControlBlock *pACB) 1907 { 1908 struct MessageUnit_E __iomem *reg = pACB->pmuE; 1909 1910 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB; 1911 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); 1912 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1913 writel(pACB->out_doorbell, ®->iobound_doorbell); 1914 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 1915 pr_notice("arcmsr%d: wait 'stop adapter background rebuild' " 1916 "timeout\n", pACB->host->host_no); 1917 } 1918 } 1919 1920 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1921 { 1922 switch (acb->adapter_type) { 1923 case ACB_ADAPTER_TYPE_A: { 1924 arcmsr_hbaA_stop_bgrb(acb); 1925 } 1926 break; 1927 1928 case ACB_ADAPTER_TYPE_B: { 1929 arcmsr_hbaB_stop_bgrb(acb); 1930 } 1931 break; 1932 case ACB_ADAPTER_TYPE_C: { 1933 arcmsr_hbaC_stop_bgrb(acb); 1934 } 1935 break; 1936 case ACB_ADAPTER_TYPE_D: 1937 arcmsr_hbaD_stop_bgrb(acb); 1938 break; 1939 case ACB_ADAPTER_TYPE_E: 1940 arcmsr_hbaE_stop_bgrb(acb); 1941 break; 1942 } 1943 } 1944 1945 static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb) 1946 { 1947 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle); 1948 } 1949 1950 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1951 { 1952 switch (acb->adapter_type) { 1953 case ACB_ADAPTER_TYPE_A: { 1954 struct MessageUnit_A __iomem *reg = acb->pmuA; 1955 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell); 1956 } 1957 break; 1958 1959 case ACB_ADAPTER_TYPE_B: { 1960 struct MessageUnit_B *reg = acb->pmuB; 1961 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); 1962 } 1963 break; 1964 case ACB_ADAPTER_TYPE_C: { 1965 struct MessageUnit_C __iomem *reg = acb->pmuC; 1966 1967 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell); 1968 } 1969 break; 1970 case ACB_ADAPTER_TYPE_D: { 1971 struct MessageUnit_D *reg = acb->pmuD; 1972 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ, 1973 reg->inbound_doorbell); 1974 } 1975 break; 1976 case ACB_ADAPTER_TYPE_E: { 1977 struct MessageUnit_E __iomem *reg = acb->pmuE; 1978 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 1979 writel(acb->out_doorbell, ®->iobound_doorbell); 1980 } 1981 break; 1982 } 1983 } 1984 1985 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1986 { 1987 switch (acb->adapter_type) { 1988 case ACB_ADAPTER_TYPE_A: { 1989 struct MessageUnit_A __iomem *reg = acb->pmuA; 1990 /* 1991 ** push inbound doorbell tell iop, driver data write ok 1992 ** and wait reply on next hwinterrupt for next Qbuffer post 1993 */ 1994 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, ®->inbound_doorbell); 1995 } 1996 break; 1997 1998 case ACB_ADAPTER_TYPE_B: { 1999 struct MessageUnit_B *reg = acb->pmuB; 2000 /* 2001 ** push inbound doorbell tell iop, driver data write ok 2002 ** and wait reply on next hwinterrupt for next Qbuffer post 2003 */ 2004 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell); 2005 } 2006 break; 2007 case ACB_ADAPTER_TYPE_C: { 2008 struct MessageUnit_C __iomem *reg = acb->pmuC; 2009 /* 2010 ** push inbound doorbell tell iop, driver data write ok 2011 ** and wait reply on next hwinterrupt for next Qbuffer post 2012 */ 2013 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, ®->inbound_doorbell); 2014 } 2015 break; 2016 case ACB_ADAPTER_TYPE_D: { 2017 struct MessageUnit_D *reg = acb->pmuD; 2018 writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY, 2019 reg->inbound_doorbell); 2020 } 2021 break; 2022 case ACB_ADAPTER_TYPE_E: { 2023 struct MessageUnit_E __iomem *reg = acb->pmuE; 2024 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK; 2025 writel(acb->out_doorbell, ®->iobound_doorbell); 2026 } 2027 break; 2028 } 2029 } 2030 2031 struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb) 2032 { 2033 struct QBUFFER __iomem *qbuffer = NULL; 2034 switch (acb->adapter_type) { 2035 2036 case ACB_ADAPTER_TYPE_A: { 2037 struct MessageUnit_A __iomem *reg = acb->pmuA; 2038 qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer; 2039 } 2040 break; 2041 2042 case ACB_ADAPTER_TYPE_B: { 2043 struct MessageUnit_B *reg = acb->pmuB; 2044 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer; 2045 } 2046 break; 2047 case ACB_ADAPTER_TYPE_C: { 2048 struct MessageUnit_C __iomem *phbcmu = acb->pmuC; 2049 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer; 2050 } 2051 break; 2052 case ACB_ADAPTER_TYPE_D: { 2053 struct MessageUnit_D *reg = acb->pmuD; 2054 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer; 2055 } 2056 break; 2057 case ACB_ADAPTER_TYPE_E: { 2058 struct MessageUnit_E __iomem *reg = acb->pmuE; 2059 qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer; 2060 } 2061 break; 2062 } 2063 return qbuffer; 2064 } 2065 2066 static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb) 2067 { 2068 struct QBUFFER __iomem *pqbuffer = NULL; 2069 switch (acb->adapter_type) { 2070 2071 case ACB_ADAPTER_TYPE_A: { 2072 struct MessageUnit_A __iomem *reg = acb->pmuA; 2073 pqbuffer = (struct QBUFFER __iomem *) ®->message_wbuffer; 2074 } 2075 break; 2076 2077 case ACB_ADAPTER_TYPE_B: { 2078 struct MessageUnit_B *reg = acb->pmuB; 2079 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer; 2080 } 2081 break; 2082 case ACB_ADAPTER_TYPE_C: { 2083 struct MessageUnit_C __iomem *reg = acb->pmuC; 2084 pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer; 2085 } 2086 break; 2087 case ACB_ADAPTER_TYPE_D: { 2088 struct MessageUnit_D *reg = acb->pmuD; 2089 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer; 2090 } 2091 break; 2092 case ACB_ADAPTER_TYPE_E: { 2093 struct MessageUnit_E __iomem *reg = acb->pmuE; 2094 pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer; 2095 } 2096 break; 2097 } 2098 return pqbuffer; 2099 } 2100 2101 static uint32_t 2102 arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb, 2103 struct QBUFFER __iomem *prbuffer) 2104 { 2105 uint8_t *pQbuffer; 2106 uint8_t *buf1 = NULL; 2107 uint32_t __iomem *iop_data; 2108 uint32_t iop_len, data_len, *buf2 = NULL; 2109 2110 iop_data = (uint32_t __iomem *)prbuffer->data; 2111 iop_len = readl(&prbuffer->data_len); 2112 if (iop_len > 0) { 2113 buf1 = kmalloc(128, GFP_ATOMIC); 2114 buf2 = (uint32_t *)buf1; 2115 if (buf1 == NULL) 2116 return 0; 2117 data_len = iop_len; 2118 while (data_len >= 4) { 2119 *buf2++ = readl(iop_data); 2120 iop_data++; 2121 data_len -= 4; 2122 } 2123 if (data_len) 2124 *buf2 = readl(iop_data); 2125 buf2 = (uint32_t *)buf1; 2126 } 2127 while (iop_len > 0) { 2128 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex]; 2129 *pQbuffer = *buf1; 2130 acb->rqbuf_putIndex++; 2131 /* if last, index number set it to 0 */ 2132 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER; 2133 buf1++; 2134 iop_len--; 2135 } 2136 kfree(buf2); 2137 /* let IOP know data has been read */ 2138 arcmsr_iop_message_read(acb); 2139 return 1; 2140 } 2141 2142 uint32_t 2143 arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 2144 struct QBUFFER __iomem *prbuffer) { 2145 2146 uint8_t *pQbuffer; 2147 uint8_t __iomem *iop_data; 2148 uint32_t iop_len; 2149 2150 if (acb->adapter_type > ACB_ADAPTER_TYPE_B) 2151 return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer); 2152 iop_data = (uint8_t __iomem *)prbuffer->data; 2153 iop_len = readl(&prbuffer->data_len); 2154 while (iop_len > 0) { 2155 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex]; 2156 *pQbuffer = readb(iop_data); 2157 acb->rqbuf_putIndex++; 2158 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER; 2159 iop_data++; 2160 iop_len--; 2161 } 2162 arcmsr_iop_message_read(acb); 2163 return 1; 2164 } 2165 2166 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 2167 { 2168 unsigned long flags; 2169 struct QBUFFER __iomem *prbuffer; 2170 int32_t buf_empty_len; 2171 2172 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2173 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2174 buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) & 2175 (ARCMSR_MAX_QBUFFER - 1); 2176 if (buf_empty_len >= readl(&prbuffer->data_len)) { 2177 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2178 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2179 } else 2180 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2181 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2182 } 2183 2184 static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb) 2185 { 2186 uint8_t *pQbuffer; 2187 struct QBUFFER __iomem *pwbuffer; 2188 uint8_t *buf1 = NULL; 2189 uint32_t __iomem *iop_data; 2190 uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data; 2191 2192 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) { 2193 buf1 = kmalloc(128, GFP_ATOMIC); 2194 buf2 = (uint32_t *)buf1; 2195 if (buf1 == NULL) 2196 return; 2197 2198 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED); 2199 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 2200 iop_data = (uint32_t __iomem *)pwbuffer->data; 2201 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex) 2202 && (allxfer_len < 124)) { 2203 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex]; 2204 *buf1 = *pQbuffer; 2205 acb->wqbuf_getIndex++; 2206 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER; 2207 buf1++; 2208 allxfer_len++; 2209 } 2210 data_len = allxfer_len; 2211 buf1 = (uint8_t *)buf2; 2212 while (data_len >= 4) { 2213 data = *buf2++; 2214 writel(data, iop_data); 2215 iop_data++; 2216 data_len -= 4; 2217 } 2218 if (data_len) { 2219 data = *buf2; 2220 writel(data, iop_data); 2221 } 2222 writel(allxfer_len, &pwbuffer->data_len); 2223 kfree(buf1); 2224 arcmsr_iop_message_wrote(acb); 2225 } 2226 } 2227 2228 void 2229 arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb) 2230 { 2231 uint8_t *pQbuffer; 2232 struct QBUFFER __iomem *pwbuffer; 2233 uint8_t __iomem *iop_data; 2234 int32_t allxfer_len = 0; 2235 2236 if (acb->adapter_type > ACB_ADAPTER_TYPE_B) { 2237 arcmsr_write_ioctldata2iop_in_DWORD(acb); 2238 return; 2239 } 2240 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) { 2241 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED); 2242 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 2243 iop_data = (uint8_t __iomem *)pwbuffer->data; 2244 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex) 2245 && (allxfer_len < 124)) { 2246 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex]; 2247 writeb(*pQbuffer, iop_data); 2248 acb->wqbuf_getIndex++; 2249 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER; 2250 iop_data++; 2251 allxfer_len++; 2252 } 2253 writel(allxfer_len, &pwbuffer->data_len); 2254 arcmsr_iop_message_wrote(acb); 2255 } 2256 } 2257 2258 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 2259 { 2260 unsigned long flags; 2261 2262 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2263 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED; 2264 if (acb->wqbuf_getIndex != acb->wqbuf_putIndex) 2265 arcmsr_write_ioctldata2iop(acb); 2266 if (acb->wqbuf_getIndex == acb->wqbuf_putIndex) 2267 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 2268 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2269 } 2270 2271 static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb) 2272 { 2273 uint32_t outbound_doorbell; 2274 struct MessageUnit_A __iomem *reg = acb->pmuA; 2275 outbound_doorbell = readl(®->outbound_doorbell); 2276 do { 2277 writel(outbound_doorbell, ®->outbound_doorbell); 2278 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) 2279 arcmsr_iop2drv_data_wrote_handle(acb); 2280 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) 2281 arcmsr_iop2drv_data_read_handle(acb); 2282 outbound_doorbell = readl(®->outbound_doorbell); 2283 } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 2284 | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)); 2285 } 2286 static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB) 2287 { 2288 uint32_t outbound_doorbell; 2289 struct MessageUnit_C __iomem *reg = pACB->pmuC; 2290 /* 2291 ******************************************************************* 2292 ** Maybe here we need to check wrqbuffer_lock is lock or not 2293 ** DOORBELL: din! don! 2294 ** check if there are any mail need to pack from firmware 2295 ******************************************************************* 2296 */ 2297 outbound_doorbell = readl(®->outbound_doorbell); 2298 do { 2299 writel(outbound_doorbell, ®->outbound_doorbell_clear); 2300 readl(®->outbound_doorbell_clear); 2301 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) 2302 arcmsr_iop2drv_data_wrote_handle(pACB); 2303 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) 2304 arcmsr_iop2drv_data_read_handle(pACB); 2305 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) 2306 arcmsr_hbaC_message_isr(pACB); 2307 outbound_doorbell = readl(®->outbound_doorbell); 2308 } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 2309 | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 2310 | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)); 2311 } 2312 2313 static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB) 2314 { 2315 uint32_t outbound_doorbell; 2316 struct MessageUnit_D *pmu = pACB->pmuD; 2317 2318 outbound_doorbell = readl(pmu->outbound_doorbell); 2319 do { 2320 writel(outbound_doorbell, pmu->outbound_doorbell); 2321 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) 2322 arcmsr_hbaD_message_isr(pACB); 2323 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) 2324 arcmsr_iop2drv_data_wrote_handle(pACB); 2325 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK) 2326 arcmsr_iop2drv_data_read_handle(pACB); 2327 outbound_doorbell = readl(pmu->outbound_doorbell); 2328 } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 2329 | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 2330 | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)); 2331 } 2332 2333 static void arcmsr_hbaE_doorbell_isr(struct AdapterControlBlock *pACB) 2334 { 2335 uint32_t outbound_doorbell, in_doorbell, tmp; 2336 struct MessageUnit_E __iomem *reg = pACB->pmuE; 2337 2338 in_doorbell = readl(®->iobound_doorbell); 2339 outbound_doorbell = in_doorbell ^ pACB->in_doorbell; 2340 do { 2341 writel(0, ®->host_int_status); /* clear interrupt */ 2342 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2343 arcmsr_iop2drv_data_wrote_handle(pACB); 2344 } 2345 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2346 arcmsr_iop2drv_data_read_handle(pACB); 2347 } 2348 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2349 arcmsr_hbaE_message_isr(pACB); 2350 } 2351 tmp = in_doorbell; 2352 in_doorbell = readl(®->iobound_doorbell); 2353 outbound_doorbell = tmp ^ in_doorbell; 2354 } while (outbound_doorbell & (ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 2355 | ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 2356 | ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE)); 2357 pACB->in_doorbell = in_doorbell; 2358 } 2359 2360 static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb) 2361 { 2362 uint32_t flag_ccb; 2363 struct MessageUnit_A __iomem *reg = acb->pmuA; 2364 struct ARCMSR_CDB *pARCMSR_CDB; 2365 struct CommandControlBlock *pCCB; 2366 bool error; 2367 unsigned long cdb_phy_addr; 2368 2369 while ((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF) { 2370 cdb_phy_addr = (flag_ccb << 5) & 0xffffffff; 2371 if (acb->cdb_phyadd_hipart) 2372 cdb_phy_addr = cdb_phy_addr | acb->cdb_phyadd_hipart; 2373 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + cdb_phy_addr); 2374 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 2375 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 2376 arcmsr_drain_donequeue(acb, pCCB, error); 2377 } 2378 } 2379 static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb) 2380 { 2381 uint32_t index; 2382 uint32_t flag_ccb; 2383 struct MessageUnit_B *reg = acb->pmuB; 2384 struct ARCMSR_CDB *pARCMSR_CDB; 2385 struct CommandControlBlock *pCCB; 2386 bool error; 2387 unsigned long cdb_phy_addr; 2388 2389 index = reg->doneq_index; 2390 while ((flag_ccb = reg->done_qbuffer[index]) != 0) { 2391 cdb_phy_addr = (flag_ccb << 5) & 0xffffffff; 2392 if (acb->cdb_phyadd_hipart) 2393 cdb_phy_addr = cdb_phy_addr | acb->cdb_phyadd_hipart; 2394 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + cdb_phy_addr); 2395 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 2396 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 2397 arcmsr_drain_donequeue(acb, pCCB, error); 2398 reg->done_qbuffer[index] = 0; 2399 index++; 2400 index %= ARCMSR_MAX_HBB_POSTQUEUE; 2401 reg->doneq_index = index; 2402 } 2403 } 2404 2405 static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb) 2406 { 2407 struct MessageUnit_C __iomem *phbcmu; 2408 struct ARCMSR_CDB *arcmsr_cdb; 2409 struct CommandControlBlock *ccb; 2410 uint32_t flag_ccb, throttling = 0; 2411 unsigned long ccb_cdb_phy; 2412 int error; 2413 2414 phbcmu = acb->pmuC; 2415 /* areca cdb command done */ 2416 /* Use correct offset and size for syncing */ 2417 2418 while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) != 2419 0xFFFFFFFF) { 2420 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 2421 if (acb->cdb_phyadd_hipart) 2422 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 2423 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset 2424 + ccb_cdb_phy); 2425 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, 2426 arcmsr_cdb); 2427 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) 2428 ? true : false; 2429 /* check if command done with no error */ 2430 arcmsr_drain_donequeue(acb, ccb, error); 2431 throttling++; 2432 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 2433 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING, 2434 &phbcmu->inbound_doorbell); 2435 throttling = 0; 2436 } 2437 } 2438 } 2439 2440 static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb) 2441 { 2442 u32 outbound_write_pointer, doneq_index, index_stripped, toggle; 2443 uint32_t addressLow; 2444 int error; 2445 struct MessageUnit_D *pmu; 2446 struct ARCMSR_CDB *arcmsr_cdb; 2447 struct CommandControlBlock *ccb; 2448 unsigned long flags, ccb_cdb_phy, cdb_phy_hipart; 2449 2450 spin_lock_irqsave(&acb->doneq_lock, flags); 2451 pmu = acb->pmuD; 2452 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1; 2453 doneq_index = pmu->doneq_index; 2454 if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) { 2455 do { 2456 toggle = doneq_index & 0x4000; 2457 index_stripped = (doneq_index & 0xFFF) + 1; 2458 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE; 2459 pmu->doneq_index = index_stripped ? (index_stripped | toggle) : 2460 ((toggle ^ 0x4000) + 1); 2461 doneq_index = pmu->doneq_index; 2462 cdb_phy_hipart = pmu->done_qbuffer[doneq_index & 2463 0xFFF].addressHigh; 2464 addressLow = pmu->done_qbuffer[doneq_index & 2465 0xFFF].addressLow; 2466 ccb_cdb_phy = (addressLow & 0xFFFFFFF0); 2467 if (acb->cdb_phyadd_hipart) 2468 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 2469 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset 2470 + ccb_cdb_phy); 2471 ccb = container_of(arcmsr_cdb, 2472 struct CommandControlBlock, arcmsr_cdb); 2473 error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) 2474 ? true : false; 2475 arcmsr_drain_donequeue(acb, ccb, error); 2476 writel(doneq_index, pmu->outboundlist_read_pointer); 2477 } while ((doneq_index & 0xFFF) != 2478 (outbound_write_pointer & 0xFFF)); 2479 } 2480 writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR, 2481 pmu->outboundlist_interrupt_cause); 2482 readl(pmu->outboundlist_interrupt_cause); 2483 spin_unlock_irqrestore(&acb->doneq_lock, flags); 2484 } 2485 2486 static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb) 2487 { 2488 uint32_t doneq_index; 2489 uint16_t cmdSMID; 2490 int error; 2491 struct MessageUnit_E __iomem *pmu; 2492 struct CommandControlBlock *ccb; 2493 unsigned long flags; 2494 2495 spin_lock_irqsave(&acb->doneq_lock, flags); 2496 doneq_index = acb->doneq_index; 2497 pmu = acb->pmuE; 2498 while ((readl(&pmu->reply_post_producer_index) & 0xFFFF) != doneq_index) { 2499 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2500 ccb = acb->pccb_pool[cmdSMID]; 2501 error = (acb->pCompletionQ[doneq_index].cmdFlag 2502 & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 2503 arcmsr_drain_donequeue(acb, ccb, error); 2504 doneq_index++; 2505 if (doneq_index >= acb->completionQ_entry) 2506 doneq_index = 0; 2507 } 2508 acb->doneq_index = doneq_index; 2509 writel(doneq_index, &pmu->reply_post_consumer_index); 2510 spin_unlock_irqrestore(&acb->doneq_lock, flags); 2511 } 2512 2513 /* 2514 ********************************************************************************** 2515 ** Handle a message interrupt 2516 ** 2517 ** The only message interrupt we expect is in response to a query for the current adapter config. 2518 ** We want this in order to compare the drivemap so that we can detect newly-attached drives. 2519 ********************************************************************************** 2520 */ 2521 static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb) 2522 { 2523 struct MessageUnit_A __iomem *reg = acb->pmuA; 2524 /*clear interrupt and message state*/ 2525 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, ®->outbound_intstatus); 2526 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2527 schedule_work(&acb->arcmsr_do_message_isr_bh); 2528 } 2529 static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb) 2530 { 2531 struct MessageUnit_B *reg = acb->pmuB; 2532 2533 /*clear interrupt and message state*/ 2534 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 2535 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2536 schedule_work(&acb->arcmsr_do_message_isr_bh); 2537 } 2538 /* 2539 ********************************************************************************** 2540 ** Handle a message interrupt 2541 ** 2542 ** The only message interrupt we expect is in response to a query for the 2543 ** current adapter config. 2544 ** We want this in order to compare the drivemap so that we can detect newly-attached drives. 2545 ********************************************************************************** 2546 */ 2547 static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb) 2548 { 2549 struct MessageUnit_C __iomem *reg = acb->pmuC; 2550 /*clear interrupt and message state*/ 2551 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, ®->outbound_doorbell_clear); 2552 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2553 schedule_work(&acb->arcmsr_do_message_isr_bh); 2554 } 2555 2556 static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb) 2557 { 2558 struct MessageUnit_D *reg = acb->pmuD; 2559 2560 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell); 2561 readl(reg->outbound_doorbell); 2562 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2563 schedule_work(&acb->arcmsr_do_message_isr_bh); 2564 } 2565 2566 static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb) 2567 { 2568 struct MessageUnit_E __iomem *reg = acb->pmuE; 2569 2570 writel(0, ®->host_int_status); 2571 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2572 schedule_work(&acb->arcmsr_do_message_isr_bh); 2573 } 2574 2575 static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb) 2576 { 2577 uint32_t outbound_intstatus; 2578 struct MessageUnit_A __iomem *reg = acb->pmuA; 2579 outbound_intstatus = readl(®->outbound_intstatus) & 2580 acb->outbound_int_enable; 2581 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) 2582 return IRQ_NONE; 2583 do { 2584 writel(outbound_intstatus, ®->outbound_intstatus); 2585 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) 2586 arcmsr_hbaA_doorbell_isr(acb); 2587 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) 2588 arcmsr_hbaA_postqueue_isr(acb); 2589 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) 2590 arcmsr_hbaA_message_isr(acb); 2591 outbound_intstatus = readl(®->outbound_intstatus) & 2592 acb->outbound_int_enable; 2593 } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT 2594 | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 2595 | ARCMSR_MU_OUTBOUND_MESSAGE0_INT)); 2596 return IRQ_HANDLED; 2597 } 2598 2599 static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb) 2600 { 2601 uint32_t outbound_doorbell; 2602 struct MessageUnit_B *reg = acb->pmuB; 2603 outbound_doorbell = readl(reg->iop2drv_doorbell) & 2604 acb->outbound_int_enable; 2605 if (!outbound_doorbell) 2606 return IRQ_NONE; 2607 do { 2608 writel(~outbound_doorbell, reg->iop2drv_doorbell); 2609 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell); 2610 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) 2611 arcmsr_iop2drv_data_wrote_handle(acb); 2612 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) 2613 arcmsr_iop2drv_data_read_handle(acb); 2614 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) 2615 arcmsr_hbaB_postqueue_isr(acb); 2616 if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) 2617 arcmsr_hbaB_message_isr(acb); 2618 outbound_doorbell = readl(reg->iop2drv_doorbell) & 2619 acb->outbound_int_enable; 2620 } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK 2621 | ARCMSR_IOP2DRV_DATA_READ_OK 2622 | ARCMSR_IOP2DRV_CDB_DONE 2623 | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)); 2624 return IRQ_HANDLED; 2625 } 2626 2627 static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB) 2628 { 2629 uint32_t host_interrupt_status; 2630 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC; 2631 /* 2632 ********************************************* 2633 ** check outbound intstatus 2634 ********************************************* 2635 */ 2636 host_interrupt_status = readl(&phbcmu->host_int_status) & 2637 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2638 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2639 if (!host_interrupt_status) 2640 return IRQ_NONE; 2641 do { 2642 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) 2643 arcmsr_hbaC_doorbell_isr(pACB); 2644 /* MU post queue interrupts*/ 2645 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) 2646 arcmsr_hbaC_postqueue_isr(pACB); 2647 host_interrupt_status = readl(&phbcmu->host_int_status); 2648 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2649 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2650 return IRQ_HANDLED; 2651 } 2652 2653 static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB) 2654 { 2655 u32 host_interrupt_status; 2656 struct MessageUnit_D *pmu = pACB->pmuD; 2657 2658 host_interrupt_status = readl(pmu->host_int_status) & 2659 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR | 2660 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR); 2661 if (!host_interrupt_status) 2662 return IRQ_NONE; 2663 do { 2664 /* MU post queue interrupts*/ 2665 if (host_interrupt_status & 2666 ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR) 2667 arcmsr_hbaD_postqueue_isr(pACB); 2668 if (host_interrupt_status & 2669 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR) 2670 arcmsr_hbaD_doorbell_isr(pACB); 2671 host_interrupt_status = readl(pmu->host_int_status); 2672 } while (host_interrupt_status & 2673 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR | 2674 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)); 2675 return IRQ_HANDLED; 2676 } 2677 2678 static irqreturn_t arcmsr_hbaE_handle_isr(struct AdapterControlBlock *pACB) 2679 { 2680 uint32_t host_interrupt_status; 2681 struct MessageUnit_E __iomem *pmu = pACB->pmuE; 2682 2683 host_interrupt_status = readl(&pmu->host_int_status) & 2684 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2685 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2686 if (!host_interrupt_status) 2687 return IRQ_NONE; 2688 do { 2689 /* MU ioctl transfer doorbell interrupts*/ 2690 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2691 arcmsr_hbaE_doorbell_isr(pACB); 2692 } 2693 /* MU post queue interrupts*/ 2694 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2695 arcmsr_hbaE_postqueue_isr(pACB); 2696 } 2697 host_interrupt_status = readl(&pmu->host_int_status); 2698 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2699 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2700 return IRQ_HANDLED; 2701 } 2702 2703 static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb) 2704 { 2705 switch (acb->adapter_type) { 2706 case ACB_ADAPTER_TYPE_A: 2707 return arcmsr_hbaA_handle_isr(acb); 2708 break; 2709 case ACB_ADAPTER_TYPE_B: 2710 return arcmsr_hbaB_handle_isr(acb); 2711 break; 2712 case ACB_ADAPTER_TYPE_C: 2713 return arcmsr_hbaC_handle_isr(acb); 2714 case ACB_ADAPTER_TYPE_D: 2715 return arcmsr_hbaD_handle_isr(acb); 2716 case ACB_ADAPTER_TYPE_E: 2717 return arcmsr_hbaE_handle_isr(acb); 2718 default: 2719 return IRQ_NONE; 2720 } 2721 } 2722 2723 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2724 { 2725 if (acb) { 2726 /* stop adapter background rebuild */ 2727 if (acb->acb_flags & ACB_F_MSG_START_BGRB) { 2728 uint32_t intmask_org; 2729 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 2730 intmask_org = arcmsr_disable_outbound_ints(acb); 2731 arcmsr_stop_adapter_bgrb(acb); 2732 arcmsr_flush_adapter_cache(acb); 2733 arcmsr_enable_outbound_ints(acb, intmask_org); 2734 } 2735 } 2736 } 2737 2738 2739 void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb) 2740 { 2741 uint32_t i; 2742 2743 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2744 for (i = 0; i < 15; i++) { 2745 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2746 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2747 acb->rqbuf_getIndex = 0; 2748 acb->rqbuf_putIndex = 0; 2749 arcmsr_iop_message_read(acb); 2750 mdelay(30); 2751 } else if (acb->rqbuf_getIndex != 2752 acb->rqbuf_putIndex) { 2753 acb->rqbuf_getIndex = 0; 2754 acb->rqbuf_putIndex = 0; 2755 mdelay(30); 2756 } else 2757 break; 2758 } 2759 } 2760 } 2761 2762 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, 2763 struct scsi_cmnd *cmd) 2764 { 2765 char *buffer; 2766 unsigned short use_sg; 2767 int retvalue = 0, transfer_len = 0; 2768 unsigned long flags; 2769 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2770 uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 | 2771 (uint32_t)cmd->cmnd[6] << 16 | 2772 (uint32_t)cmd->cmnd[7] << 8 | 2773 (uint32_t)cmd->cmnd[8]; 2774 struct scatterlist *sg; 2775 2776 use_sg = scsi_sg_count(cmd); 2777 sg = scsi_sglist(cmd); 2778 buffer = kmap_atomic(sg_page(sg)) + sg->offset; 2779 if (use_sg > 1) { 2780 retvalue = ARCMSR_MESSAGE_FAIL; 2781 goto message_out; 2782 } 2783 transfer_len += sg->length; 2784 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2785 retvalue = ARCMSR_MESSAGE_FAIL; 2786 pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__); 2787 goto message_out; 2788 } 2789 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer; 2790 switch (controlcode) { 2791 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2792 unsigned char *ver_addr; 2793 uint8_t *ptmpQbuffer; 2794 uint32_t allxfer_len = 0; 2795 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC); 2796 if (!ver_addr) { 2797 retvalue = ARCMSR_MESSAGE_FAIL; 2798 pr_info("%s: memory not enough!\n", __func__); 2799 goto message_out; 2800 } 2801 ptmpQbuffer = ver_addr; 2802 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2803 if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) { 2804 unsigned int tail = acb->rqbuf_getIndex; 2805 unsigned int head = acb->rqbuf_putIndex; 2806 unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER); 2807 2808 allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER); 2809 if (allxfer_len > ARCMSR_API_DATA_BUFLEN) 2810 allxfer_len = ARCMSR_API_DATA_BUFLEN; 2811 2812 if (allxfer_len <= cnt_to_end) 2813 memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len); 2814 else { 2815 memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end); 2816 memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end); 2817 } 2818 acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER; 2819 } 2820 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr, 2821 allxfer_len); 2822 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2823 struct QBUFFER __iomem *prbuffer; 2824 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2825 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2826 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2827 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2828 } 2829 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2830 kfree(ver_addr); 2831 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2832 if (acb->fw_flag == FW_DEADLOCK) 2833 pcmdmessagefld->cmdmessage.ReturnCode = 2834 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2835 else 2836 pcmdmessagefld->cmdmessage.ReturnCode = 2837 ARCMSR_MESSAGE_RETURNCODE_OK; 2838 break; 2839 } 2840 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2841 unsigned char *ver_addr; 2842 uint32_t user_len; 2843 int32_t cnt2end; 2844 uint8_t *pQbuffer, *ptmpuserbuffer; 2845 2846 user_len = pcmdmessagefld->cmdmessage.Length; 2847 if (user_len > ARCMSR_API_DATA_BUFLEN) { 2848 retvalue = ARCMSR_MESSAGE_FAIL; 2849 goto message_out; 2850 } 2851 2852 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC); 2853 if (!ver_addr) { 2854 retvalue = ARCMSR_MESSAGE_FAIL; 2855 goto message_out; 2856 } 2857 ptmpuserbuffer = ver_addr; 2858 2859 memcpy(ptmpuserbuffer, 2860 pcmdmessagefld->messagedatabuffer, user_len); 2861 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2862 if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) { 2863 struct SENSE_DATA *sensebuffer = 2864 (struct SENSE_DATA *)cmd->sense_buffer; 2865 arcmsr_write_ioctldata2iop(acb); 2866 /* has error report sensedata */ 2867 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS; 2868 sensebuffer->SenseKey = ILLEGAL_REQUEST; 2869 sensebuffer->AdditionalSenseLength = 0x0A; 2870 sensebuffer->AdditionalSenseCode = 0x20; 2871 sensebuffer->Valid = 1; 2872 retvalue = ARCMSR_MESSAGE_FAIL; 2873 } else { 2874 pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex]; 2875 cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex; 2876 if (user_len > cnt2end) { 2877 memcpy(pQbuffer, ptmpuserbuffer, cnt2end); 2878 ptmpuserbuffer += cnt2end; 2879 user_len -= cnt2end; 2880 acb->wqbuf_putIndex = 0; 2881 pQbuffer = acb->wqbuffer; 2882 } 2883 memcpy(pQbuffer, ptmpuserbuffer, user_len); 2884 acb->wqbuf_putIndex += user_len; 2885 acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER; 2886 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2887 acb->acb_flags &= 2888 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2889 arcmsr_write_ioctldata2iop(acb); 2890 } 2891 } 2892 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2893 kfree(ver_addr); 2894 if (acb->fw_flag == FW_DEADLOCK) 2895 pcmdmessagefld->cmdmessage.ReturnCode = 2896 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2897 else 2898 pcmdmessagefld->cmdmessage.ReturnCode = 2899 ARCMSR_MESSAGE_RETURNCODE_OK; 2900 break; 2901 } 2902 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2903 uint8_t *pQbuffer = acb->rqbuffer; 2904 2905 arcmsr_clear_iop2drv_rqueue_buffer(acb); 2906 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2907 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2908 acb->rqbuf_getIndex = 0; 2909 acb->rqbuf_putIndex = 0; 2910 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2911 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2912 if (acb->fw_flag == FW_DEADLOCK) 2913 pcmdmessagefld->cmdmessage.ReturnCode = 2914 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2915 else 2916 pcmdmessagefld->cmdmessage.ReturnCode = 2917 ARCMSR_MESSAGE_RETURNCODE_OK; 2918 break; 2919 } 2920 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2921 uint8_t *pQbuffer = acb->wqbuffer; 2922 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2923 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2924 ACB_F_MESSAGE_WQBUFFER_READED); 2925 acb->wqbuf_getIndex = 0; 2926 acb->wqbuf_putIndex = 0; 2927 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2928 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2929 if (acb->fw_flag == FW_DEADLOCK) 2930 pcmdmessagefld->cmdmessage.ReturnCode = 2931 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2932 else 2933 pcmdmessagefld->cmdmessage.ReturnCode = 2934 ARCMSR_MESSAGE_RETURNCODE_OK; 2935 break; 2936 } 2937 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2938 uint8_t *pQbuffer; 2939 arcmsr_clear_iop2drv_rqueue_buffer(acb); 2940 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2941 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2942 acb->rqbuf_getIndex = 0; 2943 acb->rqbuf_putIndex = 0; 2944 pQbuffer = acb->rqbuffer; 2945 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2946 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2947 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2948 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2949 ACB_F_MESSAGE_WQBUFFER_READED); 2950 acb->wqbuf_getIndex = 0; 2951 acb->wqbuf_putIndex = 0; 2952 pQbuffer = acb->wqbuffer; 2953 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2954 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2955 if (acb->fw_flag == FW_DEADLOCK) 2956 pcmdmessagefld->cmdmessage.ReturnCode = 2957 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2958 else 2959 pcmdmessagefld->cmdmessage.ReturnCode = 2960 ARCMSR_MESSAGE_RETURNCODE_OK; 2961 break; 2962 } 2963 case ARCMSR_MESSAGE_RETURN_CODE_3F: { 2964 if (acb->fw_flag == FW_DEADLOCK) 2965 pcmdmessagefld->cmdmessage.ReturnCode = 2966 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2967 else 2968 pcmdmessagefld->cmdmessage.ReturnCode = 2969 ARCMSR_MESSAGE_RETURNCODE_3F; 2970 break; 2971 } 2972 case ARCMSR_MESSAGE_SAY_HELLO: { 2973 int8_t *hello_string = "Hello! I am ARCMSR"; 2974 if (acb->fw_flag == FW_DEADLOCK) 2975 pcmdmessagefld->cmdmessage.ReturnCode = 2976 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2977 else 2978 pcmdmessagefld->cmdmessage.ReturnCode = 2979 ARCMSR_MESSAGE_RETURNCODE_OK; 2980 memcpy(pcmdmessagefld->messagedatabuffer, 2981 hello_string, (int16_t)strlen(hello_string)); 2982 break; 2983 } 2984 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2985 if (acb->fw_flag == FW_DEADLOCK) 2986 pcmdmessagefld->cmdmessage.ReturnCode = 2987 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2988 else 2989 pcmdmessagefld->cmdmessage.ReturnCode = 2990 ARCMSR_MESSAGE_RETURNCODE_OK; 2991 arcmsr_iop_parking(acb); 2992 break; 2993 } 2994 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2995 if (acb->fw_flag == FW_DEADLOCK) 2996 pcmdmessagefld->cmdmessage.ReturnCode = 2997 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2998 else 2999 pcmdmessagefld->cmdmessage.ReturnCode = 3000 ARCMSR_MESSAGE_RETURNCODE_OK; 3001 arcmsr_flush_adapter_cache(acb); 3002 break; 3003 } 3004 default: 3005 retvalue = ARCMSR_MESSAGE_FAIL; 3006 pr_info("%s: unknown controlcode!\n", __func__); 3007 } 3008 message_out: 3009 if (use_sg) { 3010 struct scatterlist *sg = scsi_sglist(cmd); 3011 kunmap_atomic(buffer - sg->offset); 3012 } 3013 return retvalue; 3014 } 3015 3016 static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb) 3017 { 3018 struct list_head *head = &acb->ccb_free_list; 3019 struct CommandControlBlock *ccb = NULL; 3020 unsigned long flags; 3021 spin_lock_irqsave(&acb->ccblist_lock, flags); 3022 if (!list_empty(head)) { 3023 ccb = list_entry(head->next, struct CommandControlBlock, list); 3024 list_del_init(&ccb->list); 3025 }else{ 3026 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 3027 return NULL; 3028 } 3029 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 3030 return ccb; 3031 } 3032 3033 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 3034 struct scsi_cmnd *cmd) 3035 { 3036 switch (cmd->cmnd[0]) { 3037 case INQUIRY: { 3038 unsigned char inqdata[36]; 3039 char *buffer; 3040 struct scatterlist *sg; 3041 3042 if (cmd->device->lun) { 3043 cmd->result = (DID_TIME_OUT << 16); 3044 cmd->scsi_done(cmd); 3045 return; 3046 } 3047 inqdata[0] = TYPE_PROCESSOR; 3048 /* Periph Qualifier & Periph Dev Type */ 3049 inqdata[1] = 0; 3050 /* rem media bit & Dev Type Modifier */ 3051 inqdata[2] = 0; 3052 /* ISO, ECMA, & ANSI versions */ 3053 inqdata[4] = 31; 3054 /* length of additional data */ 3055 strncpy(&inqdata[8], "Areca ", 8); 3056 /* Vendor Identification */ 3057 strncpy(&inqdata[16], "RAID controller ", 16); 3058 /* Product Identification */ 3059 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 3060 3061 sg = scsi_sglist(cmd); 3062 buffer = kmap_atomic(sg_page(sg)) + sg->offset; 3063 3064 memcpy(buffer, inqdata, sizeof(inqdata)); 3065 sg = scsi_sglist(cmd); 3066 kunmap_atomic(buffer - sg->offset); 3067 3068 cmd->scsi_done(cmd); 3069 } 3070 break; 3071 case WRITE_BUFFER: 3072 case READ_BUFFER: { 3073 if (arcmsr_iop_message_xfer(acb, cmd)) 3074 cmd->result = (DID_ERROR << 16); 3075 cmd->scsi_done(cmd); 3076 } 3077 break; 3078 default: 3079 cmd->scsi_done(cmd); 3080 } 3081 } 3082 3083 static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd, 3084 void (* done)(struct scsi_cmnd *)) 3085 { 3086 struct Scsi_Host *host = cmd->device->host; 3087 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata; 3088 struct CommandControlBlock *ccb; 3089 int target = cmd->device->id; 3090 3091 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) { 3092 cmd->result = (DID_NO_CONNECT << 16); 3093 cmd->scsi_done(cmd); 3094 return 0; 3095 } 3096 cmd->scsi_done = done; 3097 cmd->host_scribble = NULL; 3098 cmd->result = 0; 3099 if (target == 16) { 3100 /* virtual device for iop message transfer */ 3101 arcmsr_handle_virtual_command(acb, cmd); 3102 return 0; 3103 } 3104 ccb = arcmsr_get_freeccb(acb); 3105 if (!ccb) 3106 return SCSI_MLQUEUE_HOST_BUSY; 3107 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) { 3108 cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1); 3109 cmd->scsi_done(cmd); 3110 return 0; 3111 } 3112 arcmsr_post_ccb(acb, ccb); 3113 return 0; 3114 } 3115 3116 static DEF_SCSI_QCMD(arcmsr_queue_command) 3117 3118 static void arcmsr_get_adapter_config(struct AdapterControlBlock *pACB, uint32_t *rwbuffer) 3119 { 3120 int count; 3121 uint32_t *acb_firm_model = (uint32_t *)pACB->firm_model; 3122 uint32_t *acb_firm_version = (uint32_t *)pACB->firm_version; 3123 uint32_t *acb_device_map = (uint32_t *)pACB->device_map; 3124 uint32_t *firm_model = &rwbuffer[15]; 3125 uint32_t *firm_version = &rwbuffer[17]; 3126 uint32_t *device_map = &rwbuffer[21]; 3127 3128 count = 2; 3129 while (count) { 3130 *acb_firm_model = readl(firm_model); 3131 acb_firm_model++; 3132 firm_model++; 3133 count--; 3134 } 3135 count = 4; 3136 while (count) { 3137 *acb_firm_version = readl(firm_version); 3138 acb_firm_version++; 3139 firm_version++; 3140 count--; 3141 } 3142 count = 4; 3143 while (count) { 3144 *acb_device_map = readl(device_map); 3145 acb_device_map++; 3146 device_map++; 3147 count--; 3148 } 3149 pACB->signature = readl(&rwbuffer[0]); 3150 pACB->firm_request_len = readl(&rwbuffer[1]); 3151 pACB->firm_numbers_queue = readl(&rwbuffer[2]); 3152 pACB->firm_sdram_size = readl(&rwbuffer[3]); 3153 pACB->firm_hd_channels = readl(&rwbuffer[4]); 3154 pACB->firm_cfg_version = readl(&rwbuffer[25]); 3155 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n", 3156 pACB->host->host_no, 3157 pACB->firm_model, 3158 pACB->firm_version); 3159 } 3160 3161 static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb) 3162 { 3163 struct MessageUnit_A __iomem *reg = acb->pmuA; 3164 3165 arcmsr_wait_firmware_ready(acb); 3166 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3167 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 3168 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \ 3169 miscellaneous data' timeout \n", acb->host->host_no); 3170 return false; 3171 } 3172 arcmsr_get_adapter_config(acb, reg->message_rwbuffer); 3173 return true; 3174 } 3175 static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb) 3176 { 3177 struct MessageUnit_B *reg = acb->pmuB; 3178 3179 arcmsr_wait_firmware_ready(acb); 3180 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell); 3181 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3182 printk(KERN_ERR "arcmsr%d: can't set driver mode.\n", acb->host->host_no); 3183 return false; 3184 } 3185 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell); 3186 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3187 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \ 3188 miscellaneous data' timeout \n", acb->host->host_no); 3189 return false; 3190 } 3191 arcmsr_get_adapter_config(acb, reg->message_rwbuffer); 3192 return true; 3193 } 3194 3195 static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB) 3196 { 3197 uint32_t intmask_org; 3198 struct MessageUnit_C __iomem *reg = pACB->pmuC; 3199 3200 /* disable all outbound interrupt */ 3201 intmask_org = readl(®->host_int_mask); /* disable outbound message0 int */ 3202 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask); 3203 /* wait firmware ready */ 3204 arcmsr_wait_firmware_ready(pACB); 3205 /* post "get config" instruction */ 3206 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3207 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3208 /* wait message ready */ 3209 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 3210 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \ 3211 miscellaneous data' timeout \n", pACB->host->host_no); 3212 return false; 3213 } 3214 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer); 3215 return true; 3216 } 3217 3218 static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb) 3219 { 3220 struct MessageUnit_D *reg = acb->pmuD; 3221 3222 if (readl(acb->pmuD->outbound_doorbell) & 3223 ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) { 3224 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, 3225 acb->pmuD->outbound_doorbell);/*clear interrupt*/ 3226 } 3227 arcmsr_wait_firmware_ready(acb); 3228 /* post "get config" instruction */ 3229 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0); 3230 /* wait message ready */ 3231 if (!arcmsr_hbaD_wait_msgint_ready(acb)) { 3232 pr_notice("arcmsr%d: wait get adapter firmware " 3233 "miscellaneous data timeout\n", acb->host->host_no); 3234 return false; 3235 } 3236 arcmsr_get_adapter_config(acb, reg->msgcode_rwbuffer); 3237 return true; 3238 } 3239 3240 static bool arcmsr_hbaE_get_config(struct AdapterControlBlock *pACB) 3241 { 3242 struct MessageUnit_E __iomem *reg = pACB->pmuE; 3243 uint32_t intmask_org; 3244 3245 /* disable all outbound interrupt */ 3246 intmask_org = readl(®->host_int_mask); /* disable outbound message0 int */ 3247 writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, ®->host_int_mask); 3248 /* wait firmware ready */ 3249 arcmsr_wait_firmware_ready(pACB); 3250 mdelay(20); 3251 /* post "get config" instruction */ 3252 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3253 3254 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3255 writel(pACB->out_doorbell, ®->iobound_doorbell); 3256 /* wait message ready */ 3257 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 3258 pr_notice("arcmsr%d: wait get adapter firmware " 3259 "miscellaneous data timeout\n", pACB->host->host_no); 3260 return false; 3261 } 3262 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer); 3263 return true; 3264 } 3265 3266 static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 3267 { 3268 bool rtn = false; 3269 3270 switch (acb->adapter_type) { 3271 case ACB_ADAPTER_TYPE_A: 3272 rtn = arcmsr_hbaA_get_config(acb); 3273 break; 3274 case ACB_ADAPTER_TYPE_B: 3275 rtn = arcmsr_hbaB_get_config(acb); 3276 break; 3277 case ACB_ADAPTER_TYPE_C: 3278 rtn = arcmsr_hbaC_get_config(acb); 3279 break; 3280 case ACB_ADAPTER_TYPE_D: 3281 rtn = arcmsr_hbaD_get_config(acb); 3282 break; 3283 case ACB_ADAPTER_TYPE_E: 3284 rtn = arcmsr_hbaE_get_config(acb); 3285 break; 3286 default: 3287 break; 3288 } 3289 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3290 if (acb->host->can_queue >= acb->firm_numbers_queue) 3291 acb->host->can_queue = acb->maxOutstanding; 3292 else 3293 acb->maxOutstanding = acb->host->can_queue; 3294 acb->maxFreeCCB = acb->host->can_queue; 3295 if (acb->maxFreeCCB < ARCMSR_MAX_FREECCB_NUM) 3296 acb->maxFreeCCB += 64; 3297 return rtn; 3298 } 3299 3300 static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb, 3301 struct CommandControlBlock *poll_ccb) 3302 { 3303 struct MessageUnit_A __iomem *reg = acb->pmuA; 3304 struct CommandControlBlock *ccb; 3305 struct ARCMSR_CDB *arcmsr_cdb; 3306 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0; 3307 int rtn; 3308 bool error; 3309 unsigned long ccb_cdb_phy; 3310 3311 polling_hba_ccb_retry: 3312 poll_count++; 3313 outbound_intstatus = readl(®->outbound_intstatus) & acb->outbound_int_enable; 3314 writel(outbound_intstatus, ®->outbound_intstatus);/*clear interrupt*/ 3315 while (1) { 3316 if ((flag_ccb = readl(®->outbound_queueport)) == 0xFFFFFFFF) { 3317 if (poll_ccb_done){ 3318 rtn = SUCCESS; 3319 break; 3320 }else { 3321 msleep(25); 3322 if (poll_count > 100){ 3323 rtn = FAILED; 3324 break; 3325 } 3326 goto polling_hba_ccb_retry; 3327 } 3328 } 3329 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff; 3330 if (acb->cdb_phyadd_hipart) 3331 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 3332 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy); 3333 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb); 3334 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0; 3335 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) { 3336 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) { 3337 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'" 3338 " poll command abort successfully \n" 3339 , acb->host->host_no 3340 , ccb->pcmd->device->id 3341 , (u32)ccb->pcmd->device->lun 3342 , ccb); 3343 ccb->pcmd->result = DID_ABORT << 16; 3344 arcmsr_ccb_complete(ccb); 3345 continue; 3346 } 3347 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb" 3348 " command done ccb = '0x%p'" 3349 "ccboutstandingcount = %d \n" 3350 , acb->host->host_no 3351 , ccb 3352 , atomic_read(&acb->ccboutstandingcount)); 3353 continue; 3354 } 3355 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 3356 arcmsr_report_ccb_state(acb, ccb, error); 3357 } 3358 return rtn; 3359 } 3360 3361 static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb, 3362 struct CommandControlBlock *poll_ccb) 3363 { 3364 struct MessageUnit_B *reg = acb->pmuB; 3365 struct ARCMSR_CDB *arcmsr_cdb; 3366 struct CommandControlBlock *ccb; 3367 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0; 3368 int index, rtn; 3369 bool error; 3370 unsigned long ccb_cdb_phy; 3371 3372 polling_hbb_ccb_retry: 3373 poll_count++; 3374 /* clear doorbell interrupt */ 3375 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 3376 while(1){ 3377 index = reg->doneq_index; 3378 flag_ccb = reg->done_qbuffer[index]; 3379 if (flag_ccb == 0) { 3380 if (poll_ccb_done){ 3381 rtn = SUCCESS; 3382 break; 3383 }else { 3384 msleep(25); 3385 if (poll_count > 100){ 3386 rtn = FAILED; 3387 break; 3388 } 3389 goto polling_hbb_ccb_retry; 3390 } 3391 } 3392 reg->done_qbuffer[index] = 0; 3393 index++; 3394 /*if last index number set it to 0 */ 3395 index %= ARCMSR_MAX_HBB_POSTQUEUE; 3396 reg->doneq_index = index; 3397 /* check if command done with no error*/ 3398 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff; 3399 if (acb->cdb_phyadd_hipart) 3400 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 3401 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy); 3402 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb); 3403 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0; 3404 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) { 3405 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) { 3406 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'" 3407 " poll command abort successfully \n" 3408 ,acb->host->host_no 3409 ,ccb->pcmd->device->id 3410 ,(u32)ccb->pcmd->device->lun 3411 ,ccb); 3412 ccb->pcmd->result = DID_ABORT << 16; 3413 arcmsr_ccb_complete(ccb); 3414 continue; 3415 } 3416 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb" 3417 " command done ccb = '0x%p'" 3418 "ccboutstandingcount = %d \n" 3419 , acb->host->host_no 3420 , ccb 3421 , atomic_read(&acb->ccboutstandingcount)); 3422 continue; 3423 } 3424 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 3425 arcmsr_report_ccb_state(acb, ccb, error); 3426 } 3427 return rtn; 3428 } 3429 3430 static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb, 3431 struct CommandControlBlock *poll_ccb) 3432 { 3433 struct MessageUnit_C __iomem *reg = acb->pmuC; 3434 uint32_t flag_ccb; 3435 struct ARCMSR_CDB *arcmsr_cdb; 3436 bool error; 3437 struct CommandControlBlock *pCCB; 3438 uint32_t poll_ccb_done = 0, poll_count = 0; 3439 int rtn; 3440 unsigned long ccb_cdb_phy; 3441 3442 polling_hbc_ccb_retry: 3443 poll_count++; 3444 while (1) { 3445 if ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) { 3446 if (poll_ccb_done) { 3447 rtn = SUCCESS; 3448 break; 3449 } else { 3450 msleep(25); 3451 if (poll_count > 100) { 3452 rtn = FAILED; 3453 break; 3454 } 3455 goto polling_hbc_ccb_retry; 3456 } 3457 } 3458 flag_ccb = readl(®->outbound_queueport_low); 3459 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 3460 if (acb->cdb_phyadd_hipart) 3461 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 3462 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy); 3463 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb); 3464 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0; 3465 /* check ifcommand done with no error*/ 3466 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) { 3467 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 3468 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'" 3469 " poll command abort successfully \n" 3470 , acb->host->host_no 3471 , pCCB->pcmd->device->id 3472 , (u32)pCCB->pcmd->device->lun 3473 , pCCB); 3474 pCCB->pcmd->result = DID_ABORT << 16; 3475 arcmsr_ccb_complete(pCCB); 3476 continue; 3477 } 3478 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb" 3479 " command done ccb = '0x%p'" 3480 "ccboutstandingcount = %d \n" 3481 , acb->host->host_no 3482 , pCCB 3483 , atomic_read(&acb->ccboutstandingcount)); 3484 continue; 3485 } 3486 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 3487 arcmsr_report_ccb_state(acb, pCCB, error); 3488 } 3489 return rtn; 3490 } 3491 3492 static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb, 3493 struct CommandControlBlock *poll_ccb) 3494 { 3495 bool error; 3496 uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb; 3497 int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle; 3498 unsigned long flags, ccb_cdb_phy, cdb_phy_hipart; 3499 struct ARCMSR_CDB *arcmsr_cdb; 3500 struct CommandControlBlock *pCCB; 3501 struct MessageUnit_D *pmu = acb->pmuD; 3502 3503 polling_hbaD_ccb_retry: 3504 poll_count++; 3505 while (1) { 3506 spin_lock_irqsave(&acb->doneq_lock, flags); 3507 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1; 3508 doneq_index = pmu->doneq_index; 3509 if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) { 3510 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3511 if (poll_ccb_done) { 3512 rtn = SUCCESS; 3513 break; 3514 } else { 3515 msleep(25); 3516 if (poll_count > 40) { 3517 rtn = FAILED; 3518 break; 3519 } 3520 goto polling_hbaD_ccb_retry; 3521 } 3522 } 3523 toggle = doneq_index & 0x4000; 3524 index_stripped = (doneq_index & 0xFFF) + 1; 3525 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE; 3526 pmu->doneq_index = index_stripped ? (index_stripped | toggle) : 3527 ((toggle ^ 0x4000) + 1); 3528 doneq_index = pmu->doneq_index; 3529 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3530 cdb_phy_hipart = pmu->done_qbuffer[doneq_index & 3531 0xFFF].addressHigh; 3532 flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow; 3533 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 3534 if (acb->cdb_phyadd_hipart) 3535 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 3536 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + 3537 ccb_cdb_phy); 3538 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, 3539 arcmsr_cdb); 3540 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0; 3541 if ((pCCB->acb != acb) || 3542 (pCCB->startdone != ARCMSR_CCB_START)) { 3543 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 3544 pr_notice("arcmsr%d: scsi id = %d " 3545 "lun = %d ccb = '0x%p' poll command " 3546 "abort successfully\n" 3547 , acb->host->host_no 3548 , pCCB->pcmd->device->id 3549 , (u32)pCCB->pcmd->device->lun 3550 , pCCB); 3551 pCCB->pcmd->result = DID_ABORT << 16; 3552 arcmsr_ccb_complete(pCCB); 3553 continue; 3554 } 3555 pr_notice("arcmsr%d: polling an illegal " 3556 "ccb command done ccb = '0x%p' " 3557 "ccboutstandingcount = %d\n" 3558 , acb->host->host_no 3559 , pCCB 3560 , atomic_read(&acb->ccboutstandingcount)); 3561 continue; 3562 } 3563 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) 3564 ? true : false; 3565 arcmsr_report_ccb_state(acb, pCCB, error); 3566 } 3567 return rtn; 3568 } 3569 3570 static int arcmsr_hbaE_polling_ccbdone(struct AdapterControlBlock *acb, 3571 struct CommandControlBlock *poll_ccb) 3572 { 3573 bool error; 3574 uint32_t poll_ccb_done = 0, poll_count = 0, doneq_index; 3575 uint16_t cmdSMID; 3576 unsigned long flags; 3577 int rtn; 3578 struct CommandControlBlock *pCCB; 3579 struct MessageUnit_E __iomem *reg = acb->pmuE; 3580 3581 polling_hbaC_ccb_retry: 3582 poll_count++; 3583 while (1) { 3584 spin_lock_irqsave(&acb->doneq_lock, flags); 3585 doneq_index = acb->doneq_index; 3586 if ((readl(®->reply_post_producer_index) & 0xFFFF) == 3587 doneq_index) { 3588 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3589 if (poll_ccb_done) { 3590 rtn = SUCCESS; 3591 break; 3592 } else { 3593 msleep(25); 3594 if (poll_count > 40) { 3595 rtn = FAILED; 3596 break; 3597 } 3598 goto polling_hbaC_ccb_retry; 3599 } 3600 } 3601 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 3602 doneq_index++; 3603 if (doneq_index >= acb->completionQ_entry) 3604 doneq_index = 0; 3605 acb->doneq_index = doneq_index; 3606 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3607 pCCB = acb->pccb_pool[cmdSMID]; 3608 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0; 3609 /* check if command done with no error*/ 3610 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) { 3611 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 3612 pr_notice("arcmsr%d: scsi id = %d " 3613 "lun = %d ccb = '0x%p' poll command " 3614 "abort successfully\n" 3615 , acb->host->host_no 3616 , pCCB->pcmd->device->id 3617 , (u32)pCCB->pcmd->device->lun 3618 , pCCB); 3619 pCCB->pcmd->result = DID_ABORT << 16; 3620 arcmsr_ccb_complete(pCCB); 3621 continue; 3622 } 3623 pr_notice("arcmsr%d: polling an illegal " 3624 "ccb command done ccb = '0x%p' " 3625 "ccboutstandingcount = %d\n" 3626 , acb->host->host_no 3627 , pCCB 3628 , atomic_read(&acb->ccboutstandingcount)); 3629 continue; 3630 } 3631 error = (acb->pCompletionQ[doneq_index].cmdFlag & 3632 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 3633 arcmsr_report_ccb_state(acb, pCCB, error); 3634 } 3635 writel(doneq_index, ®->reply_post_consumer_index); 3636 return rtn; 3637 } 3638 3639 static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb, 3640 struct CommandControlBlock *poll_ccb) 3641 { 3642 int rtn = 0; 3643 switch (acb->adapter_type) { 3644 3645 case ACB_ADAPTER_TYPE_A: { 3646 rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb); 3647 } 3648 break; 3649 3650 case ACB_ADAPTER_TYPE_B: { 3651 rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb); 3652 } 3653 break; 3654 case ACB_ADAPTER_TYPE_C: { 3655 rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb); 3656 } 3657 break; 3658 case ACB_ADAPTER_TYPE_D: 3659 rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb); 3660 break; 3661 case ACB_ADAPTER_TYPE_E: 3662 rtn = arcmsr_hbaE_polling_ccbdone(acb, poll_ccb); 3663 break; 3664 } 3665 return rtn; 3666 } 3667 3668 static void arcmsr_set_iop_datetime(struct timer_list *t) 3669 { 3670 struct AdapterControlBlock *pacb = from_timer(pacb, t, refresh_timer); 3671 unsigned int next_time; 3672 struct tm tm; 3673 3674 union { 3675 struct { 3676 uint16_t signature; 3677 uint8_t year; 3678 uint8_t month; 3679 uint8_t date; 3680 uint8_t hour; 3681 uint8_t minute; 3682 uint8_t second; 3683 } a; 3684 struct { 3685 uint32_t msg_time[2]; 3686 } b; 3687 } datetime; 3688 3689 time64_to_tm(ktime_get_real_seconds(), -sys_tz.tz_minuteswest * 60, &tm); 3690 3691 datetime.a.signature = 0x55AA; 3692 datetime.a.year = tm.tm_year - 100; /* base 2000 instead of 1900 */ 3693 datetime.a.month = tm.tm_mon; 3694 datetime.a.date = tm.tm_mday; 3695 datetime.a.hour = tm.tm_hour; 3696 datetime.a.minute = tm.tm_min; 3697 datetime.a.second = tm.tm_sec; 3698 3699 switch (pacb->adapter_type) { 3700 case ACB_ADAPTER_TYPE_A: { 3701 struct MessageUnit_A __iomem *reg = pacb->pmuA; 3702 writel(datetime.b.msg_time[0], ®->message_rwbuffer[0]); 3703 writel(datetime.b.msg_time[1], ®->message_rwbuffer[1]); 3704 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); 3705 break; 3706 } 3707 case ACB_ADAPTER_TYPE_B: { 3708 uint32_t __iomem *rwbuffer; 3709 struct MessageUnit_B *reg = pacb->pmuB; 3710 rwbuffer = reg->message_rwbuffer; 3711 writel(datetime.b.msg_time[0], rwbuffer++); 3712 writel(datetime.b.msg_time[1], rwbuffer++); 3713 writel(ARCMSR_MESSAGE_SYNC_TIMER, reg->drv2iop_doorbell); 3714 break; 3715 } 3716 case ACB_ADAPTER_TYPE_C: { 3717 struct MessageUnit_C __iomem *reg = pacb->pmuC; 3718 writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]); 3719 writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]); 3720 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); 3721 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3722 break; 3723 } 3724 case ACB_ADAPTER_TYPE_D: { 3725 uint32_t __iomem *rwbuffer; 3726 struct MessageUnit_D *reg = pacb->pmuD; 3727 rwbuffer = reg->msgcode_rwbuffer; 3728 writel(datetime.b.msg_time[0], rwbuffer++); 3729 writel(datetime.b.msg_time[1], rwbuffer++); 3730 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, reg->inbound_msgaddr0); 3731 break; 3732 } 3733 case ACB_ADAPTER_TYPE_E: { 3734 struct MessageUnit_E __iomem *reg = pacb->pmuE; 3735 writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]); 3736 writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]); 3737 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); 3738 pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3739 writel(pacb->out_doorbell, ®->iobound_doorbell); 3740 break; 3741 } 3742 } 3743 if (sys_tz.tz_minuteswest) 3744 next_time = ARCMSR_HOURS; 3745 else 3746 next_time = ARCMSR_MINUTES; 3747 mod_timer(&pacb->refresh_timer, jiffies + msecs_to_jiffies(next_time)); 3748 } 3749 3750 static int arcmsr_iop_confirm(struct AdapterControlBlock *acb) 3751 { 3752 uint32_t cdb_phyaddr, cdb_phyaddr_hi32; 3753 dma_addr_t dma_coherent_handle; 3754 3755 /* 3756 ******************************************************************** 3757 ** here we need to tell iop 331 our freeccb.HighPart 3758 ** if freeccb.HighPart is not zero 3759 ******************************************************************** 3760 */ 3761 switch (acb->adapter_type) { 3762 case ACB_ADAPTER_TYPE_B: 3763 case ACB_ADAPTER_TYPE_D: 3764 dma_coherent_handle = acb->dma_coherent_handle2; 3765 break; 3766 case ACB_ADAPTER_TYPE_E: 3767 dma_coherent_handle = acb->dma_coherent_handle + 3768 offsetof(struct CommandControlBlock, arcmsr_cdb); 3769 break; 3770 default: 3771 dma_coherent_handle = acb->dma_coherent_handle; 3772 break; 3773 } 3774 cdb_phyaddr = lower_32_bits(dma_coherent_handle); 3775 cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle); 3776 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32; 3777 acb->cdb_phyadd_hipart = ((uint64_t)cdb_phyaddr_hi32) << 32; 3778 /* 3779 *********************************************************************** 3780 ** if adapter type B, set window of "post command Q" 3781 *********************************************************************** 3782 */ 3783 switch (acb->adapter_type) { 3784 3785 case ACB_ADAPTER_TYPE_A: { 3786 if (cdb_phyaddr_hi32 != 0) { 3787 struct MessageUnit_A __iomem *reg = acb->pmuA; 3788 writel(ARCMSR_SIGNATURE_SET_CONFIG, \ 3789 ®->message_rwbuffer[0]); 3790 writel(cdb_phyaddr_hi32, ®->message_rwbuffer[1]); 3791 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \ 3792 ®->inbound_msgaddr0); 3793 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 3794 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \ 3795 part physical address timeout\n", 3796 acb->host->host_no); 3797 return 1; 3798 } 3799 } 3800 } 3801 break; 3802 3803 case ACB_ADAPTER_TYPE_B: { 3804 uint32_t __iomem *rwbuffer; 3805 3806 struct MessageUnit_B *reg = acb->pmuB; 3807 reg->postq_index = 0; 3808 reg->doneq_index = 0; 3809 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell); 3810 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3811 printk(KERN_NOTICE "arcmsr%d: cannot set driver mode\n", \ 3812 acb->host->host_no); 3813 return 1; 3814 } 3815 rwbuffer = reg->message_rwbuffer; 3816 /* driver "set config" signature */ 3817 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++); 3818 /* normal should be zero */ 3819 writel(cdb_phyaddr_hi32, rwbuffer++); 3820 /* postQ size (256 + 8)*4 */ 3821 writel(cdb_phyaddr, rwbuffer++); 3822 /* doneQ size (256 + 8)*4 */ 3823 writel(cdb_phyaddr + 1056, rwbuffer++); 3824 /* ccb maxQ size must be --> [(256 + 8)*4]*/ 3825 writel(1056, rwbuffer); 3826 3827 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell); 3828 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3829 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \ 3830 timeout \n",acb->host->host_no); 3831 return 1; 3832 } 3833 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell); 3834 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3835 pr_err("arcmsr%d: can't set driver mode.\n", 3836 acb->host->host_no); 3837 return 1; 3838 } 3839 } 3840 break; 3841 case ACB_ADAPTER_TYPE_C: { 3842 struct MessageUnit_C __iomem *reg = acb->pmuC; 3843 3844 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n", 3845 acb->adapter_index, cdb_phyaddr_hi32); 3846 writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]); 3847 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[1]); 3848 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0); 3849 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3850 if (!arcmsr_hbaC_wait_msgint_ready(acb)) { 3851 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \ 3852 timeout \n", acb->host->host_no); 3853 return 1; 3854 } 3855 } 3856 break; 3857 case ACB_ADAPTER_TYPE_D: { 3858 uint32_t __iomem *rwbuffer; 3859 struct MessageUnit_D *reg = acb->pmuD; 3860 reg->postq_index = 0; 3861 reg->doneq_index = 0; 3862 rwbuffer = reg->msgcode_rwbuffer; 3863 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++); 3864 writel(cdb_phyaddr_hi32, rwbuffer++); 3865 writel(cdb_phyaddr, rwbuffer++); 3866 writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE * 3867 sizeof(struct InBound_SRB)), rwbuffer++); 3868 writel(0x100, rwbuffer); 3869 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0); 3870 if (!arcmsr_hbaD_wait_msgint_ready(acb)) { 3871 pr_notice("arcmsr%d: 'set command Q window' timeout\n", 3872 acb->host->host_no); 3873 return 1; 3874 } 3875 } 3876 break; 3877 case ACB_ADAPTER_TYPE_E: { 3878 struct MessageUnit_E __iomem *reg = acb->pmuE; 3879 writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]); 3880 writel(ARCMSR_SIGNATURE_1884, ®->msgcode_rwbuffer[1]); 3881 writel(cdb_phyaddr, ®->msgcode_rwbuffer[2]); 3882 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[3]); 3883 writel(acb->ccbsize, ®->msgcode_rwbuffer[4]); 3884 dma_coherent_handle = acb->dma_coherent_handle2; 3885 cdb_phyaddr = (uint32_t)(dma_coherent_handle & 0xffffffff); 3886 cdb_phyaddr_hi32 = (uint32_t)((dma_coherent_handle >> 16) >> 16); 3887 writel(cdb_phyaddr, ®->msgcode_rwbuffer[5]); 3888 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[6]); 3889 writel(acb->ioqueue_size, ®->msgcode_rwbuffer[7]); 3890 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0); 3891 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3892 writel(acb->out_doorbell, ®->iobound_doorbell); 3893 if (!arcmsr_hbaE_wait_msgint_ready(acb)) { 3894 pr_notice("arcmsr%d: 'set command Q window' timeout \n", 3895 acb->host->host_no); 3896 return 1; 3897 } 3898 } 3899 break; 3900 } 3901 return 0; 3902 } 3903 3904 static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb) 3905 { 3906 uint32_t firmware_state = 0; 3907 switch (acb->adapter_type) { 3908 3909 case ACB_ADAPTER_TYPE_A: { 3910 struct MessageUnit_A __iomem *reg = acb->pmuA; 3911 do { 3912 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3913 msleep(20); 3914 firmware_state = readl(®->outbound_msgaddr1); 3915 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0); 3916 } 3917 break; 3918 3919 case ACB_ADAPTER_TYPE_B: { 3920 struct MessageUnit_B *reg = acb->pmuB; 3921 do { 3922 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3923 msleep(20); 3924 firmware_state = readl(reg->iop2drv_doorbell); 3925 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0); 3926 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell); 3927 } 3928 break; 3929 case ACB_ADAPTER_TYPE_C: { 3930 struct MessageUnit_C __iomem *reg = acb->pmuC; 3931 do { 3932 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3933 msleep(20); 3934 firmware_state = readl(®->outbound_msgaddr1); 3935 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0); 3936 } 3937 break; 3938 case ACB_ADAPTER_TYPE_D: { 3939 struct MessageUnit_D *reg = acb->pmuD; 3940 do { 3941 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3942 msleep(20); 3943 firmware_state = readl(reg->outbound_msgaddr1); 3944 } while ((firmware_state & 3945 ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0); 3946 } 3947 break; 3948 case ACB_ADAPTER_TYPE_E: { 3949 struct MessageUnit_E __iomem *reg = acb->pmuE; 3950 do { 3951 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3952 msleep(20); 3953 firmware_state = readl(®->outbound_msgaddr1); 3954 } while ((firmware_state & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0); 3955 } 3956 break; 3957 } 3958 } 3959 3960 static void arcmsr_request_device_map(struct timer_list *t) 3961 { 3962 struct AdapterControlBlock *acb = from_timer(acb, t, eternal_timer); 3963 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || 3964 (acb->acb_flags & ACB_F_BUS_RESET) || 3965 (acb->acb_flags & ACB_F_ABORT)) { 3966 mod_timer(&acb->eternal_timer, 3967 jiffies + msecs_to_jiffies(6 * HZ)); 3968 } else { 3969 acb->fw_flag = FW_NORMAL; 3970 if (atomic_read(&acb->ante_token_value) == 3971 atomic_read(&acb->rq_map_token)) { 3972 atomic_set(&acb->rq_map_token, 16); 3973 } 3974 atomic_set(&acb->ante_token_value, 3975 atomic_read(&acb->rq_map_token)); 3976 if (atomic_dec_and_test(&acb->rq_map_token)) { 3977 mod_timer(&acb->eternal_timer, jiffies + 3978 msecs_to_jiffies(6 * HZ)); 3979 return; 3980 } 3981 switch (acb->adapter_type) { 3982 case ACB_ADAPTER_TYPE_A: { 3983 struct MessageUnit_A __iomem *reg = acb->pmuA; 3984 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3985 break; 3986 } 3987 case ACB_ADAPTER_TYPE_B: { 3988 struct MessageUnit_B *reg = acb->pmuB; 3989 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell); 3990 break; 3991 } 3992 case ACB_ADAPTER_TYPE_C: { 3993 struct MessageUnit_C __iomem *reg = acb->pmuC; 3994 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3995 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3996 break; 3997 } 3998 case ACB_ADAPTER_TYPE_D: { 3999 struct MessageUnit_D *reg = acb->pmuD; 4000 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0); 4001 break; 4002 } 4003 case ACB_ADAPTER_TYPE_E: { 4004 struct MessageUnit_E __iomem *reg = acb->pmuE; 4005 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 4006 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4007 writel(acb->out_doorbell, ®->iobound_doorbell); 4008 break; 4009 } 4010 default: 4011 return; 4012 } 4013 acb->acb_flags |= ACB_F_MSG_GET_CONFIG; 4014 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ)); 4015 } 4016 } 4017 4018 static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb) 4019 { 4020 struct MessageUnit_A __iomem *reg = acb->pmuA; 4021 acb->acb_flags |= ACB_F_MSG_START_BGRB; 4022 writel(ARCMSR_INBOUND_MESG0_START_BGRB, ®->inbound_msgaddr0); 4023 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 4024 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \ 4025 rebuild' timeout \n", acb->host->host_no); 4026 } 4027 } 4028 4029 static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb) 4030 { 4031 struct MessageUnit_B *reg = acb->pmuB; 4032 acb->acb_flags |= ACB_F_MSG_START_BGRB; 4033 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell); 4034 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 4035 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \ 4036 rebuild' timeout \n",acb->host->host_no); 4037 } 4038 } 4039 4040 static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB) 4041 { 4042 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC; 4043 pACB->acb_flags |= ACB_F_MSG_START_BGRB; 4044 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0); 4045 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell); 4046 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 4047 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \ 4048 rebuild' timeout \n", pACB->host->host_no); 4049 } 4050 return; 4051 } 4052 4053 static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB) 4054 { 4055 struct MessageUnit_D *pmu = pACB->pmuD; 4056 4057 pACB->acb_flags |= ACB_F_MSG_START_BGRB; 4058 writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0); 4059 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) { 4060 pr_notice("arcmsr%d: wait 'start adapter " 4061 "background rebuild' timeout\n", pACB->host->host_no); 4062 } 4063 } 4064 4065 static void arcmsr_hbaE_start_bgrb(struct AdapterControlBlock *pACB) 4066 { 4067 struct MessageUnit_E __iomem *pmu = pACB->pmuE; 4068 4069 pACB->acb_flags |= ACB_F_MSG_START_BGRB; 4070 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &pmu->inbound_msgaddr0); 4071 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4072 writel(pACB->out_doorbell, &pmu->iobound_doorbell); 4073 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 4074 pr_notice("arcmsr%d: wait 'start adapter " 4075 "background rebuild' timeout \n", pACB->host->host_no); 4076 } 4077 } 4078 4079 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 4080 { 4081 switch (acb->adapter_type) { 4082 case ACB_ADAPTER_TYPE_A: 4083 arcmsr_hbaA_start_bgrb(acb); 4084 break; 4085 case ACB_ADAPTER_TYPE_B: 4086 arcmsr_hbaB_start_bgrb(acb); 4087 break; 4088 case ACB_ADAPTER_TYPE_C: 4089 arcmsr_hbaC_start_bgrb(acb); 4090 break; 4091 case ACB_ADAPTER_TYPE_D: 4092 arcmsr_hbaD_start_bgrb(acb); 4093 break; 4094 case ACB_ADAPTER_TYPE_E: 4095 arcmsr_hbaE_start_bgrb(acb); 4096 break; 4097 } 4098 } 4099 4100 static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb) 4101 { 4102 switch (acb->adapter_type) { 4103 case ACB_ADAPTER_TYPE_A: { 4104 struct MessageUnit_A __iomem *reg = acb->pmuA; 4105 uint32_t outbound_doorbell; 4106 /* empty doorbell Qbuffer if door bell ringed */ 4107 outbound_doorbell = readl(®->outbound_doorbell); 4108 /*clear doorbell interrupt */ 4109 writel(outbound_doorbell, ®->outbound_doorbell); 4110 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell); 4111 } 4112 break; 4113 4114 case ACB_ADAPTER_TYPE_B: { 4115 struct MessageUnit_B *reg = acb->pmuB; 4116 uint32_t outbound_doorbell, i; 4117 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 4118 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); 4119 /* let IOP know data has been read */ 4120 for(i=0; i < 200; i++) { 4121 msleep(20); 4122 outbound_doorbell = readl(reg->iop2drv_doorbell); 4123 if( outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 4124 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 4125 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); 4126 } else 4127 break; 4128 } 4129 } 4130 break; 4131 case ACB_ADAPTER_TYPE_C: { 4132 struct MessageUnit_C __iomem *reg = acb->pmuC; 4133 uint32_t outbound_doorbell, i; 4134 /* empty doorbell Qbuffer if door bell ringed */ 4135 outbound_doorbell = readl(®->outbound_doorbell); 4136 writel(outbound_doorbell, ®->outbound_doorbell_clear); 4137 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell); 4138 for (i = 0; i < 200; i++) { 4139 msleep(20); 4140 outbound_doorbell = readl(®->outbound_doorbell); 4141 if (outbound_doorbell & 4142 ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 4143 writel(outbound_doorbell, 4144 ®->outbound_doorbell_clear); 4145 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, 4146 ®->inbound_doorbell); 4147 } else 4148 break; 4149 } 4150 } 4151 break; 4152 case ACB_ADAPTER_TYPE_D: { 4153 struct MessageUnit_D *reg = acb->pmuD; 4154 uint32_t outbound_doorbell, i; 4155 /* empty doorbell Qbuffer if door bell ringed */ 4156 outbound_doorbell = readl(reg->outbound_doorbell); 4157 writel(outbound_doorbell, reg->outbound_doorbell); 4158 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ, 4159 reg->inbound_doorbell); 4160 for (i = 0; i < 200; i++) { 4161 msleep(20); 4162 outbound_doorbell = readl(reg->outbound_doorbell); 4163 if (outbound_doorbell & 4164 ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) { 4165 writel(outbound_doorbell, 4166 reg->outbound_doorbell); 4167 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ, 4168 reg->inbound_doorbell); 4169 } else 4170 break; 4171 } 4172 } 4173 break; 4174 case ACB_ADAPTER_TYPE_E: { 4175 struct MessageUnit_E __iomem *reg = acb->pmuE; 4176 uint32_t i, tmp; 4177 4178 acb->in_doorbell = readl(®->iobound_doorbell); 4179 writel(0, ®->host_int_status); /*clear interrupt*/ 4180 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4181 writel(acb->out_doorbell, ®->iobound_doorbell); 4182 for(i=0; i < 200; i++) { 4183 msleep(20); 4184 tmp = acb->in_doorbell; 4185 acb->in_doorbell = readl(®->iobound_doorbell); 4186 if((tmp ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 4187 writel(0, ®->host_int_status); /*clear interrupt*/ 4188 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4189 writel(acb->out_doorbell, ®->iobound_doorbell); 4190 } else 4191 break; 4192 } 4193 } 4194 break; 4195 } 4196 } 4197 4198 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 4199 { 4200 switch (acb->adapter_type) { 4201 case ACB_ADAPTER_TYPE_A: 4202 return; 4203 case ACB_ADAPTER_TYPE_B: 4204 { 4205 struct MessageUnit_B *reg = acb->pmuB; 4206 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell); 4207 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 4208 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT"); 4209 return; 4210 } 4211 } 4212 break; 4213 case ACB_ADAPTER_TYPE_C: 4214 return; 4215 } 4216 return; 4217 } 4218 4219 static void arcmsr_hardware_reset(struct AdapterControlBlock *acb) 4220 { 4221 uint8_t value[64]; 4222 int i, count = 0; 4223 struct MessageUnit_A __iomem *pmuA = acb->pmuA; 4224 struct MessageUnit_C __iomem *pmuC = acb->pmuC; 4225 struct MessageUnit_D *pmuD = acb->pmuD; 4226 4227 /* backup pci config data */ 4228 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no); 4229 for (i = 0; i < 64; i++) { 4230 pci_read_config_byte(acb->pdev, i, &value[i]); 4231 } 4232 /* hardware reset signal */ 4233 if (acb->dev_id == 0x1680) { 4234 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]); 4235 } else if (acb->dev_id == 0x1880) { 4236 do { 4237 count++; 4238 writel(0xF, &pmuC->write_sequence); 4239 writel(0x4, &pmuC->write_sequence); 4240 writel(0xB, &pmuC->write_sequence); 4241 writel(0x2, &pmuC->write_sequence); 4242 writel(0x7, &pmuC->write_sequence); 4243 writel(0xD, &pmuC->write_sequence); 4244 } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5)); 4245 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic); 4246 } else if (acb->dev_id == 0x1884) { 4247 struct MessageUnit_E __iomem *pmuE = acb->pmuE; 4248 do { 4249 count++; 4250 writel(0x4, &pmuE->write_sequence_3xxx); 4251 writel(0xB, &pmuE->write_sequence_3xxx); 4252 writel(0x2, &pmuE->write_sequence_3xxx); 4253 writel(0x7, &pmuE->write_sequence_3xxx); 4254 writel(0xD, &pmuE->write_sequence_3xxx); 4255 mdelay(10); 4256 } while (((readl(&pmuE->host_diagnostic_3xxx) & 4257 ARCMSR_ARC1884_DiagWrite_ENABLE) == 0) && (count < 5)); 4258 writel(ARCMSR_ARC188X_RESET_ADAPTER, &pmuE->host_diagnostic_3xxx); 4259 } else if (acb->dev_id == 0x1214) { 4260 writel(0x20, pmuD->reset_request); 4261 } else { 4262 pci_write_config_byte(acb->pdev, 0x84, 0x20); 4263 } 4264 msleep(2000); 4265 /* write back pci config data */ 4266 for (i = 0; i < 64; i++) { 4267 pci_write_config_byte(acb->pdev, i, value[i]); 4268 } 4269 msleep(1000); 4270 return; 4271 } 4272 4273 static bool arcmsr_reset_in_progress(struct AdapterControlBlock *acb) 4274 { 4275 bool rtn = true; 4276 4277 switch(acb->adapter_type) { 4278 case ACB_ADAPTER_TYPE_A:{ 4279 struct MessageUnit_A __iomem *reg = acb->pmuA; 4280 rtn = ((readl(®->outbound_msgaddr1) & 4281 ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) ? true : false; 4282 } 4283 break; 4284 case ACB_ADAPTER_TYPE_B:{ 4285 struct MessageUnit_B *reg = acb->pmuB; 4286 rtn = ((readl(reg->iop2drv_doorbell) & 4287 ARCMSR_MESSAGE_FIRMWARE_OK) == 0) ? true : false; 4288 } 4289 break; 4290 case ACB_ADAPTER_TYPE_C:{ 4291 struct MessageUnit_C __iomem *reg = acb->pmuC; 4292 rtn = (readl(®->host_diagnostic) & 0x04) ? true : false; 4293 } 4294 break; 4295 case ACB_ADAPTER_TYPE_D:{ 4296 struct MessageUnit_D *reg = acb->pmuD; 4297 rtn = ((readl(reg->sample_at_reset) & 0x80) == 0) ? 4298 true : false; 4299 } 4300 break; 4301 case ACB_ADAPTER_TYPE_E:{ 4302 struct MessageUnit_E __iomem *reg = acb->pmuE; 4303 rtn = (readl(®->host_diagnostic_3xxx) & 4304 ARCMSR_ARC188X_RESET_ADAPTER) ? true : false; 4305 } 4306 break; 4307 } 4308 return rtn; 4309 } 4310 4311 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 4312 { 4313 uint32_t intmask_org; 4314 /* disable all outbound interrupt */ 4315 intmask_org = arcmsr_disable_outbound_ints(acb); 4316 arcmsr_wait_firmware_ready(acb); 4317 arcmsr_iop_confirm(acb); 4318 /*start background rebuild*/ 4319 arcmsr_start_adapter_bgrb(acb); 4320 /* empty doorbell Qbuffer if door bell ringed */ 4321 arcmsr_clear_doorbell_queue_buffer(acb); 4322 arcmsr_enable_eoi_mode(acb); 4323 /* enable outbound Post Queue,outbound doorbell Interrupt */ 4324 arcmsr_enable_outbound_ints(acb, intmask_org); 4325 acb->acb_flags |= ACB_F_IOP_INITED; 4326 } 4327 4328 static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb) 4329 { 4330 struct CommandControlBlock *ccb; 4331 uint32_t intmask_org; 4332 uint8_t rtnval = 0x00; 4333 int i = 0; 4334 unsigned long flags; 4335 4336 if (atomic_read(&acb->ccboutstandingcount) != 0) { 4337 /* disable all outbound interrupt */ 4338 intmask_org = arcmsr_disable_outbound_ints(acb); 4339 /* talk to iop 331 outstanding command aborted */ 4340 rtnval = arcmsr_abort_allcmd(acb); 4341 /* clear all outbound posted Q */ 4342 arcmsr_done4abort_postqueue(acb); 4343 for (i = 0; i < acb->maxFreeCCB; i++) { 4344 ccb = acb->pccb_pool[i]; 4345 if (ccb->startdone == ARCMSR_CCB_START) { 4346 scsi_dma_unmap(ccb->pcmd); 4347 ccb->startdone = ARCMSR_CCB_DONE; 4348 ccb->ccb_flags = 0; 4349 spin_lock_irqsave(&acb->ccblist_lock, flags); 4350 list_add_tail(&ccb->list, &acb->ccb_free_list); 4351 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 4352 } 4353 } 4354 atomic_set(&acb->ccboutstandingcount, 0); 4355 /* enable all outbound interrupt */ 4356 arcmsr_enable_outbound_ints(acb, intmask_org); 4357 return rtnval; 4358 } 4359 return rtnval; 4360 } 4361 4362 static int arcmsr_bus_reset(struct scsi_cmnd *cmd) 4363 { 4364 struct AdapterControlBlock *acb; 4365 int retry_count = 0; 4366 int rtn = FAILED; 4367 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata; 4368 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) 4369 return SUCCESS; 4370 pr_notice("arcmsr: executing bus reset eh.....num_resets = %d," 4371 " num_aborts = %d \n", acb->num_resets, acb->num_aborts); 4372 acb->num_resets++; 4373 4374 if (acb->acb_flags & ACB_F_BUS_RESET) { 4375 long timeout; 4376 pr_notice("arcmsr: there is a bus reset eh proceeding...\n"); 4377 timeout = wait_event_timeout(wait_q, (acb->acb_flags 4378 & ACB_F_BUS_RESET) == 0, 220 * HZ); 4379 if (timeout) 4380 return SUCCESS; 4381 } 4382 acb->acb_flags |= ACB_F_BUS_RESET; 4383 if (!arcmsr_iop_reset(acb)) { 4384 arcmsr_hardware_reset(acb); 4385 acb->acb_flags &= ~ACB_F_IOP_INITED; 4386 wait_reset_done: 4387 ssleep(ARCMSR_SLEEPTIME); 4388 if (arcmsr_reset_in_progress(acb)) { 4389 if (retry_count > ARCMSR_RETRYCOUNT) { 4390 acb->fw_flag = FW_DEADLOCK; 4391 pr_notice("arcmsr%d: waiting for hw bus reset" 4392 " return, RETRY TERMINATED!!\n", 4393 acb->host->host_no); 4394 return FAILED; 4395 } 4396 retry_count++; 4397 goto wait_reset_done; 4398 } 4399 arcmsr_iop_init(acb); 4400 atomic_set(&acb->rq_map_token, 16); 4401 atomic_set(&acb->ante_token_value, 16); 4402 acb->fw_flag = FW_NORMAL; 4403 mod_timer(&acb->eternal_timer, jiffies + 4404 msecs_to_jiffies(6 * HZ)); 4405 acb->acb_flags &= ~ACB_F_BUS_RESET; 4406 rtn = SUCCESS; 4407 pr_notice("arcmsr: scsi bus reset eh returns with success\n"); 4408 } else { 4409 acb->acb_flags &= ~ACB_F_BUS_RESET; 4410 atomic_set(&acb->rq_map_token, 16); 4411 atomic_set(&acb->ante_token_value, 16); 4412 acb->fw_flag = FW_NORMAL; 4413 mod_timer(&acb->eternal_timer, jiffies + 4414 msecs_to_jiffies(6 * HZ)); 4415 rtn = SUCCESS; 4416 } 4417 return rtn; 4418 } 4419 4420 static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb, 4421 struct CommandControlBlock *ccb) 4422 { 4423 int rtn; 4424 rtn = arcmsr_polling_ccbdone(acb, ccb); 4425 return rtn; 4426 } 4427 4428 static int arcmsr_abort(struct scsi_cmnd *cmd) 4429 { 4430 struct AdapterControlBlock *acb = 4431 (struct AdapterControlBlock *)cmd->device->host->hostdata; 4432 int i = 0; 4433 int rtn = FAILED; 4434 uint32_t intmask_org; 4435 4436 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) 4437 return SUCCESS; 4438 printk(KERN_NOTICE 4439 "arcmsr%d: abort device command of scsi id = %d lun = %d\n", 4440 acb->host->host_no, cmd->device->id, (u32)cmd->device->lun); 4441 acb->acb_flags |= ACB_F_ABORT; 4442 acb->num_aborts++; 4443 /* 4444 ************************************************ 4445 ** the all interrupt service routine is locked 4446 ** we need to handle it as soon as possible and exit 4447 ************************************************ 4448 */ 4449 if (!atomic_read(&acb->ccboutstandingcount)) { 4450 acb->acb_flags &= ~ACB_F_ABORT; 4451 return rtn; 4452 } 4453 4454 intmask_org = arcmsr_disable_outbound_ints(acb); 4455 for (i = 0; i < acb->maxFreeCCB; i++) { 4456 struct CommandControlBlock *ccb = acb->pccb_pool[i]; 4457 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) { 4458 ccb->startdone = ARCMSR_CCB_ABORTED; 4459 rtn = arcmsr_abort_one_cmd(acb, ccb); 4460 break; 4461 } 4462 } 4463 acb->acb_flags &= ~ACB_F_ABORT; 4464 arcmsr_enable_outbound_ints(acb, intmask_org); 4465 return rtn; 4466 } 4467 4468 static const char *arcmsr_info(struct Scsi_Host *host) 4469 { 4470 struct AdapterControlBlock *acb = 4471 (struct AdapterControlBlock *) host->hostdata; 4472 static char buf[256]; 4473 char *type; 4474 int raid6 = 1; 4475 switch (acb->pdev->device) { 4476 case PCI_DEVICE_ID_ARECA_1110: 4477 case PCI_DEVICE_ID_ARECA_1200: 4478 case PCI_DEVICE_ID_ARECA_1202: 4479 case PCI_DEVICE_ID_ARECA_1210: 4480 raid6 = 0; 4481 /*FALLTHRU*/ 4482 case PCI_DEVICE_ID_ARECA_1120: 4483 case PCI_DEVICE_ID_ARECA_1130: 4484 case PCI_DEVICE_ID_ARECA_1160: 4485 case PCI_DEVICE_ID_ARECA_1170: 4486 case PCI_DEVICE_ID_ARECA_1201: 4487 case PCI_DEVICE_ID_ARECA_1203: 4488 case PCI_DEVICE_ID_ARECA_1220: 4489 case PCI_DEVICE_ID_ARECA_1230: 4490 case PCI_DEVICE_ID_ARECA_1260: 4491 case PCI_DEVICE_ID_ARECA_1270: 4492 case PCI_DEVICE_ID_ARECA_1280: 4493 type = "SATA"; 4494 break; 4495 case PCI_DEVICE_ID_ARECA_1214: 4496 case PCI_DEVICE_ID_ARECA_1380: 4497 case PCI_DEVICE_ID_ARECA_1381: 4498 case PCI_DEVICE_ID_ARECA_1680: 4499 case PCI_DEVICE_ID_ARECA_1681: 4500 case PCI_DEVICE_ID_ARECA_1880: 4501 case PCI_DEVICE_ID_ARECA_1884: 4502 type = "SAS/SATA"; 4503 break; 4504 default: 4505 type = "unknown"; 4506 raid6 = 0; 4507 break; 4508 } 4509 sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n", 4510 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 4511 return buf; 4512 } 4513