1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ 2 /* Copyright (c) 2017-2019 Pensando Systems, Inc. All rights reserved. */ 3 4 #ifndef _IONIC_IF_H_ 5 #define _IONIC_IF_H_ 6 7 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ 8 #define IONIC_DEV_INFO_VERSION 1 9 #define IONIC_IFNAMSIZ 16 10 11 /** 12 * Commands 13 */ 14 enum ionic_cmd_opcode { 15 IONIC_CMD_NOP = 0, 16 17 /* Device commands */ 18 IONIC_CMD_IDENTIFY = 1, 19 IONIC_CMD_INIT = 2, 20 IONIC_CMD_RESET = 3, 21 IONIC_CMD_GETATTR = 4, 22 IONIC_CMD_SETATTR = 5, 23 24 /* Port commands */ 25 IONIC_CMD_PORT_IDENTIFY = 10, 26 IONIC_CMD_PORT_INIT = 11, 27 IONIC_CMD_PORT_RESET = 12, 28 IONIC_CMD_PORT_GETATTR = 13, 29 IONIC_CMD_PORT_SETATTR = 14, 30 31 /* LIF commands */ 32 IONIC_CMD_LIF_IDENTIFY = 20, 33 IONIC_CMD_LIF_INIT = 21, 34 IONIC_CMD_LIF_RESET = 22, 35 IONIC_CMD_LIF_GETATTR = 23, 36 IONIC_CMD_LIF_SETATTR = 24, 37 38 IONIC_CMD_RX_MODE_SET = 30, 39 IONIC_CMD_RX_FILTER_ADD = 31, 40 IONIC_CMD_RX_FILTER_DEL = 32, 41 42 /* Queue commands */ 43 IONIC_CMD_Q_INIT = 40, 44 IONIC_CMD_Q_CONTROL = 41, 45 46 /* RDMA commands */ 47 IONIC_CMD_RDMA_RESET_LIF = 50, 48 IONIC_CMD_RDMA_CREATE_EQ = 51, 49 IONIC_CMD_RDMA_CREATE_CQ = 52, 50 IONIC_CMD_RDMA_CREATE_ADMINQ = 53, 51 52 /* SR/IOV commands */ 53 IONIC_CMD_VF_GETATTR = 60, 54 IONIC_CMD_VF_SETATTR = 61, 55 56 /* QoS commands */ 57 IONIC_CMD_QOS_CLASS_IDENTIFY = 240, 58 IONIC_CMD_QOS_CLASS_INIT = 241, 59 IONIC_CMD_QOS_CLASS_RESET = 242, 60 61 /* Firmware commands */ 62 IONIC_CMD_FW_DOWNLOAD = 254, 63 IONIC_CMD_FW_CONTROL = 255, 64 }; 65 66 /** 67 * Command Return codes 68 */ 69 enum ionic_status_code { 70 IONIC_RC_SUCCESS = 0, /* Success */ 71 IONIC_RC_EVERSION = 1, /* Incorrect version for request */ 72 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */ 73 IONIC_RC_EIO = 3, /* I/O error */ 74 IONIC_RC_EPERM = 4, /* Permission denied */ 75 IONIC_RC_EQID = 5, /* Bad qid */ 76 IONIC_RC_EQTYPE = 6, /* Bad qtype */ 77 IONIC_RC_ENOENT = 7, /* No such element */ 78 IONIC_RC_EINTR = 8, /* operation interrupted */ 79 IONIC_RC_EAGAIN = 9, /* Try again */ 80 IONIC_RC_ENOMEM = 10, /* Out of memory */ 81 IONIC_RC_EFAULT = 11, /* Bad address */ 82 IONIC_RC_EBUSY = 12, /* Device or resource busy */ 83 IONIC_RC_EEXIST = 13, /* object already exists */ 84 IONIC_RC_EINVAL = 14, /* Invalid argument */ 85 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */ 86 IONIC_RC_ERANGE = 16, /* Parameter out of range */ 87 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */ 88 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ 89 IONIC_RC_ENOSUPP = 19, /* Operation not supported */ 90 IONIC_RC_ERROR = 29, /* Generic error */ 91 92 IONIC_RC_ERDMA = 30, /* Generic RDMA error */ 93 }; 94 95 enum ionic_notifyq_opcode { 96 IONIC_EVENT_LINK_CHANGE = 1, 97 IONIC_EVENT_RESET = 2, 98 IONIC_EVENT_HEARTBEAT = 3, 99 IONIC_EVENT_LOG = 4, 100 }; 101 102 /** 103 * struct cmd - General admin command format 104 * @opcode: Opcode for the command 105 * @lif_index: LIF index 106 * @cmd_data: Opcode-specific command bytes 107 */ 108 struct ionic_admin_cmd { 109 u8 opcode; 110 u8 rsvd; 111 __le16 lif_index; 112 u8 cmd_data[60]; 113 }; 114 115 /** 116 * struct ionic_admin_comp - General admin command completion format 117 * @status: The status of the command (enum status_code) 118 * @comp_index: The index in the descriptor ring for which this 119 * is the completion. 120 * @cmd_data: Command-specific bytes. 121 * @color: Color bit. (Always 0 for commands issued to the 122 * Device Cmd Registers.) 123 */ 124 struct ionic_admin_comp { 125 u8 status; 126 u8 rsvd; 127 __le16 comp_index; 128 u8 cmd_data[11]; 129 u8 color; 130 #define IONIC_COMP_COLOR_MASK 0x80 131 }; 132 133 static inline u8 color_match(u8 color, u8 done_color) 134 { 135 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color; 136 } 137 138 /** 139 * struct ionic_nop_cmd - NOP command 140 * @opcode: opcode 141 */ 142 struct ionic_nop_cmd { 143 u8 opcode; 144 u8 rsvd[63]; 145 }; 146 147 /** 148 * struct ionic_nop_comp - NOP command completion 149 * @status: The status of the command (enum status_code) 150 */ 151 struct ionic_nop_comp { 152 u8 status; 153 u8 rsvd[15]; 154 }; 155 156 /** 157 * struct ionic_dev_init_cmd - Device init command 158 * @opcode: opcode 159 * @type: device type 160 */ 161 struct ionic_dev_init_cmd { 162 u8 opcode; 163 u8 type; 164 u8 rsvd[62]; 165 }; 166 167 /** 168 * struct init_comp - Device init command completion 169 * @status: The status of the command (enum status_code) 170 */ 171 struct ionic_dev_init_comp { 172 u8 status; 173 u8 rsvd[15]; 174 }; 175 176 /** 177 * struct ionic_dev_reset_cmd - Device reset command 178 * @opcode: opcode 179 */ 180 struct ionic_dev_reset_cmd { 181 u8 opcode; 182 u8 rsvd[63]; 183 }; 184 185 /** 186 * struct reset_comp - Reset command completion 187 * @status: The status of the command (enum status_code) 188 */ 189 struct ionic_dev_reset_comp { 190 u8 status; 191 u8 rsvd[15]; 192 }; 193 194 #define IONIC_IDENTITY_VERSION_1 1 195 196 /** 197 * struct ionic_dev_identify_cmd - Driver/device identify command 198 * @opcode: opcode 199 * @ver: Highest version of identify supported by driver 200 */ 201 struct ionic_dev_identify_cmd { 202 u8 opcode; 203 u8 ver; 204 u8 rsvd[62]; 205 }; 206 207 /** 208 * struct dev_identify_comp - Driver/device identify command completion 209 * @status: The status of the command (enum status_code) 210 * @ver: Version of identify returned by device 211 */ 212 struct ionic_dev_identify_comp { 213 u8 status; 214 u8 ver; 215 u8 rsvd[14]; 216 }; 217 218 enum ionic_os_type { 219 IONIC_OS_TYPE_LINUX = 1, 220 IONIC_OS_TYPE_WIN = 2, 221 IONIC_OS_TYPE_DPDK = 3, 222 IONIC_OS_TYPE_FREEBSD = 4, 223 IONIC_OS_TYPE_IPXE = 5, 224 IONIC_OS_TYPE_ESXI = 6, 225 }; 226 227 /** 228 * union drv_identity - driver identity information 229 * @os_type: OS type (see enum os_type) 230 * @os_dist: OS distribution, numeric format 231 * @os_dist_str: OS distribution, string format 232 * @kernel_ver: Kernel version, numeric format 233 * @kernel_ver_str: Kernel version, string format 234 * @driver_ver_str: Driver version, string format 235 */ 236 union ionic_drv_identity { 237 struct { 238 __le32 os_type; 239 __le32 os_dist; 240 char os_dist_str[128]; 241 __le32 kernel_ver; 242 char kernel_ver_str[32]; 243 char driver_ver_str[32]; 244 }; 245 __le32 words[512]; 246 }; 247 248 /** 249 * union dev_identity - device identity information 250 * @version: Version of device identify 251 * @type: Identify type (0 for now) 252 * @nports: Number of ports provisioned 253 * @nlifs: Number of LIFs provisioned 254 * @nintrs: Number of interrupts provisioned 255 * @ndbpgs_per_lif: Number of doorbell pages per LIF 256 * @intr_coal_mult: Interrupt coalescing multiplication factor. 257 * Scale user-supplied interrupt coalescing 258 * value in usecs to device units using: 259 * device units = usecs * mult / div 260 * @intr_coal_div: Interrupt coalescing division factor. 261 * Scale user-supplied interrupt coalescing 262 * value in usecs to device units using: 263 * device units = usecs * mult / div 264 * 265 */ 266 union ionic_dev_identity { 267 struct { 268 u8 version; 269 u8 type; 270 u8 rsvd[2]; 271 u8 nports; 272 u8 rsvd2[3]; 273 __le32 nlifs; 274 __le32 nintrs; 275 __le32 ndbpgs_per_lif; 276 __le32 intr_coal_mult; 277 __le32 intr_coal_div; 278 }; 279 __le32 words[512]; 280 }; 281 282 enum ionic_lif_type { 283 IONIC_LIF_TYPE_CLASSIC = 0, 284 IONIC_LIF_TYPE_MACVLAN = 1, 285 IONIC_LIF_TYPE_NETQUEUE = 2, 286 }; 287 288 /** 289 * struct ionic_lif_identify_cmd - lif identify command 290 * @opcode: opcode 291 * @type: lif type (enum lif_type) 292 * @ver: version of identify returned by device 293 */ 294 struct ionic_lif_identify_cmd { 295 u8 opcode; 296 u8 type; 297 u8 ver; 298 u8 rsvd[61]; 299 }; 300 301 /** 302 * struct ionic_lif_identify_comp - lif identify command completion 303 * @status: status of the command (enum status_code) 304 * @ver: version of identify returned by device 305 */ 306 struct ionic_lif_identify_comp { 307 u8 status; 308 u8 ver; 309 u8 rsvd2[14]; 310 }; 311 312 enum ionic_lif_capability { 313 IONIC_LIF_CAP_ETH = BIT(0), 314 IONIC_LIF_CAP_RDMA = BIT(1), 315 }; 316 317 /** 318 * Logical Queue Types 319 */ 320 enum ionic_logical_qtype { 321 IONIC_QTYPE_ADMINQ = 0, 322 IONIC_QTYPE_NOTIFYQ = 1, 323 IONIC_QTYPE_RXQ = 2, 324 IONIC_QTYPE_TXQ = 3, 325 IONIC_QTYPE_EQ = 4, 326 IONIC_QTYPE_MAX = 16, 327 }; 328 329 /** 330 * struct ionic_lif_logical_qtype - Descriptor of logical to hardware queue type. 331 * @qtype: Hardware Queue Type. 332 * @qid_count: Number of Queue IDs of the logical type. 333 * @qid_base: Minimum Queue ID of the logical type. 334 */ 335 struct ionic_lif_logical_qtype { 336 u8 qtype; 337 u8 rsvd[3]; 338 __le32 qid_count; 339 __le32 qid_base; 340 }; 341 342 enum ionic_lif_state { 343 IONIC_LIF_DISABLE = 0, 344 IONIC_LIF_ENABLE = 1, 345 IONIC_LIF_HANG_RESET = 2, 346 }; 347 348 /** 349 * LIF configuration 350 * @state: lif state (enum lif_state) 351 * @name: lif name 352 * @mtu: mtu 353 * @mac: station mac address 354 * @features: features (enum ionic_eth_hw_features) 355 * @queue_count: queue counts per queue-type 356 */ 357 union ionic_lif_config { 358 struct { 359 u8 state; 360 u8 rsvd[3]; 361 char name[IONIC_IFNAMSIZ]; 362 __le32 mtu; 363 u8 mac[6]; 364 u8 rsvd2[2]; 365 __le64 features; 366 __le32 queue_count[IONIC_QTYPE_MAX]; 367 } __packed; 368 __le32 words[64]; 369 }; 370 371 /** 372 * struct ionic_lif_identity - lif identity information (type-specific) 373 * 374 * @capabilities LIF capabilities 375 * 376 * Ethernet: 377 * @version: Ethernet identify structure version. 378 * @features: Ethernet features supported on this lif type. 379 * @max_ucast_filters: Number of perfect unicast addresses supported. 380 * @max_mcast_filters: Number of perfect multicast addresses supported. 381 * @min_frame_size: Minimum size of frames to be sent 382 * @max_frame_size: Maximim size of frames to be sent 383 * @config: LIF config struct with features, mtu, mac, q counts 384 * 385 * RDMA: 386 * @version: RDMA version of opcodes and queue descriptors. 387 * @qp_opcodes: Number of rdma queue pair opcodes supported. 388 * @admin_opcodes: Number of rdma admin opcodes supported. 389 * @npts_per_lif: Page table size per lif 390 * @nmrs_per_lif: Number of memory regions per lif 391 * @nahs_per_lif: Number of address handles per lif 392 * @max_stride: Max work request stride. 393 * @cl_stride: Cache line stride. 394 * @pte_stride: Page table entry stride. 395 * @rrq_stride: Remote RQ work request stride. 396 * @rsq_stride: Remote SQ work request stride. 397 * @dcqcn_profiles: Number of DCQCN profiles 398 * @aq_qtype: RDMA Admin Qtype. 399 * @sq_qtype: RDMA Send Qtype. 400 * @rq_qtype: RDMA Receive Qtype. 401 * @cq_qtype: RDMA Completion Qtype. 402 * @eq_qtype: RDMA Event Qtype. 403 */ 404 union ionic_lif_identity { 405 struct { 406 __le64 capabilities; 407 408 struct { 409 u8 version; 410 u8 rsvd[3]; 411 __le32 max_ucast_filters; 412 __le32 max_mcast_filters; 413 __le16 rss_ind_tbl_sz; 414 __le32 min_frame_size; 415 __le32 max_frame_size; 416 u8 rsvd2[106]; 417 union ionic_lif_config config; 418 } __packed eth; 419 420 struct { 421 u8 version; 422 u8 qp_opcodes; 423 u8 admin_opcodes; 424 u8 rsvd; 425 __le32 npts_per_lif; 426 __le32 nmrs_per_lif; 427 __le32 nahs_per_lif; 428 u8 max_stride; 429 u8 cl_stride; 430 u8 pte_stride; 431 u8 rrq_stride; 432 u8 rsq_stride; 433 u8 dcqcn_profiles; 434 u8 rsvd_dimensions[10]; 435 struct ionic_lif_logical_qtype aq_qtype; 436 struct ionic_lif_logical_qtype sq_qtype; 437 struct ionic_lif_logical_qtype rq_qtype; 438 struct ionic_lif_logical_qtype cq_qtype; 439 struct ionic_lif_logical_qtype eq_qtype; 440 } __packed rdma; 441 } __packed; 442 __le32 words[512]; 443 }; 444 445 /** 446 * struct ionic_lif_init_cmd - LIF init command 447 * @opcode: opcode 448 * @type: LIF type (enum lif_type) 449 * @index: LIF index 450 * @info_pa: destination address for lif info (struct ionic_lif_info) 451 */ 452 struct ionic_lif_init_cmd { 453 u8 opcode; 454 u8 type; 455 __le16 index; 456 __le32 rsvd; 457 __le64 info_pa; 458 u8 rsvd2[48]; 459 }; 460 461 /** 462 * struct ionic_lif_init_comp - LIF init command completion 463 * @status: The status of the command (enum status_code) 464 */ 465 struct ionic_lif_init_comp { 466 u8 status; 467 u8 rsvd; 468 __le16 hw_index; 469 u8 rsvd2[12]; 470 }; 471 472 /** 473 * struct ionic_q_init_cmd - Queue init command 474 * @opcode: opcode 475 * @type: Logical queue type 476 * @ver: Queue version (defines opcode/descriptor scope) 477 * @lif_index: LIF index 478 * @index: (lif, qtype) relative admin queue index 479 * @intr_index: Interrupt control register index 480 * @pid: Process ID 481 * @flags: 482 * IRQ: Interrupt requested on completion 483 * ENA: Enable the queue. If ENA=0 the queue is initialized 484 * but remains disabled, to be later enabled with the 485 * Queue Enable command. If ENA=1, then queue is 486 * initialized and then enabled. 487 * SG: Enable Scatter-Gather on the queue. 488 * in number of descs. The actual ring size is 489 * (1 << ring_size). For example, to 490 * select a ring size of 64 descriptors write 491 * ring_size = 6. The minimum ring_size value is 2 492 * for a ring size of 4 descriptors. The maximum 493 * ring_size value is 16 for a ring size of 64k 494 * descriptors. Values of ring_size <2 and >16 are 495 * reserved. 496 * EQ: Enable the Event Queue 497 * @cos: Class of service for this queue. 498 * @ring_size: Queue ring size, encoded as a log2(size) 499 * @ring_base: Queue ring base address 500 * @cq_ring_base: Completion queue ring base address 501 * @sg_ring_base: Scatter/Gather ring base address 502 * @eq_index: Event queue index 503 */ 504 struct ionic_q_init_cmd { 505 u8 opcode; 506 u8 rsvd; 507 __le16 lif_index; 508 u8 type; 509 u8 ver; 510 u8 rsvd1[2]; 511 __le32 index; 512 __le16 pid; 513 __le16 intr_index; 514 __le16 flags; 515 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ 516 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ 517 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ 518 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ 519 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ 520 u8 cos; 521 u8 ring_size; 522 __le64 ring_base; 523 __le64 cq_ring_base; 524 __le64 sg_ring_base; 525 __le32 eq_index; 526 u8 rsvd2[16]; 527 } __packed; 528 529 /** 530 * struct ionic_q_init_comp - Queue init command completion 531 * @status: The status of the command (enum status_code) 532 * @ver: Queue version (defines opcode/descriptor scope) 533 * @comp_index: The index in the descriptor ring for which this 534 * is the completion. 535 * @hw_index: Hardware Queue ID 536 * @hw_type: Hardware Queue type 537 * @color: Color 538 */ 539 struct ionic_q_init_comp { 540 u8 status; 541 u8 ver; 542 __le16 comp_index; 543 __le32 hw_index; 544 u8 hw_type; 545 u8 rsvd2[6]; 546 u8 color; 547 }; 548 549 /* the device's internal addressing uses up to 52 bits */ 550 #define IONIC_ADDR_LEN 52 551 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 552 553 enum ionic_txq_desc_opcode { 554 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0, 555 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1, 556 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2, 557 IONIC_TXQ_DESC_OPCODE_TSO = 3, 558 }; 559 560 /** 561 * struct ionic_txq_desc - Ethernet Tx queue descriptor format 562 * @opcode: Tx operation, see TXQ_DESC_OPCODE_*: 563 * 564 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: 565 * 566 * Non-offload send. No segmentation, 567 * fragmentation or checksum calc/insertion is 568 * performed by device; packet is prepared 569 * to send by software stack and requires 570 * no further manipulation from device. 571 * 572 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: 573 * 574 * Offload 16-bit L4 checksum 575 * calculation/insertion. The device will 576 * calculate the L4 checksum value and 577 * insert the result in the packet's L4 578 * header checksum field. The L4 checksum 579 * is calculated starting at @csum_start bytes 580 * into the packet to the end of the packet. 581 * The checksum insertion position is given 582 * in @csum_offset. This feature is only 583 * applicable to protocols such as TCP, UDP 584 * and ICMP where a standard (i.e. the 585 * 'IP-style' checksum) one's complement 586 * 16-bit checksum is used, using an IP 587 * pseudo-header to seed the calculation. 588 * Software will preload the L4 checksum 589 * field with the IP pseudo-header checksum. 590 * 591 * For tunnel encapsulation, @csum_start and 592 * @csum_offset refer to the inner L4 593 * header. Supported tunnels encapsulations 594 * are: IPIP, GRE, and UDP. If the @encap 595 * is clear, no further processing by the 596 * device is required; software will 597 * calculate the outer header checksums. If 598 * the @encap is set, the device will 599 * offload the outer header checksums using 600 * LCO (local checksum offload) (see 601 * Documentation/networking/checksum-offloads.rst 602 * for more info). 603 * 604 * IONIC_TXQ_DESC_OPCODE_CSUM_HW: 605 * 606 * Offload 16-bit checksum computation to hardware. 607 * If @csum_l3 is set then the packet's L3 checksum is 608 * updated. Similarly, if @csum_l4 is set the the L4 609 * checksum is updated. If @encap is set then encap header 610 * checksums are also updated. 611 * 612 * IONIC_TXQ_DESC_OPCODE_TSO: 613 * 614 * Device preforms TCP segmentation offload 615 * (TSO). @hdr_len is the number of bytes 616 * to the end of TCP header (the offset to 617 * the TCP payload). @mss is the desired 618 * MSS, the TCP payload length for each 619 * segment. The device will calculate/ 620 * insert IP (IPv4 only) and TCP checksums 621 * for each segment. In the first data 622 * buffer containing the header template, 623 * the driver will set IPv4 checksum to 0 624 * and preload TCP checksum with the IP 625 * pseudo header calculated with IP length = 0. 626 * 627 * Supported tunnel encapsulations are IPIP, 628 * layer-3 GRE, and UDP. @hdr_len includes 629 * both outer and inner headers. The driver 630 * will set IPv4 checksum to zero and 631 * preload TCP checksum with IP pseudo 632 * header on the inner header. 633 * 634 * TCP ECN offload is supported. The device 635 * will set CWR flag in the first segment if 636 * CWR is set in the template header, and 637 * clear CWR in remaining segments. 638 * @flags: 639 * vlan: 640 * Insert an L2 VLAN header using @vlan_tci. 641 * encap: 642 * Calculate encap header checksum. 643 * csum_l3: 644 * Compute L3 header checksum. 645 * csum_l4: 646 * Compute L4 header checksum. 647 * tso_sot: 648 * TSO start 649 * tso_eot: 650 * TSO end 651 * @num_sg_elems: Number of scatter-gather elements in SG 652 * descriptor 653 * @addr: First data buffer's DMA address. 654 * (Subsequent data buffers are on txq_sg_desc). 655 * @len: First data buffer's length, in bytes 656 * @vlan_tci: VLAN tag to insert in the packet (if requested 657 * by @V-bit). Includes .1p and .1q tags 658 * @hdr_len: Length of packet headers, including 659 * encapsulating outer header, if applicable. 660 * Valid for opcodes TXQ_DESC_OPCODE_CALC_CSUM and 661 * TXQ_DESC_OPCODE_TSO. Should be set to zero for 662 * all other modes. For 663 * TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length 664 * of headers up to inner-most L4 header. For 665 * TXQ_DESC_OPCODE_TSO, @hdr_len is up to 666 * inner-most L4 payload, so inclusive of 667 * inner-most L4 header. 668 * @mss: Desired MSS value for TSO. Only applicable for 669 * TXQ_DESC_OPCODE_TSO. 670 * @csum_start: Offset into inner-most L3 header of checksum 671 * @csum_offset: Offset into inner-most L4 header of checksum 672 */ 673 674 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf 675 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 676 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf 677 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0 678 #define IONIC_TXQ_DESC_NSGE_MASK 0xf 679 #define IONIC_TXQ_DESC_NSGE_SHIFT 8 680 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 681 #define IONIC_TXQ_DESC_ADDR_SHIFT 12 682 683 /* common flags */ 684 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1 685 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2 686 687 /* flags for csum_hw opcode */ 688 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4 689 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8 690 691 /* flags for tso opcode */ 692 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 693 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 694 695 struct ionic_txq_desc { 696 __le64 cmd; 697 __le16 len; 698 union { 699 __le16 vlan_tci; 700 __le16 hword0; 701 }; 702 union { 703 __le16 csum_start; 704 __le16 hdr_len; 705 __le16 hword1; 706 }; 707 union { 708 __le16 csum_offset; 709 __le16 mss; 710 __le16 hword2; 711 }; 712 }; 713 714 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags, 715 u8 nsge, u64 addr) 716 { 717 u64 cmd; 718 719 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT; 720 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT; 721 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT; 722 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT; 723 724 return cmd; 725 }; 726 727 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, 728 u8 *nsge, u64 *addr) 729 { 730 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK; 731 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK; 732 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK; 733 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; 734 }; 735 736 #define IONIC_TX_MAX_SG_ELEMS 8 737 #define IONIC_RX_MAX_SG_ELEMS 8 738 739 /** 740 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list 741 * @addr: DMA address of SG element data buffer 742 * @len: Length of SG element data buffer, in bytes 743 */ 744 struct ionic_txq_sg_desc { 745 struct ionic_txq_sg_elem { 746 __le64 addr; 747 __le16 len; 748 __le16 rsvd[3]; 749 } elems[IONIC_TX_MAX_SG_ELEMS]; 750 }; 751 752 /** 753 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 754 * @status: The status of the command (enum status_code) 755 * @comp_index: The index in the descriptor ring for which this 756 * is the completion. 757 * @color: Color bit. 758 */ 759 struct ionic_txq_comp { 760 u8 status; 761 u8 rsvd; 762 __le16 comp_index; 763 u8 rsvd2[11]; 764 u8 color; 765 }; 766 767 enum ionic_rxq_desc_opcode { 768 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0, 769 IONIC_RXQ_DESC_OPCODE_SG = 1, 770 }; 771 772 /** 773 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format 774 * @opcode: Rx operation, see RXQ_DESC_OPCODE_*: 775 * 776 * RXQ_DESC_OPCODE_SIMPLE: 777 * 778 * Receive full packet into data buffer 779 * starting at @addr. Results of 780 * receive, including actual bytes received, 781 * are recorded in Rx completion descriptor. 782 * 783 * @len: Data buffer's length, in bytes. 784 * @addr: Data buffer's DMA address 785 */ 786 struct ionic_rxq_desc { 787 u8 opcode; 788 u8 rsvd[5]; 789 __le16 len; 790 __le64 addr; 791 }; 792 793 /** 794 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list 795 * @addr: DMA address of SG element data buffer 796 * @len: Length of SG element data buffer, in bytes 797 */ 798 struct ionic_rxq_sg_desc { 799 struct ionic_rxq_sg_elem { 800 __le64 addr; 801 __le16 len; 802 __le16 rsvd[3]; 803 } elems[IONIC_RX_MAX_SG_ELEMS]; 804 }; 805 806 /** 807 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor 808 * @status: The status of the command (enum status_code) 809 * @num_sg_elems: Number of SG elements used by this descriptor 810 * @comp_index: The index in the descriptor ring for which this 811 * is the completion. 812 * @rss_hash: 32-bit RSS hash 813 * @csum: 16-bit sum of the packet's L2 payload. 814 * If the packet's L2 payload is odd length, an extra 815 * zero-value byte is included in the @csum calculation but 816 * not included in @len. 817 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is 818 * set. Includes .1p and .1q tags. 819 * @len: Received packet length, in bytes. Excludes FCS. 820 * @csum_calc L2 payload checksum is computed or not 821 * @csum_tcp_ok: The TCP checksum calculated by the device 822 * matched the checksum in the receive packet's 823 * TCP header 824 * @csum_tcp_bad: The TCP checksum calculated by the device did 825 * not match the checksum in the receive packet's 826 * TCP header. 827 * @csum_udp_ok: The UDP checksum calculated by the device 828 * matched the checksum in the receive packet's 829 * UDP header 830 * @csum_udp_bad: The UDP checksum calculated by the device did 831 * not match the checksum in the receive packet's 832 * UDP header. 833 * @csum_ip_ok: The IPv4 checksum calculated by the device 834 * matched the checksum in the receive packet's 835 * first IPv4 header. If the receive packet 836 * contains both a tunnel IPv4 header and a 837 * transport IPv4 header, the device validates the 838 * checksum for the both IPv4 headers. 839 * @csum_ip_bad: The IPv4 checksum calculated by the device did 840 * not match the checksum in the receive packet's 841 * first IPv4 header. If the receive packet 842 * contains both a tunnel IPv4 header and a 843 * transport IPv4 header, the device validates the 844 * checksum for both IP headers. 845 * @VLAN: VLAN header was stripped and placed in @vlan_tci. 846 * @pkt_type: Packet type 847 * @color: Color bit. 848 */ 849 struct ionic_rxq_comp { 850 u8 status; 851 u8 num_sg_elems; 852 __le16 comp_index; 853 __le32 rss_hash; 854 __le16 csum; 855 __le16 vlan_tci; 856 __le16 len; 857 u8 csum_flags; 858 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 859 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 860 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 861 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 862 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 863 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 864 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 865 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80 866 u8 pkt_type_color; 867 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f 868 }; 869 870 enum ionic_pkt_type { 871 IONIC_PKT_TYPE_NON_IP = 0x000, 872 IONIC_PKT_TYPE_IPV4 = 0x001, 873 IONIC_PKT_TYPE_IPV4_TCP = 0x003, 874 IONIC_PKT_TYPE_IPV4_UDP = 0x005, 875 IONIC_PKT_TYPE_IPV6 = 0x008, 876 IONIC_PKT_TYPE_IPV6_TCP = 0x018, 877 IONIC_PKT_TYPE_IPV6_UDP = 0x028, 878 }; 879 880 enum ionic_eth_hw_features { 881 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), 882 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), 883 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), 884 IONIC_ETH_HW_RX_HASH = BIT(3), 885 IONIC_ETH_HW_RX_CSUM = BIT(4), 886 IONIC_ETH_HW_TX_SG = BIT(5), 887 IONIC_ETH_HW_RX_SG = BIT(6), 888 IONIC_ETH_HW_TX_CSUM = BIT(7), 889 IONIC_ETH_HW_TSO = BIT(8), 890 IONIC_ETH_HW_TSO_IPV6 = BIT(9), 891 IONIC_ETH_HW_TSO_ECN = BIT(10), 892 IONIC_ETH_HW_TSO_GRE = BIT(11), 893 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), 894 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), 895 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), 896 IONIC_ETH_HW_TSO_UDP = BIT(15), 897 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), 898 }; 899 900 /** 901 * struct ionic_q_control_cmd - Queue control command 902 * @opcode: opcode 903 * @type: Queue type 904 * @lif_index: LIF index 905 * @index: Queue index 906 * @oper: Operation (enum q_control_oper) 907 */ 908 struct ionic_q_control_cmd { 909 u8 opcode; 910 u8 type; 911 __le16 lif_index; 912 __le32 index; 913 u8 oper; 914 u8 rsvd[55]; 915 }; 916 917 typedef struct ionic_admin_comp ionic_q_control_comp; 918 919 enum q_control_oper { 920 IONIC_Q_DISABLE = 0, 921 IONIC_Q_ENABLE = 1, 922 IONIC_Q_HANG_RESET = 2, 923 }; 924 925 /** 926 * Physical connection type 927 */ 928 enum ionic_phy_type { 929 IONIC_PHY_TYPE_NONE = 0, 930 IONIC_PHY_TYPE_COPPER = 1, 931 IONIC_PHY_TYPE_FIBER = 2, 932 }; 933 934 /** 935 * Transceiver status 936 */ 937 enum ionic_xcvr_state { 938 IONIC_XCVR_STATE_REMOVED = 0, 939 IONIC_XCVR_STATE_INSERTED = 1, 940 IONIC_XCVR_STATE_PENDING = 2, 941 IONIC_XCVR_STATE_SPROM_READ = 3, 942 IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 943 }; 944 945 /** 946 * Supported link modes 947 */ 948 enum ionic_xcvr_pid { 949 IONIC_XCVR_PID_UNKNOWN = 0, 950 951 /* CU */ 952 IONIC_XCVR_PID_QSFP_100G_CR4 = 1, 953 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2, 954 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3, 955 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4, 956 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5, 957 958 /* Fiber */ 959 IONIC_XCVR_PID_QSFP_100G_AOC = 50, 960 IONIC_XCVR_PID_QSFP_100G_ACC = 51, 961 IONIC_XCVR_PID_QSFP_100G_SR4 = 52, 962 IONIC_XCVR_PID_QSFP_100G_LR4 = 53, 963 IONIC_XCVR_PID_QSFP_100G_ER4 = 54, 964 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55, 965 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56, 966 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57, 967 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58, 968 IONIC_XCVR_PID_SFP_25GBASE_SR = 59, 969 IONIC_XCVR_PID_SFP_25GBASE_LR = 60, 970 IONIC_XCVR_PID_SFP_25GBASE_ER = 61, 971 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62, 972 IONIC_XCVR_PID_SFP_10GBASE_SR = 63, 973 IONIC_XCVR_PID_SFP_10GBASE_LR = 64, 974 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65, 975 IONIC_XCVR_PID_SFP_10GBASE_ER = 66, 976 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67, 977 IONIC_XCVR_PID_SFP_10GBASE_CU = 68, 978 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, 979 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, 980 }; 981 982 /** 983 * Port types 984 */ 985 enum ionic_port_type { 986 IONIC_PORT_TYPE_NONE = 0, /* port type not configured */ 987 IONIC_PORT_TYPE_ETH = 1, /* port carries ethernet traffic (inband) */ 988 IONIC_PORT_TYPE_MGMT = 2, /* port carries mgmt traffic (out-of-band) */ 989 }; 990 991 /** 992 * Port config state 993 */ 994 enum ionic_port_admin_state { 995 IONIC_PORT_ADMIN_STATE_NONE = 0, /* port admin state not configured */ 996 IONIC_PORT_ADMIN_STATE_DOWN = 1, /* port is admin disabled */ 997 IONIC_PORT_ADMIN_STATE_UP = 2, /* port is admin enabled */ 998 }; 999 1000 /** 1001 * Port operational status 1002 */ 1003 enum ionic_port_oper_status { 1004 IONIC_PORT_OPER_STATUS_NONE = 0, /* port is disabled */ 1005 IONIC_PORT_OPER_STATUS_UP = 1, /* port is linked up */ 1006 IONIC_PORT_OPER_STATUS_DOWN = 2, /* port link status is down */ 1007 }; 1008 1009 /** 1010 * Ethernet Forward error correction (fec) modes 1011 */ 1012 enum ionic_port_fec_type { 1013 IONIC_PORT_FEC_TYPE_NONE = 0, /* Disabled */ 1014 IONIC_PORT_FEC_TYPE_FC = 1, /* FireCode */ 1015 IONIC_PORT_FEC_TYPE_RS = 2, /* ReedSolomon */ 1016 }; 1017 1018 /** 1019 * Ethernet pause (flow control) modes 1020 */ 1021 enum ionic_port_pause_type { 1022 IONIC_PORT_PAUSE_TYPE_NONE = 0, /* Disable Pause */ 1023 IONIC_PORT_PAUSE_TYPE_LINK = 1, /* Link level pause */ 1024 IONIC_PORT_PAUSE_TYPE_PFC = 2, /* Priority-Flow control */ 1025 }; 1026 1027 /** 1028 * Loopback modes 1029 */ 1030 enum ionic_port_loopback_mode { 1031 IONIC_PORT_LOOPBACK_MODE_NONE = 0, /* Disable loopback */ 1032 IONIC_PORT_LOOPBACK_MODE_MAC = 1, /* MAC loopback */ 1033 IONIC_PORT_LOOPBACK_MODE_PHY = 2, /* PHY/Serdes loopback */ 1034 }; 1035 1036 /** 1037 * Transceiver Status information 1038 * @state: Transceiver status (enum ionic_xcvr_state) 1039 * @phy: Physical connection type (enum ionic_phy_type) 1040 * @pid: Transceiver link mode (enum pid) 1041 * @sprom: Transceiver sprom contents 1042 */ 1043 struct ionic_xcvr_status { 1044 u8 state; 1045 u8 phy; 1046 __le16 pid; 1047 u8 sprom[256]; 1048 }; 1049 1050 /** 1051 * Port configuration 1052 * @speed: port speed (in Mbps) 1053 * @mtu: mtu 1054 * @state: port admin state (enum port_admin_state) 1055 * @an_enable: autoneg enable 1056 * @fec_type: fec type (enum ionic_port_fec_type) 1057 * @pause_type: pause type (enum ionic_port_pause_type) 1058 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1059 */ 1060 union ionic_port_config { 1061 struct { 1062 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */ 1063 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */ 1064 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */ 1065 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */ 1066 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */ 1067 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */ 1068 __le32 speed; 1069 __le32 mtu; 1070 u8 state; 1071 u8 an_enable; 1072 u8 fec_type; 1073 #define IONIC_PAUSE_TYPE_MASK 0x0f 1074 #define IONIC_PAUSE_FLAGS_MASK 0xf0 1075 #define IONIC_PAUSE_F_TX 0x10 1076 #define IONIC_PAUSE_F_RX 0x20 1077 u8 pause_type; 1078 u8 loopback_mode; 1079 }; 1080 __le32 words[64]; 1081 }; 1082 1083 /** 1084 * Port Status information 1085 * @status: link status (enum ionic_port_oper_status) 1086 * @id: port id 1087 * @speed: link speed (in Mbps) 1088 * @xcvr: tranceiver status 1089 */ 1090 struct ionic_port_status { 1091 __le32 id; 1092 __le32 speed; 1093 u8 status; 1094 u8 rsvd[51]; 1095 struct ionic_xcvr_status xcvr; 1096 } __packed; 1097 1098 /** 1099 * struct ionic_port_identify_cmd - Port identify command 1100 * @opcode: opcode 1101 * @index: port index 1102 * @ver: Highest version of identify supported by driver 1103 */ 1104 struct ionic_port_identify_cmd { 1105 u8 opcode; 1106 u8 index; 1107 u8 ver; 1108 u8 rsvd[61]; 1109 }; 1110 1111 /** 1112 * struct ionic_port_identify_comp - Port identify command completion 1113 * @status: The status of the command (enum status_code) 1114 * @ver: Version of identify returned by device 1115 */ 1116 struct ionic_port_identify_comp { 1117 u8 status; 1118 u8 ver; 1119 u8 rsvd[14]; 1120 }; 1121 1122 /** 1123 * struct ionic_port_init_cmd - Port initialization command 1124 * @opcode: opcode 1125 * @index: port index 1126 * @info_pa: destination address for port info (struct ionic_port_info) 1127 */ 1128 struct ionic_port_init_cmd { 1129 u8 opcode; 1130 u8 index; 1131 u8 rsvd[6]; 1132 __le64 info_pa; 1133 u8 rsvd2[48]; 1134 }; 1135 1136 /** 1137 * struct ionic_port_init_comp - Port initialization command completion 1138 * @status: The status of the command (enum status_code) 1139 */ 1140 struct ionic_port_init_comp { 1141 u8 status; 1142 u8 rsvd[15]; 1143 }; 1144 1145 /** 1146 * struct ionic_port_reset_cmd - Port reset command 1147 * @opcode: opcode 1148 * @index: port index 1149 */ 1150 struct ionic_port_reset_cmd { 1151 u8 opcode; 1152 u8 index; 1153 u8 rsvd[62]; 1154 }; 1155 1156 /** 1157 * struct ionic_port_reset_comp - Port reset command completion 1158 * @status: The status of the command (enum status_code) 1159 */ 1160 struct ionic_port_reset_comp { 1161 u8 status; 1162 u8 rsvd[15]; 1163 }; 1164 1165 /** 1166 * enum stats_ctl_cmd - List of commands for stats control 1167 */ 1168 enum ionic_stats_ctl_cmd { 1169 IONIC_STATS_CTL_RESET = 0, 1170 }; 1171 1172 1173 /** 1174 * enum ionic_port_attr - List of device attributes 1175 */ 1176 enum ionic_port_attr { 1177 IONIC_PORT_ATTR_STATE = 0, 1178 IONIC_PORT_ATTR_SPEED = 1, 1179 IONIC_PORT_ATTR_MTU = 2, 1180 IONIC_PORT_ATTR_AUTONEG = 3, 1181 IONIC_PORT_ATTR_FEC = 4, 1182 IONIC_PORT_ATTR_PAUSE = 5, 1183 IONIC_PORT_ATTR_LOOPBACK = 6, 1184 IONIC_PORT_ATTR_STATS_CTRL = 7, 1185 }; 1186 1187 /** 1188 * struct ionic_port_setattr_cmd - Set port attributes on the NIC 1189 * @opcode: Opcode 1190 * @index: port index 1191 * @attr: Attribute type (enum ionic_port_attr) 1192 */ 1193 struct ionic_port_setattr_cmd { 1194 u8 opcode; 1195 u8 index; 1196 u8 attr; 1197 u8 rsvd; 1198 union { 1199 u8 state; 1200 __le32 speed; 1201 __le32 mtu; 1202 u8 an_enable; 1203 u8 fec_type; 1204 u8 pause_type; 1205 u8 loopback_mode; 1206 u8 stats_ctl; 1207 u8 rsvd2[60]; 1208 }; 1209 }; 1210 1211 /** 1212 * struct ionic_port_setattr_comp - Port set attr command completion 1213 * @status: The status of the command (enum status_code) 1214 * @color: Color bit 1215 */ 1216 struct ionic_port_setattr_comp { 1217 u8 status; 1218 u8 rsvd[14]; 1219 u8 color; 1220 }; 1221 1222 /** 1223 * struct ionic_port_getattr_cmd - Get port attributes from the NIC 1224 * @opcode: Opcode 1225 * @index: port index 1226 * @attr: Attribute type (enum ionic_port_attr) 1227 */ 1228 struct ionic_port_getattr_cmd { 1229 u8 opcode; 1230 u8 index; 1231 u8 attr; 1232 u8 rsvd[61]; 1233 }; 1234 1235 /** 1236 * struct ionic_port_getattr_comp - Port get attr command completion 1237 * @status: The status of the command (enum status_code) 1238 * @color: Color bit 1239 */ 1240 struct ionic_port_getattr_comp { 1241 u8 status; 1242 u8 rsvd[3]; 1243 union { 1244 u8 state; 1245 __le32 speed; 1246 __le32 mtu; 1247 u8 an_enable; 1248 u8 fec_type; 1249 u8 pause_type; 1250 u8 loopback_mode; 1251 u8 rsvd2[11]; 1252 } __packed; 1253 u8 color; 1254 }; 1255 1256 /** 1257 * struct ionic_lif_status - Lif status register 1258 * @eid: most recent NotifyQ event id 1259 * @port_num: port the lif is connected to 1260 * @link_status: port status (enum ionic_port_oper_status) 1261 * @link_speed: speed of link in Mbps 1262 * @link_down_count: number of times link status changes 1263 */ 1264 struct ionic_lif_status { 1265 __le64 eid; 1266 u8 port_num; 1267 u8 rsvd; 1268 __le16 link_status; 1269 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */ 1270 __le16 link_down_count; 1271 u8 rsvd2[46]; 1272 }; 1273 1274 /** 1275 * struct ionic_lif_reset_cmd - LIF reset command 1276 * @opcode: opcode 1277 * @index: LIF index 1278 */ 1279 struct ionic_lif_reset_cmd { 1280 u8 opcode; 1281 u8 rsvd; 1282 __le16 index; 1283 __le32 rsvd2[15]; 1284 }; 1285 1286 typedef struct ionic_admin_comp ionic_lif_reset_comp; 1287 1288 enum ionic_dev_state { 1289 IONIC_DEV_DISABLE = 0, 1290 IONIC_DEV_ENABLE = 1, 1291 IONIC_DEV_HANG_RESET = 2, 1292 }; 1293 1294 /** 1295 * enum ionic_dev_attr - List of device attributes 1296 */ 1297 enum ionic_dev_attr { 1298 IONIC_DEV_ATTR_STATE = 0, 1299 IONIC_DEV_ATTR_NAME = 1, 1300 IONIC_DEV_ATTR_FEATURES = 2, 1301 }; 1302 1303 /** 1304 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1305 * @opcode: Opcode 1306 * @attr: Attribute type (enum ionic_dev_attr) 1307 * @state: Device state (enum ionic_dev_state) 1308 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1309 * @features: Device features 1310 */ 1311 struct ionic_dev_setattr_cmd { 1312 u8 opcode; 1313 u8 attr; 1314 __le16 rsvd; 1315 union { 1316 u8 state; 1317 char name[IONIC_IFNAMSIZ]; 1318 __le64 features; 1319 u8 rsvd2[60]; 1320 } __packed; 1321 }; 1322 1323 /** 1324 * struct ionic_dev_setattr_comp - Device set attr command completion 1325 * @status: The status of the command (enum status_code) 1326 * @features: Device features 1327 * @color: Color bit 1328 */ 1329 struct ionic_dev_setattr_comp { 1330 u8 status; 1331 u8 rsvd[3]; 1332 union { 1333 __le64 features; 1334 u8 rsvd2[11]; 1335 } __packed; 1336 u8 color; 1337 }; 1338 1339 /** 1340 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1341 * @opcode: opcode 1342 * @attr: Attribute type (enum ionic_dev_attr) 1343 */ 1344 struct ionic_dev_getattr_cmd { 1345 u8 opcode; 1346 u8 attr; 1347 u8 rsvd[62]; 1348 }; 1349 1350 /** 1351 * struct ionic_dev_setattr_comp - Device set attr command completion 1352 * @status: The status of the command (enum status_code) 1353 * @features: Device features 1354 * @color: Color bit 1355 */ 1356 struct ionic_dev_getattr_comp { 1357 u8 status; 1358 u8 rsvd[3]; 1359 union { 1360 __le64 features; 1361 u8 rsvd2[11]; 1362 } __packed; 1363 u8 color; 1364 }; 1365 1366 /** 1367 * RSS parameters 1368 */ 1369 #define IONIC_RSS_HASH_KEY_SIZE 40 1370 1371 enum ionic_rss_hash_types { 1372 IONIC_RSS_TYPE_IPV4 = BIT(0), 1373 IONIC_RSS_TYPE_IPV4_TCP = BIT(1), 1374 IONIC_RSS_TYPE_IPV4_UDP = BIT(2), 1375 IONIC_RSS_TYPE_IPV6 = BIT(3), 1376 IONIC_RSS_TYPE_IPV6_TCP = BIT(4), 1377 IONIC_RSS_TYPE_IPV6_UDP = BIT(5), 1378 }; 1379 1380 /** 1381 * enum ionic_lif_attr - List of LIF attributes 1382 */ 1383 enum ionic_lif_attr { 1384 IONIC_LIF_ATTR_STATE = 0, 1385 IONIC_LIF_ATTR_NAME = 1, 1386 IONIC_LIF_ATTR_MTU = 2, 1387 IONIC_LIF_ATTR_MAC = 3, 1388 IONIC_LIF_ATTR_FEATURES = 4, 1389 IONIC_LIF_ATTR_RSS = 5, 1390 IONIC_LIF_ATTR_STATS_CTRL = 6, 1391 }; 1392 1393 /** 1394 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC 1395 * @opcode: Opcode 1396 * @type: Attribute type (enum ionic_lif_attr) 1397 * @index: LIF index 1398 * @state: lif state (enum lif_state) 1399 * @name: The netdev name string, 0 terminated 1400 * @mtu: Mtu 1401 * @mac: Station mac 1402 * @features: Features (enum ionic_eth_hw_features) 1403 * @rss: RSS properties 1404 * @types: The hash types to enable (see rss_hash_types). 1405 * @key: The hash secret key. 1406 * @addr: Address for the indirection table shared memory. 1407 * @stats_ctl: stats control commands (enum stats_ctl_cmd) 1408 */ 1409 struct ionic_lif_setattr_cmd { 1410 u8 opcode; 1411 u8 attr; 1412 __le16 index; 1413 union { 1414 u8 state; 1415 char name[IONIC_IFNAMSIZ]; 1416 __le32 mtu; 1417 u8 mac[6]; 1418 __le64 features; 1419 struct { 1420 __le16 types; 1421 u8 key[IONIC_RSS_HASH_KEY_SIZE]; 1422 u8 rsvd[6]; 1423 __le64 addr; 1424 } rss; 1425 u8 stats_ctl; 1426 u8 rsvd[60]; 1427 } __packed; 1428 }; 1429 1430 /** 1431 * struct ionic_lif_setattr_comp - LIF set attr command completion 1432 * @status: The status of the command (enum status_code) 1433 * @comp_index: The index in the descriptor ring for which this 1434 * is the completion. 1435 * @features: features (enum ionic_eth_hw_features) 1436 * @color: Color bit 1437 */ 1438 struct ionic_lif_setattr_comp { 1439 u8 status; 1440 u8 rsvd; 1441 __le16 comp_index; 1442 union { 1443 __le64 features; 1444 u8 rsvd2[11]; 1445 } __packed; 1446 u8 color; 1447 }; 1448 1449 /** 1450 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC 1451 * @opcode: Opcode 1452 * @attr: Attribute type (enum ionic_lif_attr) 1453 * @index: LIF index 1454 */ 1455 struct ionic_lif_getattr_cmd { 1456 u8 opcode; 1457 u8 attr; 1458 __le16 index; 1459 u8 rsvd[60]; 1460 }; 1461 1462 /** 1463 * struct ionic_lif_getattr_comp - LIF get attr command completion 1464 * @status: The status of the command (enum status_code) 1465 * @comp_index: The index in the descriptor ring for which this 1466 * is the completion. 1467 * @state: lif state (enum lif_state) 1468 * @name: The netdev name string, 0 terminated 1469 * @mtu: Mtu 1470 * @mac: Station mac 1471 * @features: Features (enum ionic_eth_hw_features) 1472 * @color: Color bit 1473 */ 1474 struct ionic_lif_getattr_comp { 1475 u8 status; 1476 u8 rsvd; 1477 __le16 comp_index; 1478 union { 1479 u8 state; 1480 __le32 mtu; 1481 u8 mac[6]; 1482 __le64 features; 1483 u8 rsvd2[11]; 1484 } __packed; 1485 u8 color; 1486 }; 1487 1488 enum ionic_rx_mode { 1489 IONIC_RX_MODE_F_UNICAST = BIT(0), 1490 IONIC_RX_MODE_F_MULTICAST = BIT(1), 1491 IONIC_RX_MODE_F_BROADCAST = BIT(2), 1492 IONIC_RX_MODE_F_PROMISC = BIT(3), 1493 IONIC_RX_MODE_F_ALLMULTI = BIT(4), 1494 }; 1495 1496 /** 1497 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 1498 * @opcode: opcode 1499 * @lif_index: LIF index 1500 * @rx_mode: Rx mode flags: 1501 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets. 1502 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets. 1503 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets. 1504 * IONIC_RX_MODE_F_PROMISC: Accept any packets. 1505 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets. 1506 */ 1507 struct ionic_rx_mode_set_cmd { 1508 u8 opcode; 1509 u8 rsvd; 1510 __le16 lif_index; 1511 __le16 rx_mode; 1512 __le16 rsvd2[29]; 1513 }; 1514 1515 typedef struct ionic_admin_comp ionic_rx_mode_set_comp; 1516 1517 enum ionic_rx_filter_match_type { 1518 IONIC_RX_FILTER_MATCH_VLAN = 0, 1519 IONIC_RX_FILTER_MATCH_MAC, 1520 IONIC_RX_FILTER_MATCH_MAC_VLAN, 1521 }; 1522 1523 /** 1524 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command 1525 * @opcode: opcode 1526 * @qtype: Queue type 1527 * @lif_index: LIF index 1528 * @qid: Queue ID 1529 * @match: Rx filter match type. (See IONIC_RX_FILTER_MATCH_xxx) 1530 * @vlan: VLAN ID 1531 * @addr: MAC address (network-byte order) 1532 */ 1533 struct ionic_rx_filter_add_cmd { 1534 u8 opcode; 1535 u8 qtype; 1536 __le16 lif_index; 1537 __le32 qid; 1538 __le16 match; 1539 union { 1540 struct { 1541 __le16 vlan; 1542 } vlan; 1543 struct { 1544 u8 addr[6]; 1545 } mac; 1546 struct { 1547 __le16 vlan; 1548 u8 addr[6]; 1549 } mac_vlan; 1550 u8 rsvd[54]; 1551 }; 1552 }; 1553 1554 /** 1555 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 1556 * @status: The status of the command (enum status_code) 1557 * @comp_index: The index in the descriptor ring for which this 1558 * is the completion. 1559 * @filter_id: Filter ID 1560 * @color: Color bit. 1561 */ 1562 struct ionic_rx_filter_add_comp { 1563 u8 status; 1564 u8 rsvd; 1565 __le16 comp_index; 1566 __le32 filter_id; 1567 u8 rsvd2[7]; 1568 u8 color; 1569 }; 1570 1571 /** 1572 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 1573 * @opcode: opcode 1574 * @lif_index: LIF index 1575 * @filter_id: Filter ID 1576 */ 1577 struct ionic_rx_filter_del_cmd { 1578 u8 opcode; 1579 u8 rsvd; 1580 __le16 lif_index; 1581 __le32 filter_id; 1582 u8 rsvd2[56]; 1583 }; 1584 1585 typedef struct ionic_admin_comp ionic_rx_filter_del_comp; 1586 1587 /** 1588 * struct ionic_qos_identify_cmd - QoS identify command 1589 * @opcode: opcode 1590 * @ver: Highest version of identify supported by driver 1591 * 1592 */ 1593 struct ionic_qos_identify_cmd { 1594 u8 opcode; 1595 u8 ver; 1596 u8 rsvd[62]; 1597 }; 1598 1599 /** 1600 * struct ionic_qos_identify_comp - QoS identify command completion 1601 * @status: The status of the command (enum status_code) 1602 * @ver: Version of identify returned by device 1603 */ 1604 struct ionic_qos_identify_comp { 1605 u8 status; 1606 u8 ver; 1607 u8 rsvd[14]; 1608 }; 1609 1610 #define IONIC_QOS_CLASS_MAX 7 1611 #define IONIC_QOS_CLASS_NAME_SZ 32 1612 #define IONIC_QOS_DSCP_MAX_VALUES 64 1613 1614 /** 1615 * enum ionic_qos_class 1616 */ 1617 enum ionic_qos_class { 1618 IONIC_QOS_CLASS_DEFAULT = 0, 1619 IONIC_QOS_CLASS_USER_DEFINED_1 = 1, 1620 IONIC_QOS_CLASS_USER_DEFINED_2 = 2, 1621 IONIC_QOS_CLASS_USER_DEFINED_3 = 3, 1622 IONIC_QOS_CLASS_USER_DEFINED_4 = 4, 1623 IONIC_QOS_CLASS_USER_DEFINED_5 = 5, 1624 IONIC_QOS_CLASS_USER_DEFINED_6 = 6, 1625 }; 1626 1627 /** 1628 * enum ionic_qos_class_type - Traffic classification criteria 1629 */ 1630 enum ionic_qos_class_type { 1631 IONIC_QOS_CLASS_TYPE_NONE = 0, 1632 IONIC_QOS_CLASS_TYPE_PCP = 1, /* Dot1Q pcp */ 1633 IONIC_QOS_CLASS_TYPE_DSCP = 2, /* IP dscp */ 1634 }; 1635 1636 /** 1637 * enum ionic_qos_sched_type - Qos class scheduling type 1638 */ 1639 enum ionic_qos_sched_type { 1640 IONIC_QOS_SCHED_TYPE_STRICT = 0, /* Strict priority */ 1641 IONIC_QOS_SCHED_TYPE_DWRR = 1, /* Deficit weighted round-robin */ 1642 }; 1643 1644 enum ionic_vf_attr { 1645 IONIC_VF_ATTR_SPOOFCHK = 1, 1646 IONIC_VF_ATTR_TRUST = 2, 1647 IONIC_VF_ATTR_MAC = 3, 1648 IONIC_VF_ATTR_LINKSTATE = 4, 1649 IONIC_VF_ATTR_VLAN = 5, 1650 IONIC_VF_ATTR_RATE = 6, 1651 IONIC_VF_ATTR_STATSADDR = 7, 1652 }; 1653 1654 /** 1655 * VF link status 1656 */ 1657 enum ionic_vf_link_status { 1658 IONIC_VF_LINK_STATUS_AUTO = 0, /* link state of the uplink */ 1659 IONIC_VF_LINK_STATUS_UP = 1, /* link is always up */ 1660 IONIC_VF_LINK_STATUS_DOWN = 2, /* link is always down */ 1661 }; 1662 1663 /** 1664 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC 1665 * @opcode: Opcode 1666 * @index: VF index 1667 * @attr: Attribute type (enum ionic_vf_attr) 1668 * macaddr mac address 1669 * vlanid vlan ID 1670 * maxrate max Tx rate in Mbps 1671 * spoofchk enable address spoof checking 1672 * trust enable VF trust 1673 * linkstate set link up or down 1674 * stats_pa set DMA address for VF stats 1675 */ 1676 struct ionic_vf_setattr_cmd { 1677 u8 opcode; 1678 u8 attr; 1679 __le16 vf_index; 1680 union { 1681 u8 macaddr[6]; 1682 __le16 vlanid; 1683 __le32 maxrate; 1684 u8 spoofchk; 1685 u8 trust; 1686 u8 linkstate; 1687 __le64 stats_pa; 1688 u8 pad[60]; 1689 } __packed; 1690 }; 1691 1692 struct ionic_vf_setattr_comp { 1693 u8 status; 1694 u8 attr; 1695 __le16 vf_index; 1696 __le16 comp_index; 1697 u8 rsvd[9]; 1698 u8 color; 1699 }; 1700 1701 /** 1702 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC 1703 * @opcode: Opcode 1704 * @index: VF index 1705 * @attr: Attribute type (enum ionic_vf_attr) 1706 */ 1707 struct ionic_vf_getattr_cmd { 1708 u8 opcode; 1709 u8 attr; 1710 __le16 vf_index; 1711 u8 rsvd[60]; 1712 }; 1713 1714 struct ionic_vf_getattr_comp { 1715 u8 status; 1716 u8 attr; 1717 __le16 vf_index; 1718 union { 1719 u8 macaddr[6]; 1720 __le16 vlanid; 1721 __le32 maxrate; 1722 u8 spoofchk; 1723 u8 trust; 1724 u8 linkstate; 1725 __le64 stats_pa; 1726 u8 pad[11]; 1727 } __packed; 1728 u8 color; 1729 }; 1730 1731 /** 1732 * union ionic_qos_config - Qos configuration structure 1733 * @flags: Configuration flags 1734 * IONIC_QOS_CONFIG_F_ENABLE enable 1735 * IONIC_QOS_CONFIG_F_DROP drop/nodrop 1736 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite 1737 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite 1738 * @sched_type: Qos class scheduling type (enum ionic_qos_sched_type) 1739 * @class_type: Qos class type (enum ionic_qos_class_type) 1740 * @pause_type: Qos pause type (enum ionic_qos_pause_type) 1741 * @name: Qos class name 1742 * @mtu: MTU of the class 1743 * @pfc_dot1q_pcp: Pcp value for pause frames (valid iff F_NODROP) 1744 * @dwrr_weight: Qos class scheduling weight 1745 * @strict_rlmt: Rate limit for strict priority scheduling 1746 * @rw_dot1q_pcp: Rewrite dot1q pcp to this value (valid iff F_RW_DOT1Q_PCP) 1747 * @rw_ip_dscp: Rewrite ip dscp to this value (valid iff F_RW_IP_DSCP) 1748 * @dot1q_pcp: Dot1q pcp value 1749 * @ndscp: Number of valid dscp values in the ip_dscp field 1750 * @ip_dscp: IP dscp values 1751 */ 1752 union ionic_qos_config { 1753 struct { 1754 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) 1755 #define IONIC_QOS_CONFIG_F_DROP BIT(1) 1756 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) 1757 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) 1758 u8 flags; 1759 u8 sched_type; 1760 u8 class_type; 1761 u8 pause_type; 1762 char name[IONIC_QOS_CLASS_NAME_SZ]; 1763 __le32 mtu; 1764 /* flow control */ 1765 u8 pfc_cos; 1766 /* scheduler */ 1767 union { 1768 u8 dwrr_weight; 1769 __le64 strict_rlmt; 1770 }; 1771 /* marking */ 1772 union { 1773 u8 rw_dot1q_pcp; 1774 u8 rw_ip_dscp; 1775 }; 1776 /* classification */ 1777 union { 1778 u8 dot1q_pcp; 1779 struct { 1780 u8 ndscp; 1781 u8 ip_dscp[IONIC_QOS_DSCP_MAX_VALUES]; 1782 }; 1783 }; 1784 }; 1785 __le32 words[64]; 1786 }; 1787 1788 /** 1789 * union ionic_qos_identity - QoS identity structure 1790 * @version: Version of the identify structure 1791 * @type: QoS system type 1792 * @nclasses: Number of usable QoS classes 1793 * @config: Current configuration of classes 1794 */ 1795 union ionic_qos_identity { 1796 struct { 1797 u8 version; 1798 u8 type; 1799 u8 rsvd[62]; 1800 union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; 1801 }; 1802 __le32 words[512]; 1803 }; 1804 1805 /** 1806 * struct qos_init_cmd - QoS config init command 1807 * @opcode: Opcode 1808 * @group: Qos class id 1809 * @info_pa: destination address for qos info 1810 */ 1811 struct ionic_qos_init_cmd { 1812 u8 opcode; 1813 u8 group; 1814 u8 rsvd[6]; 1815 __le64 info_pa; 1816 u8 rsvd1[48]; 1817 }; 1818 1819 typedef struct ionic_admin_comp ionic_qos_init_comp; 1820 1821 /** 1822 * struct ionic_qos_reset_cmd - Qos config reset command 1823 * @opcode: Opcode 1824 */ 1825 struct ionic_qos_reset_cmd { 1826 u8 opcode; 1827 u8 group; 1828 u8 rsvd[62]; 1829 }; 1830 1831 typedef struct ionic_admin_comp ionic_qos_reset_comp; 1832 1833 /** 1834 * struct ionic_fw_download_cmd - Firmware download command 1835 * @opcode: opcode 1836 * @addr: dma address of the firmware buffer 1837 * @offset: offset of the firmware buffer within the full image 1838 * @length: number of valid bytes in the firmware buffer 1839 */ 1840 struct ionic_fw_download_cmd { 1841 u8 opcode; 1842 u8 rsvd[3]; 1843 __le32 offset; 1844 __le64 addr; 1845 __le32 length; 1846 }; 1847 1848 typedef struct ionic_admin_comp ionic_fw_download_comp; 1849 1850 enum ionic_fw_control_oper { 1851 IONIC_FW_RESET = 0, /* Reset firmware */ 1852 IONIC_FW_INSTALL = 1, /* Install firmware */ 1853 IONIC_FW_ACTIVATE = 2, /* Activate firmware */ 1854 }; 1855 1856 /** 1857 * struct ionic_fw_control_cmd - Firmware control command 1858 * @opcode: opcode 1859 * @oper: firmware control operation (enum ionic_fw_control_oper) 1860 * @slot: slot to activate 1861 */ 1862 struct ionic_fw_control_cmd { 1863 u8 opcode; 1864 u8 rsvd[3]; 1865 u8 oper; 1866 u8 slot; 1867 u8 rsvd1[58]; 1868 }; 1869 1870 /** 1871 * struct ionic_fw_control_comp - Firmware control copletion 1872 * @opcode: opcode 1873 * @slot: slot where the firmware was installed 1874 */ 1875 struct ionic_fw_control_comp { 1876 u8 status; 1877 u8 rsvd; 1878 __le16 comp_index; 1879 u8 slot; 1880 u8 rsvd1[10]; 1881 u8 color; 1882 }; 1883 1884 /****************************************************************** 1885 ******************* RDMA Commands ******************************** 1886 ******************************************************************/ 1887 1888 /** 1889 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 1890 * @opcode: opcode 1891 * @lif_index: lif index 1892 * 1893 * There is no rdma specific dev command completion struct. Completion uses 1894 * the common struct ionic_admin_comp. Only the status is indicated. 1895 * Nonzero status means the LIF does not support rdma. 1896 **/ 1897 struct ionic_rdma_reset_cmd { 1898 u8 opcode; 1899 u8 rsvd; 1900 __le16 lif_index; 1901 u8 rsvd2[60]; 1902 }; 1903 1904 /** 1905 * struct ionic_rdma_queue_cmd - Create RDMA Queue command 1906 * @opcode: opcode, 52, 53 1907 * @lif_index lif index 1908 * @qid_ver: (qid | (rdma version << 24)) 1909 * @cid: intr, eq_id, or cq_id 1910 * @dbid: doorbell page id 1911 * @depth_log2: log base two of queue depth 1912 * @stride_log2: log base two of queue stride 1913 * @dma_addr: address of the queue memory 1914 * @xxx_table_index: temporary, but should not need pgtbl for contig. queues. 1915 * 1916 * The same command struct is used to create an rdma event queue, completion 1917 * queue, or rdma admin queue. The cid is an interrupt number for an event 1918 * queue, an event queue id for a completion queue, or a completion queue id 1919 * for an rdma admin queue. 1920 * 1921 * The queue created via a dev command must be contiguous in dma space. 1922 * 1923 * The dev commands are intended only to be used during driver initialization, 1924 * to create queues supporting the rdma admin queue. Other queues, and other 1925 * types of rdma resources like memory regions, will be created and registered 1926 * via the rdma admin queue, and will support a more complete interface 1927 * providing scatter gather lists for larger, scattered queue buffers and 1928 * memory registration. 1929 * 1930 * There is no rdma specific dev command completion struct. Completion uses 1931 * the common struct ionic_admin_comp. Only the status is indicated. 1932 **/ 1933 struct ionic_rdma_queue_cmd { 1934 u8 opcode; 1935 u8 rsvd; 1936 __le16 lif_index; 1937 __le32 qid_ver; 1938 __le32 cid; 1939 __le16 dbid; 1940 u8 depth_log2; 1941 u8 stride_log2; 1942 __le64 dma_addr; 1943 u8 rsvd2[36]; 1944 __le32 xxx_table_index; 1945 }; 1946 1947 /****************************************************************** 1948 ******************* Notify Events ******************************** 1949 ******************************************************************/ 1950 1951 /** 1952 * struct ionic_notifyq_event 1953 * @eid: event number 1954 * @ecode: event code 1955 * @data: unspecified data about the event 1956 * 1957 * This is the generic event report struct from which the other 1958 * actual events will be formed. 1959 */ 1960 struct ionic_notifyq_event { 1961 __le64 eid; 1962 __le16 ecode; 1963 u8 data[54]; 1964 }; 1965 1966 /** 1967 * struct ionic_link_change_event 1968 * @eid: event number 1969 * @ecode: event code = EVENT_OPCODE_LINK_CHANGE 1970 * @link_status: link up or down, with error bits (enum port_status) 1971 * @link_speed: speed of the network link 1972 * 1973 * Sent when the network link state changes between UP and DOWN 1974 */ 1975 struct ionic_link_change_event { 1976 __le64 eid; 1977 __le16 ecode; 1978 __le16 link_status; 1979 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */ 1980 u8 rsvd[48]; 1981 }; 1982 1983 /** 1984 * struct ionic_reset_event 1985 * @eid: event number 1986 * @ecode: event code = EVENT_OPCODE_RESET 1987 * @reset_code: reset type 1988 * @state: 0=pending, 1=complete, 2=error 1989 * 1990 * Sent when the NIC or some subsystem is going to be or 1991 * has been reset. 1992 */ 1993 struct ionic_reset_event { 1994 __le64 eid; 1995 __le16 ecode; 1996 u8 reset_code; 1997 u8 state; 1998 u8 rsvd[52]; 1999 }; 2000 2001 /** 2002 * struct ionic_heartbeat_event 2003 * @eid: event number 2004 * @ecode: event code = EVENT_OPCODE_HEARTBEAT 2005 * 2006 * Sent periodically by the NIC to indicate continued health 2007 */ 2008 struct ionic_heartbeat_event { 2009 __le64 eid; 2010 __le16 ecode; 2011 u8 rsvd[54]; 2012 }; 2013 2014 /** 2015 * struct ionic_log_event 2016 * @eid: event number 2017 * @ecode: event code = EVENT_OPCODE_LOG 2018 * @data: log data 2019 * 2020 * Sent to notify the driver of an internal error. 2021 */ 2022 struct ionic_log_event { 2023 __le64 eid; 2024 __le16 ecode; 2025 u8 data[54]; 2026 }; 2027 2028 /** 2029 * struct ionic_port_stats 2030 */ 2031 struct ionic_port_stats { 2032 __le64 frames_rx_ok; 2033 __le64 frames_rx_all; 2034 __le64 frames_rx_bad_fcs; 2035 __le64 frames_rx_bad_all; 2036 __le64 octets_rx_ok; 2037 __le64 octets_rx_all; 2038 __le64 frames_rx_unicast; 2039 __le64 frames_rx_multicast; 2040 __le64 frames_rx_broadcast; 2041 __le64 frames_rx_pause; 2042 __le64 frames_rx_bad_length; 2043 __le64 frames_rx_undersized; 2044 __le64 frames_rx_oversized; 2045 __le64 frames_rx_fragments; 2046 __le64 frames_rx_jabber; 2047 __le64 frames_rx_pripause; 2048 __le64 frames_rx_stomped_crc; 2049 __le64 frames_rx_too_long; 2050 __le64 frames_rx_vlan_good; 2051 __le64 frames_rx_dropped; 2052 __le64 frames_rx_less_than_64b; 2053 __le64 frames_rx_64b; 2054 __le64 frames_rx_65b_127b; 2055 __le64 frames_rx_128b_255b; 2056 __le64 frames_rx_256b_511b; 2057 __le64 frames_rx_512b_1023b; 2058 __le64 frames_rx_1024b_1518b; 2059 __le64 frames_rx_1519b_2047b; 2060 __le64 frames_rx_2048b_4095b; 2061 __le64 frames_rx_4096b_8191b; 2062 __le64 frames_rx_8192b_9215b; 2063 __le64 frames_rx_other; 2064 __le64 frames_tx_ok; 2065 __le64 frames_tx_all; 2066 __le64 frames_tx_bad; 2067 __le64 octets_tx_ok; 2068 __le64 octets_tx_total; 2069 __le64 frames_tx_unicast; 2070 __le64 frames_tx_multicast; 2071 __le64 frames_tx_broadcast; 2072 __le64 frames_tx_pause; 2073 __le64 frames_tx_pripause; 2074 __le64 frames_tx_vlan; 2075 __le64 frames_tx_less_than_64b; 2076 __le64 frames_tx_64b; 2077 __le64 frames_tx_65b_127b; 2078 __le64 frames_tx_128b_255b; 2079 __le64 frames_tx_256b_511b; 2080 __le64 frames_tx_512b_1023b; 2081 __le64 frames_tx_1024b_1518b; 2082 __le64 frames_tx_1519b_2047b; 2083 __le64 frames_tx_2048b_4095b; 2084 __le64 frames_tx_4096b_8191b; 2085 __le64 frames_tx_8192b_9215b; 2086 __le64 frames_tx_other; 2087 __le64 frames_tx_pri_0; 2088 __le64 frames_tx_pri_1; 2089 __le64 frames_tx_pri_2; 2090 __le64 frames_tx_pri_3; 2091 __le64 frames_tx_pri_4; 2092 __le64 frames_tx_pri_5; 2093 __le64 frames_tx_pri_6; 2094 __le64 frames_tx_pri_7; 2095 __le64 frames_rx_pri_0; 2096 __le64 frames_rx_pri_1; 2097 __le64 frames_rx_pri_2; 2098 __le64 frames_rx_pri_3; 2099 __le64 frames_rx_pri_4; 2100 __le64 frames_rx_pri_5; 2101 __le64 frames_rx_pri_6; 2102 __le64 frames_rx_pri_7; 2103 __le64 tx_pripause_0_1us_count; 2104 __le64 tx_pripause_1_1us_count; 2105 __le64 tx_pripause_2_1us_count; 2106 __le64 tx_pripause_3_1us_count; 2107 __le64 tx_pripause_4_1us_count; 2108 __le64 tx_pripause_5_1us_count; 2109 __le64 tx_pripause_6_1us_count; 2110 __le64 tx_pripause_7_1us_count; 2111 __le64 rx_pripause_0_1us_count; 2112 __le64 rx_pripause_1_1us_count; 2113 __le64 rx_pripause_2_1us_count; 2114 __le64 rx_pripause_3_1us_count; 2115 __le64 rx_pripause_4_1us_count; 2116 __le64 rx_pripause_5_1us_count; 2117 __le64 rx_pripause_6_1us_count; 2118 __le64 rx_pripause_7_1us_count; 2119 __le64 rx_pause_1us_count; 2120 __le64 frames_tx_truncated; 2121 }; 2122 2123 struct ionic_mgmt_port_stats { 2124 __le64 frames_rx_ok; 2125 __le64 frames_rx_all; 2126 __le64 frames_rx_bad_fcs; 2127 __le64 frames_rx_bad_all; 2128 __le64 octets_rx_ok; 2129 __le64 octets_rx_all; 2130 __le64 frames_rx_unicast; 2131 __le64 frames_rx_multicast; 2132 __le64 frames_rx_broadcast; 2133 __le64 frames_rx_pause; 2134 __le64 frames_rx_bad_length0; 2135 __le64 frames_rx_undersized1; 2136 __le64 frames_rx_oversized2; 2137 __le64 frames_rx_fragments3; 2138 __le64 frames_rx_jabber4; 2139 __le64 frames_rx_64b5; 2140 __le64 frames_rx_65b_127b6; 2141 __le64 frames_rx_128b_255b7; 2142 __le64 frames_rx_256b_511b8; 2143 __le64 frames_rx_512b_1023b9; 2144 __le64 frames_rx_1024b_1518b0; 2145 __le64 frames_rx_gt_1518b1; 2146 __le64 frames_rx_fifo_full2; 2147 __le64 frames_tx_ok3; 2148 __le64 frames_tx_all4; 2149 __le64 frames_tx_bad5; 2150 __le64 octets_tx_ok6; 2151 __le64 octets_tx_total7; 2152 __le64 frames_tx_unicast8; 2153 __le64 frames_tx_multicast9; 2154 __le64 frames_tx_broadcast0; 2155 __le64 frames_tx_pause1; 2156 }; 2157 2158 /** 2159 * struct ionic_port_identity - port identity structure 2160 * @version: identity structure version 2161 * @type: type of port (enum port_type) 2162 * @num_lanes: number of lanes for the port 2163 * @autoneg: autoneg supported 2164 * @min_frame_size: minimum frame size supported 2165 * @max_frame_size: maximum frame size supported 2166 * @fec_type: supported fec types 2167 * @pause_type: supported pause types 2168 * @loopback_mode: supported loopback mode 2169 * @speeds: supported speeds 2170 * @config: current port configuration 2171 */ 2172 union ionic_port_identity { 2173 struct { 2174 u8 version; 2175 u8 type; 2176 u8 num_lanes; 2177 u8 autoneg; 2178 __le32 min_frame_size; 2179 __le32 max_frame_size; 2180 u8 fec_type[4]; 2181 u8 pause_type[2]; 2182 u8 loopback_mode[2]; 2183 __le32 speeds[16]; 2184 u8 rsvd2[44]; 2185 union ionic_port_config config; 2186 }; 2187 __le32 words[512]; 2188 }; 2189 2190 /** 2191 * struct ionic_port_info - port info structure 2192 * @port_status: port status 2193 * @port_stats: port stats 2194 */ 2195 struct ionic_port_info { 2196 union ionic_port_config config; 2197 struct ionic_port_status status; 2198 struct ionic_port_stats stats; 2199 }; 2200 2201 /** 2202 * struct ionic_lif_stats 2203 */ 2204 struct ionic_lif_stats { 2205 /* RX */ 2206 __le64 rx_ucast_bytes; 2207 __le64 rx_ucast_packets; 2208 __le64 rx_mcast_bytes; 2209 __le64 rx_mcast_packets; 2210 __le64 rx_bcast_bytes; 2211 __le64 rx_bcast_packets; 2212 __le64 rsvd0; 2213 __le64 rsvd1; 2214 /* RX drops */ 2215 __le64 rx_ucast_drop_bytes; 2216 __le64 rx_ucast_drop_packets; 2217 __le64 rx_mcast_drop_bytes; 2218 __le64 rx_mcast_drop_packets; 2219 __le64 rx_bcast_drop_bytes; 2220 __le64 rx_bcast_drop_packets; 2221 __le64 rx_dma_error; 2222 __le64 rsvd2; 2223 /* TX */ 2224 __le64 tx_ucast_bytes; 2225 __le64 tx_ucast_packets; 2226 __le64 tx_mcast_bytes; 2227 __le64 tx_mcast_packets; 2228 __le64 tx_bcast_bytes; 2229 __le64 tx_bcast_packets; 2230 __le64 rsvd3; 2231 __le64 rsvd4; 2232 /* TX drops */ 2233 __le64 tx_ucast_drop_bytes; 2234 __le64 tx_ucast_drop_packets; 2235 __le64 tx_mcast_drop_bytes; 2236 __le64 tx_mcast_drop_packets; 2237 __le64 tx_bcast_drop_bytes; 2238 __le64 tx_bcast_drop_packets; 2239 __le64 tx_dma_error; 2240 __le64 rsvd5; 2241 /* Rx Queue/Ring drops */ 2242 __le64 rx_queue_disabled; 2243 __le64 rx_queue_empty; 2244 __le64 rx_queue_error; 2245 __le64 rx_desc_fetch_error; 2246 __le64 rx_desc_data_error; 2247 __le64 rsvd6; 2248 __le64 rsvd7; 2249 __le64 rsvd8; 2250 /* Tx Queue/Ring drops */ 2251 __le64 tx_queue_disabled; 2252 __le64 tx_queue_error; 2253 __le64 tx_desc_fetch_error; 2254 __le64 tx_desc_data_error; 2255 __le64 rsvd9; 2256 __le64 rsvd10; 2257 __le64 rsvd11; 2258 __le64 rsvd12; 2259 2260 /* RDMA/ROCE TX */ 2261 __le64 tx_rdma_ucast_bytes; 2262 __le64 tx_rdma_ucast_packets; 2263 __le64 tx_rdma_mcast_bytes; 2264 __le64 tx_rdma_mcast_packets; 2265 __le64 tx_rdma_cnp_packets; 2266 __le64 rsvd13; 2267 __le64 rsvd14; 2268 __le64 rsvd15; 2269 2270 /* RDMA/ROCE RX */ 2271 __le64 rx_rdma_ucast_bytes; 2272 __le64 rx_rdma_ucast_packets; 2273 __le64 rx_rdma_mcast_bytes; 2274 __le64 rx_rdma_mcast_packets; 2275 __le64 rx_rdma_cnp_packets; 2276 __le64 rx_rdma_ecn_packets; 2277 __le64 rsvd16; 2278 __le64 rsvd17; 2279 2280 __le64 rsvd18; 2281 __le64 rsvd19; 2282 __le64 rsvd20; 2283 __le64 rsvd21; 2284 __le64 rsvd22; 2285 __le64 rsvd23; 2286 __le64 rsvd24; 2287 __le64 rsvd25; 2288 2289 __le64 rsvd26; 2290 __le64 rsvd27; 2291 __le64 rsvd28; 2292 __le64 rsvd29; 2293 __le64 rsvd30; 2294 __le64 rsvd31; 2295 __le64 rsvd32; 2296 __le64 rsvd33; 2297 2298 __le64 rsvd34; 2299 __le64 rsvd35; 2300 __le64 rsvd36; 2301 __le64 rsvd37; 2302 __le64 rsvd38; 2303 __le64 rsvd39; 2304 __le64 rsvd40; 2305 __le64 rsvd41; 2306 2307 __le64 rsvd42; 2308 __le64 rsvd43; 2309 __le64 rsvd44; 2310 __le64 rsvd45; 2311 __le64 rsvd46; 2312 __le64 rsvd47; 2313 __le64 rsvd48; 2314 __le64 rsvd49; 2315 2316 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ 2317 __le64 rdma_req_rx_pkt_seq_err; 2318 __le64 rdma_req_rx_rnr_retry_err; 2319 __le64 rdma_req_rx_remote_access_err; 2320 __le64 rdma_req_rx_remote_inv_req_err; 2321 __le64 rdma_req_rx_remote_oper_err; 2322 __le64 rdma_req_rx_implied_nak_seq_err; 2323 __le64 rdma_req_rx_cqe_err; 2324 __le64 rdma_req_rx_cqe_flush_err; 2325 2326 __le64 rdma_req_rx_dup_responses; 2327 __le64 rdma_req_rx_invalid_packets; 2328 __le64 rdma_req_tx_local_access_err; 2329 __le64 rdma_req_tx_local_oper_err; 2330 __le64 rdma_req_tx_memory_mgmt_err; 2331 __le64 rsvd52; 2332 __le64 rsvd53; 2333 __le64 rsvd54; 2334 2335 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ 2336 __le64 rdma_resp_rx_dup_requests; 2337 __le64 rdma_resp_rx_out_of_buffer; 2338 __le64 rdma_resp_rx_out_of_seq_pkts; 2339 __le64 rdma_resp_rx_cqe_err; 2340 __le64 rdma_resp_rx_cqe_flush_err; 2341 __le64 rdma_resp_rx_local_len_err; 2342 __le64 rdma_resp_rx_inv_request_err; 2343 __le64 rdma_resp_rx_local_qp_oper_err; 2344 2345 __le64 rdma_resp_rx_out_of_atomic_resource; 2346 __le64 rdma_resp_tx_pkt_seq_err; 2347 __le64 rdma_resp_tx_remote_inv_req_err; 2348 __le64 rdma_resp_tx_remote_access_err; 2349 __le64 rdma_resp_tx_remote_oper_err; 2350 __le64 rdma_resp_tx_rnr_retry_err; 2351 __le64 rsvd57; 2352 __le64 rsvd58; 2353 }; 2354 2355 /** 2356 * struct ionic_lif_info - lif info structure 2357 */ 2358 struct ionic_lif_info { 2359 union ionic_lif_config config; 2360 struct ionic_lif_status status; 2361 struct ionic_lif_stats stats; 2362 }; 2363 2364 union ionic_dev_cmd { 2365 u32 words[16]; 2366 struct ionic_admin_cmd cmd; 2367 struct ionic_nop_cmd nop; 2368 2369 struct ionic_dev_identify_cmd identify; 2370 struct ionic_dev_init_cmd init; 2371 struct ionic_dev_reset_cmd reset; 2372 struct ionic_dev_getattr_cmd getattr; 2373 struct ionic_dev_setattr_cmd setattr; 2374 2375 struct ionic_port_identify_cmd port_identify; 2376 struct ionic_port_init_cmd port_init; 2377 struct ionic_port_reset_cmd port_reset; 2378 struct ionic_port_getattr_cmd port_getattr; 2379 struct ionic_port_setattr_cmd port_setattr; 2380 2381 struct ionic_vf_setattr_cmd vf_setattr; 2382 struct ionic_vf_getattr_cmd vf_getattr; 2383 2384 struct ionic_lif_identify_cmd lif_identify; 2385 struct ionic_lif_init_cmd lif_init; 2386 struct ionic_lif_reset_cmd lif_reset; 2387 2388 struct ionic_qos_identify_cmd qos_identify; 2389 struct ionic_qos_init_cmd qos_init; 2390 struct ionic_qos_reset_cmd qos_reset; 2391 2392 struct ionic_q_init_cmd q_init; 2393 }; 2394 2395 union ionic_dev_cmd_comp { 2396 u32 words[4]; 2397 u8 status; 2398 struct ionic_admin_comp comp; 2399 struct ionic_nop_comp nop; 2400 2401 struct ionic_dev_identify_comp identify; 2402 struct ionic_dev_init_comp init; 2403 struct ionic_dev_reset_comp reset; 2404 struct ionic_dev_getattr_comp getattr; 2405 struct ionic_dev_setattr_comp setattr; 2406 2407 struct ionic_port_identify_comp port_identify; 2408 struct ionic_port_init_comp port_init; 2409 struct ionic_port_reset_comp port_reset; 2410 struct ionic_port_getattr_comp port_getattr; 2411 struct ionic_port_setattr_comp port_setattr; 2412 2413 struct ionic_vf_setattr_comp vf_setattr; 2414 struct ionic_vf_getattr_comp vf_getattr; 2415 2416 struct ionic_lif_identify_comp lif_identify; 2417 struct ionic_lif_init_comp lif_init; 2418 ionic_lif_reset_comp lif_reset; 2419 2420 struct ionic_qos_identify_comp qos_identify; 2421 ionic_qos_init_comp qos_init; 2422 ionic_qos_reset_comp qos_reset; 2423 2424 struct ionic_q_init_comp q_init; 2425 }; 2426 2427 /** 2428 * union dev_info - Device info register format (read-only) 2429 * @signature: Signature value of 0x44455649 ('DEVI'). 2430 * @version: Current version of info. 2431 * @asic_type: Asic type. 2432 * @asic_rev: Asic revision. 2433 * @fw_status: Firmware status. 2434 * @fw_heartbeat: Firmware heartbeat counter. 2435 * @serial_num: Serial number. 2436 * @fw_version: Firmware version. 2437 */ 2438 union ionic_dev_info_regs { 2439 #define IONIC_DEVINFO_FWVERS_BUFLEN 32 2440 #define IONIC_DEVINFO_SERIAL_BUFLEN 32 2441 struct { 2442 u32 signature; 2443 u8 version; 2444 u8 asic_type; 2445 u8 asic_rev; 2446 #define IONIC_FW_STS_F_RUNNING 0x1 2447 u8 fw_status; 2448 u32 fw_heartbeat; 2449 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; 2450 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; 2451 }; 2452 u32 words[512]; 2453 }; 2454 2455 /** 2456 * union ionic_dev_cmd_regs - Device command register format (read-write) 2457 * @doorbell: Device Cmd Doorbell, write-only. 2458 * Write a 1 to signal device to process cmd, 2459 * poll done for completion. 2460 * @done: Done indicator, bit 0 == 1 when command is complete. 2461 * @cmd: Opcode-specific command bytes 2462 * @comp: Opcode-specific response bytes 2463 * @data: Opcode-specific side-data 2464 */ 2465 union ionic_dev_cmd_regs { 2466 struct { 2467 u32 doorbell; 2468 u32 done; 2469 union ionic_dev_cmd cmd; 2470 union ionic_dev_cmd_comp comp; 2471 u8 rsvd[48]; 2472 u32 data[478]; 2473 } __packed; 2474 u32 words[512]; 2475 }; 2476 2477 /** 2478 * union ionic_dev_regs - Device register format in for bar 0 page 0 2479 * @info: Device info registers 2480 * @devcmd: Device command registers 2481 */ 2482 union ionic_dev_regs { 2483 struct { 2484 union ionic_dev_info_regs info; 2485 union ionic_dev_cmd_regs devcmd; 2486 } __packed; 2487 __le32 words[1024]; 2488 }; 2489 2490 union ionic_adminq_cmd { 2491 struct ionic_admin_cmd cmd; 2492 struct ionic_nop_cmd nop; 2493 struct ionic_q_init_cmd q_init; 2494 struct ionic_q_control_cmd q_control; 2495 struct ionic_lif_setattr_cmd lif_setattr; 2496 struct ionic_lif_getattr_cmd lif_getattr; 2497 struct ionic_rx_mode_set_cmd rx_mode_set; 2498 struct ionic_rx_filter_add_cmd rx_filter_add; 2499 struct ionic_rx_filter_del_cmd rx_filter_del; 2500 struct ionic_rdma_reset_cmd rdma_reset; 2501 struct ionic_rdma_queue_cmd rdma_queue; 2502 struct ionic_fw_download_cmd fw_download; 2503 struct ionic_fw_control_cmd fw_control; 2504 }; 2505 2506 union ionic_adminq_comp { 2507 struct ionic_admin_comp comp; 2508 struct ionic_nop_comp nop; 2509 struct ionic_q_init_comp q_init; 2510 struct ionic_lif_setattr_comp lif_setattr; 2511 struct ionic_lif_getattr_comp lif_getattr; 2512 struct ionic_rx_filter_add_comp rx_filter_add; 2513 struct ionic_fw_control_comp fw_control; 2514 }; 2515 2516 #define IONIC_BARS_MAX 6 2517 #define IONIC_PCI_BAR_DBELL 1 2518 2519 /* BAR0 */ 2520 #define IONIC_BAR0_SIZE 0x8000 2521 2522 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 2523 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 2524 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 2525 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 2526 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 2527 #define IONIC_DEV_CMD_DONE 0x00000001 2528 2529 #define IONIC_ASIC_TYPE_CAPRI 0 2530 2531 /** 2532 * struct ionic_doorbell - Doorbell register layout 2533 * @p_index: Producer index 2534 * @ring: Selects the specific ring of the queue to update. 2535 * Type-specific meaning: 2536 * ring=0: Default producer/consumer queue. 2537 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs 2538 * send events to EQs when armed. EQs send 2539 * interrupts when armed. 2540 * @qid: The queue id selects the queue destination for the 2541 * producer index and flags. 2542 */ 2543 struct ionic_doorbell { 2544 __le16 p_index; 2545 u8 ring; 2546 u8 qid_lo; 2547 __le16 qid_hi; 2548 u16 rsvd2; 2549 }; 2550 2551 struct ionic_intr_status { 2552 u32 status[2]; 2553 }; 2554 2555 struct ionic_notifyq_cmd { 2556 __le32 data; /* Not used but needed for qcq structure */ 2557 }; 2558 2559 union ionic_notifyq_comp { 2560 struct ionic_notifyq_event event; 2561 struct ionic_link_change_event link_change; 2562 struct ionic_reset_event reset; 2563 struct ionic_heartbeat_event heartbeat; 2564 struct ionic_log_event log; 2565 }; 2566 2567 /* Deprecate */ 2568 struct ionic_identity { 2569 union ionic_drv_identity drv; 2570 union ionic_dev_identity dev; 2571 union ionic_lif_identity lif; 2572 union ionic_port_identity port; 2573 union ionic_qos_identity qos; 2574 }; 2575 2576 #endif /* _IONIC_IF_H_ */ 2577