1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: dmsc@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes= <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x0 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clocks { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 wkup_pmx0: pinmux@4301c000 { 38 compatible = "pinctrl-single"; 39 /* Proxy 0 addressing */ 40 reg = <0x00 0x4301c000 0x00 0x178>; 41 #pinctrl-cells = <1>; 42 pinctrl-single,register-width = <32>; 43 pinctrl-single,function-mask = <0xffffffff>; 44 }; 45 46 mcu_ram: sram@41c00000 { 47 compatible = "mmio-sram"; 48 reg = <0x00 0x41c00000 0x00 0x100000>; 49 ranges = <0x0 0x00 0x41c00000 0x100000>; 50 #address-cells = <1>; 51 #size-cells = <1>; 52 }; 53 54 wkup_uart0: serial@42300000 { 55 compatible = "ti,j721e-uart", "ti,am654-uart"; 56 reg = <0x00 0x42300000 0x00 0x100>; 57 reg-shift = <2>; 58 reg-io-width = <4>; 59 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 60 clock-frequency = <48000000>; 61 current-speed = <115200>; 62 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 63 clocks = <&k3_clks 287 0>; 64 clock-names = "fclk"; 65 }; 66 67 mcu_uart0: serial@40a00000 { 68 compatible = "ti,j721e-uart", "ti,am654-uart"; 69 reg = <0x00 0x40a00000 0x00 0x100>; 70 reg-shift = <2>; 71 reg-io-width = <4>; 72 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 73 clock-frequency = <96000000>; 74 current-speed = <115200>; 75 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 76 clocks = <&k3_clks 149 0>; 77 clock-names = "fclk"; 78 }; 79 80 wkup_gpio_intr: interrupt-controller2 { 81 compatible = "ti,sci-intr"; 82 ti,intr-trigger-type = <1>; 83 interrupt-controller; 84 interrupt-parent = <&gic500>; 85 #interrupt-cells = <2>; 86 ti,sci = <&dmsc>; 87 ti,sci-dst-id = <14>; 88 ti,sci-rm-range-girq = <0x5>; 89 }; 90 91 wkup_gpio0: gpio@42110000 { 92 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 93 reg = <0x0 0x42110000 0x0 0x100>; 94 gpio-controller; 95 #gpio-cells = <2>; 96 interrupt-parent = <&wkup_gpio_intr>; 97 interrupts = <113 0>, <113 1>, <113 2>, 98 <113 3>, <113 4>, <113 5>; 99 interrupt-controller; 100 #interrupt-cells = <2>; 101 ti,ngpio = <84>; 102 ti,davinci-gpio-unbanked = <0>; 103 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 104 clocks = <&k3_clks 113 0>; 105 clock-names = "gpio"; 106 }; 107 108 wkup_gpio1: gpio@42100000 { 109 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 110 reg = <0x0 0x42100000 0x0 0x100>; 111 gpio-controller; 112 #gpio-cells = <2>; 113 interrupt-parent = <&wkup_gpio_intr>; 114 interrupts = <114 0>, <114 1>, <114 2>, 115 <114 3>, <114 4>, <114 5>; 116 interrupt-controller; 117 #interrupt-cells = <2>; 118 ti,ngpio = <84>; 119 ti,davinci-gpio-unbanked = <0>; 120 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 121 clocks = <&k3_clks 114 0>; 122 clock-names = "gpio"; 123 }; 124 125 mcu_i2c0: i2c@40b00000 { 126 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 127 reg = <0x0 0x40b00000 0x0 0x100>; 128 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 clock-names = "fck"; 132 clocks = <&k3_clks 194 0>; 133 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 134 }; 135 136 mcu_i2c1: i2c@40b10000 { 137 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 138 reg = <0x0 0x40b10000 0x0 0x100>; 139 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 clock-names = "fck"; 143 clocks = <&k3_clks 195 0>; 144 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 145 }; 146 147 wkup_i2c0: i2c@42120000 { 148 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 149 reg = <0x0 0x42120000 0x0 0x100>; 150 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 clock-names = "fck"; 154 clocks = <&k3_clks 197 0>; 155 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 156 }; 157 158 fss: fss@47000000 { 159 compatible = "simple-bus"; 160 reg = <0x0 0x47000000 0x0 0x100>; 161 #address-cells = <2>; 162 #size-cells = <2>; 163 ranges; 164 165 ospi0: spi@47040000 { 166 compatible = "ti,am654-ospi"; 167 reg = <0x0 0x47040000 0x0 0x100>, 168 <0x5 0x00000000 0x1 0x0000000>; 169 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 170 cdns,fifo-depth = <256>; 171 cdns,fifo-width = <4>; 172 cdns,trigger-address = <0x0>; 173 clocks = <&k3_clks 103 0>; 174 assigned-clocks = <&k3_clks 103 0>; 175 assigned-clock-parents = <&k3_clks 103 2>; 176 assigned-clock-rates = <166666666>; 177 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 }; 181 182 ospi1: spi@47050000 { 183 compatible = "ti,am654-ospi"; 184 reg = <0x0 0x47050000 0x0 0x100>, 185 <0x7 0x00000000 0x1 0x00000000>; 186 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 187 cdns,fifo-depth = <256>; 188 cdns,fifo-width = <4>; 189 cdns,trigger-address = <0x0>; 190 clocks = <&k3_clks 104 0>; 191 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 }; 195 }; 196 197 tscadc0: tscadc@40200000 { 198 compatible = "ti,am3359-tscadc"; 199 reg = <0x0 0x40200000 0x0 0x1000>; 200 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 201 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 202 clocks = <&k3_clks 0 1>; 203 assigned-clocks = <&k3_clks 0 3>; 204 assigned-clock-rates = <60000000>; 205 clock-names = "adc_tsc_fck"; 206 207 adc { 208 #io-channel-cells = <1>; 209 compatible = "ti,am3359-adc"; 210 }; 211 }; 212 213 tscadc1: tscadc@40210000 { 214 compatible = "ti,am3359-tscadc"; 215 reg = <0x0 0x40210000 0x0 0x1000>; 216 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 217 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 218 clocks = <&k3_clks 1 1>; 219 assigned-clocks = <&k3_clks 1 3>; 220 assigned-clock-rates = <60000000>; 221 clock-names = "adc_tsc_fck"; 222 223 adc { 224 #io-channel-cells = <1>; 225 compatible = "ti,am3359-adc"; 226 }; 227 }; 228 229 mcu_navss { 230 compatible = "simple-mfd"; 231 #address-cells = <2>; 232 #size-cells = <2>; 233 ranges; 234 dma-coherent; 235 dma-ranges; 236 237 ti,sci-dev-id = <232>; 238 239 mcu_ringacc: ringacc@2b800000 { 240 compatible = "ti,am654-navss-ringacc"; 241 reg = <0x0 0x2b800000 0x0 0x400000>, 242 <0x0 0x2b000000 0x0 0x400000>, 243 <0x0 0x28590000 0x0 0x100>, 244 <0x0 0x2a500000 0x0 0x40000>; 245 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 246 ti,num-rings = <286>; 247 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 248 ti,sci = <&dmsc>; 249 ti,sci-dev-id = <235>; 250 msi-parent = <&main_udmass_inta>; 251 }; 252 253 mcu_udmap: dma-controller@285c0000 { 254 compatible = "ti,j721e-navss-mcu-udmap"; 255 reg = <0x0 0x285c0000 0x0 0x100>, 256 <0x0 0x2a800000 0x0 0x40000>, 257 <0x0 0x2aa00000 0x0 0x40000>; 258 reg-names = "gcfg", "rchanrt", "tchanrt"; 259 msi-parent = <&main_udmass_inta>; 260 #dma-cells = <1>; 261 262 ti,sci = <&dmsc>; 263 ti,sci-dev-id = <236>; 264 ti,ringacc = <&mcu_ringacc>; 265 266 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 267 <0x0f>; /* TX_HCHAN */ 268 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 269 <0x0b>; /* RX_HCHAN */ 270 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 271 }; 272 }; 273}; 274