1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/video/omap2/dss/venc.c 4 * 5 * Copyright (C) 2009 Nokia Corporation 6 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 7 * 8 * VENC settings from TI's DSS driver 9 */ 10 11 #define DSS_SUBSYS_NAME "VENC" 12 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/clk.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/mutex.h> 19 #include <linux/completion.h> 20 #include <linux/delay.h> 21 #include <linux/string.h> 22 #include <linux/seq_file.h> 23 #include <linux/platform_device.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/of.h> 27 #include <linux/component.h> 28 29 #include <video/omapfb_dss.h> 30 31 #include "dss.h" 32 #include "dss_features.h" 33 34 /* Venc registers */ 35 #define VENC_REV_ID 0x00 36 #define VENC_STATUS 0x04 37 #define VENC_F_CONTROL 0x08 38 #define VENC_VIDOUT_CTRL 0x10 39 #define VENC_SYNC_CTRL 0x14 40 #define VENC_LLEN 0x1C 41 #define VENC_FLENS 0x20 42 #define VENC_HFLTR_CTRL 0x24 43 #define VENC_CC_CARR_WSS_CARR 0x28 44 #define VENC_C_PHASE 0x2C 45 #define VENC_GAIN_U 0x30 46 #define VENC_GAIN_V 0x34 47 #define VENC_GAIN_Y 0x38 48 #define VENC_BLACK_LEVEL 0x3C 49 #define VENC_BLANK_LEVEL 0x40 50 #define VENC_X_COLOR 0x44 51 #define VENC_M_CONTROL 0x48 52 #define VENC_BSTAMP_WSS_DATA 0x4C 53 #define VENC_S_CARR 0x50 54 #define VENC_LINE21 0x54 55 #define VENC_LN_SEL 0x58 56 #define VENC_L21__WC_CTL 0x5C 57 #define VENC_HTRIGGER_VTRIGGER 0x60 58 #define VENC_SAVID__EAVID 0x64 59 #define VENC_FLEN__FAL 0x68 60 #define VENC_LAL__PHASE_RESET 0x6C 61 #define VENC_HS_INT_START_STOP_X 0x70 62 #define VENC_HS_EXT_START_STOP_X 0x74 63 #define VENC_VS_INT_START_X 0x78 64 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C 65 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80 66 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84 67 #define VENC_VS_EXT_STOP_Y 0x88 68 #define VENC_AVID_START_STOP_X 0x90 69 #define VENC_AVID_START_STOP_Y 0x94 70 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0 71 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4 72 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8 73 #define VENC_TVDETGP_INT_START_STOP_X 0xB0 74 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4 75 #define VENC_GEN_CTRL 0xB8 76 #define VENC_OUTPUT_CONTROL 0xC4 77 #define VENC_OUTPUT_TEST 0xC8 78 #define VENC_DAC_B__DAC_C 0xC8 79 80 struct venc_config { 81 u32 f_control; 82 u32 vidout_ctrl; 83 u32 sync_ctrl; 84 u32 llen; 85 u32 flens; 86 u32 hfltr_ctrl; 87 u32 cc_carr_wss_carr; 88 u32 c_phase; 89 u32 gain_u; 90 u32 gain_v; 91 u32 gain_y; 92 u32 black_level; 93 u32 blank_level; 94 u32 x_color; 95 u32 m_control; 96 u32 bstamp_wss_data; 97 u32 s_carr; 98 u32 line21; 99 u32 ln_sel; 100 u32 l21__wc_ctl; 101 u32 htrigger_vtrigger; 102 u32 savid__eavid; 103 u32 flen__fal; 104 u32 lal__phase_reset; 105 u32 hs_int_start_stop_x; 106 u32 hs_ext_start_stop_x; 107 u32 vs_int_start_x; 108 u32 vs_int_stop_x__vs_int_start_y; 109 u32 vs_int_stop_y__vs_ext_start_x; 110 u32 vs_ext_stop_x__vs_ext_start_y; 111 u32 vs_ext_stop_y; 112 u32 avid_start_stop_x; 113 u32 avid_start_stop_y; 114 u32 fid_int_start_x__fid_int_start_y; 115 u32 fid_int_offset_y__fid_ext_start_x; 116 u32 fid_ext_start_y__fid_ext_offset_y; 117 u32 tvdetgp_int_start_stop_x; 118 u32 tvdetgp_int_start_stop_y; 119 u32 gen_ctrl; 120 }; 121 122 /* from TRM */ 123 static const struct venc_config venc_config_pal_trm = { 124 .f_control = 0, 125 .vidout_ctrl = 1, 126 .sync_ctrl = 0x40, 127 .llen = 0x35F, /* 863 */ 128 .flens = 0x270, /* 624 */ 129 .hfltr_ctrl = 0, 130 .cc_carr_wss_carr = 0x2F7225ED, 131 .c_phase = 0, 132 .gain_u = 0x111, 133 .gain_v = 0x181, 134 .gain_y = 0x140, 135 .black_level = 0x3B, 136 .blank_level = 0x3B, 137 .x_color = 0x7, 138 .m_control = 0x2, 139 .bstamp_wss_data = 0x3F, 140 .s_carr = 0x2A098ACB, 141 .line21 = 0, 142 .ln_sel = 0x01290015, 143 .l21__wc_ctl = 0x0000F603, 144 .htrigger_vtrigger = 0, 145 146 .savid__eavid = 0x06A70108, 147 .flen__fal = 0x00180270, 148 .lal__phase_reset = 0x00040135, 149 .hs_int_start_stop_x = 0x00880358, 150 .hs_ext_start_stop_x = 0x000F035F, 151 .vs_int_start_x = 0x01A70000, 152 .vs_int_stop_x__vs_int_start_y = 0x000001A7, 153 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000, 154 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF, 155 .vs_ext_stop_y = 0x00000025, 156 .avid_start_stop_x = 0x03530083, 157 .avid_start_stop_y = 0x026C002E, 158 .fid_int_start_x__fid_int_start_y = 0x0001008A, 159 .fid_int_offset_y__fid_ext_start_x = 0x002E0138, 160 .fid_ext_start_y__fid_ext_offset_y = 0x01380001, 161 162 .tvdetgp_int_start_stop_x = 0x00140001, 163 .tvdetgp_int_start_stop_y = 0x00010001, 164 .gen_ctrl = 0x00FF0000, 165 }; 166 167 /* from TRM */ 168 static const struct venc_config venc_config_ntsc_trm = { 169 .f_control = 0, 170 .vidout_ctrl = 1, 171 .sync_ctrl = 0x8040, 172 .llen = 0x359, 173 .flens = 0x20C, 174 .hfltr_ctrl = 0, 175 .cc_carr_wss_carr = 0x043F2631, 176 .c_phase = 0, 177 .gain_u = 0x102, 178 .gain_v = 0x16C, 179 .gain_y = 0x12F, 180 .black_level = 0x43, 181 .blank_level = 0x38, 182 .x_color = 0x7, 183 .m_control = 0x1, 184 .bstamp_wss_data = 0x38, 185 .s_carr = 0x21F07C1F, 186 .line21 = 0, 187 .ln_sel = 0x01310011, 188 .l21__wc_ctl = 0x0000F003, 189 .htrigger_vtrigger = 0, 190 191 .savid__eavid = 0x069300F4, 192 .flen__fal = 0x0016020C, 193 .lal__phase_reset = 0x00060107, 194 .hs_int_start_stop_x = 0x008E0350, 195 .hs_ext_start_stop_x = 0x000F0359, 196 .vs_int_start_x = 0x01A00000, 197 .vs_int_stop_x__vs_int_start_y = 0x020701A0, 198 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, 199 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, 200 .vs_ext_stop_y = 0x00000006, 201 .avid_start_stop_x = 0x03480078, 202 .avid_start_stop_y = 0x02060024, 203 .fid_int_start_x__fid_int_start_y = 0x0001008A, 204 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, 205 .fid_ext_start_y__fid_ext_offset_y = 0x01060006, 206 207 .tvdetgp_int_start_stop_x = 0x00140001, 208 .tvdetgp_int_start_stop_y = 0x00010001, 209 .gen_ctrl = 0x00F90000, 210 }; 211 212 const struct omap_video_timings omap_dss_pal_timings = { 213 .x_res = 720, 214 .y_res = 574, 215 .pixelclock = 13500000, 216 .hsw = 64, 217 .hfp = 12, 218 .hbp = 68, 219 .vsw = 5, 220 .vfp = 5, 221 .vbp = 41, 222 223 .interlace = true, 224 }; 225 EXPORT_SYMBOL(omap_dss_pal_timings); 226 227 const struct omap_video_timings omap_dss_ntsc_timings = { 228 .x_res = 720, 229 .y_res = 482, 230 .pixelclock = 13500000, 231 .hsw = 64, 232 .hfp = 16, 233 .hbp = 58, 234 .vsw = 6, 235 .vfp = 6, 236 .vbp = 31, 237 238 .interlace = true, 239 }; 240 EXPORT_SYMBOL(omap_dss_ntsc_timings); 241 242 static struct { 243 struct platform_device *pdev; 244 void __iomem *base; 245 struct mutex venc_lock; 246 u32 wss_data; 247 struct regulator *vdda_dac_reg; 248 249 struct clk *tv_dac_clk; 250 251 struct omap_video_timings timings; 252 enum omap_dss_venc_type type; 253 bool invert_polarity; 254 255 struct omap_dss_device output; 256 } venc; 257 258 static inline void venc_write_reg(int idx, u32 val) 259 { 260 __raw_writel(val, venc.base + idx); 261 } 262 263 static inline u32 venc_read_reg(int idx) 264 { 265 u32 l = __raw_readl(venc.base + idx); 266 return l; 267 } 268 269 static void venc_write_config(const struct venc_config *config) 270 { 271 DSSDBG("write venc conf\n"); 272 273 venc_write_reg(VENC_LLEN, config->llen); 274 venc_write_reg(VENC_FLENS, config->flens); 275 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); 276 venc_write_reg(VENC_C_PHASE, config->c_phase); 277 venc_write_reg(VENC_GAIN_U, config->gain_u); 278 venc_write_reg(VENC_GAIN_V, config->gain_v); 279 venc_write_reg(VENC_GAIN_Y, config->gain_y); 280 venc_write_reg(VENC_BLACK_LEVEL, config->black_level); 281 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level); 282 venc_write_reg(VENC_M_CONTROL, config->m_control); 283 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | 284 venc.wss_data); 285 venc_write_reg(VENC_S_CARR, config->s_carr); 286 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl); 287 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid); 288 venc_write_reg(VENC_FLEN__FAL, config->flen__fal); 289 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset); 290 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x); 291 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x); 292 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x); 293 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y, 294 config->vs_int_stop_x__vs_int_start_y); 295 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X, 296 config->vs_int_stop_y__vs_ext_start_x); 297 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y, 298 config->vs_ext_stop_x__vs_ext_start_y); 299 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y); 300 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x); 301 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y); 302 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y, 303 config->fid_int_start_x__fid_int_start_y); 304 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, 305 config->fid_int_offset_y__fid_ext_start_x); 306 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, 307 config->fid_ext_start_y__fid_ext_offset_y); 308 309 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C)); 310 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl); 311 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl); 312 venc_write_reg(VENC_X_COLOR, config->x_color); 313 venc_write_reg(VENC_LINE21, config->line21); 314 venc_write_reg(VENC_LN_SEL, config->ln_sel); 315 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger); 316 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X, 317 config->tvdetgp_int_start_stop_x); 318 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y, 319 config->tvdetgp_int_start_stop_y); 320 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl); 321 venc_write_reg(VENC_F_CONTROL, config->f_control); 322 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl); 323 } 324 325 static void venc_reset(void) 326 { 327 int t = 1000; 328 329 venc_write_reg(VENC_F_CONTROL, 1<<8); 330 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) { 331 if (--t == 0) { 332 DSSERR("Failed to reset venc\n"); 333 return; 334 } 335 } 336 337 #ifdef CONFIG_FB_OMAP2_DSS_SLEEP_AFTER_VENC_RESET 338 /* the magical sleep that makes things work */ 339 /* XXX more info? What bug this circumvents? */ 340 msleep(20); 341 #endif 342 } 343 344 static int venc_runtime_get(void) 345 { 346 int r; 347 348 DSSDBG("venc_runtime_get\n"); 349 350 r = pm_runtime_get_sync(&venc.pdev->dev); 351 WARN_ON(r < 0); 352 return r < 0 ? r : 0; 353 } 354 355 static void venc_runtime_put(void) 356 { 357 int r; 358 359 DSSDBG("venc_runtime_put\n"); 360 361 r = pm_runtime_put_sync(&venc.pdev->dev); 362 WARN_ON(r < 0 && r != -ENOSYS); 363 } 364 365 static const struct venc_config *venc_timings_to_config( 366 struct omap_video_timings *timings) 367 { 368 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) 369 return &venc_config_pal_trm; 370 371 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) 372 return &venc_config_ntsc_trm; 373 374 BUG(); 375 return NULL; 376 } 377 378 static int venc_power_on(struct omap_dss_device *dssdev) 379 { 380 struct omap_overlay_manager *mgr = venc.output.manager; 381 u32 l; 382 int r; 383 384 r = venc_runtime_get(); 385 if (r) 386 goto err0; 387 388 venc_reset(); 389 venc_write_config(venc_timings_to_config(&venc.timings)); 390 391 dss_set_venc_output(venc.type); 392 dss_set_dac_pwrdn_bgz(1); 393 394 l = 0; 395 396 if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) 397 l |= 1 << 1; 398 else /* S-Video */ 399 l |= (1 << 0) | (1 << 2); 400 401 if (venc.invert_polarity == false) 402 l |= 1 << 3; 403 404 venc_write_reg(VENC_OUTPUT_CONTROL, l); 405 406 dss_mgr_set_timings(mgr, &venc.timings); 407 408 r = regulator_enable(venc.vdda_dac_reg); 409 if (r) 410 goto err1; 411 412 r = dss_mgr_enable(mgr); 413 if (r) 414 goto err2; 415 416 return 0; 417 418 err2: 419 regulator_disable(venc.vdda_dac_reg); 420 err1: 421 venc_write_reg(VENC_OUTPUT_CONTROL, 0); 422 dss_set_dac_pwrdn_bgz(0); 423 424 venc_runtime_put(); 425 err0: 426 return r; 427 } 428 429 static void venc_power_off(struct omap_dss_device *dssdev) 430 { 431 struct omap_overlay_manager *mgr = venc.output.manager; 432 433 venc_write_reg(VENC_OUTPUT_CONTROL, 0); 434 dss_set_dac_pwrdn_bgz(0); 435 436 dss_mgr_disable(mgr); 437 438 regulator_disable(venc.vdda_dac_reg); 439 440 venc_runtime_put(); 441 } 442 443 static int venc_display_enable(struct omap_dss_device *dssdev) 444 { 445 struct omap_dss_device *out = &venc.output; 446 int r; 447 448 DSSDBG("venc_display_enable\n"); 449 450 mutex_lock(&venc.venc_lock); 451 452 if (out->manager == NULL) { 453 DSSERR("Failed to enable display: no output/manager\n"); 454 r = -ENODEV; 455 goto err0; 456 } 457 458 r = venc_power_on(dssdev); 459 if (r) 460 goto err0; 461 462 venc.wss_data = 0; 463 464 mutex_unlock(&venc.venc_lock); 465 466 return 0; 467 err0: 468 mutex_unlock(&venc.venc_lock); 469 return r; 470 } 471 472 static void venc_display_disable(struct omap_dss_device *dssdev) 473 { 474 DSSDBG("venc_display_disable\n"); 475 476 mutex_lock(&venc.venc_lock); 477 478 venc_power_off(dssdev); 479 480 mutex_unlock(&venc.venc_lock); 481 } 482 483 static void venc_set_timings(struct omap_dss_device *dssdev, 484 struct omap_video_timings *timings) 485 { 486 DSSDBG("venc_set_timings\n"); 487 488 mutex_lock(&venc.venc_lock); 489 490 /* Reset WSS data when the TV standard changes. */ 491 if (memcmp(&venc.timings, timings, sizeof(*timings))) 492 venc.wss_data = 0; 493 494 venc.timings = *timings; 495 496 dispc_set_tv_pclk(13500000); 497 498 mutex_unlock(&venc.venc_lock); 499 } 500 501 static int venc_check_timings(struct omap_dss_device *dssdev, 502 struct omap_video_timings *timings) 503 { 504 DSSDBG("venc_check_timings\n"); 505 506 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) 507 return 0; 508 509 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) 510 return 0; 511 512 return -EINVAL; 513 } 514 515 static void venc_get_timings(struct omap_dss_device *dssdev, 516 struct omap_video_timings *timings) 517 { 518 mutex_lock(&venc.venc_lock); 519 520 *timings = venc.timings; 521 522 mutex_unlock(&venc.venc_lock); 523 } 524 525 static u32 venc_get_wss(struct omap_dss_device *dssdev) 526 { 527 /* Invert due to VENC_L21_WC_CTL:INV=1 */ 528 return (venc.wss_data >> 8) ^ 0xfffff; 529 } 530 531 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss) 532 { 533 const struct venc_config *config; 534 int r; 535 536 DSSDBG("venc_set_wss\n"); 537 538 mutex_lock(&venc.venc_lock); 539 540 config = venc_timings_to_config(&venc.timings); 541 542 /* Invert due to VENC_L21_WC_CTL:INV=1 */ 543 venc.wss_data = (wss ^ 0xfffff) << 8; 544 545 r = venc_runtime_get(); 546 if (r) 547 goto err; 548 549 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | 550 venc.wss_data); 551 552 venc_runtime_put(); 553 554 err: 555 mutex_unlock(&venc.venc_lock); 556 557 return r; 558 } 559 560 static void venc_set_type(struct omap_dss_device *dssdev, 561 enum omap_dss_venc_type type) 562 { 563 mutex_lock(&venc.venc_lock); 564 565 venc.type = type; 566 567 mutex_unlock(&venc.venc_lock); 568 } 569 570 static void venc_invert_vid_out_polarity(struct omap_dss_device *dssdev, 571 bool invert_polarity) 572 { 573 mutex_lock(&venc.venc_lock); 574 575 venc.invert_polarity = invert_polarity; 576 577 mutex_unlock(&venc.venc_lock); 578 } 579 580 static int venc_init_regulator(void) 581 { 582 struct regulator *vdda_dac; 583 584 if (venc.vdda_dac_reg != NULL) 585 return 0; 586 587 if (venc.pdev->dev.of_node) 588 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda"); 589 else 590 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac"); 591 592 if (IS_ERR(vdda_dac)) { 593 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER) 594 DSSERR("can't get VDDA_DAC regulator\n"); 595 return PTR_ERR(vdda_dac); 596 } 597 598 venc.vdda_dac_reg = vdda_dac; 599 600 return 0; 601 } 602 603 static void venc_dump_regs(struct seq_file *s) 604 { 605 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r)) 606 607 if (venc_runtime_get()) 608 return; 609 610 DUMPREG(VENC_F_CONTROL); 611 DUMPREG(VENC_VIDOUT_CTRL); 612 DUMPREG(VENC_SYNC_CTRL); 613 DUMPREG(VENC_LLEN); 614 DUMPREG(VENC_FLENS); 615 DUMPREG(VENC_HFLTR_CTRL); 616 DUMPREG(VENC_CC_CARR_WSS_CARR); 617 DUMPREG(VENC_C_PHASE); 618 DUMPREG(VENC_GAIN_U); 619 DUMPREG(VENC_GAIN_V); 620 DUMPREG(VENC_GAIN_Y); 621 DUMPREG(VENC_BLACK_LEVEL); 622 DUMPREG(VENC_BLANK_LEVEL); 623 DUMPREG(VENC_X_COLOR); 624 DUMPREG(VENC_M_CONTROL); 625 DUMPREG(VENC_BSTAMP_WSS_DATA); 626 DUMPREG(VENC_S_CARR); 627 DUMPREG(VENC_LINE21); 628 DUMPREG(VENC_LN_SEL); 629 DUMPREG(VENC_L21__WC_CTL); 630 DUMPREG(VENC_HTRIGGER_VTRIGGER); 631 DUMPREG(VENC_SAVID__EAVID); 632 DUMPREG(VENC_FLEN__FAL); 633 DUMPREG(VENC_LAL__PHASE_RESET); 634 DUMPREG(VENC_HS_INT_START_STOP_X); 635 DUMPREG(VENC_HS_EXT_START_STOP_X); 636 DUMPREG(VENC_VS_INT_START_X); 637 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y); 638 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X); 639 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y); 640 DUMPREG(VENC_VS_EXT_STOP_Y); 641 DUMPREG(VENC_AVID_START_STOP_X); 642 DUMPREG(VENC_AVID_START_STOP_Y); 643 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y); 644 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X); 645 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y); 646 DUMPREG(VENC_TVDETGP_INT_START_STOP_X); 647 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y); 648 DUMPREG(VENC_GEN_CTRL); 649 DUMPREG(VENC_OUTPUT_CONTROL); 650 DUMPREG(VENC_OUTPUT_TEST); 651 652 venc_runtime_put(); 653 654 #undef DUMPREG 655 } 656 657 static int venc_get_clocks(struct platform_device *pdev) 658 { 659 struct clk *clk; 660 661 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) { 662 clk = devm_clk_get(&pdev->dev, "tv_dac_clk"); 663 if (IS_ERR(clk)) { 664 DSSERR("can't get tv_dac_clk\n"); 665 return PTR_ERR(clk); 666 } 667 } else { 668 clk = NULL; 669 } 670 671 venc.tv_dac_clk = clk; 672 673 return 0; 674 } 675 676 static int venc_connect(struct omap_dss_device *dssdev, 677 struct omap_dss_device *dst) 678 { 679 struct omap_overlay_manager *mgr; 680 int r; 681 682 r = venc_init_regulator(); 683 if (r) 684 return r; 685 686 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); 687 if (!mgr) 688 return -ENODEV; 689 690 r = dss_mgr_connect(mgr, dssdev); 691 if (r) 692 return r; 693 694 r = omapdss_output_set_device(dssdev, dst); 695 if (r) { 696 DSSERR("failed to connect output to new device: %s\n", 697 dst->name); 698 dss_mgr_disconnect(mgr, dssdev); 699 return r; 700 } 701 702 return 0; 703 } 704 705 static void venc_disconnect(struct omap_dss_device *dssdev, 706 struct omap_dss_device *dst) 707 { 708 WARN_ON(dst != dssdev->dst); 709 710 if (dst != dssdev->dst) 711 return; 712 713 omapdss_output_unset_device(dssdev); 714 715 if (dssdev->manager) 716 dss_mgr_disconnect(dssdev->manager, dssdev); 717 } 718 719 static const struct omapdss_atv_ops venc_ops = { 720 .connect = venc_connect, 721 .disconnect = venc_disconnect, 722 723 .enable = venc_display_enable, 724 .disable = venc_display_disable, 725 726 .check_timings = venc_check_timings, 727 .set_timings = venc_set_timings, 728 .get_timings = venc_get_timings, 729 730 .set_type = venc_set_type, 731 .invert_vid_out_polarity = venc_invert_vid_out_polarity, 732 733 .set_wss = venc_set_wss, 734 .get_wss = venc_get_wss, 735 }; 736 737 static void venc_init_output(struct platform_device *pdev) 738 { 739 struct omap_dss_device *out = &venc.output; 740 741 out->dev = &pdev->dev; 742 out->id = OMAP_DSS_OUTPUT_VENC; 743 out->output_type = OMAP_DISPLAY_TYPE_VENC; 744 out->name = "venc.0"; 745 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; 746 out->ops.atv = &venc_ops; 747 out->owner = THIS_MODULE; 748 749 omapdss_register_output(out); 750 } 751 752 static void venc_uninit_output(struct platform_device *pdev) 753 { 754 struct omap_dss_device *out = &venc.output; 755 756 omapdss_unregister_output(out); 757 } 758 759 static int venc_probe_of(struct platform_device *pdev) 760 { 761 struct device_node *node = pdev->dev.of_node; 762 struct device_node *ep; 763 u32 channels; 764 int r; 765 766 ep = omapdss_of_get_first_endpoint(node); 767 if (!ep) 768 return 0; 769 770 venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity"); 771 772 r = of_property_read_u32(ep, "ti,channels", &channels); 773 if (r) { 774 dev_err(&pdev->dev, 775 "failed to read property 'ti,channels': %d\n", r); 776 goto err; 777 } 778 779 switch (channels) { 780 case 1: 781 venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE; 782 break; 783 case 2: 784 venc.type = OMAP_DSS_VENC_TYPE_SVIDEO; 785 break; 786 default: 787 dev_err(&pdev->dev, "bad channel propert '%d'\n", channels); 788 r = -EINVAL; 789 goto err; 790 } 791 792 of_node_put(ep); 793 794 return 0; 795 err: 796 of_node_put(ep); 797 798 return 0; 799 } 800 801 /* VENC HW IP initialisation */ 802 static int venc_bind(struct device *dev, struct device *master, void *data) 803 { 804 struct platform_device *pdev = to_platform_device(dev); 805 u8 rev_id; 806 struct resource *venc_mem; 807 int r; 808 809 venc.pdev = pdev; 810 811 mutex_init(&venc.venc_lock); 812 813 venc.wss_data = 0; 814 815 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0); 816 if (!venc_mem) { 817 DSSERR("can't get IORESOURCE_MEM VENC\n"); 818 return -EINVAL; 819 } 820 821 venc.base = devm_ioremap(&pdev->dev, venc_mem->start, 822 resource_size(venc_mem)); 823 if (!venc.base) { 824 DSSERR("can't ioremap VENC\n"); 825 return -ENOMEM; 826 } 827 828 r = venc_get_clocks(pdev); 829 if (r) 830 return r; 831 832 pm_runtime_enable(&pdev->dev); 833 834 r = venc_runtime_get(); 835 if (r) 836 goto err_runtime_get; 837 838 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); 839 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id); 840 841 venc_runtime_put(); 842 843 if (pdev->dev.of_node) { 844 r = venc_probe_of(pdev); 845 if (r) { 846 DSSERR("Invalid DT data\n"); 847 goto err_probe_of; 848 } 849 } 850 851 dss_debugfs_create_file("venc", venc_dump_regs); 852 853 venc_init_output(pdev); 854 855 return 0; 856 857 err_probe_of: 858 err_runtime_get: 859 pm_runtime_disable(&pdev->dev); 860 return r; 861 } 862 863 static void venc_unbind(struct device *dev, struct device *master, void *data) 864 { 865 struct platform_device *pdev = to_platform_device(dev); 866 867 venc_uninit_output(pdev); 868 869 pm_runtime_disable(&pdev->dev); 870 } 871 872 static const struct component_ops venc_component_ops = { 873 .bind = venc_bind, 874 .unbind = venc_unbind, 875 }; 876 877 static int venc_probe(struct platform_device *pdev) 878 { 879 return component_add(&pdev->dev, &venc_component_ops); 880 } 881 882 static int venc_remove(struct platform_device *pdev) 883 { 884 component_del(&pdev->dev, &venc_component_ops); 885 return 0; 886 } 887 888 static int venc_runtime_suspend(struct device *dev) 889 { 890 if (venc.tv_dac_clk) 891 clk_disable_unprepare(venc.tv_dac_clk); 892 893 dispc_runtime_put(); 894 895 return 0; 896 } 897 898 static int venc_runtime_resume(struct device *dev) 899 { 900 int r; 901 902 r = dispc_runtime_get(); 903 if (r < 0) 904 return r; 905 906 if (venc.tv_dac_clk) 907 clk_prepare_enable(venc.tv_dac_clk); 908 909 return 0; 910 } 911 912 static const struct dev_pm_ops venc_pm_ops = { 913 .runtime_suspend = venc_runtime_suspend, 914 .runtime_resume = venc_runtime_resume, 915 }; 916 917 static const struct of_device_id venc_of_match[] = { 918 { .compatible = "ti,omap2-venc", }, 919 { .compatible = "ti,omap3-venc", }, 920 { .compatible = "ti,omap4-venc", }, 921 {}, 922 }; 923 924 static struct platform_driver omap_venchw_driver = { 925 .probe = venc_probe, 926 .remove = venc_remove, 927 .driver = { 928 .name = "omapdss_venc", 929 .pm = &venc_pm_ops, 930 .of_match_table = venc_of_match, 931 .suppress_bind_attrs = true, 932 }, 933 }; 934 935 int __init venc_init_platform_driver(void) 936 { 937 return platform_driver_register(&omap_venchw_driver); 938 } 939 940 void venc_uninit_platform_driver(void) 941 { 942 platform_driver_unregister(&omap_venchw_driver); 943 } 944