1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 31 #include <video/display_timing.h> 32 #include <video/of_display_timing.h> 33 #include <video/videomode.h> 34 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_device.h> 37 #include <drm/drm_mipi_dsi.h> 38 #include <drm/drm_panel.h> 39 40 /** 41 * @modes: Pointer to array of fixed modes appropriate for this panel. If 42 * only one mode then this can just be the address of this the mode. 43 * NOTE: cannot be used with "timings" and also if this is specified 44 * then you cannot override the mode in the device tree. 45 * @num_modes: Number of elements in modes array. 46 * @timings: Pointer to array of display timings. NOTE: cannot be used with 47 * "modes" and also these will be used to validate a device tree 48 * override if one is present. 49 * @num_timings: Number of elements in timings array. 50 * @bpc: Bits per color. 51 * @size: Structure containing the physical size of this panel. 52 * @delay: Structure containing various delay values for this panel. 53 * @bus_format: See MEDIA_BUS_FMT_... defines. 54 * @bus_flags: See DRM_BUS_FLAG_... defines. 55 */ 56 struct panel_desc { 57 const struct drm_display_mode *modes; 58 unsigned int num_modes; 59 const struct display_timing *timings; 60 unsigned int num_timings; 61 62 unsigned int bpc; 63 64 /** 65 * @width: width (in millimeters) of the panel's active display area 66 * @height: height (in millimeters) of the panel's active display area 67 */ 68 struct { 69 unsigned int width; 70 unsigned int height; 71 } size; 72 73 /** 74 * @prepare: the time (in milliseconds) that it takes for the panel to 75 * become ready and start receiving video data 76 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 77 * Plug Detect isn't used. 78 * @enable: the time (in milliseconds) that it takes for the panel to 79 * display the first valid frame after starting to receive 80 * video data 81 * @disable: the time (in milliseconds) that it takes for the panel to 82 * turn the display off (no content is visible) 83 * @unprepare: the time (in milliseconds) that it takes for the panel 84 * to power itself down completely 85 */ 86 struct { 87 unsigned int prepare; 88 unsigned int hpd_absent_delay; 89 unsigned int enable; 90 unsigned int disable; 91 unsigned int unprepare; 92 } delay; 93 94 u32 bus_format; 95 u32 bus_flags; 96 int connector_type; 97 }; 98 99 struct panel_simple { 100 struct drm_panel base; 101 bool prepared; 102 bool enabled; 103 bool no_hpd; 104 105 const struct panel_desc *desc; 106 107 struct regulator *supply; 108 struct i2c_adapter *ddc; 109 110 struct gpio_desc *enable_gpio; 111 112 struct drm_display_mode override_mode; 113 }; 114 115 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 116 { 117 return container_of(panel, struct panel_simple, base); 118 } 119 120 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 121 struct drm_connector *connector) 122 { 123 struct drm_display_mode *mode; 124 unsigned int i, num = 0; 125 126 for (i = 0; i < panel->desc->num_timings; i++) { 127 const struct display_timing *dt = &panel->desc->timings[i]; 128 struct videomode vm; 129 130 videomode_from_timing(dt, &vm); 131 mode = drm_mode_create(connector->dev); 132 if (!mode) { 133 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 134 dt->hactive.typ, dt->vactive.typ); 135 continue; 136 } 137 138 drm_display_mode_from_videomode(&vm, mode); 139 140 mode->type |= DRM_MODE_TYPE_DRIVER; 141 142 if (panel->desc->num_timings == 1) 143 mode->type |= DRM_MODE_TYPE_PREFERRED; 144 145 drm_mode_probed_add(connector, mode); 146 num++; 147 } 148 149 return num; 150 } 151 152 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 153 struct drm_connector *connector) 154 { 155 struct drm_display_mode *mode; 156 unsigned int i, num = 0; 157 158 for (i = 0; i < panel->desc->num_modes; i++) { 159 const struct drm_display_mode *m = &panel->desc->modes[i]; 160 161 mode = drm_mode_duplicate(connector->dev, m); 162 if (!mode) { 163 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 164 m->hdisplay, m->vdisplay, m->vrefresh); 165 continue; 166 } 167 168 mode->type |= DRM_MODE_TYPE_DRIVER; 169 170 if (panel->desc->num_modes == 1) 171 mode->type |= DRM_MODE_TYPE_PREFERRED; 172 173 drm_mode_set_name(mode); 174 175 drm_mode_probed_add(connector, mode); 176 num++; 177 } 178 179 return num; 180 } 181 182 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 183 struct drm_connector *connector) 184 { 185 struct drm_display_mode *mode; 186 bool has_override = panel->override_mode.type; 187 unsigned int num = 0; 188 189 if (!panel->desc) 190 return 0; 191 192 if (has_override) { 193 mode = drm_mode_duplicate(connector->dev, 194 &panel->override_mode); 195 if (mode) { 196 drm_mode_probed_add(connector, mode); 197 num = 1; 198 } else { 199 dev_err(panel->base.dev, "failed to add override mode\n"); 200 } 201 } 202 203 /* Only add timings if override was not there or failed to validate */ 204 if (num == 0 && panel->desc->num_timings) 205 num = panel_simple_get_timings_modes(panel, connector); 206 207 /* 208 * Only add fixed modes if timings/override added no mode. 209 * 210 * We should only ever have either the display timings specified 211 * or a fixed mode. Anything else is rather bogus. 212 */ 213 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 214 if (num == 0) 215 num = panel_simple_get_display_modes(panel, connector); 216 217 connector->display_info.bpc = panel->desc->bpc; 218 connector->display_info.width_mm = panel->desc->size.width; 219 connector->display_info.height_mm = panel->desc->size.height; 220 if (panel->desc->bus_format) 221 drm_display_info_set_bus_formats(&connector->display_info, 222 &panel->desc->bus_format, 1); 223 connector->display_info.bus_flags = panel->desc->bus_flags; 224 225 return num; 226 } 227 228 static int panel_simple_disable(struct drm_panel *panel) 229 { 230 struct panel_simple *p = to_panel_simple(panel); 231 232 if (!p->enabled) 233 return 0; 234 235 if (p->desc->delay.disable) 236 msleep(p->desc->delay.disable); 237 238 p->enabled = false; 239 240 return 0; 241 } 242 243 static int panel_simple_unprepare(struct drm_panel *panel) 244 { 245 struct panel_simple *p = to_panel_simple(panel); 246 247 if (!p->prepared) 248 return 0; 249 250 gpiod_set_value_cansleep(p->enable_gpio, 0); 251 252 regulator_disable(p->supply); 253 254 if (p->desc->delay.unprepare) 255 msleep(p->desc->delay.unprepare); 256 257 p->prepared = false; 258 259 return 0; 260 } 261 262 static int panel_simple_prepare(struct drm_panel *panel) 263 { 264 struct panel_simple *p = to_panel_simple(panel); 265 unsigned int delay; 266 int err; 267 268 if (p->prepared) 269 return 0; 270 271 err = regulator_enable(p->supply); 272 if (err < 0) { 273 dev_err(panel->dev, "failed to enable supply: %d\n", err); 274 return err; 275 } 276 277 gpiod_set_value_cansleep(p->enable_gpio, 1); 278 279 delay = p->desc->delay.prepare; 280 if (p->no_hpd) 281 delay += p->desc->delay.hpd_absent_delay; 282 if (delay) 283 msleep(delay); 284 285 p->prepared = true; 286 287 return 0; 288 } 289 290 static int panel_simple_enable(struct drm_panel *panel) 291 { 292 struct panel_simple *p = to_panel_simple(panel); 293 294 if (p->enabled) 295 return 0; 296 297 if (p->desc->delay.enable) 298 msleep(p->desc->delay.enable); 299 300 p->enabled = true; 301 302 return 0; 303 } 304 305 static int panel_simple_get_modes(struct drm_panel *panel, 306 struct drm_connector *connector) 307 { 308 struct panel_simple *p = to_panel_simple(panel); 309 int num = 0; 310 311 /* probe EDID if a DDC bus is available */ 312 if (p->ddc) { 313 struct edid *edid = drm_get_edid(connector, p->ddc); 314 315 drm_connector_update_edid_property(connector, edid); 316 if (edid) { 317 num += drm_add_edid_modes(connector, edid); 318 kfree(edid); 319 } 320 } 321 322 /* add hard-coded panel modes */ 323 num += panel_simple_get_non_edid_modes(p, connector); 324 325 return num; 326 } 327 328 static int panel_simple_get_timings(struct drm_panel *panel, 329 unsigned int num_timings, 330 struct display_timing *timings) 331 { 332 struct panel_simple *p = to_panel_simple(panel); 333 unsigned int i; 334 335 if (p->desc->num_timings < num_timings) 336 num_timings = p->desc->num_timings; 337 338 if (timings) 339 for (i = 0; i < num_timings; i++) 340 timings[i] = p->desc->timings[i]; 341 342 return p->desc->num_timings; 343 } 344 345 static const struct drm_panel_funcs panel_simple_funcs = { 346 .disable = panel_simple_disable, 347 .unprepare = panel_simple_unprepare, 348 .prepare = panel_simple_prepare, 349 .enable = panel_simple_enable, 350 .get_modes = panel_simple_get_modes, 351 .get_timings = panel_simple_get_timings, 352 }; 353 354 static struct panel_desc panel_dpi; 355 356 static int panel_dpi_probe(struct device *dev, 357 struct panel_simple *panel) 358 { 359 struct display_timing *timing; 360 const struct device_node *np; 361 struct panel_desc *desc; 362 unsigned int bus_flags; 363 struct videomode vm; 364 int ret; 365 366 np = dev->of_node; 367 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 368 if (!desc) 369 return -ENOMEM; 370 371 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 372 if (!timing) 373 return -ENOMEM; 374 375 ret = of_get_display_timing(np, "panel-timing", timing); 376 if (ret < 0) { 377 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 378 np); 379 return ret; 380 } 381 382 desc->timings = timing; 383 desc->num_timings = 1; 384 385 of_property_read_u32(np, "width-mm", &desc->size.width); 386 of_property_read_u32(np, "height-mm", &desc->size.height); 387 388 /* Extract bus_flags from display_timing */ 389 bus_flags = 0; 390 vm.flags = timing->flags; 391 drm_bus_flags_from_videomode(&vm, &bus_flags); 392 desc->bus_flags = bus_flags; 393 394 /* We do not know the connector for the DT node, so guess it */ 395 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 396 397 panel->desc = desc; 398 399 return 0; 400 } 401 402 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 403 (to_check->field.typ >= bounds->field.min && \ 404 to_check->field.typ <= bounds->field.max) 405 static void panel_simple_parse_panel_timing_node(struct device *dev, 406 struct panel_simple *panel, 407 const struct display_timing *ot) 408 { 409 const struct panel_desc *desc = panel->desc; 410 struct videomode vm; 411 unsigned int i; 412 413 if (WARN_ON(desc->num_modes)) { 414 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 415 return; 416 } 417 if (WARN_ON(!desc->num_timings)) { 418 dev_err(dev, "Reject override mode: no timings specified\n"); 419 return; 420 } 421 422 for (i = 0; i < panel->desc->num_timings; i++) { 423 const struct display_timing *dt = &panel->desc->timings[i]; 424 425 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 426 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 427 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 428 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 429 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 430 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 431 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 432 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 433 continue; 434 435 if (ot->flags != dt->flags) 436 continue; 437 438 videomode_from_timing(ot, &vm); 439 drm_display_mode_from_videomode(&vm, &panel->override_mode); 440 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 441 DRM_MODE_TYPE_PREFERRED; 442 break; 443 } 444 445 if (WARN_ON(!panel->override_mode.type)) 446 dev_err(dev, "Reject override mode: No display_timing found\n"); 447 } 448 449 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 450 { 451 struct panel_simple *panel; 452 struct display_timing dt; 453 struct device_node *ddc; 454 int err; 455 456 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 457 if (!panel) 458 return -ENOMEM; 459 460 panel->enabled = false; 461 panel->prepared = false; 462 panel->desc = desc; 463 464 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 465 466 panel->supply = devm_regulator_get(dev, "power"); 467 if (IS_ERR(panel->supply)) 468 return PTR_ERR(panel->supply); 469 470 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 471 GPIOD_OUT_LOW); 472 if (IS_ERR(panel->enable_gpio)) { 473 err = PTR_ERR(panel->enable_gpio); 474 if (err != -EPROBE_DEFER) 475 dev_err(dev, "failed to request GPIO: %d\n", err); 476 return err; 477 } 478 479 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 480 if (ddc) { 481 panel->ddc = of_find_i2c_adapter_by_node(ddc); 482 of_node_put(ddc); 483 484 if (!panel->ddc) 485 return -EPROBE_DEFER; 486 } 487 488 if (desc == &panel_dpi) { 489 /* Handle the generic panel-dpi binding */ 490 err = panel_dpi_probe(dev, panel); 491 if (err) 492 goto free_ddc; 493 } else { 494 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 495 panel_simple_parse_panel_timing_node(dev, panel, &dt); 496 } 497 498 drm_panel_init(&panel->base, dev, &panel_simple_funcs, 499 desc->connector_type); 500 501 err = drm_panel_of_backlight(&panel->base); 502 if (err) 503 goto free_ddc; 504 505 err = drm_panel_add(&panel->base); 506 if (err < 0) 507 goto free_ddc; 508 509 dev_set_drvdata(dev, panel); 510 511 return 0; 512 513 free_ddc: 514 if (panel->ddc) 515 put_device(&panel->ddc->dev); 516 517 return err; 518 } 519 520 static int panel_simple_remove(struct device *dev) 521 { 522 struct panel_simple *panel = dev_get_drvdata(dev); 523 524 drm_panel_remove(&panel->base); 525 drm_panel_disable(&panel->base); 526 drm_panel_unprepare(&panel->base); 527 528 if (panel->ddc) 529 put_device(&panel->ddc->dev); 530 531 return 0; 532 } 533 534 static void panel_simple_shutdown(struct device *dev) 535 { 536 struct panel_simple *panel = dev_get_drvdata(dev); 537 538 drm_panel_disable(&panel->base); 539 drm_panel_unprepare(&panel->base); 540 } 541 542 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 543 .clock = 9000, 544 .hdisplay = 480, 545 .hsync_start = 480 + 2, 546 .hsync_end = 480 + 2 + 41, 547 .htotal = 480 + 2 + 41 + 2, 548 .vdisplay = 272, 549 .vsync_start = 272 + 2, 550 .vsync_end = 272 + 2 + 10, 551 .vtotal = 272 + 2 + 10 + 2, 552 .vrefresh = 60, 553 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 554 }; 555 556 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 557 .modes = &ire_am_480272h3tmqw_t01h_mode, 558 .num_modes = 1, 559 .bpc = 8, 560 .size = { 561 .width = 105, 562 .height = 67, 563 }, 564 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 565 }; 566 567 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 568 .clock = 33333, 569 .hdisplay = 800, 570 .hsync_start = 800 + 0, 571 .hsync_end = 800 + 0 + 255, 572 .htotal = 800 + 0 + 255 + 0, 573 .vdisplay = 480, 574 .vsync_start = 480 + 2, 575 .vsync_end = 480 + 2 + 45, 576 .vtotal = 480 + 2 + 45 + 0, 577 .vrefresh = 60, 578 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 579 }; 580 581 static const struct panel_desc ampire_am800480r3tmqwa1h = { 582 .modes = &ire_am800480r3tmqwa1h_mode, 583 .num_modes = 1, 584 .bpc = 6, 585 .size = { 586 .width = 152, 587 .height = 91, 588 }, 589 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 590 }; 591 592 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 593 .pixelclock = { 26400000, 33300000, 46800000 }, 594 .hactive = { 800, 800, 800 }, 595 .hfront_porch = { 16, 210, 354 }, 596 .hback_porch = { 45, 36, 6 }, 597 .hsync_len = { 1, 10, 40 }, 598 .vactive = { 480, 480, 480 }, 599 .vfront_porch = { 7, 22, 147 }, 600 .vback_porch = { 22, 13, 3 }, 601 .vsync_len = { 1, 10, 20 }, 602 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 603 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 604 }; 605 606 static const struct panel_desc armadeus_st0700_adapt = { 607 .timings = &santek_st0700i5y_rbslw_f_timing, 608 .num_timings = 1, 609 .bpc = 6, 610 .size = { 611 .width = 154, 612 .height = 86, 613 }, 614 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 615 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 616 }; 617 618 static const struct drm_display_mode auo_b101aw03_mode = { 619 .clock = 51450, 620 .hdisplay = 1024, 621 .hsync_start = 1024 + 156, 622 .hsync_end = 1024 + 156 + 8, 623 .htotal = 1024 + 156 + 8 + 156, 624 .vdisplay = 600, 625 .vsync_start = 600 + 16, 626 .vsync_end = 600 + 16 + 6, 627 .vtotal = 600 + 16 + 6 + 16, 628 .vrefresh = 60, 629 }; 630 631 static const struct panel_desc auo_b101aw03 = { 632 .modes = &auo_b101aw03_mode, 633 .num_modes = 1, 634 .bpc = 6, 635 .size = { 636 .width = 223, 637 .height = 125, 638 }, 639 }; 640 641 static const struct display_timing auo_b101ean01_timing = { 642 .pixelclock = { 65300000, 72500000, 75000000 }, 643 .hactive = { 1280, 1280, 1280 }, 644 .hfront_porch = { 18, 119, 119 }, 645 .hback_porch = { 21, 21, 21 }, 646 .hsync_len = { 32, 32, 32 }, 647 .vactive = { 800, 800, 800 }, 648 .vfront_porch = { 4, 4, 4 }, 649 .vback_porch = { 8, 8, 8 }, 650 .vsync_len = { 18, 20, 20 }, 651 }; 652 653 static const struct panel_desc auo_b101ean01 = { 654 .timings = &auo_b101ean01_timing, 655 .num_timings = 1, 656 .bpc = 6, 657 .size = { 658 .width = 217, 659 .height = 136, 660 }, 661 }; 662 663 static const struct drm_display_mode auo_b101xtn01_mode = { 664 .clock = 72000, 665 .hdisplay = 1366, 666 .hsync_start = 1366 + 20, 667 .hsync_end = 1366 + 20 + 70, 668 .htotal = 1366 + 20 + 70, 669 .vdisplay = 768, 670 .vsync_start = 768 + 14, 671 .vsync_end = 768 + 14 + 42, 672 .vtotal = 768 + 14 + 42, 673 .vrefresh = 60, 674 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 675 }; 676 677 static const struct panel_desc auo_b101xtn01 = { 678 .modes = &auo_b101xtn01_mode, 679 .num_modes = 1, 680 .bpc = 6, 681 .size = { 682 .width = 223, 683 .height = 125, 684 }, 685 }; 686 687 static const struct drm_display_mode auo_b116xak01_mode = { 688 .clock = 69300, 689 .hdisplay = 1366, 690 .hsync_start = 1366 + 48, 691 .hsync_end = 1366 + 48 + 32, 692 .htotal = 1366 + 48 + 32 + 10, 693 .vdisplay = 768, 694 .vsync_start = 768 + 4, 695 .vsync_end = 768 + 4 + 6, 696 .vtotal = 768 + 4 + 6 + 15, 697 .vrefresh = 60, 698 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 699 }; 700 701 static const struct panel_desc auo_b116xak01 = { 702 .modes = &auo_b116xak01_mode, 703 .num_modes = 1, 704 .bpc = 6, 705 .size = { 706 .width = 256, 707 .height = 144, 708 }, 709 .delay = { 710 .hpd_absent_delay = 200, 711 }, 712 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 713 .connector_type = DRM_MODE_CONNECTOR_eDP, 714 }; 715 716 static const struct drm_display_mode auo_b116xw03_mode = { 717 .clock = 70589, 718 .hdisplay = 1366, 719 .hsync_start = 1366 + 40, 720 .hsync_end = 1366 + 40 + 40, 721 .htotal = 1366 + 40 + 40 + 32, 722 .vdisplay = 768, 723 .vsync_start = 768 + 10, 724 .vsync_end = 768 + 10 + 12, 725 .vtotal = 768 + 10 + 12 + 6, 726 .vrefresh = 60, 727 }; 728 729 static const struct panel_desc auo_b116xw03 = { 730 .modes = &auo_b116xw03_mode, 731 .num_modes = 1, 732 .bpc = 6, 733 .size = { 734 .width = 256, 735 .height = 144, 736 }, 737 }; 738 739 static const struct drm_display_mode auo_b133xtn01_mode = { 740 .clock = 69500, 741 .hdisplay = 1366, 742 .hsync_start = 1366 + 48, 743 .hsync_end = 1366 + 48 + 32, 744 .htotal = 1366 + 48 + 32 + 20, 745 .vdisplay = 768, 746 .vsync_start = 768 + 3, 747 .vsync_end = 768 + 3 + 6, 748 .vtotal = 768 + 3 + 6 + 13, 749 .vrefresh = 60, 750 }; 751 752 static const struct panel_desc auo_b133xtn01 = { 753 .modes = &auo_b133xtn01_mode, 754 .num_modes = 1, 755 .bpc = 6, 756 .size = { 757 .width = 293, 758 .height = 165, 759 }, 760 }; 761 762 static const struct drm_display_mode auo_b133htn01_mode = { 763 .clock = 150660, 764 .hdisplay = 1920, 765 .hsync_start = 1920 + 172, 766 .hsync_end = 1920 + 172 + 80, 767 .htotal = 1920 + 172 + 80 + 60, 768 .vdisplay = 1080, 769 .vsync_start = 1080 + 25, 770 .vsync_end = 1080 + 25 + 10, 771 .vtotal = 1080 + 25 + 10 + 10, 772 .vrefresh = 60, 773 }; 774 775 static const struct panel_desc auo_b133htn01 = { 776 .modes = &auo_b133htn01_mode, 777 .num_modes = 1, 778 .bpc = 6, 779 .size = { 780 .width = 293, 781 .height = 165, 782 }, 783 .delay = { 784 .prepare = 105, 785 .enable = 20, 786 .unprepare = 50, 787 }, 788 }; 789 790 static const struct display_timing auo_g070vvn01_timings = { 791 .pixelclock = { 33300000, 34209000, 45000000 }, 792 .hactive = { 800, 800, 800 }, 793 .hfront_porch = { 20, 40, 200 }, 794 .hback_porch = { 87, 40, 1 }, 795 .hsync_len = { 1, 48, 87 }, 796 .vactive = { 480, 480, 480 }, 797 .vfront_porch = { 5, 13, 200 }, 798 .vback_porch = { 31, 31, 29 }, 799 .vsync_len = { 1, 1, 3 }, 800 }; 801 802 static const struct panel_desc auo_g070vvn01 = { 803 .timings = &auo_g070vvn01_timings, 804 .num_timings = 1, 805 .bpc = 8, 806 .size = { 807 .width = 152, 808 .height = 91, 809 }, 810 .delay = { 811 .prepare = 200, 812 .enable = 50, 813 .disable = 50, 814 .unprepare = 1000, 815 }, 816 }; 817 818 static const struct drm_display_mode auo_g101evn010_mode = { 819 .clock = 68930, 820 .hdisplay = 1280, 821 .hsync_start = 1280 + 82, 822 .hsync_end = 1280 + 82 + 2, 823 .htotal = 1280 + 82 + 2 + 84, 824 .vdisplay = 800, 825 .vsync_start = 800 + 8, 826 .vsync_end = 800 + 8 + 2, 827 .vtotal = 800 + 8 + 2 + 6, 828 .vrefresh = 60, 829 }; 830 831 static const struct panel_desc auo_g101evn010 = { 832 .modes = &auo_g101evn010_mode, 833 .num_modes = 1, 834 .bpc = 6, 835 .size = { 836 .width = 216, 837 .height = 135, 838 }, 839 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 840 }; 841 842 static const struct drm_display_mode auo_g104sn02_mode = { 843 .clock = 40000, 844 .hdisplay = 800, 845 .hsync_start = 800 + 40, 846 .hsync_end = 800 + 40 + 216, 847 .htotal = 800 + 40 + 216 + 128, 848 .vdisplay = 600, 849 .vsync_start = 600 + 10, 850 .vsync_end = 600 + 10 + 35, 851 .vtotal = 600 + 10 + 35 + 2, 852 .vrefresh = 60, 853 }; 854 855 static const struct panel_desc auo_g104sn02 = { 856 .modes = &auo_g104sn02_mode, 857 .num_modes = 1, 858 .bpc = 8, 859 .size = { 860 .width = 211, 861 .height = 158, 862 }, 863 }; 864 865 static const struct display_timing auo_g133han01_timings = { 866 .pixelclock = { 134000000, 141200000, 149000000 }, 867 .hactive = { 1920, 1920, 1920 }, 868 .hfront_porch = { 39, 58, 77 }, 869 .hback_porch = { 59, 88, 117 }, 870 .hsync_len = { 28, 42, 56 }, 871 .vactive = { 1080, 1080, 1080 }, 872 .vfront_porch = { 3, 8, 11 }, 873 .vback_porch = { 5, 14, 19 }, 874 .vsync_len = { 4, 14, 19 }, 875 }; 876 877 static const struct panel_desc auo_g133han01 = { 878 .timings = &auo_g133han01_timings, 879 .num_timings = 1, 880 .bpc = 8, 881 .size = { 882 .width = 293, 883 .height = 165, 884 }, 885 .delay = { 886 .prepare = 200, 887 .enable = 50, 888 .disable = 50, 889 .unprepare = 1000, 890 }, 891 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 892 .connector_type = DRM_MODE_CONNECTOR_LVDS, 893 }; 894 895 static const struct display_timing auo_g185han01_timings = { 896 .pixelclock = { 120000000, 144000000, 175000000 }, 897 .hactive = { 1920, 1920, 1920 }, 898 .hfront_porch = { 36, 120, 148 }, 899 .hback_porch = { 24, 88, 108 }, 900 .hsync_len = { 20, 48, 64 }, 901 .vactive = { 1080, 1080, 1080 }, 902 .vfront_porch = { 6, 10, 40 }, 903 .vback_porch = { 2, 5, 20 }, 904 .vsync_len = { 2, 5, 20 }, 905 }; 906 907 static const struct panel_desc auo_g185han01 = { 908 .timings = &auo_g185han01_timings, 909 .num_timings = 1, 910 .bpc = 8, 911 .size = { 912 .width = 409, 913 .height = 230, 914 }, 915 .delay = { 916 .prepare = 50, 917 .enable = 200, 918 .disable = 110, 919 .unprepare = 1000, 920 }, 921 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 922 .connector_type = DRM_MODE_CONNECTOR_LVDS, 923 }; 924 925 static const struct display_timing auo_p320hvn03_timings = { 926 .pixelclock = { 106000000, 148500000, 164000000 }, 927 .hactive = { 1920, 1920, 1920 }, 928 .hfront_porch = { 25, 50, 130 }, 929 .hback_porch = { 25, 50, 130 }, 930 .hsync_len = { 20, 40, 105 }, 931 .vactive = { 1080, 1080, 1080 }, 932 .vfront_porch = { 8, 17, 150 }, 933 .vback_porch = { 8, 17, 150 }, 934 .vsync_len = { 4, 11, 100 }, 935 }; 936 937 static const struct panel_desc auo_p320hvn03 = { 938 .timings = &auo_p320hvn03_timings, 939 .num_timings = 1, 940 .bpc = 8, 941 .size = { 942 .width = 698, 943 .height = 393, 944 }, 945 .delay = { 946 .prepare = 1, 947 .enable = 450, 948 .unprepare = 500, 949 }, 950 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 951 .connector_type = DRM_MODE_CONNECTOR_LVDS, 952 }; 953 954 static const struct drm_display_mode auo_t215hvn01_mode = { 955 .clock = 148800, 956 .hdisplay = 1920, 957 .hsync_start = 1920 + 88, 958 .hsync_end = 1920 + 88 + 44, 959 .htotal = 1920 + 88 + 44 + 148, 960 .vdisplay = 1080, 961 .vsync_start = 1080 + 4, 962 .vsync_end = 1080 + 4 + 5, 963 .vtotal = 1080 + 4 + 5 + 36, 964 .vrefresh = 60, 965 }; 966 967 static const struct panel_desc auo_t215hvn01 = { 968 .modes = &auo_t215hvn01_mode, 969 .num_modes = 1, 970 .bpc = 8, 971 .size = { 972 .width = 430, 973 .height = 270, 974 }, 975 .delay = { 976 .disable = 5, 977 .unprepare = 1000, 978 } 979 }; 980 981 static const struct drm_display_mode avic_tm070ddh03_mode = { 982 .clock = 51200, 983 .hdisplay = 1024, 984 .hsync_start = 1024 + 160, 985 .hsync_end = 1024 + 160 + 4, 986 .htotal = 1024 + 160 + 4 + 156, 987 .vdisplay = 600, 988 .vsync_start = 600 + 17, 989 .vsync_end = 600 + 17 + 1, 990 .vtotal = 600 + 17 + 1 + 17, 991 .vrefresh = 60, 992 }; 993 994 static const struct panel_desc avic_tm070ddh03 = { 995 .modes = &avic_tm070ddh03_mode, 996 .num_modes = 1, 997 .bpc = 8, 998 .size = { 999 .width = 154, 1000 .height = 90, 1001 }, 1002 .delay = { 1003 .prepare = 20, 1004 .enable = 200, 1005 .disable = 200, 1006 }, 1007 }; 1008 1009 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1010 .clock = 30000, 1011 .hdisplay = 800, 1012 .hsync_start = 800 + 40, 1013 .hsync_end = 800 + 40 + 48, 1014 .htotal = 800 + 40 + 48 + 40, 1015 .vdisplay = 480, 1016 .vsync_start = 480 + 13, 1017 .vsync_end = 480 + 13 + 3, 1018 .vtotal = 480 + 13 + 3 + 29, 1019 }; 1020 1021 static const struct panel_desc bananapi_s070wv20_ct16 = { 1022 .modes = &bananapi_s070wv20_ct16_mode, 1023 .num_modes = 1, 1024 .bpc = 6, 1025 .size = { 1026 .width = 154, 1027 .height = 86, 1028 }, 1029 }; 1030 1031 static const struct drm_display_mode boe_hv070wsa_mode = { 1032 .clock = 42105, 1033 .hdisplay = 1024, 1034 .hsync_start = 1024 + 30, 1035 .hsync_end = 1024 + 30 + 30, 1036 .htotal = 1024 + 30 + 30 + 30, 1037 .vdisplay = 600, 1038 .vsync_start = 600 + 10, 1039 .vsync_end = 600 + 10 + 10, 1040 .vtotal = 600 + 10 + 10 + 10, 1041 .vrefresh = 60, 1042 }; 1043 1044 static const struct panel_desc boe_hv070wsa = { 1045 .modes = &boe_hv070wsa_mode, 1046 .num_modes = 1, 1047 .size = { 1048 .width = 154, 1049 .height = 90, 1050 }, 1051 }; 1052 1053 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1054 { 1055 .clock = 71900, 1056 .hdisplay = 1280, 1057 .hsync_start = 1280 + 48, 1058 .hsync_end = 1280 + 48 + 32, 1059 .htotal = 1280 + 48 + 32 + 80, 1060 .vdisplay = 800, 1061 .vsync_start = 800 + 3, 1062 .vsync_end = 800 + 3 + 5, 1063 .vtotal = 800 + 3 + 5 + 24, 1064 .vrefresh = 60, 1065 }, 1066 { 1067 .clock = 57500, 1068 .hdisplay = 1280, 1069 .hsync_start = 1280 + 48, 1070 .hsync_end = 1280 + 48 + 32, 1071 .htotal = 1280 + 48 + 32 + 80, 1072 .vdisplay = 800, 1073 .vsync_start = 800 + 3, 1074 .vsync_end = 800 + 3 + 5, 1075 .vtotal = 800 + 3 + 5 + 24, 1076 .vrefresh = 48, 1077 }, 1078 }; 1079 1080 static const struct panel_desc boe_nv101wxmn51 = { 1081 .modes = boe_nv101wxmn51_modes, 1082 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1083 .bpc = 8, 1084 .size = { 1085 .width = 217, 1086 .height = 136, 1087 }, 1088 .delay = { 1089 .prepare = 210, 1090 .enable = 50, 1091 .unprepare = 160, 1092 }, 1093 }; 1094 1095 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1096 { 1097 .clock = 148500, 1098 .hdisplay = 1920, 1099 .hsync_start = 1920 + 48, 1100 .hsync_end = 1920 + 48 + 32, 1101 .htotal = 2200, 1102 .vdisplay = 1080, 1103 .vsync_start = 1080 + 3, 1104 .vsync_end = 1080 + 3 + 5, 1105 .vtotal = 1125, 1106 .vrefresh = 60, 1107 }, 1108 }; 1109 1110 static const struct panel_desc boe_nv140fhmn49 = { 1111 .modes = boe_nv140fhmn49_modes, 1112 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1113 .bpc = 6, 1114 .size = { 1115 .width = 309, 1116 .height = 174, 1117 }, 1118 .delay = { 1119 .prepare = 210, 1120 .enable = 50, 1121 .unprepare = 160, 1122 }, 1123 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1124 .connector_type = DRM_MODE_CONNECTOR_eDP, 1125 }; 1126 1127 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1128 .clock = 9000, 1129 .hdisplay = 480, 1130 .hsync_start = 480 + 5, 1131 .hsync_end = 480 + 5 + 5, 1132 .htotal = 480 + 5 + 5 + 40, 1133 .vdisplay = 272, 1134 .vsync_start = 272 + 8, 1135 .vsync_end = 272 + 8 + 8, 1136 .vtotal = 272 + 8 + 8 + 8, 1137 .vrefresh = 60, 1138 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1139 }; 1140 1141 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1142 .modes = &cdtech_s043wq26h_ct7_mode, 1143 .num_modes = 1, 1144 .bpc = 8, 1145 .size = { 1146 .width = 95, 1147 .height = 54, 1148 }, 1149 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1150 }; 1151 1152 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1153 .clock = 35000, 1154 .hdisplay = 800, 1155 .hsync_start = 800 + 40, 1156 .hsync_end = 800 + 40 + 40, 1157 .htotal = 800 + 40 + 40 + 48, 1158 .vdisplay = 480, 1159 .vsync_start = 480 + 29, 1160 .vsync_end = 480 + 29 + 13, 1161 .vtotal = 480 + 29 + 13 + 3, 1162 .vrefresh = 60, 1163 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1164 }; 1165 1166 static const struct panel_desc cdtech_s070wv95_ct16 = { 1167 .modes = &cdtech_s070wv95_ct16_mode, 1168 .num_modes = 1, 1169 .bpc = 8, 1170 .size = { 1171 .width = 154, 1172 .height = 85, 1173 }, 1174 }; 1175 1176 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1177 .clock = 66770, 1178 .hdisplay = 800, 1179 .hsync_start = 800 + 49, 1180 .hsync_end = 800 + 49 + 33, 1181 .htotal = 800 + 49 + 33 + 17, 1182 .vdisplay = 1280, 1183 .vsync_start = 1280 + 1, 1184 .vsync_end = 1280 + 1 + 7, 1185 .vtotal = 1280 + 1 + 7 + 15, 1186 .vrefresh = 60, 1187 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1188 }; 1189 1190 static const struct panel_desc chunghwa_claa070wp03xg = { 1191 .modes = &chunghwa_claa070wp03xg_mode, 1192 .num_modes = 1, 1193 .bpc = 6, 1194 .size = { 1195 .width = 94, 1196 .height = 150, 1197 }, 1198 }; 1199 1200 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1201 .clock = 72070, 1202 .hdisplay = 1366, 1203 .hsync_start = 1366 + 58, 1204 .hsync_end = 1366 + 58 + 58, 1205 .htotal = 1366 + 58 + 58 + 58, 1206 .vdisplay = 768, 1207 .vsync_start = 768 + 4, 1208 .vsync_end = 768 + 4 + 4, 1209 .vtotal = 768 + 4 + 4 + 4, 1210 .vrefresh = 60, 1211 }; 1212 1213 static const struct panel_desc chunghwa_claa101wa01a = { 1214 .modes = &chunghwa_claa101wa01a_mode, 1215 .num_modes = 1, 1216 .bpc = 6, 1217 .size = { 1218 .width = 220, 1219 .height = 120, 1220 }, 1221 }; 1222 1223 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1224 .clock = 69300, 1225 .hdisplay = 1366, 1226 .hsync_start = 1366 + 48, 1227 .hsync_end = 1366 + 48 + 32, 1228 .htotal = 1366 + 48 + 32 + 20, 1229 .vdisplay = 768, 1230 .vsync_start = 768 + 16, 1231 .vsync_end = 768 + 16 + 8, 1232 .vtotal = 768 + 16 + 8 + 16, 1233 .vrefresh = 60, 1234 }; 1235 1236 static const struct panel_desc chunghwa_claa101wb01 = { 1237 .modes = &chunghwa_claa101wb01_mode, 1238 .num_modes = 1, 1239 .bpc = 6, 1240 .size = { 1241 .width = 223, 1242 .height = 125, 1243 }, 1244 }; 1245 1246 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1247 .clock = 33260, 1248 .hdisplay = 800, 1249 .hsync_start = 800 + 40, 1250 .hsync_end = 800 + 40 + 128, 1251 .htotal = 800 + 40 + 128 + 88, 1252 .vdisplay = 480, 1253 .vsync_start = 480 + 10, 1254 .vsync_end = 480 + 10 + 2, 1255 .vtotal = 480 + 10 + 2 + 33, 1256 .vrefresh = 60, 1257 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1258 }; 1259 1260 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1261 .modes = &dataimage_scf0700c48ggu18_mode, 1262 .num_modes = 1, 1263 .bpc = 8, 1264 .size = { 1265 .width = 152, 1266 .height = 91, 1267 }, 1268 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1269 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1270 }; 1271 1272 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1273 .pixelclock = { 45000000, 51200000, 57000000 }, 1274 .hactive = { 1024, 1024, 1024 }, 1275 .hfront_porch = { 100, 106, 113 }, 1276 .hback_porch = { 100, 106, 113 }, 1277 .hsync_len = { 100, 108, 114 }, 1278 .vactive = { 600, 600, 600 }, 1279 .vfront_porch = { 8, 11, 15 }, 1280 .vback_porch = { 8, 11, 15 }, 1281 .vsync_len = { 9, 13, 15 }, 1282 .flags = DISPLAY_FLAGS_DE_HIGH, 1283 }; 1284 1285 static const struct panel_desc dlc_dlc0700yzg_1 = { 1286 .timings = &dlc_dlc0700yzg_1_timing, 1287 .num_timings = 1, 1288 .bpc = 6, 1289 .size = { 1290 .width = 154, 1291 .height = 86, 1292 }, 1293 .delay = { 1294 .prepare = 30, 1295 .enable = 200, 1296 .disable = 200, 1297 }, 1298 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1299 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1300 }; 1301 1302 static const struct display_timing dlc_dlc1010gig_timing = { 1303 .pixelclock = { 68900000, 71100000, 73400000 }, 1304 .hactive = { 1280, 1280, 1280 }, 1305 .hfront_porch = { 43, 53, 63 }, 1306 .hback_porch = { 43, 53, 63 }, 1307 .hsync_len = { 44, 54, 64 }, 1308 .vactive = { 800, 800, 800 }, 1309 .vfront_porch = { 5, 8, 11 }, 1310 .vback_porch = { 5, 8, 11 }, 1311 .vsync_len = { 5, 7, 11 }, 1312 .flags = DISPLAY_FLAGS_DE_HIGH, 1313 }; 1314 1315 static const struct panel_desc dlc_dlc1010gig = { 1316 .timings = &dlc_dlc1010gig_timing, 1317 .num_timings = 1, 1318 .bpc = 8, 1319 .size = { 1320 .width = 216, 1321 .height = 135, 1322 }, 1323 .delay = { 1324 .prepare = 60, 1325 .enable = 150, 1326 .disable = 100, 1327 .unprepare = 60, 1328 }, 1329 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1330 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1331 }; 1332 1333 static const struct drm_display_mode edt_et035012dm6_mode = { 1334 .clock = 6500, 1335 .hdisplay = 320, 1336 .hsync_start = 320 + 20, 1337 .hsync_end = 320 + 20 + 30, 1338 .htotal = 320 + 20 + 68, 1339 .vdisplay = 240, 1340 .vsync_start = 240 + 4, 1341 .vsync_end = 240 + 4 + 4, 1342 .vtotal = 240 + 4 + 4 + 14, 1343 .vrefresh = 60, 1344 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1345 }; 1346 1347 static const struct panel_desc edt_et035012dm6 = { 1348 .modes = &edt_et035012dm6_mode, 1349 .num_modes = 1, 1350 .bpc = 8, 1351 .size = { 1352 .width = 70, 1353 .height = 52, 1354 }, 1355 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1356 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1357 }; 1358 1359 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1360 .clock = 10870, 1361 .hdisplay = 480, 1362 .hsync_start = 480 + 8, 1363 .hsync_end = 480 + 8 + 4, 1364 .htotal = 480 + 8 + 4 + 41, 1365 1366 /* 1367 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1368 * fb_align 1369 */ 1370 1371 .vdisplay = 288, 1372 .vsync_start = 288 + 2, 1373 .vsync_end = 288 + 2 + 4, 1374 .vtotal = 288 + 2 + 4 + 10, 1375 .vrefresh = 60, 1376 }; 1377 1378 static const struct panel_desc edt_etm043080dh6gp = { 1379 .modes = &edt_etm043080dh6gp_mode, 1380 .num_modes = 1, 1381 .bpc = 8, 1382 .size = { 1383 .width = 100, 1384 .height = 65, 1385 }, 1386 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1387 .connector_type = DRM_MODE_CONNECTOR_DPI, 1388 }; 1389 1390 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1391 .clock = 9000, 1392 .hdisplay = 480, 1393 .hsync_start = 480 + 2, 1394 .hsync_end = 480 + 2 + 41, 1395 .htotal = 480 + 2 + 41 + 2, 1396 .vdisplay = 272, 1397 .vsync_start = 272 + 2, 1398 .vsync_end = 272 + 2 + 10, 1399 .vtotal = 272 + 2 + 10 + 2, 1400 .vrefresh = 60, 1401 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1402 }; 1403 1404 static const struct panel_desc edt_etm0430g0dh6 = { 1405 .modes = &edt_etm0430g0dh6_mode, 1406 .num_modes = 1, 1407 .bpc = 6, 1408 .size = { 1409 .width = 95, 1410 .height = 54, 1411 }, 1412 }; 1413 1414 static const struct drm_display_mode edt_et057090dhu_mode = { 1415 .clock = 25175, 1416 .hdisplay = 640, 1417 .hsync_start = 640 + 16, 1418 .hsync_end = 640 + 16 + 30, 1419 .htotal = 640 + 16 + 30 + 114, 1420 .vdisplay = 480, 1421 .vsync_start = 480 + 10, 1422 .vsync_end = 480 + 10 + 3, 1423 .vtotal = 480 + 10 + 3 + 32, 1424 .vrefresh = 60, 1425 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1426 }; 1427 1428 static const struct panel_desc edt_et057090dhu = { 1429 .modes = &edt_et057090dhu_mode, 1430 .num_modes = 1, 1431 .bpc = 6, 1432 .size = { 1433 .width = 115, 1434 .height = 86, 1435 }, 1436 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1437 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1438 }; 1439 1440 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1441 .clock = 33260, 1442 .hdisplay = 800, 1443 .hsync_start = 800 + 40, 1444 .hsync_end = 800 + 40 + 128, 1445 .htotal = 800 + 40 + 128 + 88, 1446 .vdisplay = 480, 1447 .vsync_start = 480 + 10, 1448 .vsync_end = 480 + 10 + 2, 1449 .vtotal = 480 + 10 + 2 + 33, 1450 .vrefresh = 60, 1451 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1452 }; 1453 1454 static const struct panel_desc edt_etm0700g0dh6 = { 1455 .modes = &edt_etm0700g0dh6_mode, 1456 .num_modes = 1, 1457 .bpc = 6, 1458 .size = { 1459 .width = 152, 1460 .height = 91, 1461 }, 1462 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1463 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1464 }; 1465 1466 static const struct panel_desc edt_etm0700g0bdh6 = { 1467 .modes = &edt_etm0700g0dh6_mode, 1468 .num_modes = 1, 1469 .bpc = 6, 1470 .size = { 1471 .width = 152, 1472 .height = 91, 1473 }, 1474 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1475 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1476 }; 1477 1478 static const struct display_timing evervision_vgg804821_timing = { 1479 .pixelclock = { 27600000, 33300000, 50000000 }, 1480 .hactive = { 800, 800, 800 }, 1481 .hfront_porch = { 40, 66, 70 }, 1482 .hback_porch = { 40, 67, 70 }, 1483 .hsync_len = { 40, 67, 70 }, 1484 .vactive = { 480, 480, 480 }, 1485 .vfront_porch = { 6, 10, 10 }, 1486 .vback_porch = { 7, 11, 11 }, 1487 .vsync_len = { 7, 11, 11 }, 1488 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1489 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1490 DISPLAY_FLAGS_SYNC_NEGEDGE, 1491 }; 1492 1493 static const struct panel_desc evervision_vgg804821 = { 1494 .timings = &evervision_vgg804821_timing, 1495 .num_timings = 1, 1496 .bpc = 8, 1497 .size = { 1498 .width = 108, 1499 .height = 64, 1500 }, 1501 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1502 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1503 }; 1504 1505 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1506 .clock = 32260, 1507 .hdisplay = 800, 1508 .hsync_start = 800 + 168, 1509 .hsync_end = 800 + 168 + 64, 1510 .htotal = 800 + 168 + 64 + 88, 1511 .vdisplay = 480, 1512 .vsync_start = 480 + 37, 1513 .vsync_end = 480 + 37 + 2, 1514 .vtotal = 480 + 37 + 2 + 8, 1515 .vrefresh = 60, 1516 }; 1517 1518 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1519 .modes = &foxlink_fl500wvr00_a0t_mode, 1520 .num_modes = 1, 1521 .bpc = 8, 1522 .size = { 1523 .width = 108, 1524 .height = 65, 1525 }, 1526 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1527 }; 1528 1529 static const struct drm_display_mode frida_frd350h54004_mode = { 1530 .clock = 6000, 1531 .hdisplay = 320, 1532 .hsync_start = 320 + 44, 1533 .hsync_end = 320 + 44 + 16, 1534 .htotal = 320 + 44 + 16 + 20, 1535 .vdisplay = 240, 1536 .vsync_start = 240 + 2, 1537 .vsync_end = 240 + 2 + 6, 1538 .vtotal = 240 + 2 + 6 + 2, 1539 .vrefresh = 60, 1540 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1541 }; 1542 1543 static const struct panel_desc frida_frd350h54004 = { 1544 .modes = &frida_frd350h54004_mode, 1545 .num_modes = 1, 1546 .bpc = 8, 1547 .size = { 1548 .width = 77, 1549 .height = 64, 1550 }, 1551 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1552 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1553 .connector_type = DRM_MODE_CONNECTOR_DPI, 1554 }; 1555 1556 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1557 .clock = 67185, 1558 .hdisplay = 800, 1559 .hsync_start = 800 + 20, 1560 .hsync_end = 800 + 20 + 24, 1561 .htotal = 800 + 20 + 24 + 20, 1562 .vdisplay = 1280, 1563 .vsync_start = 1280 + 4, 1564 .vsync_end = 1280 + 4 + 8, 1565 .vtotal = 1280 + 4 + 8 + 4, 1566 .vrefresh = 60, 1567 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1568 }; 1569 1570 static const struct panel_desc friendlyarm_hd702e = { 1571 .modes = &friendlyarm_hd702e_mode, 1572 .num_modes = 1, 1573 .size = { 1574 .width = 94, 1575 .height = 151, 1576 }, 1577 }; 1578 1579 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1580 .clock = 9000, 1581 .hdisplay = 480, 1582 .hsync_start = 480 + 5, 1583 .hsync_end = 480 + 5 + 1, 1584 .htotal = 480 + 5 + 1 + 40, 1585 .vdisplay = 272, 1586 .vsync_start = 272 + 8, 1587 .vsync_end = 272 + 8 + 1, 1588 .vtotal = 272 + 8 + 1 + 8, 1589 .vrefresh = 60, 1590 }; 1591 1592 static const struct panel_desc giantplus_gpg482739qs5 = { 1593 .modes = &giantplus_gpg482739qs5_mode, 1594 .num_modes = 1, 1595 .bpc = 8, 1596 .size = { 1597 .width = 95, 1598 .height = 54, 1599 }, 1600 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1601 }; 1602 1603 static const struct display_timing giantplus_gpm940b0_timing = { 1604 .pixelclock = { 13500000, 27000000, 27500000 }, 1605 .hactive = { 320, 320, 320 }, 1606 .hfront_porch = { 14, 686, 718 }, 1607 .hback_porch = { 50, 70, 255 }, 1608 .hsync_len = { 1, 1, 1 }, 1609 .vactive = { 240, 240, 240 }, 1610 .vfront_porch = { 1, 1, 179 }, 1611 .vback_porch = { 1, 21, 31 }, 1612 .vsync_len = { 1, 1, 6 }, 1613 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1614 }; 1615 1616 static const struct panel_desc giantplus_gpm940b0 = { 1617 .timings = &giantplus_gpm940b0_timing, 1618 .num_timings = 1, 1619 .bpc = 8, 1620 .size = { 1621 .width = 60, 1622 .height = 45, 1623 }, 1624 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1625 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1626 }; 1627 1628 static const struct display_timing hannstar_hsd070pww1_timing = { 1629 .pixelclock = { 64300000, 71100000, 82000000 }, 1630 .hactive = { 1280, 1280, 1280 }, 1631 .hfront_porch = { 1, 1, 10 }, 1632 .hback_porch = { 1, 1, 10 }, 1633 /* 1634 * According to the data sheet, the minimum horizontal blanking interval 1635 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1636 * minimum working horizontal blanking interval to be 60 clocks. 1637 */ 1638 .hsync_len = { 58, 158, 661 }, 1639 .vactive = { 800, 800, 800 }, 1640 .vfront_porch = { 1, 1, 10 }, 1641 .vback_porch = { 1, 1, 10 }, 1642 .vsync_len = { 1, 21, 203 }, 1643 .flags = DISPLAY_FLAGS_DE_HIGH, 1644 }; 1645 1646 static const struct panel_desc hannstar_hsd070pww1 = { 1647 .timings = &hannstar_hsd070pww1_timing, 1648 .num_timings = 1, 1649 .bpc = 6, 1650 .size = { 1651 .width = 151, 1652 .height = 94, 1653 }, 1654 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1655 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1656 }; 1657 1658 static const struct display_timing hannstar_hsd100pxn1_timing = { 1659 .pixelclock = { 55000000, 65000000, 75000000 }, 1660 .hactive = { 1024, 1024, 1024 }, 1661 .hfront_porch = { 40, 40, 40 }, 1662 .hback_porch = { 220, 220, 220 }, 1663 .hsync_len = { 20, 60, 100 }, 1664 .vactive = { 768, 768, 768 }, 1665 .vfront_porch = { 7, 7, 7 }, 1666 .vback_porch = { 21, 21, 21 }, 1667 .vsync_len = { 10, 10, 10 }, 1668 .flags = DISPLAY_FLAGS_DE_HIGH, 1669 }; 1670 1671 static const struct panel_desc hannstar_hsd100pxn1 = { 1672 .timings = &hannstar_hsd100pxn1_timing, 1673 .num_timings = 1, 1674 .bpc = 6, 1675 .size = { 1676 .width = 203, 1677 .height = 152, 1678 }, 1679 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1680 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1681 }; 1682 1683 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1684 .clock = 33333, 1685 .hdisplay = 800, 1686 .hsync_start = 800 + 85, 1687 .hsync_end = 800 + 85 + 86, 1688 .htotal = 800 + 85 + 86 + 85, 1689 .vdisplay = 480, 1690 .vsync_start = 480 + 16, 1691 .vsync_end = 480 + 16 + 13, 1692 .vtotal = 480 + 16 + 13 + 16, 1693 .vrefresh = 60, 1694 }; 1695 1696 static const struct panel_desc hitachi_tx23d38vm0caa = { 1697 .modes = &hitachi_tx23d38vm0caa_mode, 1698 .num_modes = 1, 1699 .bpc = 6, 1700 .size = { 1701 .width = 195, 1702 .height = 117, 1703 }, 1704 .delay = { 1705 .enable = 160, 1706 .disable = 160, 1707 }, 1708 }; 1709 1710 static const struct drm_display_mode innolux_at043tn24_mode = { 1711 .clock = 9000, 1712 .hdisplay = 480, 1713 .hsync_start = 480 + 2, 1714 .hsync_end = 480 + 2 + 41, 1715 .htotal = 480 + 2 + 41 + 2, 1716 .vdisplay = 272, 1717 .vsync_start = 272 + 2, 1718 .vsync_end = 272 + 2 + 10, 1719 .vtotal = 272 + 2 + 10 + 2, 1720 .vrefresh = 60, 1721 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1722 }; 1723 1724 static const struct panel_desc innolux_at043tn24 = { 1725 .modes = &innolux_at043tn24_mode, 1726 .num_modes = 1, 1727 .bpc = 8, 1728 .size = { 1729 .width = 95, 1730 .height = 54, 1731 }, 1732 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1733 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1734 }; 1735 1736 static const struct drm_display_mode innolux_at070tn92_mode = { 1737 .clock = 33333, 1738 .hdisplay = 800, 1739 .hsync_start = 800 + 210, 1740 .hsync_end = 800 + 210 + 20, 1741 .htotal = 800 + 210 + 20 + 46, 1742 .vdisplay = 480, 1743 .vsync_start = 480 + 22, 1744 .vsync_end = 480 + 22 + 10, 1745 .vtotal = 480 + 22 + 23 + 10, 1746 .vrefresh = 60, 1747 }; 1748 1749 static const struct panel_desc innolux_at070tn92 = { 1750 .modes = &innolux_at070tn92_mode, 1751 .num_modes = 1, 1752 .size = { 1753 .width = 154, 1754 .height = 86, 1755 }, 1756 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1757 }; 1758 1759 static const struct display_timing innolux_g070y2_l01_timing = { 1760 .pixelclock = { 28000000, 29500000, 32000000 }, 1761 .hactive = { 800, 800, 800 }, 1762 .hfront_porch = { 61, 91, 141 }, 1763 .hback_porch = { 60, 90, 140 }, 1764 .hsync_len = { 12, 12, 12 }, 1765 .vactive = { 480, 480, 480 }, 1766 .vfront_porch = { 4, 9, 30 }, 1767 .vback_porch = { 4, 8, 28 }, 1768 .vsync_len = { 2, 2, 2 }, 1769 .flags = DISPLAY_FLAGS_DE_HIGH, 1770 }; 1771 1772 static const struct panel_desc innolux_g070y2_l01 = { 1773 .timings = &innolux_g070y2_l01_timing, 1774 .num_timings = 1, 1775 .bpc = 6, 1776 .size = { 1777 .width = 152, 1778 .height = 91, 1779 }, 1780 .delay = { 1781 .prepare = 10, 1782 .enable = 100, 1783 .disable = 100, 1784 .unprepare = 800, 1785 }, 1786 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1787 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1788 }; 1789 1790 static const struct display_timing innolux_g101ice_l01_timing = { 1791 .pixelclock = { 60400000, 71100000, 74700000 }, 1792 .hactive = { 1280, 1280, 1280 }, 1793 .hfront_porch = { 41, 80, 100 }, 1794 .hback_porch = { 40, 79, 99 }, 1795 .hsync_len = { 1, 1, 1 }, 1796 .vactive = { 800, 800, 800 }, 1797 .vfront_porch = { 5, 11, 14 }, 1798 .vback_porch = { 4, 11, 14 }, 1799 .vsync_len = { 1, 1, 1 }, 1800 .flags = DISPLAY_FLAGS_DE_HIGH, 1801 }; 1802 1803 static const struct panel_desc innolux_g101ice_l01 = { 1804 .timings = &innolux_g101ice_l01_timing, 1805 .num_timings = 1, 1806 .bpc = 8, 1807 .size = { 1808 .width = 217, 1809 .height = 135, 1810 }, 1811 .delay = { 1812 .enable = 200, 1813 .disable = 200, 1814 }, 1815 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1816 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1817 }; 1818 1819 static const struct display_timing innolux_g121i1_l01_timing = { 1820 .pixelclock = { 67450000, 71000000, 74550000 }, 1821 .hactive = { 1280, 1280, 1280 }, 1822 .hfront_porch = { 40, 80, 160 }, 1823 .hback_porch = { 39, 79, 159 }, 1824 .hsync_len = { 1, 1, 1 }, 1825 .vactive = { 800, 800, 800 }, 1826 .vfront_porch = { 5, 11, 100 }, 1827 .vback_porch = { 4, 11, 99 }, 1828 .vsync_len = { 1, 1, 1 }, 1829 }; 1830 1831 static const struct panel_desc innolux_g121i1_l01 = { 1832 .timings = &innolux_g121i1_l01_timing, 1833 .num_timings = 1, 1834 .bpc = 6, 1835 .size = { 1836 .width = 261, 1837 .height = 163, 1838 }, 1839 .delay = { 1840 .enable = 200, 1841 .disable = 20, 1842 }, 1843 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1844 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1845 }; 1846 1847 static const struct drm_display_mode innolux_g121x1_l03_mode = { 1848 .clock = 65000, 1849 .hdisplay = 1024, 1850 .hsync_start = 1024 + 0, 1851 .hsync_end = 1024 + 1, 1852 .htotal = 1024 + 0 + 1 + 320, 1853 .vdisplay = 768, 1854 .vsync_start = 768 + 38, 1855 .vsync_end = 768 + 38 + 1, 1856 .vtotal = 768 + 38 + 1 + 0, 1857 .vrefresh = 60, 1858 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1859 }; 1860 1861 static const struct panel_desc innolux_g121x1_l03 = { 1862 .modes = &innolux_g121x1_l03_mode, 1863 .num_modes = 1, 1864 .bpc = 6, 1865 .size = { 1866 .width = 246, 1867 .height = 185, 1868 }, 1869 .delay = { 1870 .enable = 200, 1871 .unprepare = 200, 1872 .disable = 400, 1873 }, 1874 }; 1875 1876 /* 1877 * Datasheet specifies that at 60 Hz refresh rate: 1878 * - total horizontal time: { 1506, 1592, 1716 } 1879 * - total vertical time: { 788, 800, 868 } 1880 * 1881 * ...but doesn't go into exactly how that should be split into a front 1882 * porch, back porch, or sync length. For now we'll leave a single setting 1883 * here which allows a bit of tweaking of the pixel clock at the expense of 1884 * refresh rate. 1885 */ 1886 static const struct display_timing innolux_n116bge_timing = { 1887 .pixelclock = { 72600000, 76420000, 80240000 }, 1888 .hactive = { 1366, 1366, 1366 }, 1889 .hfront_porch = { 136, 136, 136 }, 1890 .hback_porch = { 60, 60, 60 }, 1891 .hsync_len = { 30, 30, 30 }, 1892 .vactive = { 768, 768, 768 }, 1893 .vfront_porch = { 8, 8, 8 }, 1894 .vback_porch = { 12, 12, 12 }, 1895 .vsync_len = { 12, 12, 12 }, 1896 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 1897 }; 1898 1899 static const struct panel_desc innolux_n116bge = { 1900 .timings = &innolux_n116bge_timing, 1901 .num_timings = 1, 1902 .bpc = 6, 1903 .size = { 1904 .width = 256, 1905 .height = 144, 1906 }, 1907 }; 1908 1909 static const struct drm_display_mode innolux_n156bge_l21_mode = { 1910 .clock = 69300, 1911 .hdisplay = 1366, 1912 .hsync_start = 1366 + 16, 1913 .hsync_end = 1366 + 16 + 34, 1914 .htotal = 1366 + 16 + 34 + 50, 1915 .vdisplay = 768, 1916 .vsync_start = 768 + 2, 1917 .vsync_end = 768 + 2 + 6, 1918 .vtotal = 768 + 2 + 6 + 12, 1919 .vrefresh = 60, 1920 }; 1921 1922 static const struct panel_desc innolux_n156bge_l21 = { 1923 .modes = &innolux_n156bge_l21_mode, 1924 .num_modes = 1, 1925 .bpc = 6, 1926 .size = { 1927 .width = 344, 1928 .height = 193, 1929 }, 1930 }; 1931 1932 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 1933 .clock = 206016, 1934 .hdisplay = 2160, 1935 .hsync_start = 2160 + 48, 1936 .hsync_end = 2160 + 48 + 32, 1937 .htotal = 2160 + 48 + 32 + 80, 1938 .vdisplay = 1440, 1939 .vsync_start = 1440 + 3, 1940 .vsync_end = 1440 + 3 + 10, 1941 .vtotal = 1440 + 3 + 10 + 27, 1942 .vrefresh = 60, 1943 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1944 }; 1945 1946 static const struct panel_desc innolux_p120zdg_bf1 = { 1947 .modes = &innolux_p120zdg_bf1_mode, 1948 .num_modes = 1, 1949 .bpc = 8, 1950 .size = { 1951 .width = 254, 1952 .height = 169, 1953 }, 1954 .delay = { 1955 .hpd_absent_delay = 200, 1956 .unprepare = 500, 1957 }, 1958 }; 1959 1960 static const struct drm_display_mode innolux_zj070na_01p_mode = { 1961 .clock = 51501, 1962 .hdisplay = 1024, 1963 .hsync_start = 1024 + 128, 1964 .hsync_end = 1024 + 128 + 64, 1965 .htotal = 1024 + 128 + 64 + 128, 1966 .vdisplay = 600, 1967 .vsync_start = 600 + 16, 1968 .vsync_end = 600 + 16 + 4, 1969 .vtotal = 600 + 16 + 4 + 16, 1970 .vrefresh = 60, 1971 }; 1972 1973 static const struct panel_desc innolux_zj070na_01p = { 1974 .modes = &innolux_zj070na_01p_mode, 1975 .num_modes = 1, 1976 .bpc = 6, 1977 .size = { 1978 .width = 154, 1979 .height = 90, 1980 }, 1981 }; 1982 1983 static const struct display_timing koe_tx14d24vm1bpa_timing = { 1984 .pixelclock = { 5580000, 5850000, 6200000 }, 1985 .hactive = { 320, 320, 320 }, 1986 .hfront_porch = { 30, 30, 30 }, 1987 .hback_porch = { 30, 30, 30 }, 1988 .hsync_len = { 1, 5, 17 }, 1989 .vactive = { 240, 240, 240 }, 1990 .vfront_porch = { 6, 6, 6 }, 1991 .vback_porch = { 5, 5, 5 }, 1992 .vsync_len = { 1, 2, 11 }, 1993 .flags = DISPLAY_FLAGS_DE_HIGH, 1994 }; 1995 1996 static const struct panel_desc koe_tx14d24vm1bpa = { 1997 .timings = &koe_tx14d24vm1bpa_timing, 1998 .num_timings = 1, 1999 .bpc = 6, 2000 .size = { 2001 .width = 115, 2002 .height = 86, 2003 }, 2004 }; 2005 2006 static const struct display_timing koe_tx31d200vm0baa_timing = { 2007 .pixelclock = { 39600000, 43200000, 48000000 }, 2008 .hactive = { 1280, 1280, 1280 }, 2009 .hfront_porch = { 16, 36, 56 }, 2010 .hback_porch = { 16, 36, 56 }, 2011 .hsync_len = { 8, 8, 8 }, 2012 .vactive = { 480, 480, 480 }, 2013 .vfront_porch = { 6, 21, 33 }, 2014 .vback_porch = { 6, 21, 33 }, 2015 .vsync_len = { 8, 8, 8 }, 2016 .flags = DISPLAY_FLAGS_DE_HIGH, 2017 }; 2018 2019 static const struct panel_desc koe_tx31d200vm0baa = { 2020 .timings = &koe_tx31d200vm0baa_timing, 2021 .num_timings = 1, 2022 .bpc = 6, 2023 .size = { 2024 .width = 292, 2025 .height = 109, 2026 }, 2027 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2028 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2029 }; 2030 2031 static const struct display_timing kyo_tcg121xglp_timing = { 2032 .pixelclock = { 52000000, 65000000, 71000000 }, 2033 .hactive = { 1024, 1024, 1024 }, 2034 .hfront_porch = { 2, 2, 2 }, 2035 .hback_porch = { 2, 2, 2 }, 2036 .hsync_len = { 86, 124, 244 }, 2037 .vactive = { 768, 768, 768 }, 2038 .vfront_porch = { 2, 2, 2 }, 2039 .vback_porch = { 2, 2, 2 }, 2040 .vsync_len = { 6, 34, 73 }, 2041 .flags = DISPLAY_FLAGS_DE_HIGH, 2042 }; 2043 2044 static const struct panel_desc kyo_tcg121xglp = { 2045 .timings = &kyo_tcg121xglp_timing, 2046 .num_timings = 1, 2047 .bpc = 8, 2048 .size = { 2049 .width = 246, 2050 .height = 184, 2051 }, 2052 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2053 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2054 }; 2055 2056 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2057 .clock = 7000, 2058 .hdisplay = 320, 2059 .hsync_start = 320 + 20, 2060 .hsync_end = 320 + 20 + 30, 2061 .htotal = 320 + 20 + 30 + 38, 2062 .vdisplay = 240, 2063 .vsync_start = 240 + 4, 2064 .vsync_end = 240 + 4 + 3, 2065 .vtotal = 240 + 4 + 3 + 15, 2066 .vrefresh = 60, 2067 }; 2068 2069 static const struct panel_desc lemaker_bl035_rgb_002 = { 2070 .modes = &lemaker_bl035_rgb_002_mode, 2071 .num_modes = 1, 2072 .size = { 2073 .width = 70, 2074 .height = 52, 2075 }, 2076 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2077 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2078 }; 2079 2080 static const struct drm_display_mode lg_lb070wv8_mode = { 2081 .clock = 33246, 2082 .hdisplay = 800, 2083 .hsync_start = 800 + 88, 2084 .hsync_end = 800 + 88 + 80, 2085 .htotal = 800 + 88 + 80 + 88, 2086 .vdisplay = 480, 2087 .vsync_start = 480 + 10, 2088 .vsync_end = 480 + 10 + 25, 2089 .vtotal = 480 + 10 + 25 + 10, 2090 .vrefresh = 60, 2091 }; 2092 2093 static const struct panel_desc lg_lb070wv8 = { 2094 .modes = &lg_lb070wv8_mode, 2095 .num_modes = 1, 2096 .bpc = 16, 2097 .size = { 2098 .width = 151, 2099 .height = 91, 2100 }, 2101 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2102 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2103 }; 2104 2105 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2106 .clock = 200000, 2107 .hdisplay = 1536, 2108 .hsync_start = 1536 + 12, 2109 .hsync_end = 1536 + 12 + 16, 2110 .htotal = 1536 + 12 + 16 + 48, 2111 .vdisplay = 2048, 2112 .vsync_start = 2048 + 8, 2113 .vsync_end = 2048 + 8 + 4, 2114 .vtotal = 2048 + 8 + 4 + 8, 2115 .vrefresh = 60, 2116 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2117 }; 2118 2119 static const struct panel_desc lg_lp079qx1_sp0v = { 2120 .modes = &lg_lp079qx1_sp0v_mode, 2121 .num_modes = 1, 2122 .size = { 2123 .width = 129, 2124 .height = 171, 2125 }, 2126 }; 2127 2128 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2129 .clock = 205210, 2130 .hdisplay = 2048, 2131 .hsync_start = 2048 + 150, 2132 .hsync_end = 2048 + 150 + 5, 2133 .htotal = 2048 + 150 + 5 + 5, 2134 .vdisplay = 1536, 2135 .vsync_start = 1536 + 3, 2136 .vsync_end = 1536 + 3 + 1, 2137 .vtotal = 1536 + 3 + 1 + 9, 2138 .vrefresh = 60, 2139 }; 2140 2141 static const struct panel_desc lg_lp097qx1_spa1 = { 2142 .modes = &lg_lp097qx1_spa1_mode, 2143 .num_modes = 1, 2144 .size = { 2145 .width = 208, 2146 .height = 147, 2147 }, 2148 }; 2149 2150 static const struct drm_display_mode lg_lp120up1_mode = { 2151 .clock = 162300, 2152 .hdisplay = 1920, 2153 .hsync_start = 1920 + 40, 2154 .hsync_end = 1920 + 40 + 40, 2155 .htotal = 1920 + 40 + 40+ 80, 2156 .vdisplay = 1280, 2157 .vsync_start = 1280 + 4, 2158 .vsync_end = 1280 + 4 + 4, 2159 .vtotal = 1280 + 4 + 4 + 12, 2160 .vrefresh = 60, 2161 }; 2162 2163 static const struct panel_desc lg_lp120up1 = { 2164 .modes = &lg_lp120up1_mode, 2165 .num_modes = 1, 2166 .bpc = 8, 2167 .size = { 2168 .width = 267, 2169 .height = 183, 2170 }, 2171 }; 2172 2173 static const struct drm_display_mode lg_lp129qe_mode = { 2174 .clock = 285250, 2175 .hdisplay = 2560, 2176 .hsync_start = 2560 + 48, 2177 .hsync_end = 2560 + 48 + 32, 2178 .htotal = 2560 + 48 + 32 + 80, 2179 .vdisplay = 1700, 2180 .vsync_start = 1700 + 3, 2181 .vsync_end = 1700 + 3 + 10, 2182 .vtotal = 1700 + 3 + 10 + 36, 2183 .vrefresh = 60, 2184 }; 2185 2186 static const struct panel_desc lg_lp129qe = { 2187 .modes = &lg_lp129qe_mode, 2188 .num_modes = 1, 2189 .bpc = 8, 2190 .size = { 2191 .width = 272, 2192 .height = 181, 2193 }, 2194 }; 2195 2196 static const struct display_timing logictechno_lt161010_2nh_timing = { 2197 .pixelclock = { 26400000, 33300000, 46800000 }, 2198 .hactive = { 800, 800, 800 }, 2199 .hfront_porch = { 16, 210, 354 }, 2200 .hback_porch = { 46, 46, 46 }, 2201 .hsync_len = { 1, 20, 40 }, 2202 .vactive = { 480, 480, 480 }, 2203 .vfront_porch = { 7, 22, 147 }, 2204 .vback_porch = { 23, 23, 23 }, 2205 .vsync_len = { 1, 10, 20 }, 2206 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2207 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2208 DISPLAY_FLAGS_SYNC_POSEDGE, 2209 }; 2210 2211 static const struct panel_desc logictechno_lt161010_2nh = { 2212 .timings = &logictechno_lt161010_2nh_timing, 2213 .num_timings = 1, 2214 .size = { 2215 .width = 154, 2216 .height = 86, 2217 }, 2218 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2219 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2220 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2221 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2222 .connector_type = DRM_MODE_CONNECTOR_DPI, 2223 }; 2224 2225 static const struct display_timing logictechno_lt170410_2whc_timing = { 2226 .pixelclock = { 68900000, 71100000, 73400000 }, 2227 .hactive = { 1280, 1280, 1280 }, 2228 .hfront_porch = { 23, 60, 71 }, 2229 .hback_porch = { 23, 60, 71 }, 2230 .hsync_len = { 15, 40, 47 }, 2231 .vactive = { 800, 800, 800 }, 2232 .vfront_porch = { 5, 7, 10 }, 2233 .vback_porch = { 5, 7, 10 }, 2234 .vsync_len = { 6, 9, 12 }, 2235 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2236 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2237 DISPLAY_FLAGS_SYNC_POSEDGE, 2238 }; 2239 2240 static const struct panel_desc logictechno_lt170410_2whc = { 2241 .timings = &logictechno_lt170410_2whc_timing, 2242 .num_timings = 1, 2243 .size = { 2244 .width = 217, 2245 .height = 136, 2246 }, 2247 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2248 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2249 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2250 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2251 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2252 }; 2253 2254 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2255 .clock = 30400, 2256 .hdisplay = 800, 2257 .hsync_start = 800 + 0, 2258 .hsync_end = 800 + 1, 2259 .htotal = 800 + 0 + 1 + 160, 2260 .vdisplay = 480, 2261 .vsync_start = 480 + 0, 2262 .vsync_end = 480 + 48 + 1, 2263 .vtotal = 480 + 48 + 1 + 0, 2264 .vrefresh = 60, 2265 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2266 }; 2267 2268 static const struct drm_display_mode logicpd_type_28_mode = { 2269 .clock = 9107, 2270 .hdisplay = 480, 2271 .hsync_start = 480 + 3, 2272 .hsync_end = 480 + 3 + 42, 2273 .htotal = 480 + 3 + 42 + 2, 2274 2275 .vdisplay = 272, 2276 .vsync_start = 272 + 2, 2277 .vsync_end = 272 + 2 + 11, 2278 .vtotal = 272 + 2 + 11 + 3, 2279 .vrefresh = 60, 2280 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2281 }; 2282 2283 static const struct panel_desc logicpd_type_28 = { 2284 .modes = &logicpd_type_28_mode, 2285 .num_modes = 1, 2286 .bpc = 8, 2287 .size = { 2288 .width = 105, 2289 .height = 67, 2290 }, 2291 .delay = { 2292 .prepare = 200, 2293 .enable = 200, 2294 .unprepare = 200, 2295 .disable = 200, 2296 }, 2297 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2298 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2299 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2300 }; 2301 2302 static const struct panel_desc mitsubishi_aa070mc01 = { 2303 .modes = &mitsubishi_aa070mc01_mode, 2304 .num_modes = 1, 2305 .bpc = 8, 2306 .size = { 2307 .width = 152, 2308 .height = 91, 2309 }, 2310 2311 .delay = { 2312 .enable = 200, 2313 .unprepare = 200, 2314 .disable = 400, 2315 }, 2316 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2317 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2318 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2319 }; 2320 2321 static const struct display_timing nec_nl12880bc20_05_timing = { 2322 .pixelclock = { 67000000, 71000000, 75000000 }, 2323 .hactive = { 1280, 1280, 1280 }, 2324 .hfront_porch = { 2, 30, 30 }, 2325 .hback_porch = { 6, 100, 100 }, 2326 .hsync_len = { 2, 30, 30 }, 2327 .vactive = { 800, 800, 800 }, 2328 .vfront_porch = { 5, 5, 5 }, 2329 .vback_porch = { 11, 11, 11 }, 2330 .vsync_len = { 7, 7, 7 }, 2331 }; 2332 2333 static const struct panel_desc nec_nl12880bc20_05 = { 2334 .timings = &nec_nl12880bc20_05_timing, 2335 .num_timings = 1, 2336 .bpc = 8, 2337 .size = { 2338 .width = 261, 2339 .height = 163, 2340 }, 2341 .delay = { 2342 .enable = 50, 2343 .disable = 50, 2344 }, 2345 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2346 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2347 }; 2348 2349 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2350 .clock = 10870, 2351 .hdisplay = 480, 2352 .hsync_start = 480 + 2, 2353 .hsync_end = 480 + 2 + 41, 2354 .htotal = 480 + 2 + 41 + 2, 2355 .vdisplay = 272, 2356 .vsync_start = 272 + 2, 2357 .vsync_end = 272 + 2 + 4, 2358 .vtotal = 272 + 2 + 4 + 2, 2359 .vrefresh = 74, 2360 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2361 }; 2362 2363 static const struct panel_desc nec_nl4827hc19_05b = { 2364 .modes = &nec_nl4827hc19_05b_mode, 2365 .num_modes = 1, 2366 .bpc = 8, 2367 .size = { 2368 .width = 95, 2369 .height = 54, 2370 }, 2371 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2372 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2373 }; 2374 2375 static const struct drm_display_mode netron_dy_e231732_mode = { 2376 .clock = 66000, 2377 .hdisplay = 1024, 2378 .hsync_start = 1024 + 160, 2379 .hsync_end = 1024 + 160 + 70, 2380 .htotal = 1024 + 160 + 70 + 90, 2381 .vdisplay = 600, 2382 .vsync_start = 600 + 127, 2383 .vsync_end = 600 + 127 + 20, 2384 .vtotal = 600 + 127 + 20 + 3, 2385 .vrefresh = 60, 2386 }; 2387 2388 static const struct panel_desc netron_dy_e231732 = { 2389 .modes = &netron_dy_e231732_mode, 2390 .num_modes = 1, 2391 .size = { 2392 .width = 154, 2393 .height = 87, 2394 }, 2395 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2396 }; 2397 2398 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 2399 { 2400 .clock = 138500, 2401 .hdisplay = 1920, 2402 .hsync_start = 1920 + 48, 2403 .hsync_end = 1920 + 48 + 32, 2404 .htotal = 1920 + 48 + 32 + 80, 2405 .vdisplay = 1080, 2406 .vsync_start = 1080 + 3, 2407 .vsync_end = 1080 + 3 + 5, 2408 .vtotal = 1080 + 3 + 5 + 23, 2409 .vrefresh = 60, 2410 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2411 }, { 2412 .clock = 110920, 2413 .hdisplay = 1920, 2414 .hsync_start = 1920 + 48, 2415 .hsync_end = 1920 + 48 + 32, 2416 .htotal = 1920 + 48 + 32 + 80, 2417 .vdisplay = 1080, 2418 .vsync_start = 1080 + 3, 2419 .vsync_end = 1080 + 3 + 5, 2420 .vtotal = 1080 + 3 + 5 + 23, 2421 .vrefresh = 48, 2422 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2423 } 2424 }; 2425 2426 static const struct panel_desc neweast_wjfh116008a = { 2427 .modes = neweast_wjfh116008a_modes, 2428 .num_modes = 2, 2429 .bpc = 6, 2430 .size = { 2431 .width = 260, 2432 .height = 150, 2433 }, 2434 .delay = { 2435 .prepare = 110, 2436 .enable = 20, 2437 .unprepare = 500, 2438 }, 2439 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2440 .connector_type = DRM_MODE_CONNECTOR_eDP, 2441 }; 2442 2443 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2444 .clock = 9000, 2445 .hdisplay = 480, 2446 .hsync_start = 480 + 2, 2447 .hsync_end = 480 + 2 + 41, 2448 .htotal = 480 + 2 + 41 + 2, 2449 .vdisplay = 272, 2450 .vsync_start = 272 + 2, 2451 .vsync_end = 272 + 2 + 10, 2452 .vtotal = 272 + 2 + 10 + 2, 2453 .vrefresh = 60, 2454 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2455 }; 2456 2457 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2458 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2459 .num_modes = 1, 2460 .bpc = 8, 2461 .size = { 2462 .width = 95, 2463 .height = 54, 2464 }, 2465 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2466 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2467 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2468 }; 2469 2470 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2471 .pixelclock = { 130000000, 148350000, 163000000 }, 2472 .hactive = { 1920, 1920, 1920 }, 2473 .hfront_porch = { 80, 100, 100 }, 2474 .hback_porch = { 100, 120, 120 }, 2475 .hsync_len = { 50, 60, 60 }, 2476 .vactive = { 1080, 1080, 1080 }, 2477 .vfront_porch = { 12, 30, 30 }, 2478 .vback_porch = { 4, 10, 10 }, 2479 .vsync_len = { 4, 5, 5 }, 2480 }; 2481 2482 static const struct panel_desc nlt_nl192108ac18_02d = { 2483 .timings = &nlt_nl192108ac18_02d_timing, 2484 .num_timings = 1, 2485 .bpc = 8, 2486 .size = { 2487 .width = 344, 2488 .height = 194, 2489 }, 2490 .delay = { 2491 .unprepare = 500, 2492 }, 2493 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2494 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2495 }; 2496 2497 static const struct drm_display_mode nvd_9128_mode = { 2498 .clock = 29500, 2499 .hdisplay = 800, 2500 .hsync_start = 800 + 130, 2501 .hsync_end = 800 + 130 + 98, 2502 .htotal = 800 + 0 + 130 + 98, 2503 .vdisplay = 480, 2504 .vsync_start = 480 + 10, 2505 .vsync_end = 480 + 10 + 50, 2506 .vtotal = 480 + 0 + 10 + 50, 2507 }; 2508 2509 static const struct panel_desc nvd_9128 = { 2510 .modes = &nvd_9128_mode, 2511 .num_modes = 1, 2512 .bpc = 8, 2513 .size = { 2514 .width = 156, 2515 .height = 88, 2516 }, 2517 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2518 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2519 }; 2520 2521 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2522 .pixelclock = { 30000000, 30000000, 40000000 }, 2523 .hactive = { 800, 800, 800 }, 2524 .hfront_porch = { 40, 40, 40 }, 2525 .hback_porch = { 40, 40, 40 }, 2526 .hsync_len = { 1, 48, 48 }, 2527 .vactive = { 480, 480, 480 }, 2528 .vfront_porch = { 13, 13, 13 }, 2529 .vback_porch = { 29, 29, 29 }, 2530 .vsync_len = { 3, 3, 3 }, 2531 .flags = DISPLAY_FLAGS_DE_HIGH, 2532 }; 2533 2534 static const struct panel_desc okaya_rs800480t_7x0gp = { 2535 .timings = &okaya_rs800480t_7x0gp_timing, 2536 .num_timings = 1, 2537 .bpc = 6, 2538 .size = { 2539 .width = 154, 2540 .height = 87, 2541 }, 2542 .delay = { 2543 .prepare = 41, 2544 .enable = 50, 2545 .unprepare = 41, 2546 .disable = 50, 2547 }, 2548 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2549 }; 2550 2551 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2552 .clock = 9000, 2553 .hdisplay = 480, 2554 .hsync_start = 480 + 5, 2555 .hsync_end = 480 + 5 + 30, 2556 .htotal = 480 + 5 + 30 + 10, 2557 .vdisplay = 272, 2558 .vsync_start = 272 + 8, 2559 .vsync_end = 272 + 8 + 5, 2560 .vtotal = 272 + 8 + 5 + 3, 2561 .vrefresh = 60, 2562 }; 2563 2564 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2565 .modes = &olimex_lcd_olinuxino_43ts_mode, 2566 .num_modes = 1, 2567 .size = { 2568 .width = 95, 2569 .height = 54, 2570 }, 2571 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2572 }; 2573 2574 /* 2575 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2576 * pixel clocks, but this is the timing that was being used in the Adafruit 2577 * installation instructions. 2578 */ 2579 static const struct drm_display_mode ontat_yx700wv03_mode = { 2580 .clock = 29500, 2581 .hdisplay = 800, 2582 .hsync_start = 824, 2583 .hsync_end = 896, 2584 .htotal = 992, 2585 .vdisplay = 480, 2586 .vsync_start = 483, 2587 .vsync_end = 493, 2588 .vtotal = 500, 2589 .vrefresh = 60, 2590 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2591 }; 2592 2593 /* 2594 * Specification at: 2595 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2596 */ 2597 static const struct panel_desc ontat_yx700wv03 = { 2598 .modes = &ontat_yx700wv03_mode, 2599 .num_modes = 1, 2600 .bpc = 8, 2601 .size = { 2602 .width = 154, 2603 .height = 83, 2604 }, 2605 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2606 }; 2607 2608 static const struct drm_display_mode ortustech_com37h3m_mode = { 2609 .clock = 22230, 2610 .hdisplay = 480, 2611 .hsync_start = 480 + 40, 2612 .hsync_end = 480 + 40 + 10, 2613 .htotal = 480 + 40 + 10 + 40, 2614 .vdisplay = 640, 2615 .vsync_start = 640 + 4, 2616 .vsync_end = 640 + 4 + 2, 2617 .vtotal = 640 + 4 + 2 + 4, 2618 .vrefresh = 60, 2619 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2620 }; 2621 2622 static const struct panel_desc ortustech_com37h3m = { 2623 .modes = &ortustech_com37h3m_mode, 2624 .num_modes = 1, 2625 .bpc = 8, 2626 .size = { 2627 .width = 56, /* 56.16mm */ 2628 .height = 75, /* 74.88mm */ 2629 }, 2630 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2631 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 2632 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2633 }; 2634 2635 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 2636 .clock = 25000, 2637 .hdisplay = 480, 2638 .hsync_start = 480 + 10, 2639 .hsync_end = 480 + 10 + 10, 2640 .htotal = 480 + 10 + 10 + 15, 2641 .vdisplay = 800, 2642 .vsync_start = 800 + 3, 2643 .vsync_end = 800 + 3 + 3, 2644 .vtotal = 800 + 3 + 3 + 3, 2645 .vrefresh = 60, 2646 }; 2647 2648 static const struct panel_desc ortustech_com43h4m85ulc = { 2649 .modes = &ortustech_com43h4m85ulc_mode, 2650 .num_modes = 1, 2651 .bpc = 8, 2652 .size = { 2653 .width = 56, 2654 .height = 93, 2655 }, 2656 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2657 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2658 .connector_type = DRM_MODE_CONNECTOR_DPI, 2659 }; 2660 2661 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 2662 .clock = 33000, 2663 .hdisplay = 800, 2664 .hsync_start = 800 + 210, 2665 .hsync_end = 800 + 210 + 30, 2666 .htotal = 800 + 210 + 30 + 16, 2667 .vdisplay = 480, 2668 .vsync_start = 480 + 22, 2669 .vsync_end = 480 + 22 + 13, 2670 .vtotal = 480 + 22 + 13 + 10, 2671 .vrefresh = 60, 2672 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2673 }; 2674 2675 static const struct panel_desc osddisplays_osd070t1718_19ts = { 2676 .modes = &osddisplays_osd070t1718_19ts_mode, 2677 .num_modes = 1, 2678 .bpc = 8, 2679 .size = { 2680 .width = 152, 2681 .height = 91, 2682 }, 2683 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2684 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2685 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2686 .connector_type = DRM_MODE_CONNECTOR_DPI, 2687 }; 2688 2689 static const struct drm_display_mode pda_91_00156_a0_mode = { 2690 .clock = 33300, 2691 .hdisplay = 800, 2692 .hsync_start = 800 + 1, 2693 .hsync_end = 800 + 1 + 64, 2694 .htotal = 800 + 1 + 64 + 64, 2695 .vdisplay = 480, 2696 .vsync_start = 480 + 1, 2697 .vsync_end = 480 + 1 + 23, 2698 .vtotal = 480 + 1 + 23 + 22, 2699 .vrefresh = 60, 2700 }; 2701 2702 static const struct panel_desc pda_91_00156_a0 = { 2703 .modes = &pda_91_00156_a0_mode, 2704 .num_modes = 1, 2705 .size = { 2706 .width = 152, 2707 .height = 91, 2708 }, 2709 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2710 }; 2711 2712 2713 static const struct drm_display_mode qd43003c0_40_mode = { 2714 .clock = 9000, 2715 .hdisplay = 480, 2716 .hsync_start = 480 + 8, 2717 .hsync_end = 480 + 8 + 4, 2718 .htotal = 480 + 8 + 4 + 39, 2719 .vdisplay = 272, 2720 .vsync_start = 272 + 4, 2721 .vsync_end = 272 + 4 + 10, 2722 .vtotal = 272 + 4 + 10 + 2, 2723 .vrefresh = 60, 2724 }; 2725 2726 static const struct panel_desc qd43003c0_40 = { 2727 .modes = &qd43003c0_40_mode, 2728 .num_modes = 1, 2729 .bpc = 8, 2730 .size = { 2731 .width = 95, 2732 .height = 53, 2733 }, 2734 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2735 }; 2736 2737 static const struct display_timing rocktech_rk070er9427_timing = { 2738 .pixelclock = { 26400000, 33300000, 46800000 }, 2739 .hactive = { 800, 800, 800 }, 2740 .hfront_porch = { 16, 210, 354 }, 2741 .hback_porch = { 46, 46, 46 }, 2742 .hsync_len = { 1, 1, 1 }, 2743 .vactive = { 480, 480, 480 }, 2744 .vfront_porch = { 7, 22, 147 }, 2745 .vback_porch = { 23, 23, 23 }, 2746 .vsync_len = { 1, 1, 1 }, 2747 .flags = DISPLAY_FLAGS_DE_HIGH, 2748 }; 2749 2750 static const struct panel_desc rocktech_rk070er9427 = { 2751 .timings = &rocktech_rk070er9427_timing, 2752 .num_timings = 1, 2753 .bpc = 6, 2754 .size = { 2755 .width = 154, 2756 .height = 86, 2757 }, 2758 .delay = { 2759 .prepare = 41, 2760 .enable = 50, 2761 .unprepare = 41, 2762 .disable = 50, 2763 }, 2764 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2765 }; 2766 2767 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 2768 .clock = 71100, 2769 .hdisplay = 1280, 2770 .hsync_start = 1280 + 48, 2771 .hsync_end = 1280 + 48 + 32, 2772 .htotal = 1280 + 48 + 32 + 80, 2773 .vdisplay = 800, 2774 .vsync_start = 800 + 2, 2775 .vsync_end = 800 + 2 + 5, 2776 .vtotal = 800 + 2 + 5 + 16, 2777 .vrefresh = 60, 2778 }; 2779 2780 static const struct panel_desc rocktech_rk101ii01d_ct = { 2781 .modes = &rocktech_rk101ii01d_ct_mode, 2782 .num_modes = 1, 2783 .size = { 2784 .width = 217, 2785 .height = 136, 2786 }, 2787 .delay = { 2788 .prepare = 50, 2789 .disable = 50, 2790 }, 2791 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2792 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2793 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2794 }; 2795 2796 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 2797 .clock = 271560, 2798 .hdisplay = 2560, 2799 .hsync_start = 2560 + 48, 2800 .hsync_end = 2560 + 48 + 32, 2801 .htotal = 2560 + 48 + 32 + 80, 2802 .vdisplay = 1600, 2803 .vsync_start = 1600 + 2, 2804 .vsync_end = 1600 + 2 + 5, 2805 .vtotal = 1600 + 2 + 5 + 57, 2806 .vrefresh = 60, 2807 }; 2808 2809 static const struct panel_desc samsung_lsn122dl01_c01 = { 2810 .modes = &samsung_lsn122dl01_c01_mode, 2811 .num_modes = 1, 2812 .size = { 2813 .width = 263, 2814 .height = 164, 2815 }, 2816 }; 2817 2818 static const struct drm_display_mode samsung_ltn101nt05_mode = { 2819 .clock = 54030, 2820 .hdisplay = 1024, 2821 .hsync_start = 1024 + 24, 2822 .hsync_end = 1024 + 24 + 136, 2823 .htotal = 1024 + 24 + 136 + 160, 2824 .vdisplay = 600, 2825 .vsync_start = 600 + 3, 2826 .vsync_end = 600 + 3 + 6, 2827 .vtotal = 600 + 3 + 6 + 61, 2828 .vrefresh = 60, 2829 }; 2830 2831 static const struct panel_desc samsung_ltn101nt05 = { 2832 .modes = &samsung_ltn101nt05_mode, 2833 .num_modes = 1, 2834 .bpc = 6, 2835 .size = { 2836 .width = 223, 2837 .height = 125, 2838 }, 2839 }; 2840 2841 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 2842 .clock = 76300, 2843 .hdisplay = 1366, 2844 .hsync_start = 1366 + 64, 2845 .hsync_end = 1366 + 64 + 48, 2846 .htotal = 1366 + 64 + 48 + 128, 2847 .vdisplay = 768, 2848 .vsync_start = 768 + 2, 2849 .vsync_end = 768 + 2 + 5, 2850 .vtotal = 768 + 2 + 5 + 17, 2851 .vrefresh = 60, 2852 }; 2853 2854 static const struct panel_desc samsung_ltn140at29_301 = { 2855 .modes = &samsung_ltn140at29_301_mode, 2856 .num_modes = 1, 2857 .bpc = 6, 2858 .size = { 2859 .width = 320, 2860 .height = 187, 2861 }, 2862 }; 2863 2864 static const struct display_timing satoz_sat050at40h12r2_timing = { 2865 .pixelclock = {33300000, 33300000, 50000000}, 2866 .hactive = {800, 800, 800}, 2867 .hfront_porch = {16, 210, 354}, 2868 .hback_porch = {46, 46, 46}, 2869 .hsync_len = {1, 1, 40}, 2870 .vactive = {480, 480, 480}, 2871 .vfront_porch = {7, 22, 147}, 2872 .vback_porch = {23, 23, 23}, 2873 .vsync_len = {1, 1, 20}, 2874 }; 2875 2876 static const struct panel_desc satoz_sat050at40h12r2 = { 2877 .timings = &satoz_sat050at40h12r2_timing, 2878 .num_timings = 1, 2879 .bpc = 8, 2880 .size = { 2881 .width = 108, 2882 .height = 65, 2883 }, 2884 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2885 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2886 }; 2887 2888 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 2889 .clock = 168480, 2890 .hdisplay = 1920, 2891 .hsync_start = 1920 + 48, 2892 .hsync_end = 1920 + 48 + 32, 2893 .htotal = 1920 + 48 + 32 + 80, 2894 .vdisplay = 1280, 2895 .vsync_start = 1280 + 3, 2896 .vsync_end = 1280 + 3 + 10, 2897 .vtotal = 1280 + 3 + 10 + 57, 2898 .vrefresh = 60, 2899 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2900 }; 2901 2902 static const struct panel_desc sharp_ld_d5116z01b = { 2903 .modes = &sharp_ld_d5116z01b_mode, 2904 .num_modes = 1, 2905 .bpc = 8, 2906 .size = { 2907 .width = 260, 2908 .height = 120, 2909 }, 2910 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2911 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2912 }; 2913 2914 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 2915 .clock = 33260, 2916 .hdisplay = 800, 2917 .hsync_start = 800 + 64, 2918 .hsync_end = 800 + 64 + 128, 2919 .htotal = 800 + 64 + 128 + 64, 2920 .vdisplay = 480, 2921 .vsync_start = 480 + 8, 2922 .vsync_end = 480 + 8 + 2, 2923 .vtotal = 480 + 8 + 2 + 35, 2924 .vrefresh = 60, 2925 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 2926 }; 2927 2928 static const struct panel_desc sharp_lq070y3dg3b = { 2929 .modes = &sharp_lq070y3dg3b_mode, 2930 .num_modes = 1, 2931 .bpc = 8, 2932 .size = { 2933 .width = 152, /* 152.4mm */ 2934 .height = 91, /* 91.4mm */ 2935 }, 2936 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2937 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 2938 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2939 }; 2940 2941 static const struct drm_display_mode sharp_lq035q7db03_mode = { 2942 .clock = 5500, 2943 .hdisplay = 240, 2944 .hsync_start = 240 + 16, 2945 .hsync_end = 240 + 16 + 7, 2946 .htotal = 240 + 16 + 7 + 5, 2947 .vdisplay = 320, 2948 .vsync_start = 320 + 9, 2949 .vsync_end = 320 + 9 + 1, 2950 .vtotal = 320 + 9 + 1 + 7, 2951 .vrefresh = 60, 2952 }; 2953 2954 static const struct panel_desc sharp_lq035q7db03 = { 2955 .modes = &sharp_lq035q7db03_mode, 2956 .num_modes = 1, 2957 .bpc = 6, 2958 .size = { 2959 .width = 54, 2960 .height = 72, 2961 }, 2962 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2963 }; 2964 2965 static const struct display_timing sharp_lq101k1ly04_timing = { 2966 .pixelclock = { 60000000, 65000000, 80000000 }, 2967 .hactive = { 1280, 1280, 1280 }, 2968 .hfront_porch = { 20, 20, 20 }, 2969 .hback_porch = { 20, 20, 20 }, 2970 .hsync_len = { 10, 10, 10 }, 2971 .vactive = { 800, 800, 800 }, 2972 .vfront_porch = { 4, 4, 4 }, 2973 .vback_porch = { 4, 4, 4 }, 2974 .vsync_len = { 4, 4, 4 }, 2975 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 2976 }; 2977 2978 static const struct panel_desc sharp_lq101k1ly04 = { 2979 .timings = &sharp_lq101k1ly04_timing, 2980 .num_timings = 1, 2981 .bpc = 8, 2982 .size = { 2983 .width = 217, 2984 .height = 136, 2985 }, 2986 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 2987 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2988 }; 2989 2990 static const struct display_timing sharp_lq123p1jx31_timing = { 2991 .pixelclock = { 252750000, 252750000, 266604720 }, 2992 .hactive = { 2400, 2400, 2400 }, 2993 .hfront_porch = { 48, 48, 48 }, 2994 .hback_porch = { 80, 80, 84 }, 2995 .hsync_len = { 32, 32, 32 }, 2996 .vactive = { 1600, 1600, 1600 }, 2997 .vfront_porch = { 3, 3, 3 }, 2998 .vback_porch = { 33, 33, 120 }, 2999 .vsync_len = { 10, 10, 10 }, 3000 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3001 }; 3002 3003 static const struct panel_desc sharp_lq123p1jx31 = { 3004 .timings = &sharp_lq123p1jx31_timing, 3005 .num_timings = 1, 3006 .bpc = 8, 3007 .size = { 3008 .width = 259, 3009 .height = 173, 3010 }, 3011 .delay = { 3012 .prepare = 110, 3013 .enable = 50, 3014 .unprepare = 550, 3015 }, 3016 }; 3017 3018 static const struct display_timing sharp_ls020b1dd01d_timing = { 3019 .pixelclock = { 2000000, 4200000, 5000000 }, 3020 .hactive = { 240, 240, 240 }, 3021 .hfront_porch = { 66, 66, 66 }, 3022 .hback_porch = { 1, 1, 1 }, 3023 .hsync_len = { 1, 1, 1 }, 3024 .vactive = { 160, 160, 160 }, 3025 .vfront_porch = { 52, 52, 52 }, 3026 .vback_porch = { 6, 6, 6 }, 3027 .vsync_len = { 10, 10, 10 }, 3028 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW, 3029 }; 3030 3031 static const struct panel_desc sharp_ls020b1dd01d = { 3032 .timings = &sharp_ls020b1dd01d_timing, 3033 .num_timings = 1, 3034 .bpc = 6, 3035 .size = { 3036 .width = 42, 3037 .height = 28, 3038 }, 3039 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3040 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3041 | DRM_BUS_FLAG_PIXDATA_NEGEDGE 3042 | DRM_BUS_FLAG_SHARP_SIGNALS, 3043 }; 3044 3045 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3046 .clock = 33300, 3047 .hdisplay = 800, 3048 .hsync_start = 800 + 1, 3049 .hsync_end = 800 + 1 + 64, 3050 .htotal = 800 + 1 + 64 + 64, 3051 .vdisplay = 480, 3052 .vsync_start = 480 + 1, 3053 .vsync_end = 480 + 1 + 23, 3054 .vtotal = 480 + 1 + 23 + 22, 3055 .vrefresh = 60, 3056 }; 3057 3058 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3059 .modes = &shelly_sca07010_bfn_lnn_mode, 3060 .num_modes = 1, 3061 .size = { 3062 .width = 152, 3063 .height = 91, 3064 }, 3065 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3066 }; 3067 3068 static const struct drm_display_mode starry_kr122ea0sra_mode = { 3069 .clock = 147000, 3070 .hdisplay = 1920, 3071 .hsync_start = 1920 + 16, 3072 .hsync_end = 1920 + 16 + 16, 3073 .htotal = 1920 + 16 + 16 + 32, 3074 .vdisplay = 1200, 3075 .vsync_start = 1200 + 15, 3076 .vsync_end = 1200 + 15 + 2, 3077 .vtotal = 1200 + 15 + 2 + 18, 3078 .vrefresh = 60, 3079 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3080 }; 3081 3082 static const struct panel_desc starry_kr122ea0sra = { 3083 .modes = &starry_kr122ea0sra_mode, 3084 .num_modes = 1, 3085 .size = { 3086 .width = 263, 3087 .height = 164, 3088 }, 3089 .delay = { 3090 .prepare = 10 + 200, 3091 .enable = 50, 3092 .unprepare = 10 + 500, 3093 }, 3094 }; 3095 3096 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3097 .clock = 30000, 3098 .hdisplay = 800, 3099 .hsync_start = 800 + 39, 3100 .hsync_end = 800 + 39 + 47, 3101 .htotal = 800 + 39 + 47 + 39, 3102 .vdisplay = 480, 3103 .vsync_start = 480 + 13, 3104 .vsync_end = 480 + 13 + 2, 3105 .vtotal = 480 + 13 + 2 + 29, 3106 .vrefresh = 62, 3107 }; 3108 3109 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3110 .modes = &tfc_s9700rtwv43tr_01b_mode, 3111 .num_modes = 1, 3112 .bpc = 8, 3113 .size = { 3114 .width = 155, 3115 .height = 90, 3116 }, 3117 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3118 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3119 }; 3120 3121 static const struct display_timing tianma_tm070jdhg30_timing = { 3122 .pixelclock = { 62600000, 68200000, 78100000 }, 3123 .hactive = { 1280, 1280, 1280 }, 3124 .hfront_porch = { 15, 64, 159 }, 3125 .hback_porch = { 5, 5, 5 }, 3126 .hsync_len = { 1, 1, 256 }, 3127 .vactive = { 800, 800, 800 }, 3128 .vfront_porch = { 3, 40, 99 }, 3129 .vback_porch = { 2, 2, 2 }, 3130 .vsync_len = { 1, 1, 128 }, 3131 .flags = DISPLAY_FLAGS_DE_HIGH, 3132 }; 3133 3134 static const struct panel_desc tianma_tm070jdhg30 = { 3135 .timings = &tianma_tm070jdhg30_timing, 3136 .num_timings = 1, 3137 .bpc = 8, 3138 .size = { 3139 .width = 151, 3140 .height = 95, 3141 }, 3142 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3143 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3144 }; 3145 3146 static const struct display_timing tianma_tm070rvhg71_timing = { 3147 .pixelclock = { 27700000, 29200000, 39600000 }, 3148 .hactive = { 800, 800, 800 }, 3149 .hfront_porch = { 12, 40, 212 }, 3150 .hback_porch = { 88, 88, 88 }, 3151 .hsync_len = { 1, 1, 40 }, 3152 .vactive = { 480, 480, 480 }, 3153 .vfront_porch = { 1, 13, 88 }, 3154 .vback_porch = { 32, 32, 32 }, 3155 .vsync_len = { 1, 1, 3 }, 3156 .flags = DISPLAY_FLAGS_DE_HIGH, 3157 }; 3158 3159 static const struct panel_desc tianma_tm070rvhg71 = { 3160 .timings = &tianma_tm070rvhg71_timing, 3161 .num_timings = 1, 3162 .bpc = 8, 3163 .size = { 3164 .width = 154, 3165 .height = 86, 3166 }, 3167 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3168 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3169 }; 3170 3171 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3172 { 3173 .clock = 10000, 3174 .hdisplay = 320, 3175 .hsync_start = 320 + 50, 3176 .hsync_end = 320 + 50 + 6, 3177 .htotal = 320 + 50 + 6 + 38, 3178 .vdisplay = 240, 3179 .vsync_start = 240 + 3, 3180 .vsync_end = 240 + 3 + 1, 3181 .vtotal = 240 + 3 + 1 + 17, 3182 .vrefresh = 60, 3183 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3184 }, 3185 }; 3186 3187 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3188 .modes = ti_nspire_cx_lcd_mode, 3189 .num_modes = 1, 3190 .bpc = 8, 3191 .size = { 3192 .width = 65, 3193 .height = 49, 3194 }, 3195 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3196 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE, 3197 }; 3198 3199 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3200 { 3201 .clock = 10000, 3202 .hdisplay = 320, 3203 .hsync_start = 320 + 6, 3204 .hsync_end = 320 + 6 + 6, 3205 .htotal = 320 + 6 + 6 + 6, 3206 .vdisplay = 240, 3207 .vsync_start = 240 + 0, 3208 .vsync_end = 240 + 0 + 1, 3209 .vtotal = 240 + 0 + 1 + 0, 3210 .vrefresh = 60, 3211 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3212 }, 3213 }; 3214 3215 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3216 .modes = ti_nspire_classic_lcd_mode, 3217 .num_modes = 1, 3218 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3219 .bpc = 8, 3220 .size = { 3221 .width = 71, 3222 .height = 53, 3223 }, 3224 /* This is the grayscale bus format */ 3225 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3226 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 3227 }; 3228 3229 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3230 .clock = 79500, 3231 .hdisplay = 1280, 3232 .hsync_start = 1280 + 192, 3233 .hsync_end = 1280 + 192 + 128, 3234 .htotal = 1280 + 192 + 128 + 64, 3235 .vdisplay = 768, 3236 .vsync_start = 768 + 20, 3237 .vsync_end = 768 + 20 + 7, 3238 .vtotal = 768 + 20 + 7 + 3, 3239 .vrefresh = 60, 3240 }; 3241 3242 static const struct panel_desc toshiba_lt089ac29000 = { 3243 .modes = &toshiba_lt089ac29000_mode, 3244 .num_modes = 1, 3245 .size = { 3246 .width = 194, 3247 .height = 116, 3248 }, 3249 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3250 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3251 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3252 }; 3253 3254 static const struct drm_display_mode tpk_f07a_0102_mode = { 3255 .clock = 33260, 3256 .hdisplay = 800, 3257 .hsync_start = 800 + 40, 3258 .hsync_end = 800 + 40 + 128, 3259 .htotal = 800 + 40 + 128 + 88, 3260 .vdisplay = 480, 3261 .vsync_start = 480 + 10, 3262 .vsync_end = 480 + 10 + 2, 3263 .vtotal = 480 + 10 + 2 + 33, 3264 .vrefresh = 60, 3265 }; 3266 3267 static const struct panel_desc tpk_f07a_0102 = { 3268 .modes = &tpk_f07a_0102_mode, 3269 .num_modes = 1, 3270 .size = { 3271 .width = 152, 3272 .height = 91, 3273 }, 3274 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3275 }; 3276 3277 static const struct drm_display_mode tpk_f10a_0102_mode = { 3278 .clock = 45000, 3279 .hdisplay = 1024, 3280 .hsync_start = 1024 + 176, 3281 .hsync_end = 1024 + 176 + 5, 3282 .htotal = 1024 + 176 + 5 + 88, 3283 .vdisplay = 600, 3284 .vsync_start = 600 + 20, 3285 .vsync_end = 600 + 20 + 5, 3286 .vtotal = 600 + 20 + 5 + 25, 3287 .vrefresh = 60, 3288 }; 3289 3290 static const struct panel_desc tpk_f10a_0102 = { 3291 .modes = &tpk_f10a_0102_mode, 3292 .num_modes = 1, 3293 .size = { 3294 .width = 223, 3295 .height = 125, 3296 }, 3297 }; 3298 3299 static const struct display_timing urt_umsh_8596md_timing = { 3300 .pixelclock = { 33260000, 33260000, 33260000 }, 3301 .hactive = { 800, 800, 800 }, 3302 .hfront_porch = { 41, 41, 41 }, 3303 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3304 .hsync_len = { 71, 128, 128 }, 3305 .vactive = { 480, 480, 480 }, 3306 .vfront_porch = { 10, 10, 10 }, 3307 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3308 .vsync_len = { 2, 2, 2 }, 3309 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3310 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3311 }; 3312 3313 static const struct panel_desc urt_umsh_8596md_lvds = { 3314 .timings = &urt_umsh_8596md_timing, 3315 .num_timings = 1, 3316 .bpc = 6, 3317 .size = { 3318 .width = 152, 3319 .height = 91, 3320 }, 3321 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3322 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3323 }; 3324 3325 static const struct panel_desc urt_umsh_8596md_parallel = { 3326 .timings = &urt_umsh_8596md_timing, 3327 .num_timings = 1, 3328 .bpc = 6, 3329 .size = { 3330 .width = 152, 3331 .height = 91, 3332 }, 3333 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3334 }; 3335 3336 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3337 .clock = 33333, 3338 .hdisplay = 800, 3339 .hsync_start = 800 + 210, 3340 .hsync_end = 800 + 210 + 20, 3341 .htotal = 800 + 210 + 20 + 46, 3342 .vdisplay = 480, 3343 .vsync_start = 480 + 22, 3344 .vsync_end = 480 + 22 + 10, 3345 .vtotal = 480 + 22 + 10 + 23, 3346 .vrefresh = 60, 3347 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3348 }; 3349 3350 static const struct panel_desc vl050_8048nt_c01 = { 3351 .modes = &vl050_8048nt_c01_mode, 3352 .num_modes = 1, 3353 .bpc = 8, 3354 .size = { 3355 .width = 120, 3356 .height = 76, 3357 }, 3358 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3359 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3360 }; 3361 3362 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3363 .clock = 6410, 3364 .hdisplay = 320, 3365 .hsync_start = 320 + 20, 3366 .hsync_end = 320 + 20 + 30, 3367 .htotal = 320 + 20 + 30 + 38, 3368 .vdisplay = 240, 3369 .vsync_start = 240 + 4, 3370 .vsync_end = 240 + 4 + 3, 3371 .vtotal = 240 + 4 + 3 + 15, 3372 .vrefresh = 60, 3373 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3374 }; 3375 3376 static const struct panel_desc winstar_wf35ltiacd = { 3377 .modes = &winstar_wf35ltiacd_mode, 3378 .num_modes = 1, 3379 .bpc = 8, 3380 .size = { 3381 .width = 70, 3382 .height = 53, 3383 }, 3384 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3385 }; 3386 3387 static const struct drm_display_mode arm_rtsm_mode[] = { 3388 { 3389 .clock = 65000, 3390 .hdisplay = 1024, 3391 .hsync_start = 1024 + 24, 3392 .hsync_end = 1024 + 24 + 136, 3393 .htotal = 1024 + 24 + 136 + 160, 3394 .vdisplay = 768, 3395 .vsync_start = 768 + 3, 3396 .vsync_end = 768 + 3 + 6, 3397 .vtotal = 768 + 3 + 6 + 29, 3398 .vrefresh = 60, 3399 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3400 }, 3401 }; 3402 3403 static const struct panel_desc arm_rtsm = { 3404 .modes = arm_rtsm_mode, 3405 .num_modes = 1, 3406 .bpc = 8, 3407 .size = { 3408 .width = 400, 3409 .height = 300, 3410 }, 3411 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3412 }; 3413 3414 static const struct of_device_id platform_of_match[] = { 3415 { 3416 .compatible = "ampire,am-480272h3tmqw-t01h", 3417 .data = &ire_am_480272h3tmqw_t01h, 3418 }, { 3419 .compatible = "ampire,am800480r3tmqwa1h", 3420 .data = &ire_am800480r3tmqwa1h, 3421 }, { 3422 .compatible = "arm,rtsm-display", 3423 .data = &arm_rtsm, 3424 }, { 3425 .compatible = "armadeus,st0700-adapt", 3426 .data = &armadeus_st0700_adapt, 3427 }, { 3428 .compatible = "auo,b101aw03", 3429 .data = &auo_b101aw03, 3430 }, { 3431 .compatible = "auo,b101ean01", 3432 .data = &auo_b101ean01, 3433 }, { 3434 .compatible = "auo,b101xtn01", 3435 .data = &auo_b101xtn01, 3436 }, { 3437 .compatible = "auo,b116xa01", 3438 .data = &auo_b116xak01, 3439 }, { 3440 .compatible = "auo,b116xw03", 3441 .data = &auo_b116xw03, 3442 }, { 3443 .compatible = "auo,b133htn01", 3444 .data = &auo_b133htn01, 3445 }, { 3446 .compatible = "auo,b133xtn01", 3447 .data = &auo_b133xtn01, 3448 }, { 3449 .compatible = "auo,g070vvn01", 3450 .data = &auo_g070vvn01, 3451 }, { 3452 .compatible = "auo,g101evn010", 3453 .data = &auo_g101evn010, 3454 }, { 3455 .compatible = "auo,g104sn02", 3456 .data = &auo_g104sn02, 3457 }, { 3458 .compatible = "auo,g133han01", 3459 .data = &auo_g133han01, 3460 }, { 3461 .compatible = "auo,g185han01", 3462 .data = &auo_g185han01, 3463 }, { 3464 .compatible = "auo,p320hvn03", 3465 .data = &auo_p320hvn03, 3466 }, { 3467 .compatible = "auo,t215hvn01", 3468 .data = &auo_t215hvn01, 3469 }, { 3470 .compatible = "avic,tm070ddh03", 3471 .data = &avic_tm070ddh03, 3472 }, { 3473 .compatible = "bananapi,s070wv20-ct16", 3474 .data = &bananapi_s070wv20_ct16, 3475 }, { 3476 .compatible = "boe,hv070wsa-100", 3477 .data = &boe_hv070wsa 3478 }, { 3479 .compatible = "boe,nv101wxmn51", 3480 .data = &boe_nv101wxmn51, 3481 }, { 3482 .compatible = "boe,nv140fhmn49", 3483 .data = &boe_nv140fhmn49, 3484 }, { 3485 .compatible = "cdtech,s043wq26h-ct7", 3486 .data = &cdtech_s043wq26h_ct7, 3487 }, { 3488 .compatible = "cdtech,s070wv95-ct16", 3489 .data = &cdtech_s070wv95_ct16, 3490 }, { 3491 .compatible = "chunghwa,claa070wp03xg", 3492 .data = &chunghwa_claa070wp03xg, 3493 }, { 3494 .compatible = "chunghwa,claa101wa01a", 3495 .data = &chunghwa_claa101wa01a 3496 }, { 3497 .compatible = "chunghwa,claa101wb01", 3498 .data = &chunghwa_claa101wb01 3499 }, { 3500 .compatible = "dataimage,scf0700c48ggu18", 3501 .data = &dataimage_scf0700c48ggu18, 3502 }, { 3503 .compatible = "dlc,dlc0700yzg-1", 3504 .data = &dlc_dlc0700yzg_1, 3505 }, { 3506 .compatible = "dlc,dlc1010gig", 3507 .data = &dlc_dlc1010gig, 3508 }, { 3509 .compatible = "edt,et035012dm6", 3510 .data = &edt_et035012dm6, 3511 }, { 3512 .compatible = "edt,etm043080dh6gp", 3513 .data = &edt_etm043080dh6gp, 3514 }, { 3515 .compatible = "edt,etm0430g0dh6", 3516 .data = &edt_etm0430g0dh6, 3517 }, { 3518 .compatible = "edt,et057090dhu", 3519 .data = &edt_et057090dhu, 3520 }, { 3521 .compatible = "edt,et070080dh6", 3522 .data = &edt_etm0700g0dh6, 3523 }, { 3524 .compatible = "edt,etm0700g0dh6", 3525 .data = &edt_etm0700g0dh6, 3526 }, { 3527 .compatible = "edt,etm0700g0bdh6", 3528 .data = &edt_etm0700g0bdh6, 3529 }, { 3530 .compatible = "edt,etm0700g0edh6", 3531 .data = &edt_etm0700g0bdh6, 3532 }, { 3533 .compatible = "evervision,vgg804821", 3534 .data = &evervision_vgg804821, 3535 }, { 3536 .compatible = "foxlink,fl500wvr00-a0t", 3537 .data = &foxlink_fl500wvr00_a0t, 3538 }, { 3539 .compatible = "frida,frd350h54004", 3540 .data = &frida_frd350h54004, 3541 }, { 3542 .compatible = "friendlyarm,hd702e", 3543 .data = &friendlyarm_hd702e, 3544 }, { 3545 .compatible = "giantplus,gpg482739qs5", 3546 .data = &giantplus_gpg482739qs5 3547 }, { 3548 .compatible = "giantplus,gpm940b0", 3549 .data = &giantplus_gpm940b0, 3550 }, { 3551 .compatible = "hannstar,hsd070pww1", 3552 .data = &hannstar_hsd070pww1, 3553 }, { 3554 .compatible = "hannstar,hsd100pxn1", 3555 .data = &hannstar_hsd100pxn1, 3556 }, { 3557 .compatible = "hit,tx23d38vm0caa", 3558 .data = &hitachi_tx23d38vm0caa 3559 }, { 3560 .compatible = "innolux,at043tn24", 3561 .data = &innolux_at043tn24, 3562 }, { 3563 .compatible = "innolux,at070tn92", 3564 .data = &innolux_at070tn92, 3565 }, { 3566 .compatible = "innolux,g070y2-l01", 3567 .data = &innolux_g070y2_l01, 3568 }, { 3569 .compatible = "innolux,g101ice-l01", 3570 .data = &innolux_g101ice_l01 3571 }, { 3572 .compatible = "innolux,g121i1-l01", 3573 .data = &innolux_g121i1_l01 3574 }, { 3575 .compatible = "innolux,g121x1-l03", 3576 .data = &innolux_g121x1_l03, 3577 }, { 3578 .compatible = "innolux,n116bge", 3579 .data = &innolux_n116bge, 3580 }, { 3581 .compatible = "innolux,n156bge-l21", 3582 .data = &innolux_n156bge_l21, 3583 }, { 3584 .compatible = "innolux,p120zdg-bf1", 3585 .data = &innolux_p120zdg_bf1, 3586 }, { 3587 .compatible = "innolux,zj070na-01p", 3588 .data = &innolux_zj070na_01p, 3589 }, { 3590 .compatible = "koe,tx14d24vm1bpa", 3591 .data = &koe_tx14d24vm1bpa, 3592 }, { 3593 .compatible = "koe,tx31d200vm0baa", 3594 .data = &koe_tx31d200vm0baa, 3595 }, { 3596 .compatible = "kyo,tcg121xglp", 3597 .data = &kyo_tcg121xglp, 3598 }, { 3599 .compatible = "lemaker,bl035-rgb-002", 3600 .data = &lemaker_bl035_rgb_002, 3601 }, { 3602 .compatible = "lg,lb070wv8", 3603 .data = &lg_lb070wv8, 3604 }, { 3605 .compatible = "lg,lp079qx1-sp0v", 3606 .data = &lg_lp079qx1_sp0v, 3607 }, { 3608 .compatible = "lg,lp097qx1-spa1", 3609 .data = &lg_lp097qx1_spa1, 3610 }, { 3611 .compatible = "lg,lp120up1", 3612 .data = &lg_lp120up1, 3613 }, { 3614 .compatible = "lg,lp129qe", 3615 .data = &lg_lp129qe, 3616 }, { 3617 .compatible = "logicpd,type28", 3618 .data = &logicpd_type_28, 3619 }, { 3620 .compatible = "logictechno,lt161010-2nhc", 3621 .data = &logictechno_lt161010_2nh, 3622 }, { 3623 .compatible = "logictechno,lt161010-2nhr", 3624 .data = &logictechno_lt161010_2nh, 3625 }, { 3626 .compatible = "logictechno,lt170410-2whc", 3627 .data = &logictechno_lt170410_2whc, 3628 }, { 3629 .compatible = "mitsubishi,aa070mc01-ca1", 3630 .data = &mitsubishi_aa070mc01, 3631 }, { 3632 .compatible = "nec,nl12880bc20-05", 3633 .data = &nec_nl12880bc20_05, 3634 }, { 3635 .compatible = "nec,nl4827hc19-05b", 3636 .data = &nec_nl4827hc19_05b, 3637 }, { 3638 .compatible = "netron-dy,e231732", 3639 .data = &netron_dy_e231732, 3640 }, { 3641 .compatible = "neweast,wjfh116008a", 3642 .data = &neweast_wjfh116008a, 3643 }, { 3644 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 3645 .data = &newhaven_nhd_43_480272ef_atxl, 3646 }, { 3647 .compatible = "nlt,nl192108ac18-02d", 3648 .data = &nlt_nl192108ac18_02d, 3649 }, { 3650 .compatible = "nvd,9128", 3651 .data = &nvd_9128, 3652 }, { 3653 .compatible = "okaya,rs800480t-7x0gp", 3654 .data = &okaya_rs800480t_7x0gp, 3655 }, { 3656 .compatible = "olimex,lcd-olinuxino-43-ts", 3657 .data = &olimex_lcd_olinuxino_43ts, 3658 }, { 3659 .compatible = "ontat,yx700wv03", 3660 .data = &ontat_yx700wv03, 3661 }, { 3662 .compatible = "ortustech,com37h3m05dtc", 3663 .data = &ortustech_com37h3m, 3664 }, { 3665 .compatible = "ortustech,com37h3m99dtc", 3666 .data = &ortustech_com37h3m, 3667 }, { 3668 .compatible = "ortustech,com43h4m85ulc", 3669 .data = &ortustech_com43h4m85ulc, 3670 }, { 3671 .compatible = "osddisplays,osd070t1718-19ts", 3672 .data = &osddisplays_osd070t1718_19ts, 3673 }, { 3674 .compatible = "pda,91-00156-a0", 3675 .data = &pda_91_00156_a0, 3676 }, { 3677 .compatible = "qiaodian,qd43003c0-40", 3678 .data = &qd43003c0_40, 3679 }, { 3680 .compatible = "rocktech,rk070er9427", 3681 .data = &rocktech_rk070er9427, 3682 }, { 3683 .compatible = "rocktech,rk101ii01d-ct", 3684 .data = &rocktech_rk101ii01d_ct, 3685 }, { 3686 .compatible = "samsung,lsn122dl01-c01", 3687 .data = &samsung_lsn122dl01_c01, 3688 }, { 3689 .compatible = "samsung,ltn101nt05", 3690 .data = &samsung_ltn101nt05, 3691 }, { 3692 .compatible = "samsung,ltn140at29-301", 3693 .data = &samsung_ltn140at29_301, 3694 }, { 3695 .compatible = "satoz,sat050at40h12r2", 3696 .data = &satoz_sat050at40h12r2, 3697 }, { 3698 .compatible = "sharp,ld-d5116z01b", 3699 .data = &sharp_ld_d5116z01b, 3700 }, { 3701 .compatible = "sharp,lq035q7db03", 3702 .data = &sharp_lq035q7db03, 3703 }, { 3704 .compatible = "sharp,lq070y3dg3b", 3705 .data = &sharp_lq070y3dg3b, 3706 }, { 3707 .compatible = "sharp,lq101k1ly04", 3708 .data = &sharp_lq101k1ly04, 3709 }, { 3710 .compatible = "sharp,lq123p1jx31", 3711 .data = &sharp_lq123p1jx31, 3712 }, { 3713 .compatible = "sharp,ls020b1dd01d", 3714 .data = &sharp_ls020b1dd01d, 3715 }, { 3716 .compatible = "shelly,sca07010-bfn-lnn", 3717 .data = &shelly_sca07010_bfn_lnn, 3718 }, { 3719 .compatible = "starry,kr122ea0sra", 3720 .data = &starry_kr122ea0sra, 3721 }, { 3722 .compatible = "tfc,s9700rtwv43tr-01b", 3723 .data = &tfc_s9700rtwv43tr_01b, 3724 }, { 3725 .compatible = "tianma,tm070jdhg30", 3726 .data = &tianma_tm070jdhg30, 3727 }, { 3728 .compatible = "tianma,tm070rvhg71", 3729 .data = &tianma_tm070rvhg71, 3730 }, { 3731 .compatible = "ti,nspire-cx-lcd-panel", 3732 .data = &ti_nspire_cx_lcd_panel, 3733 }, { 3734 .compatible = "ti,nspire-classic-lcd-panel", 3735 .data = &ti_nspire_classic_lcd_panel, 3736 }, { 3737 .compatible = "toshiba,lt089ac29000", 3738 .data = &toshiba_lt089ac29000, 3739 }, { 3740 .compatible = "tpk,f07a-0102", 3741 .data = &tpk_f07a_0102, 3742 }, { 3743 .compatible = "tpk,f10a-0102", 3744 .data = &tpk_f10a_0102, 3745 }, { 3746 .compatible = "urt,umsh-8596md-t", 3747 .data = &urt_umsh_8596md_parallel, 3748 }, { 3749 .compatible = "urt,umsh-8596md-1t", 3750 .data = &urt_umsh_8596md_parallel, 3751 }, { 3752 .compatible = "urt,umsh-8596md-7t", 3753 .data = &urt_umsh_8596md_parallel, 3754 }, { 3755 .compatible = "urt,umsh-8596md-11t", 3756 .data = &urt_umsh_8596md_lvds, 3757 }, { 3758 .compatible = "urt,umsh-8596md-19t", 3759 .data = &urt_umsh_8596md_lvds, 3760 }, { 3761 .compatible = "urt,umsh-8596md-20t", 3762 .data = &urt_umsh_8596md_parallel, 3763 }, { 3764 .compatible = "vxt,vl050-8048nt-c01", 3765 .data = &vl050_8048nt_c01, 3766 }, { 3767 .compatible = "winstar,wf35ltiacd", 3768 .data = &winstar_wf35ltiacd, 3769 }, { 3770 /* Must be the last entry */ 3771 .compatible = "panel-dpi", 3772 .data = &panel_dpi, 3773 }, { 3774 /* sentinel */ 3775 } 3776 }; 3777 MODULE_DEVICE_TABLE(of, platform_of_match); 3778 3779 static int panel_simple_platform_probe(struct platform_device *pdev) 3780 { 3781 const struct of_device_id *id; 3782 3783 id = of_match_node(platform_of_match, pdev->dev.of_node); 3784 if (!id) 3785 return -ENODEV; 3786 3787 return panel_simple_probe(&pdev->dev, id->data); 3788 } 3789 3790 static int panel_simple_platform_remove(struct platform_device *pdev) 3791 { 3792 return panel_simple_remove(&pdev->dev); 3793 } 3794 3795 static void panel_simple_platform_shutdown(struct platform_device *pdev) 3796 { 3797 panel_simple_shutdown(&pdev->dev); 3798 } 3799 3800 static struct platform_driver panel_simple_platform_driver = { 3801 .driver = { 3802 .name = "panel-simple", 3803 .of_match_table = platform_of_match, 3804 }, 3805 .probe = panel_simple_platform_probe, 3806 .remove = panel_simple_platform_remove, 3807 .shutdown = panel_simple_platform_shutdown, 3808 }; 3809 3810 struct panel_desc_dsi { 3811 struct panel_desc desc; 3812 3813 unsigned long flags; 3814 enum mipi_dsi_pixel_format format; 3815 unsigned int lanes; 3816 }; 3817 3818 static const struct drm_display_mode auo_b080uan01_mode = { 3819 .clock = 154500, 3820 .hdisplay = 1200, 3821 .hsync_start = 1200 + 62, 3822 .hsync_end = 1200 + 62 + 4, 3823 .htotal = 1200 + 62 + 4 + 62, 3824 .vdisplay = 1920, 3825 .vsync_start = 1920 + 9, 3826 .vsync_end = 1920 + 9 + 2, 3827 .vtotal = 1920 + 9 + 2 + 8, 3828 .vrefresh = 60, 3829 }; 3830 3831 static const struct panel_desc_dsi auo_b080uan01 = { 3832 .desc = { 3833 .modes = &auo_b080uan01_mode, 3834 .num_modes = 1, 3835 .bpc = 8, 3836 .size = { 3837 .width = 108, 3838 .height = 272, 3839 }, 3840 }, 3841 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 3842 .format = MIPI_DSI_FMT_RGB888, 3843 .lanes = 4, 3844 }; 3845 3846 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 3847 .clock = 160000, 3848 .hdisplay = 1200, 3849 .hsync_start = 1200 + 120, 3850 .hsync_end = 1200 + 120 + 20, 3851 .htotal = 1200 + 120 + 20 + 21, 3852 .vdisplay = 1920, 3853 .vsync_start = 1920 + 21, 3854 .vsync_end = 1920 + 21 + 3, 3855 .vtotal = 1920 + 21 + 3 + 18, 3856 .vrefresh = 60, 3857 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3858 }; 3859 3860 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 3861 .desc = { 3862 .modes = &boe_tv080wum_nl0_mode, 3863 .num_modes = 1, 3864 .size = { 3865 .width = 107, 3866 .height = 172, 3867 }, 3868 }, 3869 .flags = MIPI_DSI_MODE_VIDEO | 3870 MIPI_DSI_MODE_VIDEO_BURST | 3871 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 3872 .format = MIPI_DSI_FMT_RGB888, 3873 .lanes = 4, 3874 }; 3875 3876 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 3877 .clock = 71000, 3878 .hdisplay = 800, 3879 .hsync_start = 800 + 32, 3880 .hsync_end = 800 + 32 + 1, 3881 .htotal = 800 + 32 + 1 + 57, 3882 .vdisplay = 1280, 3883 .vsync_start = 1280 + 28, 3884 .vsync_end = 1280 + 28 + 1, 3885 .vtotal = 1280 + 28 + 1 + 14, 3886 .vrefresh = 60, 3887 }; 3888 3889 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 3890 .desc = { 3891 .modes = &lg_ld070wx3_sl01_mode, 3892 .num_modes = 1, 3893 .bpc = 8, 3894 .size = { 3895 .width = 94, 3896 .height = 151, 3897 }, 3898 }, 3899 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 3900 .format = MIPI_DSI_FMT_RGB888, 3901 .lanes = 4, 3902 }; 3903 3904 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 3905 .clock = 67000, 3906 .hdisplay = 720, 3907 .hsync_start = 720 + 12, 3908 .hsync_end = 720 + 12 + 4, 3909 .htotal = 720 + 12 + 4 + 112, 3910 .vdisplay = 1280, 3911 .vsync_start = 1280 + 8, 3912 .vsync_end = 1280 + 8 + 4, 3913 .vtotal = 1280 + 8 + 4 + 12, 3914 .vrefresh = 60, 3915 }; 3916 3917 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 3918 .desc = { 3919 .modes = &lg_lh500wx1_sd03_mode, 3920 .num_modes = 1, 3921 .bpc = 8, 3922 .size = { 3923 .width = 62, 3924 .height = 110, 3925 }, 3926 }, 3927 .flags = MIPI_DSI_MODE_VIDEO, 3928 .format = MIPI_DSI_FMT_RGB888, 3929 .lanes = 4, 3930 }; 3931 3932 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 3933 .clock = 157200, 3934 .hdisplay = 1920, 3935 .hsync_start = 1920 + 154, 3936 .hsync_end = 1920 + 154 + 16, 3937 .htotal = 1920 + 154 + 16 + 32, 3938 .vdisplay = 1200, 3939 .vsync_start = 1200 + 17, 3940 .vsync_end = 1200 + 17 + 2, 3941 .vtotal = 1200 + 17 + 2 + 16, 3942 .vrefresh = 60, 3943 }; 3944 3945 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 3946 .desc = { 3947 .modes = &panasonic_vvx10f004b00_mode, 3948 .num_modes = 1, 3949 .bpc = 8, 3950 .size = { 3951 .width = 217, 3952 .height = 136, 3953 }, 3954 }, 3955 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 3956 MIPI_DSI_CLOCK_NON_CONTINUOUS, 3957 .format = MIPI_DSI_FMT_RGB888, 3958 .lanes = 4, 3959 }; 3960 3961 static const struct drm_display_mode lg_acx467akm_7_mode = { 3962 .clock = 150000, 3963 .hdisplay = 1080, 3964 .hsync_start = 1080 + 2, 3965 .hsync_end = 1080 + 2 + 2, 3966 .htotal = 1080 + 2 + 2 + 2, 3967 .vdisplay = 1920, 3968 .vsync_start = 1920 + 2, 3969 .vsync_end = 1920 + 2 + 2, 3970 .vtotal = 1920 + 2 + 2 + 2, 3971 .vrefresh = 60, 3972 }; 3973 3974 static const struct panel_desc_dsi lg_acx467akm_7 = { 3975 .desc = { 3976 .modes = &lg_acx467akm_7_mode, 3977 .num_modes = 1, 3978 .bpc = 8, 3979 .size = { 3980 .width = 62, 3981 .height = 110, 3982 }, 3983 }, 3984 .flags = 0, 3985 .format = MIPI_DSI_FMT_RGB888, 3986 .lanes = 4, 3987 }; 3988 3989 static const struct drm_display_mode osd101t2045_53ts_mode = { 3990 .clock = 154500, 3991 .hdisplay = 1920, 3992 .hsync_start = 1920 + 112, 3993 .hsync_end = 1920 + 112 + 16, 3994 .htotal = 1920 + 112 + 16 + 32, 3995 .vdisplay = 1200, 3996 .vsync_start = 1200 + 16, 3997 .vsync_end = 1200 + 16 + 2, 3998 .vtotal = 1200 + 16 + 2 + 16, 3999 .vrefresh = 60, 4000 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4001 }; 4002 4003 static const struct panel_desc_dsi osd101t2045_53ts = { 4004 .desc = { 4005 .modes = &osd101t2045_53ts_mode, 4006 .num_modes = 1, 4007 .bpc = 8, 4008 .size = { 4009 .width = 217, 4010 .height = 136, 4011 }, 4012 }, 4013 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4014 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4015 MIPI_DSI_MODE_EOT_PACKET, 4016 .format = MIPI_DSI_FMT_RGB888, 4017 .lanes = 4, 4018 }; 4019 4020 static const struct of_device_id dsi_of_match[] = { 4021 { 4022 .compatible = "auo,b080uan01", 4023 .data = &auo_b080uan01 4024 }, { 4025 .compatible = "boe,tv080wum-nl0", 4026 .data = &boe_tv080wum_nl0 4027 }, { 4028 .compatible = "lg,ld070wx3-sl01", 4029 .data = &lg_ld070wx3_sl01 4030 }, { 4031 .compatible = "lg,lh500wx1-sd03", 4032 .data = &lg_lh500wx1_sd03 4033 }, { 4034 .compatible = "panasonic,vvx10f004b00", 4035 .data = &panasonic_vvx10f004b00 4036 }, { 4037 .compatible = "lg,acx467akm-7", 4038 .data = &lg_acx467akm_7 4039 }, { 4040 .compatible = "osddisplays,osd101t2045-53ts", 4041 .data = &osd101t2045_53ts 4042 }, { 4043 /* sentinel */ 4044 } 4045 }; 4046 MODULE_DEVICE_TABLE(of, dsi_of_match); 4047 4048 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4049 { 4050 const struct panel_desc_dsi *desc; 4051 const struct of_device_id *id; 4052 int err; 4053 4054 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4055 if (!id) 4056 return -ENODEV; 4057 4058 desc = id->data; 4059 4060 err = panel_simple_probe(&dsi->dev, &desc->desc); 4061 if (err < 0) 4062 return err; 4063 4064 dsi->mode_flags = desc->flags; 4065 dsi->format = desc->format; 4066 dsi->lanes = desc->lanes; 4067 4068 err = mipi_dsi_attach(dsi); 4069 if (err) { 4070 struct panel_simple *panel = dev_get_drvdata(&dsi->dev); 4071 4072 drm_panel_remove(&panel->base); 4073 } 4074 4075 return err; 4076 } 4077 4078 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4079 { 4080 int err; 4081 4082 err = mipi_dsi_detach(dsi); 4083 if (err < 0) 4084 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4085 4086 return panel_simple_remove(&dsi->dev); 4087 } 4088 4089 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4090 { 4091 panel_simple_shutdown(&dsi->dev); 4092 } 4093 4094 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4095 .driver = { 4096 .name = "panel-simple-dsi", 4097 .of_match_table = dsi_of_match, 4098 }, 4099 .probe = panel_simple_dsi_probe, 4100 .remove = panel_simple_dsi_remove, 4101 .shutdown = panel_simple_dsi_shutdown, 4102 }; 4103 4104 static int __init panel_simple_init(void) 4105 { 4106 int err; 4107 4108 err = platform_driver_register(&panel_simple_platform_driver); 4109 if (err < 0) 4110 return err; 4111 4112 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4113 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4114 if (err < 0) 4115 return err; 4116 } 4117 4118 return 0; 4119 } 4120 module_init(panel_simple_init); 4121 4122 static void __exit panel_simple_exit(void) 4123 { 4124 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4125 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4126 4127 platform_driver_unregister(&panel_simple_platform_driver); 4128 } 4129 module_exit(panel_simple_exit); 4130 4131 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4132 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4133 MODULE_LICENSE("GPL and additional rights"); 4134