1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_FW_H_ 6 #define __RTW_FW_H_ 7 8 #define H2C_PKT_SIZE 32 9 #define H2C_PKT_HDR_SIZE 8 10 11 /* FW bin information */ 12 #define FW_HDR_SIZE 64 13 #define FW_HDR_CHKSUM_SIZE 8 14 15 #define FW_NLO_INFO_CHECK_SIZE 4 16 17 #define FIFO_PAGE_SIZE_SHIFT 12 18 #define FIFO_PAGE_SIZE 4096 19 #define RSVD_PAGE_START_ADDR 0x780 20 #define FIFO_DUMP_ADDR 0x8000 21 22 enum rtw_c2h_cmd_id { 23 C2H_BT_INFO = 0x09, 24 C2H_BT_MP_INFO = 0x0b, 25 C2H_RA_RPT = 0x0c, 26 C2H_HW_FEATURE_REPORT = 0x19, 27 C2H_WLAN_INFO = 0x27, 28 C2H_HW_FEATURE_DUMP = 0xfd, 29 C2H_HALMAC = 0xff, 30 }; 31 32 enum rtw_c2h_cmd_id_ext { 33 C2H_CCX_RPT = 0x0f, 34 }; 35 36 struct rtw_c2h_cmd { 37 u8 id; 38 u8 seq; 39 u8 payload[0]; 40 } __packed; 41 42 enum rtw_rsvd_packet_type { 43 RSVD_BEACON, 44 RSVD_PS_POLL, 45 RSVD_PROBE_RESP, 46 RSVD_NULL, 47 RSVD_QOS_NULL, 48 RSVD_LPS_PG_DPK, 49 RSVD_LPS_PG_INFO, 50 RSVD_PROBE_REQ, 51 RSVD_NLO_INFO, 52 RSVD_CH_INFO, 53 }; 54 55 enum rtw_fw_rf_type { 56 FW_RF_1T2R = 0, 57 FW_RF_2T4R = 1, 58 FW_RF_2T2R = 2, 59 FW_RF_2T3R = 3, 60 FW_RF_1T1R = 4, 61 FW_RF_2T2R_GREEN = 5, 62 FW_RF_3T3R = 6, 63 FW_RF_3T4R = 7, 64 FW_RF_4T4R = 8, 65 FW_RF_MAX_TYPE = 0xF, 66 }; 67 68 struct rtw_coex_info_req { 69 u8 seq; 70 u8 op_code; 71 u8 para1; 72 u8 para2; 73 u8 para3; 74 }; 75 76 struct rtw_iqk_para { 77 u8 clear; 78 u8 segment_iqk; 79 }; 80 81 struct rtw_lps_pg_dpk_hdr { 82 u16 dpk_path_ok; 83 u8 dpk_txagc[2]; 84 u16 dpk_gs[2]; 85 u32 coef[2][20]; 86 u8 dpk_ch; 87 } __packed; 88 89 struct rtw_lps_pg_info_hdr { 90 u8 macid; 91 u8 mbssid; 92 u8 pattern_count; 93 u8 mu_tab_group_id; 94 u8 sec_cam_count; 95 u8 tx_bu_page_count; 96 u16 rsvd; 97 u8 sec_cam[MAX_PG_CAM_BACKUP_NUM]; 98 } __packed; 99 100 struct rtw_rsvd_page { 101 struct list_head list; 102 struct sk_buff *skb; 103 enum rtw_rsvd_packet_type type; 104 u8 page; 105 bool add_txdesc; 106 struct cfg80211_ssid *ssid; 107 }; 108 109 enum rtw_keep_alive_pkt_type { 110 KEEP_ALIVE_NULL_PKT = 0, 111 KEEP_ALIVE_ARP_RSP = 1, 112 }; 113 114 struct rtw_nlo_info_hdr { 115 u8 nlo_count; 116 u8 hidden_ap_count; 117 u8 rsvd1[2]; 118 u8 pattern_check[FW_NLO_INFO_CHECK_SIZE]; 119 u8 rsvd2[8]; 120 u8 ssid_len[16]; 121 u8 chiper[16]; 122 u8 rsvd3[16]; 123 u8 location[8]; 124 } __packed; 125 126 enum rtw_packet_type { 127 RTW_PACKET_PROBE_REQ = 0x00, 128 129 RTW_PACKET_UNDEFINE = 0x7FFFFFFF, 130 }; 131 132 struct rtw_fw_wow_keep_alive_para { 133 bool adopt; 134 u8 pkt_type; 135 u8 period; /* unit: sec */ 136 }; 137 138 struct rtw_fw_wow_disconnect_para { 139 bool adopt; 140 u8 period; /* unit: sec */ 141 u8 retry_count; 142 }; 143 144 struct rtw_ch_switch_option { 145 u8 periodic_option; 146 u32 tsf_high; 147 u32 tsf_low; 148 u8 dest_ch_en; 149 u8 absolute_time_en; 150 u8 dest_ch; 151 u8 normal_period; 152 u8 normal_period_sel; 153 u8 normal_cycle; 154 u8 slow_period; 155 u8 slow_period_sel; 156 u8 nlo_en; 157 }; 158 159 struct rtw_fw_hdr { 160 __le16 signature; 161 u8 category; 162 u8 function; 163 __le16 version; /* 0x04 */ 164 u8 subversion; 165 u8 subindex; 166 __le32 rsvd; /* 0x08 */ 167 __le32 rsvd2; /* 0x0C */ 168 u8 month; /* 0x10 */ 169 u8 day; 170 u8 hour; 171 u8 min; 172 __le16 year; /* 0x14 */ 173 __le16 rsvd3; 174 u8 mem_usage; /* 0x18 */ 175 u8 rsvd4[3]; 176 __le16 h2c_fmt_ver; /* 0x1C */ 177 __le16 rsvd5; 178 __le32 dmem_addr; /* 0x20 */ 179 __le32 dmem_size; 180 __le32 rsvd6; 181 __le32 rsvd7; 182 __le32 imem_size; /* 0x30 */ 183 __le32 emem_size; 184 __le32 emem_addr; 185 __le32 imem_addr; 186 } __packed; 187 188 /* C2H */ 189 #define GET_CCX_REPORT_SEQNUM(c2h_payload) (c2h_payload[8] & 0xfc) 190 #define GET_CCX_REPORT_STATUS(c2h_payload) (c2h_payload[9] & 0xc0) 191 192 #define GET_RA_REPORT_RATE(c2h_payload) (c2h_payload[0] & 0x7f) 193 #define GET_RA_REPORT_SGI(c2h_payload) ((c2h_payload[0] & 0x80) >> 7) 194 #define GET_RA_REPORT_BW(c2h_payload) (c2h_payload[6]) 195 #define GET_RA_REPORT_MACID(c2h_payload) (c2h_payload[1]) 196 197 /* PKT H2C */ 198 #define H2C_PKT_CMD_ID 0xFF 199 #define H2C_PKT_CATEGORY 0x01 200 201 #define H2C_PKT_GENERAL_INFO 0x0D 202 #define H2C_PKT_PHYDM_INFO 0x11 203 #define H2C_PKT_IQK 0x0E 204 205 #define H2C_PKT_CH_SWITCH 0x02 206 #define H2C_PKT_UPDATE_PKT 0x0C 207 208 #define H2C_PKT_CH_SWITCH_LEN 0x20 209 #define H2C_PKT_UPDATE_PKT_LEN 0x4 210 211 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ 212 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0)) 213 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ 214 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 215 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ 216 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16)) 217 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ 218 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0)) 219 220 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id) 221 { 222 SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY); 223 SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID); 224 SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id); 225 } 226 227 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ 228 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16)) 229 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ 230 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 231 232 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ 233 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0)) 234 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ 235 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 236 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ 237 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 238 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ 239 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 240 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \ 241 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28)) 242 #define IQK_SET_CLEAR(h2c_pkt, value) \ 243 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 244 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \ 245 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 246 247 #define CHSW_INFO_SET_CH(pkt, value) \ 248 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0)) 249 #define CHSW_INFO_SET_PRI_CH_IDX(pkt, value) \ 250 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8)) 251 #define CHSW_INFO_SET_BW(pkt, value) \ 252 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12)) 253 #define CHSW_INFO_SET_TIMEOUT(pkt, value) \ 254 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16)) 255 #define CHSW_INFO_SET_ACTION_ID(pkt, value) \ 256 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24)) 257 258 #define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \ 259 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0)) 260 #define UPDATE_PKT_SET_PKT_ID(h2c_pkt, value) \ 261 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 262 #define UPDATE_PKT_SET_LOCATION(h2c_pkt, value) \ 263 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24)) 264 265 #define CH_SWITCH_SET_START(h2c_pkt, value) \ 266 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 267 #define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \ 268 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 269 #define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \ 270 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2)) 271 #define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \ 272 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3)) 273 #define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \ 274 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 275 #define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \ 276 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 277 #define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \ 278 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 279 #define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \ 280 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0)) 281 #define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \ 282 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8)) 283 #define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \ 284 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14)) 285 #define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \ 286 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16)) 287 #define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \ 288 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22)) 289 #define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \ 290 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24)) 291 #define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \ 292 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0)) 293 #define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \ 294 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0)) 295 #define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \ 296 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0)) 297 298 /* Command H2C */ 299 #define H2C_CMD_RSVD_PAGE 0x0 300 #define H2C_CMD_MEDIA_STATUS_RPT 0x01 301 #define H2C_CMD_SET_PWR_MODE 0x20 302 #define H2C_CMD_LPS_PG_INFO 0x2b 303 #define H2C_CMD_RA_INFO 0x40 304 #define H2C_CMD_RSSI_MONITOR 0x42 305 306 #define H2C_CMD_COEX_TDMA_TYPE 0x60 307 #define H2C_CMD_QUERY_BT_INFO 0x61 308 #define H2C_CMD_FORCE_BT_TX_POWER 0x62 309 #define H2C_CMD_IGNORE_WLAN_ACTION 0x63 310 #define H2C_CMD_WL_CH_INFO 0x66 311 #define H2C_CMD_QUERY_BT_MP_INFO 0x67 312 #define H2C_CMD_BT_WIFI_CONTROL 0x69 313 314 #define H2C_CMD_KEEP_ALIVE 0x03 315 #define H2C_CMD_DISCONNECT_DECISION 0x04 316 #define H2C_CMD_WOWLAN 0x80 317 #define H2C_CMD_REMOTE_WAKE_CTRL 0x81 318 #define H2C_CMD_AOAC_GLOBAL_INFO 0x82 319 #define H2C_CMD_NLO_INFO 0x8C 320 321 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \ 322 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0)) 323 324 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \ 325 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 326 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \ 327 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 328 329 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \ 330 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8)) 331 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \ 332 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16)) 333 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \ 334 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20)) 335 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \ 336 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 337 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \ 338 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5)) 339 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \ 340 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 341 #define LPS_PG_INFO_LOC(h2c_pkt, value) \ 342 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 343 #define LPS_PG_DPK_LOC(h2c_pkt, value) \ 344 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 345 #define LPS_PG_SEC_CAM_EN(h2c_pkt, value) \ 346 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 347 #define LPS_PG_PATTERN_CAM_EN(h2c_pkt, value) \ 348 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 349 #define SET_RSSI_INFO_MACID(h2c_pkt, value) \ 350 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 351 #define SET_RSSI_INFO_RSSI(h2c_pkt, value) \ 352 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 353 #define SET_RSSI_INFO_STBC(h2c_pkt, value) \ 354 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1)) 355 #define SET_RA_INFO_MACID(h2c_pkt, value) \ 356 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 357 #define SET_RA_INFO_RATE_ID(h2c_pkt, value) \ 358 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16)) 359 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value) \ 360 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21)) 361 #define SET_RA_INFO_SGI_EN(h2c_pkt, value) \ 362 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23)) 363 #define SET_RA_INFO_BW_MODE(h2c_pkt, value) \ 364 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24)) 365 #define SET_RA_INFO_LDPC(h2c_pkt, value) \ 366 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26)) 367 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value) \ 368 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27)) 369 #define SET_RA_INFO_VHT_EN(h2c_pkt, value) \ 370 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28)) 371 #define SET_RA_INFO_DIS_PT(h2c_pkt, value) \ 372 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30)) 373 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value) \ 374 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 375 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value) \ 376 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 377 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value) \ 378 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 379 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \ 380 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24)) 381 #define SET_QUERY_BT_INFO(h2c_pkt, value) \ 382 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 383 #define SET_WL_CH_INFO_LINK(h2c_pkt, value) \ 384 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 385 #define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \ 386 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 387 #define SET_WL_CH_INFO_BW(h2c_pkt, value) \ 388 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 389 #define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \ 390 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12)) 391 #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \ 392 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 393 #define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \ 394 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 395 #define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \ 396 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 397 #define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \ 398 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 399 #define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \ 400 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 401 #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \ 402 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 403 #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \ 404 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 405 #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \ 406 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 407 #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \ 408 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 409 #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \ 410 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 411 #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \ 412 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 413 #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \ 414 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 415 #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \ 416 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 417 #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \ 418 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 419 #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \ 420 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 421 #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \ 422 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 423 #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \ 424 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 425 426 #define SET_KEEP_ALIVE_ENABLE(h2c_pkt, value) \ 427 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 428 #define SET_KEEP_ALIVE_ADOPT(h2c_pkt, value) \ 429 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 430 #define SET_KEEP_ALIVE_PKT_TYPE(h2c_pkt, value) \ 431 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 432 #define SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \ 433 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 434 435 #define SET_DISCONNECT_DECISION_ENABLE(h2c_pkt, value) \ 436 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 437 #define SET_DISCONNECT_DECISION_ADOPT(h2c_pkt, value) \ 438 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 439 #define SET_DISCONNECT_DECISION_CHECK_PERIOD(h2c_pkt, value) \ 440 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 441 #define SET_DISCONNECT_DECISION_TRY_PKT_NUM(h2c_pkt, value) \ 442 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 443 444 #define SET_WOWLAN_FUNC_ENABLE(h2c_pkt, value) \ 445 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 446 #define SET_WOWLAN_PATTERN_MATCH_ENABLE(h2c_pkt, value) \ 447 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 448 #define SET_WOWLAN_MAGIC_PKT_ENABLE(h2c_pkt, value) \ 449 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 450 #define SET_WOWLAN_UNICAST_PKT_ENABLE(h2c_pkt, value) \ 451 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(11)) 452 #define SET_WOWLAN_REKEY_WAKEUP_ENABLE(h2c_pkt, value) \ 453 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(14)) 454 #define SET_WOWLAN_DEAUTH_WAKEUP_ENABLE(h2c_pkt, value) \ 455 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(15)) 456 457 #define SET_REMOTE_WAKECTRL_ENABLE(h2c_pkt, value) \ 458 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 459 #define SET_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(h2c_pkt, value) \ 460 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(12)) 461 462 #define SET_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(h2c_pkt, value) \ 463 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 464 #define SET_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(h2c_pkt, value) \ 465 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 466 467 #define SET_NLO_FUN_EN(h2c_pkt, value) \ 468 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 469 #define SET_NLO_PS_32K(h2c_pkt, value) \ 470 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 471 #define SET_NLO_IGNORE_SECURITY(h2c_pkt, value) \ 472 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 473 #define SET_NLO_LOC_NLO_INFO(h2c_pkt, value) \ 474 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 475 476 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb) 477 { 478 u32 pkt_offset; 479 480 pkt_offset = *((u32 *)skb->cb); 481 return (struct rtw_c2h_cmd *)(skb->data + pkt_offset); 482 } 483 484 void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset, 485 struct sk_buff *skb); 486 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb); 487 void rtw_fw_send_general_info(struct rtw_dev *rtwdev); 488 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev); 489 490 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para); 491 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev); 492 void rtw_fw_set_pg_info(struct rtw_dev *rtwdev); 493 void rtw_fw_query_bt_info(struct rtw_dev *rtwdev); 494 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw); 495 void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev, 496 struct rtw_coex_info_req *req); 497 void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl); 498 void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable); 499 void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev, 500 u8 para1, u8 para2, u8 para3, u8 para4, u8 para5); 501 void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data); 502 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 503 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 504 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn); 505 void rtw_add_rsvd_page(struct rtw_dev *rtwdev, enum rtw_rsvd_packet_type type, 506 bool txdesc); 507 void rtw_add_rsvd_page_probe_req(struct rtw_dev *rtwdev, 508 struct cfg80211_ssid *ssid); 509 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 510 u8 *buf, u32 size); 511 void rtw_reset_rsvd_page(struct rtw_dev *rtwdev); 512 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev, 513 struct ieee80211_vif *vif); 514 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev); 515 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev, 516 u32 offset, u32 size, u32 *buf); 517 void rtw_fw_set_remote_wake_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); 518 void rtw_fw_set_wowlan_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); 519 void rtw_fw_set_keep_alive_cmd(struct rtw_dev *rtwdev, bool enable); 520 void rtw_fw_set_disconnect_decision_cmd(struct rtw_dev *rtwdev, bool enable); 521 void rtw_fw_set_aoac_global_info_cmd(struct rtw_dev *rtwdev, 522 u8 pairwise_key_enc, 523 u8 group_key_enc); 524 525 void rtw_fw_set_nlo_info(struct rtw_dev *rtwdev, bool enable); 526 void rtw_fw_update_pkt_probe_req(struct rtw_dev *rtwdev, 527 struct cfg80211_ssid *ssid); 528 void rtw_fw_channel_switch(struct rtw_dev *rtwdev, bool enable); 529 #endif 530