1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3 
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
9 #endif
10 #include <linux/if_vlan.h>
11 #include <linux/ip.h>
12 #include <linux/ipv6.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/aer.h>
16 #include <linux/skbuff.h>
17 #include <linux/sctp.h>
18 #include <net/gre.h>
19 #include <net/ip6_checksum.h>
20 #include <net/pkt_cls.h>
21 #include <net/tcp.h>
22 #include <net/vxlan.h>
23 
24 #include "hnae3.h"
25 #include "hns3_enet.h"
26 /* All hns3 tracepoints are defined by the include below, which
27  * must be included exactly once across the whole kernel with
28  * CREATE_TRACE_POINTS defined
29  */
30 #define CREATE_TRACE_POINTS
31 #include "hns3_trace.h"
32 
33 #define hns3_set_field(origin, shift, val)	((origin) |= ((val) << (shift)))
34 #define hns3_tx_bd_count(S)	DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
35 
36 #define hns3_rl_err(fmt, ...)						\
37 	do {								\
38 		if (net_ratelimit())					\
39 			netdev_err(fmt, ##__VA_ARGS__);			\
40 	} while (0)
41 
42 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
43 
44 static const char hns3_driver_name[] = "hns3";
45 static const char hns3_driver_string[] =
46 			"Hisilicon Ethernet Network Driver for Hip08 Family";
47 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
48 static struct hnae3_client client;
49 
50 static int debug = -1;
51 module_param(debug, int, 0);
52 MODULE_PARM_DESC(debug, " Network interface message level setting");
53 
54 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
55 			   NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
56 
57 #define HNS3_INNER_VLAN_TAG	1
58 #define HNS3_OUTER_VLAN_TAG	2
59 
60 #define HNS3_MIN_TX_LEN		33U
61 
62 /* hns3_pci_tbl - PCI Device ID Table
63  *
64  * Last entry must be all 0s
65  *
66  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67  *   Class, Class Mask, private data (not used) }
68  */
69 static const struct pci_device_id hns3_pci_tbl[] = {
70 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
71 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
72 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
73 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
74 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
75 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
77 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
78 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
79 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
80 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
81 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
82 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
83 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
84 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
85 	/* required last entry */
86 	{0, }
87 };
88 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
89 
90 static irqreturn_t hns3_irq_handle(int irq, void *vector)
91 {
92 	struct hns3_enet_tqp_vector *tqp_vector = vector;
93 
94 	napi_schedule_irqoff(&tqp_vector->napi);
95 
96 	return IRQ_HANDLED;
97 }
98 
99 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
100 {
101 	struct hns3_enet_tqp_vector *tqp_vectors;
102 	unsigned int i;
103 
104 	for (i = 0; i < priv->vector_num; i++) {
105 		tqp_vectors = &priv->tqp_vector[i];
106 
107 		if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
108 			continue;
109 
110 		/* clear the affinity mask */
111 		irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
112 
113 		/* release the irq resource */
114 		free_irq(tqp_vectors->vector_irq, tqp_vectors);
115 		tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
116 	}
117 }
118 
119 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
120 {
121 	struct hns3_enet_tqp_vector *tqp_vectors;
122 	int txrx_int_idx = 0;
123 	int rx_int_idx = 0;
124 	int tx_int_idx = 0;
125 	unsigned int i;
126 	int ret;
127 
128 	for (i = 0; i < priv->vector_num; i++) {
129 		tqp_vectors = &priv->tqp_vector[i];
130 
131 		if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
132 			continue;
133 
134 		if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
135 			snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
136 				 "%s-%s-%s-%d", hns3_driver_name,
137 				 pci_name(priv->ae_handle->pdev),
138 				 "TxRx", txrx_int_idx++);
139 			txrx_int_idx++;
140 		} else if (tqp_vectors->rx_group.ring) {
141 			snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
142 				 "%s-%s-%s-%d", hns3_driver_name,
143 				 pci_name(priv->ae_handle->pdev),
144 				 "Rx", rx_int_idx++);
145 		} else if (tqp_vectors->tx_group.ring) {
146 			snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
147 				 "%s-%s-%s-%d", hns3_driver_name,
148 				 pci_name(priv->ae_handle->pdev),
149 				 "Tx", tx_int_idx++);
150 		} else {
151 			/* Skip this unused q_vector */
152 			continue;
153 		}
154 
155 		tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
156 
157 		ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
158 				  tqp_vectors->name, tqp_vectors);
159 		if (ret) {
160 			netdev_err(priv->netdev, "request irq(%d) fail\n",
161 				   tqp_vectors->vector_irq);
162 			hns3_nic_uninit_irq(priv);
163 			return ret;
164 		}
165 
166 		disable_irq(tqp_vectors->vector_irq);
167 
168 		irq_set_affinity_hint(tqp_vectors->vector_irq,
169 				      &tqp_vectors->affinity_mask);
170 
171 		tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
172 	}
173 
174 	return 0;
175 }
176 
177 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
178 				 u32 mask_en)
179 {
180 	writel(mask_en, tqp_vector->mask_addr);
181 }
182 
183 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
184 {
185 	napi_enable(&tqp_vector->napi);
186 	enable_irq(tqp_vector->vector_irq);
187 
188 	/* enable vector */
189 	hns3_mask_vector_irq(tqp_vector, 1);
190 }
191 
192 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
193 {
194 	/* disable vector */
195 	hns3_mask_vector_irq(tqp_vector, 0);
196 
197 	disable_irq(tqp_vector->vector_irq);
198 	napi_disable(&tqp_vector->napi);
199 }
200 
201 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
202 				 u32 rl_value)
203 {
204 	u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
205 
206 	/* this defines the configuration for RL (Interrupt Rate Limiter).
207 	 * Rl defines rate of interrupts i.e. number of interrupts-per-second
208 	 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
209 	 */
210 
211 	if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
212 	    !tqp_vector->rx_group.coal.gl_adapt_enable)
213 		/* According to the hardware, the range of rl_reg is
214 		 * 0-59 and the unit is 4.
215 		 */
216 		rl_reg |=  HNS3_INT_RL_ENABLE_MASK;
217 
218 	writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
219 }
220 
221 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
222 				    u32 gl_value)
223 {
224 	u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
225 
226 	writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
227 }
228 
229 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
230 				    u32 gl_value)
231 {
232 	u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
233 
234 	writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
235 }
236 
237 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
238 				   struct hns3_nic_priv *priv)
239 {
240 	/* initialize the configuration for interrupt coalescing.
241 	 * 1. GL (Interrupt Gap Limiter)
242 	 * 2. RL (Interrupt Rate Limiter)
243 	 *
244 	 * Default: enable interrupt coalescing self-adaptive and GL
245 	 */
246 	tqp_vector->tx_group.coal.gl_adapt_enable = 1;
247 	tqp_vector->rx_group.coal.gl_adapt_enable = 1;
248 
249 	tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
250 	tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
251 
252 	tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
253 	tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
254 }
255 
256 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
257 				      struct hns3_nic_priv *priv)
258 {
259 	struct hnae3_handle *h = priv->ae_handle;
260 
261 	hns3_set_vector_coalesce_tx_gl(tqp_vector,
262 				       tqp_vector->tx_group.coal.int_gl);
263 	hns3_set_vector_coalesce_rx_gl(tqp_vector,
264 				       tqp_vector->rx_group.coal.int_gl);
265 	hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
266 }
267 
268 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
269 {
270 	struct hnae3_handle *h = hns3_get_handle(netdev);
271 	struct hnae3_knic_private_info *kinfo = &h->kinfo;
272 	unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
273 	int i, ret;
274 
275 	if (kinfo->num_tc <= 1) {
276 		netdev_reset_tc(netdev);
277 	} else {
278 		ret = netdev_set_num_tc(netdev, kinfo->num_tc);
279 		if (ret) {
280 			netdev_err(netdev,
281 				   "netdev_set_num_tc fail, ret=%d!\n", ret);
282 			return ret;
283 		}
284 
285 		for (i = 0; i < HNAE3_MAX_TC; i++) {
286 			if (!kinfo->tc_info[i].enable)
287 				continue;
288 
289 			netdev_set_tc_queue(netdev,
290 					    kinfo->tc_info[i].tc,
291 					    kinfo->tc_info[i].tqp_count,
292 					    kinfo->tc_info[i].tqp_offset);
293 		}
294 	}
295 
296 	ret = netif_set_real_num_tx_queues(netdev, queue_size);
297 	if (ret) {
298 		netdev_err(netdev,
299 			   "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
300 		return ret;
301 	}
302 
303 	ret = netif_set_real_num_rx_queues(netdev, queue_size);
304 	if (ret) {
305 		netdev_err(netdev,
306 			   "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
307 		return ret;
308 	}
309 
310 	return 0;
311 }
312 
313 static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
314 {
315 	u16 alloc_tqps, max_rss_size, rss_size;
316 
317 	h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
318 	rss_size = alloc_tqps / h->kinfo.num_tc;
319 
320 	return min_t(u16, rss_size, max_rss_size);
321 }
322 
323 static void hns3_tqp_enable(struct hnae3_queue *tqp)
324 {
325 	u32 rcb_reg;
326 
327 	rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
328 	rcb_reg |= BIT(HNS3_RING_EN_B);
329 	hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
330 }
331 
332 static void hns3_tqp_disable(struct hnae3_queue *tqp)
333 {
334 	u32 rcb_reg;
335 
336 	rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
337 	rcb_reg &= ~BIT(HNS3_RING_EN_B);
338 	hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
339 }
340 
341 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
342 {
343 #ifdef CONFIG_RFS_ACCEL
344 	free_irq_cpu_rmap(netdev->rx_cpu_rmap);
345 	netdev->rx_cpu_rmap = NULL;
346 #endif
347 }
348 
349 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
350 {
351 #ifdef CONFIG_RFS_ACCEL
352 	struct hns3_nic_priv *priv = netdev_priv(netdev);
353 	struct hns3_enet_tqp_vector *tqp_vector;
354 	int i, ret;
355 
356 	if (!netdev->rx_cpu_rmap) {
357 		netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
358 		if (!netdev->rx_cpu_rmap)
359 			return -ENOMEM;
360 	}
361 
362 	for (i = 0; i < priv->vector_num; i++) {
363 		tqp_vector = &priv->tqp_vector[i];
364 		ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
365 				       tqp_vector->vector_irq);
366 		if (ret) {
367 			hns3_free_rx_cpu_rmap(netdev);
368 			return ret;
369 		}
370 	}
371 #endif
372 	return 0;
373 }
374 
375 static int hns3_nic_net_up(struct net_device *netdev)
376 {
377 	struct hns3_nic_priv *priv = netdev_priv(netdev);
378 	struct hnae3_handle *h = priv->ae_handle;
379 	int i, j;
380 	int ret;
381 
382 	ret = hns3_nic_reset_all_ring(h);
383 	if (ret)
384 		return ret;
385 
386 	clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
387 
388 	/* enable the vectors */
389 	for (i = 0; i < priv->vector_num; i++)
390 		hns3_vector_enable(&priv->tqp_vector[i]);
391 
392 	/* enable rcb */
393 	for (j = 0; j < h->kinfo.num_tqps; j++)
394 		hns3_tqp_enable(h->kinfo.tqp[j]);
395 
396 	/* start the ae_dev */
397 	ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
398 	if (ret) {
399 		set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
400 		while (j--)
401 			hns3_tqp_disable(h->kinfo.tqp[j]);
402 
403 		for (j = i - 1; j >= 0; j--)
404 			hns3_vector_disable(&priv->tqp_vector[j]);
405 	}
406 
407 	return ret;
408 }
409 
410 static void hns3_config_xps(struct hns3_nic_priv *priv)
411 {
412 	int i;
413 
414 	for (i = 0; i < priv->vector_num; i++) {
415 		struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
416 		struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
417 
418 		while (ring) {
419 			int ret;
420 
421 			ret = netif_set_xps_queue(priv->netdev,
422 						  &tqp_vector->affinity_mask,
423 						  ring->tqp->tqp_index);
424 			if (ret)
425 				netdev_warn(priv->netdev,
426 					    "set xps queue failed: %d", ret);
427 
428 			ring = ring->next;
429 		}
430 	}
431 }
432 
433 static int hns3_nic_net_open(struct net_device *netdev)
434 {
435 	struct hns3_nic_priv *priv = netdev_priv(netdev);
436 	struct hnae3_handle *h = hns3_get_handle(netdev);
437 	struct hnae3_knic_private_info *kinfo;
438 	int i, ret;
439 
440 	if (hns3_nic_resetting(netdev))
441 		return -EBUSY;
442 
443 	netif_carrier_off(netdev);
444 
445 	ret = hns3_nic_set_real_num_queue(netdev);
446 	if (ret)
447 		return ret;
448 
449 	ret = hns3_nic_net_up(netdev);
450 	if (ret) {
451 		netdev_err(netdev, "net up fail, ret=%d!\n", ret);
452 		return ret;
453 	}
454 
455 	kinfo = &h->kinfo;
456 	for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
457 		netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]);
458 
459 	if (h->ae_algo->ops->set_timer_task)
460 		h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
461 
462 	hns3_config_xps(priv);
463 
464 	netif_dbg(h, drv, netdev, "net open\n");
465 
466 	return 0;
467 }
468 
469 static void hns3_reset_tx_queue(struct hnae3_handle *h)
470 {
471 	struct net_device *ndev = h->kinfo.netdev;
472 	struct hns3_nic_priv *priv = netdev_priv(ndev);
473 	struct netdev_queue *dev_queue;
474 	u32 i;
475 
476 	for (i = 0; i < h->kinfo.num_tqps; i++) {
477 		dev_queue = netdev_get_tx_queue(ndev,
478 						priv->ring[i].queue_index);
479 		netdev_tx_reset_queue(dev_queue);
480 	}
481 }
482 
483 static void hns3_nic_net_down(struct net_device *netdev)
484 {
485 	struct hns3_nic_priv *priv = netdev_priv(netdev);
486 	struct hnae3_handle *h = hns3_get_handle(netdev);
487 	const struct hnae3_ae_ops *ops;
488 	int i;
489 
490 	/* disable vectors */
491 	for (i = 0; i < priv->vector_num; i++)
492 		hns3_vector_disable(&priv->tqp_vector[i]);
493 
494 	/* disable rcb */
495 	for (i = 0; i < h->kinfo.num_tqps; i++)
496 		hns3_tqp_disable(h->kinfo.tqp[i]);
497 
498 	/* stop ae_dev */
499 	ops = priv->ae_handle->ae_algo->ops;
500 	if (ops->stop)
501 		ops->stop(priv->ae_handle);
502 
503 	/* delay ring buffer clearing to hns3_reset_notify_uninit_enet
504 	 * during reset process, because driver may not be able
505 	 * to disable the ring through firmware when downing the netdev.
506 	 */
507 	if (!hns3_nic_resetting(netdev))
508 		hns3_clear_all_ring(priv->ae_handle, false);
509 
510 	hns3_reset_tx_queue(priv->ae_handle);
511 }
512 
513 static int hns3_nic_net_stop(struct net_device *netdev)
514 {
515 	struct hns3_nic_priv *priv = netdev_priv(netdev);
516 	struct hnae3_handle *h = hns3_get_handle(netdev);
517 
518 	if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
519 		return 0;
520 
521 	netif_dbg(h, drv, netdev, "net stop\n");
522 
523 	if (h->ae_algo->ops->set_timer_task)
524 		h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
525 
526 	netif_tx_stop_all_queues(netdev);
527 	netif_carrier_off(netdev);
528 
529 	hns3_nic_net_down(netdev);
530 
531 	return 0;
532 }
533 
534 static int hns3_nic_uc_sync(struct net_device *netdev,
535 			    const unsigned char *addr)
536 {
537 	struct hnae3_handle *h = hns3_get_handle(netdev);
538 
539 	if (h->ae_algo->ops->add_uc_addr)
540 		return h->ae_algo->ops->add_uc_addr(h, addr);
541 
542 	return 0;
543 }
544 
545 static int hns3_nic_uc_unsync(struct net_device *netdev,
546 			      const unsigned char *addr)
547 {
548 	struct hnae3_handle *h = hns3_get_handle(netdev);
549 
550 	/* need ignore the request of removing device address, because
551 	 * we store the device address and other addresses of uc list
552 	 * in the function's mac filter list.
553 	 */
554 	if (ether_addr_equal(addr, netdev->dev_addr))
555 		return 0;
556 
557 	if (h->ae_algo->ops->rm_uc_addr)
558 		return h->ae_algo->ops->rm_uc_addr(h, addr);
559 
560 	return 0;
561 }
562 
563 static int hns3_nic_mc_sync(struct net_device *netdev,
564 			    const unsigned char *addr)
565 {
566 	struct hnae3_handle *h = hns3_get_handle(netdev);
567 
568 	if (h->ae_algo->ops->add_mc_addr)
569 		return h->ae_algo->ops->add_mc_addr(h, addr);
570 
571 	return 0;
572 }
573 
574 static int hns3_nic_mc_unsync(struct net_device *netdev,
575 			      const unsigned char *addr)
576 {
577 	struct hnae3_handle *h = hns3_get_handle(netdev);
578 
579 	if (h->ae_algo->ops->rm_mc_addr)
580 		return h->ae_algo->ops->rm_mc_addr(h, addr);
581 
582 	return 0;
583 }
584 
585 static u8 hns3_get_netdev_flags(struct net_device *netdev)
586 {
587 	u8 flags = 0;
588 
589 	if (netdev->flags & IFF_PROMISC) {
590 		flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
591 	} else {
592 		flags |= HNAE3_VLAN_FLTR;
593 		if (netdev->flags & IFF_ALLMULTI)
594 			flags |= HNAE3_USER_MPE;
595 	}
596 
597 	return flags;
598 }
599 
600 static void hns3_nic_set_rx_mode(struct net_device *netdev)
601 {
602 	struct hnae3_handle *h = hns3_get_handle(netdev);
603 	u8 new_flags;
604 
605 	new_flags = hns3_get_netdev_flags(netdev);
606 
607 	__dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
608 	__dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
609 
610 	/* User mode Promisc mode enable and vlan filtering is disabled to
611 	 * let all packets in.
612 	 */
613 	h->netdev_flags = new_flags;
614 	hns3_request_update_promisc_mode(h);
615 }
616 
617 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
618 {
619 	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
620 
621 	if (ops->request_update_promisc_mode)
622 		ops->request_update_promisc_mode(handle);
623 }
624 
625 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
626 {
627 	struct hns3_nic_priv *priv = netdev_priv(netdev);
628 	struct hnae3_handle *h = priv->ae_handle;
629 
630 	if (h->ae_algo->ops->set_promisc_mode) {
631 		return h->ae_algo->ops->set_promisc_mode(h,
632 						promisc_flags & HNAE3_UPE,
633 						promisc_flags & HNAE3_MPE);
634 	}
635 
636 	return 0;
637 }
638 
639 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
640 {
641 	struct hns3_nic_priv *priv = netdev_priv(netdev);
642 	struct hnae3_handle *h = priv->ae_handle;
643 	bool last_state;
644 
645 	if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
646 		last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
647 		if (enable != last_state) {
648 			netdev_info(netdev,
649 				    "%s vlan filter\n",
650 				    enable ? "enable" : "disable");
651 			h->ae_algo->ops->enable_vlan_filter(h, enable);
652 		}
653 	}
654 }
655 
656 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
657 			u16 *mss, u32 *type_cs_vlan_tso)
658 {
659 	u32 l4_offset, hdr_len;
660 	union l3_hdr_info l3;
661 	union l4_hdr_info l4;
662 	u32 l4_paylen;
663 	int ret;
664 
665 	if (!skb_is_gso(skb))
666 		return 0;
667 
668 	ret = skb_cow_head(skb, 0);
669 	if (unlikely(ret < 0))
670 		return ret;
671 
672 	l3.hdr = skb_network_header(skb);
673 	l4.hdr = skb_transport_header(skb);
674 
675 	/* Software should clear the IPv4's checksum field when tso is
676 	 * needed.
677 	 */
678 	if (l3.v4->version == 4)
679 		l3.v4->check = 0;
680 
681 	/* tunnel packet */
682 	if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
683 					 SKB_GSO_GRE_CSUM |
684 					 SKB_GSO_UDP_TUNNEL |
685 					 SKB_GSO_UDP_TUNNEL_CSUM)) {
686 		if ((!(skb_shinfo(skb)->gso_type &
687 		    SKB_GSO_PARTIAL)) &&
688 		    (skb_shinfo(skb)->gso_type &
689 		    SKB_GSO_UDP_TUNNEL_CSUM)) {
690 			/* Software should clear the udp's checksum
691 			 * field when tso is needed.
692 			 */
693 			l4.udp->check = 0;
694 		}
695 		/* reset l3&l4 pointers from outer to inner headers */
696 		l3.hdr = skb_inner_network_header(skb);
697 		l4.hdr = skb_inner_transport_header(skb);
698 
699 		/* Software should clear the IPv4's checksum field when
700 		 * tso is needed.
701 		 */
702 		if (l3.v4->version == 4)
703 			l3.v4->check = 0;
704 	}
705 
706 	/* normal or tunnel packet */
707 	l4_offset = l4.hdr - skb->data;
708 	hdr_len = (l4.tcp->doff << 2) + l4_offset;
709 
710 	/* remove payload length from inner pseudo checksum when tso */
711 	l4_paylen = skb->len - l4_offset;
712 	csum_replace_by_diff(&l4.tcp->check,
713 			     (__force __wsum)htonl(l4_paylen));
714 
715 	/* find the txbd field values */
716 	*paylen = skb->len - hdr_len;
717 	hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
718 
719 	/* get MSS for TSO */
720 	*mss = skb_shinfo(skb)->gso_size;
721 
722 	trace_hns3_tso(skb);
723 
724 	return 0;
725 }
726 
727 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
728 				u8 *il4_proto)
729 {
730 	union l3_hdr_info l3;
731 	unsigned char *l4_hdr;
732 	unsigned char *exthdr;
733 	u8 l4_proto_tmp;
734 	__be16 frag_off;
735 
736 	/* find outer header point */
737 	l3.hdr = skb_network_header(skb);
738 	l4_hdr = skb_transport_header(skb);
739 
740 	if (skb->protocol == htons(ETH_P_IPV6)) {
741 		exthdr = l3.hdr + sizeof(*l3.v6);
742 		l4_proto_tmp = l3.v6->nexthdr;
743 		if (l4_hdr != exthdr)
744 			ipv6_skip_exthdr(skb, exthdr - skb->data,
745 					 &l4_proto_tmp, &frag_off);
746 	} else if (skb->protocol == htons(ETH_P_IP)) {
747 		l4_proto_tmp = l3.v4->protocol;
748 	} else {
749 		return -EINVAL;
750 	}
751 
752 	*ol4_proto = l4_proto_tmp;
753 
754 	/* tunnel packet */
755 	if (!skb->encapsulation) {
756 		*il4_proto = 0;
757 		return 0;
758 	}
759 
760 	/* find inner header point */
761 	l3.hdr = skb_inner_network_header(skb);
762 	l4_hdr = skb_inner_transport_header(skb);
763 
764 	if (l3.v6->version == 6) {
765 		exthdr = l3.hdr + sizeof(*l3.v6);
766 		l4_proto_tmp = l3.v6->nexthdr;
767 		if (l4_hdr != exthdr)
768 			ipv6_skip_exthdr(skb, exthdr - skb->data,
769 					 &l4_proto_tmp, &frag_off);
770 	} else if (l3.v4->version == 4) {
771 		l4_proto_tmp = l3.v4->protocol;
772 	}
773 
774 	*il4_proto = l4_proto_tmp;
775 
776 	return 0;
777 }
778 
779 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
780  * and it is udp packet, which has a dest port as the IANA assigned.
781  * the hardware is expected to do the checksum offload, but the
782  * hardware will not do the checksum offload when udp dest port is
783  * 4789.
784  */
785 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
786 {
787 	union l4_hdr_info l4;
788 
789 	l4.hdr = skb_transport_header(skb);
790 
791 	if (!(!skb->encapsulation &&
792 	      l4.udp->dest == htons(IANA_VXLAN_UDP_PORT)))
793 		return false;
794 
795 	skb_checksum_help(skb);
796 
797 	return true;
798 }
799 
800 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
801 				  u32 *ol_type_vlan_len_msec)
802 {
803 	u32 l2_len, l3_len, l4_len;
804 	unsigned char *il2_hdr;
805 	union l3_hdr_info l3;
806 	union l4_hdr_info l4;
807 
808 	l3.hdr = skb_network_header(skb);
809 	l4.hdr = skb_transport_header(skb);
810 
811 	/* compute OL2 header size, defined in 2 Bytes */
812 	l2_len = l3.hdr - skb->data;
813 	hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
814 
815 	/* compute OL3 header size, defined in 4 Bytes */
816 	l3_len = l4.hdr - l3.hdr;
817 	hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
818 
819 	il2_hdr = skb_inner_mac_header(skb);
820 	/* compute OL4 header size, defined in 4 Bytes */
821 	l4_len = il2_hdr - l4.hdr;
822 	hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
823 
824 	/* define outer network header type */
825 	if (skb->protocol == htons(ETH_P_IP)) {
826 		if (skb_is_gso(skb))
827 			hns3_set_field(*ol_type_vlan_len_msec,
828 				       HNS3_TXD_OL3T_S,
829 				       HNS3_OL3T_IPV4_CSUM);
830 		else
831 			hns3_set_field(*ol_type_vlan_len_msec,
832 				       HNS3_TXD_OL3T_S,
833 				       HNS3_OL3T_IPV4_NO_CSUM);
834 
835 	} else if (skb->protocol == htons(ETH_P_IPV6)) {
836 		hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
837 			       HNS3_OL3T_IPV6);
838 	}
839 
840 	if (ol4_proto == IPPROTO_UDP)
841 		hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
842 			       HNS3_TUN_MAC_IN_UDP);
843 	else if (ol4_proto == IPPROTO_GRE)
844 		hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
845 			       HNS3_TUN_NVGRE);
846 }
847 
848 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
849 			   u8 il4_proto, u32 *type_cs_vlan_tso,
850 			   u32 *ol_type_vlan_len_msec)
851 {
852 	unsigned char *l2_hdr = skb->data;
853 	u32 l4_proto = ol4_proto;
854 	union l4_hdr_info l4;
855 	union l3_hdr_info l3;
856 	u32 l2_len, l3_len;
857 
858 	l4.hdr = skb_transport_header(skb);
859 	l3.hdr = skb_network_header(skb);
860 
861 	/* handle encapsulation skb */
862 	if (skb->encapsulation) {
863 		/* If this is a not UDP/GRE encapsulation skb */
864 		if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
865 			/* drop the skb tunnel packet if hardware don't support,
866 			 * because hardware can't calculate csum when TSO.
867 			 */
868 			if (skb_is_gso(skb))
869 				return -EDOM;
870 
871 			/* the stack computes the IP header already,
872 			 * driver calculate l4 checksum when not TSO.
873 			 */
874 			skb_checksum_help(skb);
875 			return 0;
876 		}
877 
878 		hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
879 
880 		/* switch to inner header */
881 		l2_hdr = skb_inner_mac_header(skb);
882 		l3.hdr = skb_inner_network_header(skb);
883 		l4.hdr = skb_inner_transport_header(skb);
884 		l4_proto = il4_proto;
885 	}
886 
887 	if (l3.v4->version == 4) {
888 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
889 			       HNS3_L3T_IPV4);
890 
891 		/* the stack computes the IP header already, the only time we
892 		 * need the hardware to recompute it is in the case of TSO.
893 		 */
894 		if (skb_is_gso(skb))
895 			hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
896 	} else if (l3.v6->version == 6) {
897 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
898 			       HNS3_L3T_IPV6);
899 	}
900 
901 	/* compute inner(/normal) L2 header size, defined in 2 Bytes */
902 	l2_len = l3.hdr - l2_hdr;
903 	hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
904 
905 	/* compute inner(/normal) L3 header size, defined in 4 Bytes */
906 	l3_len = l4.hdr - l3.hdr;
907 	hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
908 
909 	/* compute inner(/normal) L4 header size, defined in 4 Bytes */
910 	switch (l4_proto) {
911 	case IPPROTO_TCP:
912 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
913 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
914 			       HNS3_L4T_TCP);
915 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
916 			       l4.tcp->doff);
917 		break;
918 	case IPPROTO_UDP:
919 		if (hns3_tunnel_csum_bug(skb))
920 			break;
921 
922 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
923 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
924 			       HNS3_L4T_UDP);
925 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
926 			       (sizeof(struct udphdr) >> 2));
927 		break;
928 	case IPPROTO_SCTP:
929 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
930 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
931 			       HNS3_L4T_SCTP);
932 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
933 			       (sizeof(struct sctphdr) >> 2));
934 		break;
935 	default:
936 		/* drop the skb tunnel packet if hardware don't support,
937 		 * because hardware can't calculate csum when TSO.
938 		 */
939 		if (skb_is_gso(skb))
940 			return -EDOM;
941 
942 		/* the stack computes the IP header already,
943 		 * driver calculate l4 checksum when not TSO.
944 		 */
945 		skb_checksum_help(skb);
946 		return 0;
947 	}
948 
949 	return 0;
950 }
951 
952 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
953 			     struct sk_buff *skb)
954 {
955 	struct hnae3_handle *handle = tx_ring->tqp->handle;
956 	struct vlan_ethhdr *vhdr;
957 	int rc;
958 
959 	if (!(skb->protocol == htons(ETH_P_8021Q) ||
960 	      skb_vlan_tag_present(skb)))
961 		return 0;
962 
963 	/* Since HW limitation, if port based insert VLAN enabled, only one VLAN
964 	 * header is allowed in skb, otherwise it will cause RAS error.
965 	 */
966 	if (unlikely(skb_vlan_tagged_multi(skb) &&
967 		     handle->port_base_vlan_state ==
968 		     HNAE3_PORT_BASE_VLAN_ENABLE))
969 		return -EINVAL;
970 
971 	if (skb->protocol == htons(ETH_P_8021Q) &&
972 	    !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
973 		/* When HW VLAN acceleration is turned off, and the stack
974 		 * sets the protocol to 802.1q, the driver just need to
975 		 * set the protocol to the encapsulated ethertype.
976 		 */
977 		skb->protocol = vlan_get_protocol(skb);
978 		return 0;
979 	}
980 
981 	if (skb_vlan_tag_present(skb)) {
982 		/* Based on hw strategy, use out_vtag in two layer tag case,
983 		 * and use inner_vtag in one tag case.
984 		 */
985 		if (skb->protocol == htons(ETH_P_8021Q) &&
986 		    handle->port_base_vlan_state ==
987 		    HNAE3_PORT_BASE_VLAN_DISABLE)
988 			rc = HNS3_OUTER_VLAN_TAG;
989 		else
990 			rc = HNS3_INNER_VLAN_TAG;
991 
992 		skb->protocol = vlan_get_protocol(skb);
993 		return rc;
994 	}
995 
996 	rc = skb_cow_head(skb, 0);
997 	if (unlikely(rc < 0))
998 		return rc;
999 
1000 	vhdr = (struct vlan_ethhdr *)skb->data;
1001 	vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1002 					 & VLAN_PRIO_MASK);
1003 
1004 	skb->protocol = vlan_get_protocol(skb);
1005 	return 0;
1006 }
1007 
1008 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1009 			      struct sk_buff *skb, struct hns3_desc *desc)
1010 {
1011 	u32 ol_type_vlan_len_msec = 0;
1012 	u32 type_cs_vlan_tso = 0;
1013 	u32 paylen = skb->len;
1014 	u16 inner_vtag = 0;
1015 	u16 out_vtag = 0;
1016 	u16 mss = 0;
1017 	int ret;
1018 
1019 	ret = hns3_handle_vtags(ring, skb);
1020 	if (unlikely(ret < 0)) {
1021 		u64_stats_update_begin(&ring->syncp);
1022 		ring->stats.tx_vlan_err++;
1023 		u64_stats_update_end(&ring->syncp);
1024 		return ret;
1025 	} else if (ret == HNS3_INNER_VLAN_TAG) {
1026 		inner_vtag = skb_vlan_tag_get(skb);
1027 		inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1028 				VLAN_PRIO_MASK;
1029 		hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1030 	} else if (ret == HNS3_OUTER_VLAN_TAG) {
1031 		out_vtag = skb_vlan_tag_get(skb);
1032 		out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1033 				VLAN_PRIO_MASK;
1034 		hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1035 			       1);
1036 	}
1037 
1038 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
1039 		u8 ol4_proto, il4_proto;
1040 
1041 		skb_reset_mac_len(skb);
1042 
1043 		ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1044 		if (unlikely(ret < 0)) {
1045 			u64_stats_update_begin(&ring->syncp);
1046 			ring->stats.tx_l4_proto_err++;
1047 			u64_stats_update_end(&ring->syncp);
1048 			return ret;
1049 		}
1050 
1051 		ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1052 				      &type_cs_vlan_tso,
1053 				      &ol_type_vlan_len_msec);
1054 		if (unlikely(ret < 0)) {
1055 			u64_stats_update_begin(&ring->syncp);
1056 			ring->stats.tx_l2l3l4_err++;
1057 			u64_stats_update_end(&ring->syncp);
1058 			return ret;
1059 		}
1060 
1061 		ret = hns3_set_tso(skb, &paylen, &mss,
1062 				   &type_cs_vlan_tso);
1063 		if (unlikely(ret < 0)) {
1064 			u64_stats_update_begin(&ring->syncp);
1065 			ring->stats.tx_tso_err++;
1066 			u64_stats_update_end(&ring->syncp);
1067 			return ret;
1068 		}
1069 	}
1070 
1071 	/* Set txbd */
1072 	desc->tx.ol_type_vlan_len_msec =
1073 		cpu_to_le32(ol_type_vlan_len_msec);
1074 	desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
1075 	desc->tx.paylen = cpu_to_le32(paylen);
1076 	desc->tx.mss = cpu_to_le16(mss);
1077 	desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1078 	desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1079 
1080 	return 0;
1081 }
1082 
1083 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
1084 			  unsigned int size, enum hns_desc_type type)
1085 {
1086 #define HNS3_LIKELY_BD_NUM	1
1087 
1088 	struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1089 	struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1090 	struct device *dev = ring_to_dev(ring);
1091 	skb_frag_t *frag;
1092 	unsigned int frag_buf_num;
1093 	int k, sizeoflast;
1094 	dma_addr_t dma;
1095 
1096 	if (type == DESC_TYPE_SKB) {
1097 		struct sk_buff *skb = (struct sk_buff *)priv;
1098 		int ret;
1099 
1100 		ret = hns3_fill_skb_desc(ring, skb, desc);
1101 		if (unlikely(ret < 0))
1102 			return ret;
1103 
1104 		dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1105 	} else if (type == DESC_TYPE_FRAGLIST_SKB) {
1106 		struct sk_buff *skb = (struct sk_buff *)priv;
1107 
1108 		dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1109 	} else {
1110 		frag = (skb_frag_t *)priv;
1111 		dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1112 	}
1113 
1114 	if (unlikely(dma_mapping_error(dev, dma))) {
1115 		u64_stats_update_begin(&ring->syncp);
1116 		ring->stats.sw_err_cnt++;
1117 		u64_stats_update_end(&ring->syncp);
1118 		return -ENOMEM;
1119 	}
1120 
1121 	desc_cb->length = size;
1122 
1123 	if (likely(size <= HNS3_MAX_BD_SIZE)) {
1124 		desc_cb->priv = priv;
1125 		desc_cb->dma = dma;
1126 		desc_cb->type = type;
1127 		desc->addr = cpu_to_le64(dma);
1128 		desc->tx.send_size = cpu_to_le16(size);
1129 		desc->tx.bdtp_fe_sc_vld_ra_ri =
1130 			cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1131 
1132 		trace_hns3_tx_desc(ring, ring->next_to_use);
1133 		ring_ptr_move_fw(ring, next_to_use);
1134 		return HNS3_LIKELY_BD_NUM;
1135 	}
1136 
1137 	frag_buf_num = hns3_tx_bd_count(size);
1138 	sizeoflast = size & HNS3_TX_LAST_SIZE_M;
1139 	sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1140 
1141 	/* When frag size is bigger than hardware limit, split this frag */
1142 	for (k = 0; k < frag_buf_num; k++) {
1143 		/* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1144 		desc_cb->priv = priv;
1145 		desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1146 		desc_cb->type = ((type == DESC_TYPE_FRAGLIST_SKB ||
1147 				  type == DESC_TYPE_SKB) && !k) ?
1148 				type : DESC_TYPE_PAGE;
1149 
1150 		/* now, fill the descriptor */
1151 		desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1152 		desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1153 				     (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1154 		desc->tx.bdtp_fe_sc_vld_ra_ri =
1155 				cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1156 
1157 		trace_hns3_tx_desc(ring, ring->next_to_use);
1158 		/* move ring pointer to next */
1159 		ring_ptr_move_fw(ring, next_to_use);
1160 
1161 		desc_cb = &ring->desc_cb[ring->next_to_use];
1162 		desc = &ring->desc[ring->next_to_use];
1163 	}
1164 
1165 	return frag_buf_num;
1166 }
1167 
1168 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1169 				    unsigned int bd_num)
1170 {
1171 	unsigned int size;
1172 	int i;
1173 
1174 	size = skb_headlen(skb);
1175 	while (size > HNS3_MAX_BD_SIZE) {
1176 		bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1177 		size -= HNS3_MAX_BD_SIZE;
1178 
1179 		if (bd_num > HNS3_MAX_TSO_BD_NUM)
1180 			return bd_num;
1181 	}
1182 
1183 	if (size) {
1184 		bd_size[bd_num++] = size;
1185 		if (bd_num > HNS3_MAX_TSO_BD_NUM)
1186 			return bd_num;
1187 	}
1188 
1189 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1190 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1191 		size = skb_frag_size(frag);
1192 		if (!size)
1193 			continue;
1194 
1195 		while (size > HNS3_MAX_BD_SIZE) {
1196 			bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1197 			size -= HNS3_MAX_BD_SIZE;
1198 
1199 			if (bd_num > HNS3_MAX_TSO_BD_NUM)
1200 				return bd_num;
1201 		}
1202 
1203 		bd_size[bd_num++] = size;
1204 		if (bd_num > HNS3_MAX_TSO_BD_NUM)
1205 			return bd_num;
1206 	}
1207 
1208 	return bd_num;
1209 }
1210 
1211 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size)
1212 {
1213 	struct sk_buff *frag_skb;
1214 	unsigned int bd_num = 0;
1215 
1216 	/* If the total len is within the max bd limit */
1217 	if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) &&
1218 		   skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM))
1219 		return skb_shinfo(skb)->nr_frags + 1U;
1220 
1221 	/* The below case will always be linearized, return
1222 	 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized.
1223 	 */
1224 	if (unlikely(skb->len > HNS3_MAX_TSO_SIZE ||
1225 		     (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)))
1226 		return HNS3_MAX_TSO_BD_NUM + 1U;
1227 
1228 	bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1229 
1230 	if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1231 		return bd_num;
1232 
1233 	skb_walk_frags(skb, frag_skb) {
1234 		bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num);
1235 		if (bd_num > HNS3_MAX_TSO_BD_NUM)
1236 			return bd_num;
1237 	}
1238 
1239 	return bd_num;
1240 }
1241 
1242 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1243 {
1244 	if (!skb->encapsulation)
1245 		return skb_transport_offset(skb) + tcp_hdrlen(skb);
1246 
1247 	return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1248 }
1249 
1250 /* HW need every continuous 8 buffer data to be larger than MSS,
1251  * we simplify it by ensuring skb_headlen + the first continuous
1252  * 7 frags to to be larger than gso header len + mss, and the remaining
1253  * continuous 7 frags to be larger than MSS except the last 7 frags.
1254  */
1255 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1256 				     unsigned int bd_num)
1257 {
1258 	unsigned int tot_len = 0;
1259 	int i;
1260 
1261 	for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++)
1262 		tot_len += bd_size[i];
1263 
1264 	/* ensure the first 8 frags is greater than mss + header */
1265 	if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] <
1266 	    skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1267 		return true;
1268 
1269 	/* ensure every continuous 7 buffer is greater than mss
1270 	 * except the last one.
1271 	 */
1272 	for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) {
1273 		tot_len -= bd_size[i];
1274 		tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U];
1275 
1276 		if (tot_len < skb_shinfo(skb)->gso_size)
1277 			return true;
1278 	}
1279 
1280 	return false;
1281 }
1282 
1283 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1284 {
1285 	int i = 0;
1286 
1287 	for (i = 0; i < MAX_SKB_FRAGS; i++)
1288 		size[i] = skb_frag_size(&shinfo->frags[i]);
1289 }
1290 
1291 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1292 				  struct net_device *netdev,
1293 				  struct sk_buff *skb)
1294 {
1295 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1296 	unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1297 	unsigned int bd_num;
1298 
1299 	bd_num = hns3_tx_bd_num(skb, bd_size);
1300 	if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1301 		if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1302 		    !hns3_skb_need_linearized(skb, bd_size, bd_num)) {
1303 			trace_hns3_over_8bd(skb);
1304 			goto out;
1305 		}
1306 
1307 		if (__skb_linearize(skb))
1308 			return -ENOMEM;
1309 
1310 		bd_num = hns3_tx_bd_count(skb->len);
1311 		if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) ||
1312 		    (!skb_is_gso(skb) &&
1313 		     bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1314 			trace_hns3_over_8bd(skb);
1315 			return -ENOMEM;
1316 		}
1317 
1318 		u64_stats_update_begin(&ring->syncp);
1319 		ring->stats.tx_copy++;
1320 		u64_stats_update_end(&ring->syncp);
1321 	}
1322 
1323 out:
1324 	if (likely(ring_space(ring) >= bd_num))
1325 		return bd_num;
1326 
1327 	netif_stop_subqueue(netdev, ring->queue_index);
1328 	smp_mb(); /* Memory barrier before checking ring_space */
1329 
1330 	/* Start queue in case hns3_clean_tx_ring has just made room
1331 	 * available and has not seen the queue stopped state performed
1332 	 * by netif_stop_subqueue above.
1333 	 */
1334 	if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1335 	    !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1336 		netif_start_subqueue(netdev, ring->queue_index);
1337 		return bd_num;
1338 	}
1339 
1340 	return -EBUSY;
1341 }
1342 
1343 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1344 {
1345 	struct device *dev = ring_to_dev(ring);
1346 	unsigned int i;
1347 
1348 	for (i = 0; i < ring->desc_num; i++) {
1349 		/* check if this is where we started */
1350 		if (ring->next_to_use == next_to_use_orig)
1351 			break;
1352 
1353 		/* rollback one */
1354 		ring_ptr_move_bw(ring, next_to_use);
1355 
1356 		/* unmap the descriptor dma address */
1357 		if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB ||
1358 		    ring->desc_cb[ring->next_to_use].type ==
1359 		    DESC_TYPE_FRAGLIST_SKB)
1360 			dma_unmap_single(dev,
1361 					 ring->desc_cb[ring->next_to_use].dma,
1362 					ring->desc_cb[ring->next_to_use].length,
1363 					DMA_TO_DEVICE);
1364 		else if (ring->desc_cb[ring->next_to_use].length)
1365 			dma_unmap_page(dev,
1366 				       ring->desc_cb[ring->next_to_use].dma,
1367 				       ring->desc_cb[ring->next_to_use].length,
1368 				       DMA_TO_DEVICE);
1369 
1370 		ring->desc_cb[ring->next_to_use].length = 0;
1371 		ring->desc_cb[ring->next_to_use].dma = 0;
1372 	}
1373 }
1374 
1375 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
1376 				 struct sk_buff *skb, enum hns_desc_type type)
1377 {
1378 	unsigned int size = skb_headlen(skb);
1379 	int i, ret, bd_num = 0;
1380 
1381 	if (size) {
1382 		ret = hns3_fill_desc(ring, skb, size, type);
1383 		if (unlikely(ret < 0))
1384 			return ret;
1385 
1386 		bd_num += ret;
1387 	}
1388 
1389 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1390 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1391 
1392 		size = skb_frag_size(frag);
1393 		if (!size)
1394 			continue;
1395 
1396 		ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE);
1397 		if (unlikely(ret < 0))
1398 			return ret;
1399 
1400 		bd_num += ret;
1401 	}
1402 
1403 	return bd_num;
1404 }
1405 
1406 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
1407 {
1408 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1409 	struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
1410 	struct netdev_queue *dev_queue;
1411 	int pre_ntu, next_to_use_head;
1412 	struct sk_buff *frag_skb;
1413 	int bd_num = 0;
1414 	int ret;
1415 
1416 	/* Hardware can only handle short frames above 32 bytes */
1417 	if (skb_put_padto(skb, HNS3_MIN_TX_LEN))
1418 		return NETDEV_TX_OK;
1419 
1420 	/* Prefetch the data used later */
1421 	prefetch(skb->data);
1422 
1423 	ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
1424 	if (unlikely(ret <= 0)) {
1425 		if (ret == -EBUSY) {
1426 			u64_stats_update_begin(&ring->syncp);
1427 			ring->stats.tx_busy++;
1428 			u64_stats_update_end(&ring->syncp);
1429 			return NETDEV_TX_BUSY;
1430 		} else if (ret == -ENOMEM) {
1431 			u64_stats_update_begin(&ring->syncp);
1432 			ring->stats.sw_err_cnt++;
1433 			u64_stats_update_end(&ring->syncp);
1434 		}
1435 
1436 		hns3_rl_err(netdev, "xmit error: %d!\n", ret);
1437 		goto out_err_tx_ok;
1438 	}
1439 
1440 	next_to_use_head = ring->next_to_use;
1441 
1442 	ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
1443 	if (unlikely(ret < 0))
1444 		goto fill_err;
1445 
1446 	bd_num += ret;
1447 
1448 	skb_walk_frags(skb, frag_skb) {
1449 		ret = hns3_fill_skb_to_desc(ring, frag_skb,
1450 					    DESC_TYPE_FRAGLIST_SKB);
1451 		if (unlikely(ret < 0))
1452 			goto fill_err;
1453 
1454 		bd_num += ret;
1455 	}
1456 
1457 	pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
1458 					(ring->desc_num - 1);
1459 	ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
1460 				cpu_to_le16(BIT(HNS3_TXD_FE_B));
1461 	trace_hns3_tx_desc(ring, pre_ntu);
1462 
1463 	/* Complete translate all packets */
1464 	dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
1465 	netdev_tx_sent_queue(dev_queue, skb->len);
1466 
1467 	wmb(); /* Commit all data before submit */
1468 
1469 	hnae3_queue_xmit(ring->tqp, bd_num);
1470 
1471 	return NETDEV_TX_OK;
1472 
1473 fill_err:
1474 	hns3_clear_desc(ring, next_to_use_head);
1475 
1476 out_err_tx_ok:
1477 	dev_kfree_skb_any(skb);
1478 	return NETDEV_TX_OK;
1479 }
1480 
1481 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1482 {
1483 	struct hnae3_handle *h = hns3_get_handle(netdev);
1484 	struct sockaddr *mac_addr = p;
1485 	int ret;
1486 
1487 	if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1488 		return -EADDRNOTAVAIL;
1489 
1490 	if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1491 		netdev_info(netdev, "already using mac address %pM\n",
1492 			    mac_addr->sa_data);
1493 		return 0;
1494 	}
1495 
1496 	/* For VF device, if there is a perm_addr, then the user will not
1497 	 * be allowed to change the address.
1498 	 */
1499 	if (!hns3_is_phys_func(h->pdev) &&
1500 	    !is_zero_ether_addr(netdev->perm_addr)) {
1501 		netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
1502 			   netdev->perm_addr, mac_addr->sa_data);
1503 		return -EPERM;
1504 	}
1505 
1506 	ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
1507 	if (ret) {
1508 		netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1509 		return ret;
1510 	}
1511 
1512 	ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1513 
1514 	return 0;
1515 }
1516 
1517 static int hns3_nic_do_ioctl(struct net_device *netdev,
1518 			     struct ifreq *ifr, int cmd)
1519 {
1520 	struct hnae3_handle *h = hns3_get_handle(netdev);
1521 
1522 	if (!netif_running(netdev))
1523 		return -EINVAL;
1524 
1525 	if (!h->ae_algo->ops->do_ioctl)
1526 		return -EOPNOTSUPP;
1527 
1528 	return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1529 }
1530 
1531 static int hns3_nic_set_features(struct net_device *netdev,
1532 				 netdev_features_t features)
1533 {
1534 	netdev_features_t changed = netdev->features ^ features;
1535 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1536 	struct hnae3_handle *h = priv->ae_handle;
1537 	bool enable;
1538 	int ret;
1539 
1540 	if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1541 		enable = !!(features & NETIF_F_GRO_HW);
1542 		ret = h->ae_algo->ops->set_gro_en(h, enable);
1543 		if (ret)
1544 			return ret;
1545 	}
1546 
1547 	if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1548 	    h->ae_algo->ops->enable_hw_strip_rxvtag) {
1549 		enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1550 		ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
1551 		if (ret)
1552 			return ret;
1553 	}
1554 
1555 	if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1556 		enable = !!(features & NETIF_F_NTUPLE);
1557 		h->ae_algo->ops->enable_fd(h, enable);
1558 	}
1559 
1560 	netdev->features = features;
1561 	return 0;
1562 }
1563 
1564 static netdev_features_t hns3_features_check(struct sk_buff *skb,
1565 					     struct net_device *dev,
1566 					     netdev_features_t features)
1567 {
1568 #define HNS3_MAX_HDR_LEN	480U
1569 #define HNS3_MAX_L4_HDR_LEN	60U
1570 
1571 	size_t len;
1572 
1573 	if (skb->ip_summed != CHECKSUM_PARTIAL)
1574 		return features;
1575 
1576 	if (skb->encapsulation)
1577 		len = skb_inner_transport_header(skb) - skb->data;
1578 	else
1579 		len = skb_transport_header(skb) - skb->data;
1580 
1581 	/* Assume L4 is 60 byte as TCP is the only protocol with a
1582 	 * a flexible value, and it's max len is 60 bytes.
1583 	 */
1584 	len += HNS3_MAX_L4_HDR_LEN;
1585 
1586 	/* Hardware only supports checksum on the skb with a max header
1587 	 * len of 480 bytes.
1588 	 */
1589 	if (len > HNS3_MAX_HDR_LEN)
1590 		features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
1591 
1592 	return features;
1593 }
1594 
1595 static void hns3_nic_get_stats64(struct net_device *netdev,
1596 				 struct rtnl_link_stats64 *stats)
1597 {
1598 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1599 	int queue_num = priv->ae_handle->kinfo.num_tqps;
1600 	struct hnae3_handle *handle = priv->ae_handle;
1601 	struct hns3_enet_ring *ring;
1602 	u64 rx_length_errors = 0;
1603 	u64 rx_crc_errors = 0;
1604 	u64 rx_multicast = 0;
1605 	unsigned int start;
1606 	u64 tx_errors = 0;
1607 	u64 rx_errors = 0;
1608 	unsigned int idx;
1609 	u64 tx_bytes = 0;
1610 	u64 rx_bytes = 0;
1611 	u64 tx_pkts = 0;
1612 	u64 rx_pkts = 0;
1613 	u64 tx_drop = 0;
1614 	u64 rx_drop = 0;
1615 
1616 	if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1617 		return;
1618 
1619 	handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1620 
1621 	for (idx = 0; idx < queue_num; idx++) {
1622 		/* fetch the tx stats */
1623 		ring = &priv->ring[idx];
1624 		do {
1625 			start = u64_stats_fetch_begin_irq(&ring->syncp);
1626 			tx_bytes += ring->stats.tx_bytes;
1627 			tx_pkts += ring->stats.tx_pkts;
1628 			tx_drop += ring->stats.sw_err_cnt;
1629 			tx_drop += ring->stats.tx_vlan_err;
1630 			tx_drop += ring->stats.tx_l4_proto_err;
1631 			tx_drop += ring->stats.tx_l2l3l4_err;
1632 			tx_drop += ring->stats.tx_tso_err;
1633 			tx_errors += ring->stats.sw_err_cnt;
1634 			tx_errors += ring->stats.tx_vlan_err;
1635 			tx_errors += ring->stats.tx_l4_proto_err;
1636 			tx_errors += ring->stats.tx_l2l3l4_err;
1637 			tx_errors += ring->stats.tx_tso_err;
1638 		} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1639 
1640 		/* fetch the rx stats */
1641 		ring = &priv->ring[idx + queue_num];
1642 		do {
1643 			start = u64_stats_fetch_begin_irq(&ring->syncp);
1644 			rx_bytes += ring->stats.rx_bytes;
1645 			rx_pkts += ring->stats.rx_pkts;
1646 			rx_drop += ring->stats.l2_err;
1647 			rx_errors += ring->stats.l2_err;
1648 			rx_errors += ring->stats.l3l4_csum_err;
1649 			rx_crc_errors += ring->stats.l2_err;
1650 			rx_multicast += ring->stats.rx_multicast;
1651 			rx_length_errors += ring->stats.err_pkt_len;
1652 		} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1653 	}
1654 
1655 	stats->tx_bytes = tx_bytes;
1656 	stats->tx_packets = tx_pkts;
1657 	stats->rx_bytes = rx_bytes;
1658 	stats->rx_packets = rx_pkts;
1659 
1660 	stats->rx_errors = rx_errors;
1661 	stats->multicast = rx_multicast;
1662 	stats->rx_length_errors = rx_length_errors;
1663 	stats->rx_crc_errors = rx_crc_errors;
1664 	stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1665 
1666 	stats->tx_errors = tx_errors;
1667 	stats->rx_dropped = rx_drop;
1668 	stats->tx_dropped = tx_drop;
1669 	stats->collisions = netdev->stats.collisions;
1670 	stats->rx_over_errors = netdev->stats.rx_over_errors;
1671 	stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1672 	stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1673 	stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1674 	stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1675 	stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1676 	stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1677 	stats->tx_window_errors = netdev->stats.tx_window_errors;
1678 	stats->rx_compressed = netdev->stats.rx_compressed;
1679 	stats->tx_compressed = netdev->stats.tx_compressed;
1680 }
1681 
1682 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
1683 {
1684 	struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
1685 	u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1686 	struct hnae3_knic_private_info *kinfo;
1687 	u8 tc = mqprio_qopt->qopt.num_tc;
1688 	u16 mode = mqprio_qopt->mode;
1689 	u8 hw = mqprio_qopt->qopt.hw;
1690 	struct hnae3_handle *h;
1691 
1692 	if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1693 	       mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1694 		return -EOPNOTSUPP;
1695 
1696 	if (tc > HNAE3_MAX_TC)
1697 		return -EINVAL;
1698 
1699 	if (!netdev)
1700 		return -EINVAL;
1701 
1702 	h = hns3_get_handle(netdev);
1703 	kinfo = &h->kinfo;
1704 
1705 	netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
1706 
1707 	return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1708 		kinfo->dcb_ops->setup_tc(h, tc ? tc : 1, prio_tc) : -EOPNOTSUPP;
1709 }
1710 
1711 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
1712 			     void *type_data)
1713 {
1714 	if (type != TC_SETUP_QDISC_MQPRIO)
1715 		return -EOPNOTSUPP;
1716 
1717 	return hns3_setup_tc(dev, type_data);
1718 }
1719 
1720 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1721 				__be16 proto, u16 vid)
1722 {
1723 	struct hnae3_handle *h = hns3_get_handle(netdev);
1724 	int ret = -EIO;
1725 
1726 	if (h->ae_algo->ops->set_vlan_filter)
1727 		ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1728 
1729 	return ret;
1730 }
1731 
1732 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1733 				 __be16 proto, u16 vid)
1734 {
1735 	struct hnae3_handle *h = hns3_get_handle(netdev);
1736 	int ret = -EIO;
1737 
1738 	if (h->ae_algo->ops->set_vlan_filter)
1739 		ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1740 
1741 	return ret;
1742 }
1743 
1744 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1745 				u8 qos, __be16 vlan_proto)
1746 {
1747 	struct hnae3_handle *h = hns3_get_handle(netdev);
1748 	int ret = -EIO;
1749 
1750 	netif_dbg(h, drv, netdev,
1751 		  "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
1752 		  vf, vlan, qos, ntohs(vlan_proto));
1753 
1754 	if (h->ae_algo->ops->set_vf_vlan_filter)
1755 		ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1756 							  qos, vlan_proto);
1757 
1758 	return ret;
1759 }
1760 
1761 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
1762 {
1763 	struct hnae3_handle *handle = hns3_get_handle(netdev);
1764 
1765 	if (hns3_nic_resetting(netdev))
1766 		return -EBUSY;
1767 
1768 	if (!handle->ae_algo->ops->set_vf_spoofchk)
1769 		return -EOPNOTSUPP;
1770 
1771 	return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
1772 }
1773 
1774 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
1775 {
1776 	struct hnae3_handle *handle = hns3_get_handle(netdev);
1777 
1778 	if (!handle->ae_algo->ops->set_vf_trust)
1779 		return -EOPNOTSUPP;
1780 
1781 	return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
1782 }
1783 
1784 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1785 {
1786 	struct hnae3_handle *h = hns3_get_handle(netdev);
1787 	int ret;
1788 
1789 	if (hns3_nic_resetting(netdev))
1790 		return -EBUSY;
1791 
1792 	if (!h->ae_algo->ops->set_mtu)
1793 		return -EOPNOTSUPP;
1794 
1795 	netif_dbg(h, drv, netdev,
1796 		  "change mtu from %u to %d\n", netdev->mtu, new_mtu);
1797 
1798 	ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1799 	if (ret)
1800 		netdev_err(netdev, "failed to change MTU in hardware %d\n",
1801 			   ret);
1802 	else
1803 		netdev->mtu = new_mtu;
1804 
1805 	return ret;
1806 }
1807 
1808 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1809 {
1810 	struct hns3_nic_priv *priv = netdev_priv(ndev);
1811 	struct hnae3_handle *h = hns3_get_handle(ndev);
1812 	struct hns3_enet_ring *tx_ring;
1813 	struct napi_struct *napi;
1814 	int timeout_queue = 0;
1815 	int hw_head, hw_tail;
1816 	int fbd_num, fbd_oft;
1817 	int ebd_num, ebd_oft;
1818 	int bd_num, bd_err;
1819 	int ring_en, tc;
1820 	int i;
1821 
1822 	/* Find the stopped queue the same way the stack does */
1823 	for (i = 0; i < ndev->num_tx_queues; i++) {
1824 		struct netdev_queue *q;
1825 		unsigned long trans_start;
1826 
1827 		q = netdev_get_tx_queue(ndev, i);
1828 		trans_start = q->trans_start;
1829 		if (netif_xmit_stopped(q) &&
1830 		    time_after(jiffies,
1831 			       (trans_start + ndev->watchdog_timeo))) {
1832 			timeout_queue = i;
1833 			netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
1834 				    q->state,
1835 				    jiffies_to_msecs(jiffies - trans_start));
1836 			break;
1837 		}
1838 	}
1839 
1840 	if (i == ndev->num_tx_queues) {
1841 		netdev_info(ndev,
1842 			    "no netdev TX timeout queue found, timeout count: %llu\n",
1843 			    priv->tx_timeout_count);
1844 		return false;
1845 	}
1846 
1847 	priv->tx_timeout_count++;
1848 
1849 	tx_ring = &priv->ring[timeout_queue];
1850 	napi = &tx_ring->tqp_vector->napi;
1851 
1852 	netdev_info(ndev,
1853 		    "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1854 		    priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1855 		    tx_ring->next_to_clean, napi->state);
1856 
1857 	netdev_info(ndev,
1858 		    "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n",
1859 		    tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
1860 		    tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt);
1861 
1862 	netdev_info(ndev,
1863 		    "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n",
1864 		    tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt,
1865 		    tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1866 
1867 	/* When mac received many pause frames continuous, it's unable to send
1868 	 * packets, which may cause tx timeout
1869 	 */
1870 	if (h->ae_algo->ops->get_mac_stats) {
1871 		struct hns3_mac_stats mac_stats;
1872 
1873 		h->ae_algo->ops->get_mac_stats(h, &mac_stats);
1874 		netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
1875 			    mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
1876 	}
1877 
1878 	hw_head = readl_relaxed(tx_ring->tqp->io_base +
1879 				HNS3_RING_TX_RING_HEAD_REG);
1880 	hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1881 				HNS3_RING_TX_RING_TAIL_REG);
1882 	fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1883 				HNS3_RING_TX_RING_FBDNUM_REG);
1884 	fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1885 				HNS3_RING_TX_RING_OFFSET_REG);
1886 	ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1887 				HNS3_RING_TX_RING_EBDNUM_REG);
1888 	ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1889 				HNS3_RING_TX_RING_EBD_OFFSET_REG);
1890 	bd_num = readl_relaxed(tx_ring->tqp->io_base +
1891 			       HNS3_RING_TX_RING_BD_NUM_REG);
1892 	bd_err = readl_relaxed(tx_ring->tqp->io_base +
1893 			       HNS3_RING_TX_RING_BD_ERR_REG);
1894 	ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1895 	tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1896 
1897 	netdev_info(ndev,
1898 		    "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1899 		    bd_num, hw_head, hw_tail, bd_err,
1900 		    readl(tx_ring->tqp_vector->mask_addr));
1901 	netdev_info(ndev,
1902 		    "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1903 		    ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
1904 
1905 	return true;
1906 }
1907 
1908 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
1909 {
1910 	struct hns3_nic_priv *priv = netdev_priv(ndev);
1911 	struct hnae3_handle *h = priv->ae_handle;
1912 
1913 	if (!hns3_get_tx_timeo_queue_info(ndev))
1914 		return;
1915 
1916 	/* request the reset, and let the hclge to determine
1917 	 * which reset level should be done
1918 	 */
1919 	if (h->ae_algo->ops->reset_event)
1920 		h->ae_algo->ops->reset_event(h->pdev, h);
1921 }
1922 
1923 #ifdef CONFIG_RFS_ACCEL
1924 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1925 			      u16 rxq_index, u32 flow_id)
1926 {
1927 	struct hnae3_handle *h = hns3_get_handle(dev);
1928 	struct flow_keys fkeys;
1929 
1930 	if (!h->ae_algo->ops->add_arfs_entry)
1931 		return -EOPNOTSUPP;
1932 
1933 	if (skb->encapsulation)
1934 		return -EPROTONOSUPPORT;
1935 
1936 	if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
1937 		return -EPROTONOSUPPORT;
1938 
1939 	if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
1940 	     fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
1941 	    (fkeys.basic.ip_proto != IPPROTO_TCP &&
1942 	     fkeys.basic.ip_proto != IPPROTO_UDP))
1943 		return -EPROTONOSUPPORT;
1944 
1945 	return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
1946 }
1947 #endif
1948 
1949 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
1950 				  struct ifla_vf_info *ivf)
1951 {
1952 	struct hnae3_handle *h = hns3_get_handle(ndev);
1953 
1954 	if (!h->ae_algo->ops->get_vf_config)
1955 		return -EOPNOTSUPP;
1956 
1957 	return h->ae_algo->ops->get_vf_config(h, vf, ivf);
1958 }
1959 
1960 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
1961 				      int link_state)
1962 {
1963 	struct hnae3_handle *h = hns3_get_handle(ndev);
1964 
1965 	if (!h->ae_algo->ops->set_vf_link_state)
1966 		return -EOPNOTSUPP;
1967 
1968 	return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
1969 }
1970 
1971 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
1972 				int min_tx_rate, int max_tx_rate)
1973 {
1974 	struct hnae3_handle *h = hns3_get_handle(ndev);
1975 
1976 	if (!h->ae_algo->ops->set_vf_rate)
1977 		return -EOPNOTSUPP;
1978 
1979 	return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
1980 					    false);
1981 }
1982 
1983 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
1984 {
1985 	struct hnae3_handle *h = hns3_get_handle(netdev);
1986 
1987 	if (!h->ae_algo->ops->set_vf_mac)
1988 		return -EOPNOTSUPP;
1989 
1990 	if (is_multicast_ether_addr(mac)) {
1991 		netdev_err(netdev,
1992 			   "Invalid MAC:%pM specified. Could not set MAC\n",
1993 			   mac);
1994 		return -EINVAL;
1995 	}
1996 
1997 	return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
1998 }
1999 
2000 static const struct net_device_ops hns3_nic_netdev_ops = {
2001 	.ndo_open		= hns3_nic_net_open,
2002 	.ndo_stop		= hns3_nic_net_stop,
2003 	.ndo_start_xmit		= hns3_nic_net_xmit,
2004 	.ndo_tx_timeout		= hns3_nic_net_timeout,
2005 	.ndo_set_mac_address	= hns3_nic_net_set_mac_address,
2006 	.ndo_do_ioctl		= hns3_nic_do_ioctl,
2007 	.ndo_change_mtu		= hns3_nic_change_mtu,
2008 	.ndo_set_features	= hns3_nic_set_features,
2009 	.ndo_features_check	= hns3_features_check,
2010 	.ndo_get_stats64	= hns3_nic_get_stats64,
2011 	.ndo_setup_tc		= hns3_nic_setup_tc,
2012 	.ndo_set_rx_mode	= hns3_nic_set_rx_mode,
2013 	.ndo_vlan_rx_add_vid	= hns3_vlan_rx_add_vid,
2014 	.ndo_vlan_rx_kill_vid	= hns3_vlan_rx_kill_vid,
2015 	.ndo_set_vf_vlan	= hns3_ndo_set_vf_vlan,
2016 	.ndo_set_vf_spoofchk	= hns3_set_vf_spoofchk,
2017 	.ndo_set_vf_trust	= hns3_set_vf_trust,
2018 #ifdef CONFIG_RFS_ACCEL
2019 	.ndo_rx_flow_steer	= hns3_rx_flow_steer,
2020 #endif
2021 	.ndo_get_vf_config	= hns3_nic_get_vf_config,
2022 	.ndo_set_vf_link_state	= hns3_nic_set_vf_link_state,
2023 	.ndo_set_vf_rate	= hns3_nic_set_vf_rate,
2024 	.ndo_set_vf_mac		= hns3_nic_set_vf_mac,
2025 };
2026 
2027 bool hns3_is_phys_func(struct pci_dev *pdev)
2028 {
2029 	u32 dev_id = pdev->device;
2030 
2031 	switch (dev_id) {
2032 	case HNAE3_DEV_ID_GE:
2033 	case HNAE3_DEV_ID_25GE:
2034 	case HNAE3_DEV_ID_25GE_RDMA:
2035 	case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
2036 	case HNAE3_DEV_ID_50GE_RDMA:
2037 	case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
2038 	case HNAE3_DEV_ID_100G_RDMA_MACSEC:
2039 		return true;
2040 	case HNAE3_DEV_ID_100G_VF:
2041 	case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
2042 		return false;
2043 	default:
2044 		dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2045 			 dev_id);
2046 	}
2047 
2048 	return false;
2049 }
2050 
2051 static void hns3_disable_sriov(struct pci_dev *pdev)
2052 {
2053 	/* If our VFs are assigned we cannot shut down SR-IOV
2054 	 * without causing issues, so just leave the hardware
2055 	 * available but disabled
2056 	 */
2057 	if (pci_vfs_assigned(pdev)) {
2058 		dev_warn(&pdev->dev,
2059 			 "disabling driver while VFs are assigned\n");
2060 		return;
2061 	}
2062 
2063 	pci_disable_sriov(pdev);
2064 }
2065 
2066 static void hns3_get_dev_capability(struct pci_dev *pdev,
2067 				    struct hnae3_ae_dev *ae_dev)
2068 {
2069 	if (pdev->revision >= 0x21) {
2070 		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
2071 		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
2072 	}
2073 }
2074 
2075 /* hns3_probe - Device initialization routine
2076  * @pdev: PCI device information struct
2077  * @ent: entry in hns3_pci_tbl
2078  *
2079  * hns3_probe initializes a PF identified by a pci_dev structure.
2080  * The OS initialization, configuring of the PF private structure,
2081  * and a hardware reset occur.
2082  *
2083  * Returns 0 on success, negative on failure
2084  */
2085 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2086 {
2087 	struct hnae3_ae_dev *ae_dev;
2088 	int ret;
2089 
2090 	ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
2091 	if (!ae_dev)
2092 		return -ENOMEM;
2093 
2094 	ae_dev->pdev = pdev;
2095 	ae_dev->flag = ent->driver_data;
2096 	hns3_get_dev_capability(pdev, ae_dev);
2097 	pci_set_drvdata(pdev, ae_dev);
2098 
2099 	ret = hnae3_register_ae_dev(ae_dev);
2100 	if (ret) {
2101 		devm_kfree(&pdev->dev, ae_dev);
2102 		pci_set_drvdata(pdev, NULL);
2103 	}
2104 
2105 	return ret;
2106 }
2107 
2108 /* hns3_remove - Device removal routine
2109  * @pdev: PCI device information struct
2110  */
2111 static void hns3_remove(struct pci_dev *pdev)
2112 {
2113 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2114 
2115 	if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2116 		hns3_disable_sriov(pdev);
2117 
2118 	hnae3_unregister_ae_dev(ae_dev);
2119 	pci_set_drvdata(pdev, NULL);
2120 }
2121 
2122 /**
2123  * hns3_pci_sriov_configure
2124  * @pdev: pointer to a pci_dev structure
2125  * @num_vfs: number of VFs to allocate
2126  *
2127  * Enable or change the number of VFs. Called when the user updates the number
2128  * of VFs in sysfs.
2129  **/
2130 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
2131 {
2132 	int ret;
2133 
2134 	if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2135 		dev_warn(&pdev->dev, "Can not config SRIOV\n");
2136 		return -EINVAL;
2137 	}
2138 
2139 	if (num_vfs) {
2140 		ret = pci_enable_sriov(pdev, num_vfs);
2141 		if (ret)
2142 			dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
2143 		else
2144 			return num_vfs;
2145 	} else if (!pci_vfs_assigned(pdev)) {
2146 		pci_disable_sriov(pdev);
2147 	} else {
2148 		dev_warn(&pdev->dev,
2149 			 "Unable to free VFs because some are assigned to VMs.\n");
2150 	}
2151 
2152 	return 0;
2153 }
2154 
2155 static void hns3_shutdown(struct pci_dev *pdev)
2156 {
2157 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2158 
2159 	hnae3_unregister_ae_dev(ae_dev);
2160 	devm_kfree(&pdev->dev, ae_dev);
2161 	pci_set_drvdata(pdev, NULL);
2162 
2163 	if (system_state == SYSTEM_POWER_OFF)
2164 		pci_set_power_state(pdev, PCI_D3hot);
2165 }
2166 
2167 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
2168 					    pci_channel_state_t state)
2169 {
2170 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2171 	pci_ers_result_t ret;
2172 
2173 	dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
2174 
2175 	if (state == pci_channel_io_perm_failure)
2176 		return PCI_ERS_RESULT_DISCONNECT;
2177 
2178 	if (!ae_dev || !ae_dev->ops) {
2179 		dev_err(&pdev->dev,
2180 			"Can't recover - error happened before device initialized\n");
2181 		return PCI_ERS_RESULT_NONE;
2182 	}
2183 
2184 	if (ae_dev->ops->handle_hw_ras_error)
2185 		ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
2186 	else
2187 		return PCI_ERS_RESULT_NONE;
2188 
2189 	return ret;
2190 }
2191 
2192 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
2193 {
2194 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2195 	const struct hnae3_ae_ops *ops;
2196 	enum hnae3_reset_type reset_type;
2197 	struct device *dev = &pdev->dev;
2198 
2199 	if (!ae_dev || !ae_dev->ops)
2200 		return PCI_ERS_RESULT_NONE;
2201 
2202 	ops = ae_dev->ops;
2203 	/* request the reset */
2204 	if (ops->reset_event && ops->get_reset_level &&
2205 	    ops->set_default_reset_request) {
2206 		if (ae_dev->hw_err_reset_req) {
2207 			reset_type = ops->get_reset_level(ae_dev,
2208 						&ae_dev->hw_err_reset_req);
2209 			ops->set_default_reset_request(ae_dev, reset_type);
2210 			dev_info(dev, "requesting reset due to PCI error\n");
2211 			ops->reset_event(pdev, NULL);
2212 		}
2213 
2214 		return PCI_ERS_RESULT_RECOVERED;
2215 	}
2216 
2217 	return PCI_ERS_RESULT_DISCONNECT;
2218 }
2219 
2220 static void hns3_reset_prepare(struct pci_dev *pdev)
2221 {
2222 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2223 
2224 	dev_info(&pdev->dev, "FLR prepare\n");
2225 	if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
2226 		ae_dev->ops->flr_prepare(ae_dev);
2227 }
2228 
2229 static void hns3_reset_done(struct pci_dev *pdev)
2230 {
2231 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2232 
2233 	dev_info(&pdev->dev, "FLR done\n");
2234 	if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
2235 		ae_dev->ops->flr_done(ae_dev);
2236 }
2237 
2238 static const struct pci_error_handlers hns3_err_handler = {
2239 	.error_detected = hns3_error_detected,
2240 	.slot_reset     = hns3_slot_reset,
2241 	.reset_prepare	= hns3_reset_prepare,
2242 	.reset_done	= hns3_reset_done,
2243 };
2244 
2245 static struct pci_driver hns3_driver = {
2246 	.name     = hns3_driver_name,
2247 	.id_table = hns3_pci_tbl,
2248 	.probe    = hns3_probe,
2249 	.remove   = hns3_remove,
2250 	.shutdown = hns3_shutdown,
2251 	.sriov_configure = hns3_pci_sriov_configure,
2252 	.err_handler    = &hns3_err_handler,
2253 };
2254 
2255 /* set default feature to hns3 */
2256 static void hns3_set_default_feature(struct net_device *netdev)
2257 {
2258 	struct hnae3_handle *h = hns3_get_handle(netdev);
2259 	struct pci_dev *pdev = h->pdev;
2260 
2261 	netdev->priv_flags |= IFF_UNICAST_FLT;
2262 
2263 	netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2264 		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2265 		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2266 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2267 		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2268 		NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST;
2269 
2270 	netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2271 
2272 	netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2273 		NETIF_F_HW_VLAN_CTAG_FILTER |
2274 		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2275 		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2276 		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2277 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2278 		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2279 		NETIF_F_FRAGLIST;
2280 
2281 	netdev->vlan_features |=
2282 		NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2283 		NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2284 		NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2285 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2286 		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2287 		NETIF_F_FRAGLIST;
2288 
2289 	netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2290 		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2291 		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2292 		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2293 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2294 		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2295 		NETIF_F_FRAGLIST;
2296 
2297 	if (pdev->revision >= 0x21) {
2298 		netdev->hw_features |= NETIF_F_GRO_HW;
2299 		netdev->features |= NETIF_F_GRO_HW;
2300 
2301 		if (!(h->flags & HNAE3_SUPPORT_VF)) {
2302 			netdev->hw_features |= NETIF_F_NTUPLE;
2303 			netdev->features |= NETIF_F_NTUPLE;
2304 		}
2305 	}
2306 }
2307 
2308 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2309 			     struct hns3_desc_cb *cb)
2310 {
2311 	unsigned int order = hns3_page_order(ring);
2312 	struct page *p;
2313 
2314 	p = dev_alloc_pages(order);
2315 	if (!p)
2316 		return -ENOMEM;
2317 
2318 	cb->priv = p;
2319 	cb->page_offset = 0;
2320 	cb->reuse_flag = 0;
2321 	cb->buf  = page_address(p);
2322 	cb->length = hns3_page_size(ring);
2323 	cb->type = DESC_TYPE_PAGE;
2324 
2325 	return 0;
2326 }
2327 
2328 static void hns3_free_buffer(struct hns3_enet_ring *ring,
2329 			     struct hns3_desc_cb *cb)
2330 {
2331 	if (cb->type == DESC_TYPE_SKB)
2332 		dev_kfree_skb_any((struct sk_buff *)cb->priv);
2333 	else if (!HNAE3_IS_TX_RING(ring))
2334 		put_page((struct page *)cb->priv);
2335 	memset(cb, 0, sizeof(*cb));
2336 }
2337 
2338 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2339 {
2340 	cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2341 			       cb->length, ring_to_dma_dir(ring));
2342 
2343 	if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
2344 		return -EIO;
2345 
2346 	return 0;
2347 }
2348 
2349 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2350 			      struct hns3_desc_cb *cb)
2351 {
2352 	if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB)
2353 		dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2354 				 ring_to_dma_dir(ring));
2355 	else if (cb->length)
2356 		dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2357 			       ring_to_dma_dir(ring));
2358 }
2359 
2360 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2361 {
2362 	hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2363 	ring->desc[i].addr = 0;
2364 }
2365 
2366 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2367 {
2368 	struct hns3_desc_cb *cb = &ring->desc_cb[i];
2369 
2370 	if (!ring->desc_cb[i].dma)
2371 		return;
2372 
2373 	hns3_buffer_detach(ring, i);
2374 	hns3_free_buffer(ring, cb);
2375 }
2376 
2377 static void hns3_free_buffers(struct hns3_enet_ring *ring)
2378 {
2379 	int i;
2380 
2381 	for (i = 0; i < ring->desc_num; i++)
2382 		hns3_free_buffer_detach(ring, i);
2383 }
2384 
2385 /* free desc along with its attached buffer */
2386 static void hns3_free_desc(struct hns3_enet_ring *ring)
2387 {
2388 	int size = ring->desc_num * sizeof(ring->desc[0]);
2389 
2390 	hns3_free_buffers(ring);
2391 
2392 	if (ring->desc) {
2393 		dma_free_coherent(ring_to_dev(ring), size,
2394 				  ring->desc, ring->desc_dma_addr);
2395 		ring->desc = NULL;
2396 	}
2397 }
2398 
2399 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2400 {
2401 	int size = ring->desc_num * sizeof(ring->desc[0]);
2402 
2403 	ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2404 					&ring->desc_dma_addr, GFP_KERNEL);
2405 	if (!ring->desc)
2406 		return -ENOMEM;
2407 
2408 	return 0;
2409 }
2410 
2411 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2412 				   struct hns3_desc_cb *cb)
2413 {
2414 	int ret;
2415 
2416 	ret = hns3_alloc_buffer(ring, cb);
2417 	if (ret)
2418 		goto out;
2419 
2420 	ret = hns3_map_buffer(ring, cb);
2421 	if (ret)
2422 		goto out_with_buf;
2423 
2424 	return 0;
2425 
2426 out_with_buf:
2427 	hns3_free_buffer(ring, cb);
2428 out:
2429 	return ret;
2430 }
2431 
2432 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2433 {
2434 	int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2435 
2436 	if (ret)
2437 		return ret;
2438 
2439 	ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2440 
2441 	return 0;
2442 }
2443 
2444 /* Allocate memory for raw pkg, and map with dma */
2445 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2446 {
2447 	int i, j, ret;
2448 
2449 	for (i = 0; i < ring->desc_num; i++) {
2450 		ret = hns3_alloc_buffer_attach(ring, i);
2451 		if (ret)
2452 			goto out_buffer_fail;
2453 	}
2454 
2455 	return 0;
2456 
2457 out_buffer_fail:
2458 	for (j = i - 1; j >= 0; j--)
2459 		hns3_free_buffer_detach(ring, j);
2460 	return ret;
2461 }
2462 
2463 /* detach a in-used buffer and replace with a reserved one */
2464 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2465 				struct hns3_desc_cb *res_cb)
2466 {
2467 	hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2468 	ring->desc_cb[i] = *res_cb;
2469 	ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2470 	ring->desc[i].rx.bd_base_info = 0;
2471 }
2472 
2473 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2474 {
2475 	ring->desc_cb[i].reuse_flag = 0;
2476 	ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
2477 					 ring->desc_cb[i].page_offset);
2478 	ring->desc[i].rx.bd_base_info = 0;
2479 }
2480 
2481 static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2482 				  int *bytes, int *pkts)
2483 {
2484 	int ntc = ring->next_to_clean;
2485 	struct hns3_desc_cb *desc_cb;
2486 
2487 	while (head != ntc) {
2488 		desc_cb = &ring->desc_cb[ntc];
2489 		(*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2490 		(*bytes) += desc_cb->length;
2491 		/* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2492 		hns3_free_buffer_detach(ring, ntc);
2493 
2494 		if (++ntc == ring->desc_num)
2495 			ntc = 0;
2496 
2497 		/* Issue prefetch for next Tx descriptor */
2498 		prefetch(&ring->desc_cb[ntc]);
2499 	}
2500 
2501 	/* This smp_store_release() pairs with smp_load_acquire() in
2502 	 * ring_space called by hns3_nic_net_xmit.
2503 	 */
2504 	smp_store_release(&ring->next_to_clean, ntc);
2505 }
2506 
2507 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2508 {
2509 	int u = ring->next_to_use;
2510 	int c = ring->next_to_clean;
2511 
2512 	if (unlikely(h > ring->desc_num))
2513 		return 0;
2514 
2515 	return u > c ? (h > c && h <= u) : (h > c || h <= u);
2516 }
2517 
2518 void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
2519 {
2520 	struct net_device *netdev = ring_to_netdev(ring);
2521 	struct hns3_nic_priv *priv = netdev_priv(netdev);
2522 	struct netdev_queue *dev_queue;
2523 	int bytes, pkts;
2524 	int head;
2525 
2526 	head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2527 
2528 	if (is_ring_empty(ring) || head == ring->next_to_clean)
2529 		return; /* no data to poll */
2530 
2531 	rmb(); /* Make sure head is ready before touch any data */
2532 
2533 	if (unlikely(!is_valid_clean_head(ring, head))) {
2534 		hns3_rl_err(netdev, "wrong head (%d, %d-%d)\n", head,
2535 			    ring->next_to_use, ring->next_to_clean);
2536 
2537 		u64_stats_update_begin(&ring->syncp);
2538 		ring->stats.io_err_cnt++;
2539 		u64_stats_update_end(&ring->syncp);
2540 		return;
2541 	}
2542 
2543 	bytes = 0;
2544 	pkts = 0;
2545 	hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
2546 
2547 	ring->tqp_vector->tx_group.total_bytes += bytes;
2548 	ring->tqp_vector->tx_group.total_packets += pkts;
2549 
2550 	u64_stats_update_begin(&ring->syncp);
2551 	ring->stats.tx_bytes += bytes;
2552 	ring->stats.tx_pkts += pkts;
2553 	u64_stats_update_end(&ring->syncp);
2554 
2555 	dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2556 	netdev_tx_completed_queue(dev_queue, pkts, bytes);
2557 
2558 	if (unlikely(netif_carrier_ok(netdev) &&
2559 		     ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
2560 		/* Make sure that anybody stopping the queue after this
2561 		 * sees the new next_to_clean.
2562 		 */
2563 		smp_mb();
2564 		if (netif_tx_queue_stopped(dev_queue) &&
2565 		    !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
2566 			netif_tx_wake_queue(dev_queue);
2567 			ring->stats.restart_queue++;
2568 		}
2569 	}
2570 }
2571 
2572 static int hns3_desc_unused(struct hns3_enet_ring *ring)
2573 {
2574 	int ntc = ring->next_to_clean;
2575 	int ntu = ring->next_to_use;
2576 
2577 	return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2578 }
2579 
2580 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
2581 				      int cleand_count)
2582 {
2583 	struct hns3_desc_cb *desc_cb;
2584 	struct hns3_desc_cb res_cbs;
2585 	int i, ret;
2586 
2587 	for (i = 0; i < cleand_count; i++) {
2588 		desc_cb = &ring->desc_cb[ring->next_to_use];
2589 		if (desc_cb->reuse_flag) {
2590 			u64_stats_update_begin(&ring->syncp);
2591 			ring->stats.reuse_pg_cnt++;
2592 			u64_stats_update_end(&ring->syncp);
2593 
2594 			hns3_reuse_buffer(ring, ring->next_to_use);
2595 		} else {
2596 			ret = hns3_reserve_buffer_map(ring, &res_cbs);
2597 			if (ret) {
2598 				u64_stats_update_begin(&ring->syncp);
2599 				ring->stats.sw_err_cnt++;
2600 				u64_stats_update_end(&ring->syncp);
2601 
2602 				hns3_rl_err(ring_to_netdev(ring),
2603 					    "alloc rx buffer failed: %d\n",
2604 					    ret);
2605 				break;
2606 			}
2607 			hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2608 
2609 			u64_stats_update_begin(&ring->syncp);
2610 			ring->stats.non_reuse_pg++;
2611 			u64_stats_update_end(&ring->syncp);
2612 		}
2613 
2614 		ring_ptr_move_fw(ring, next_to_use);
2615 	}
2616 
2617 	wmb(); /* Make all data has been write before submit */
2618 	writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2619 }
2620 
2621 static bool hns3_page_is_reusable(struct page *page)
2622 {
2623 	return page_to_nid(page) == numa_mem_id() &&
2624 		!page_is_pfmemalloc(page);
2625 }
2626 
2627 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2628 				struct hns3_enet_ring *ring, int pull_len,
2629 				struct hns3_desc_cb *desc_cb)
2630 {
2631 	struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2632 	int size = le16_to_cpu(desc->rx.size);
2633 	u32 truesize = hns3_buf_size(ring);
2634 
2635 	skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
2636 			size - pull_len, truesize);
2637 
2638 	/* Avoid re-using remote pages, or the stack is still using the page
2639 	 * when page_offset rollback to zero, flag default unreuse
2640 	 */
2641 	if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) ||
2642 	    (!desc_cb->page_offset && page_count(desc_cb->priv) > 1))
2643 		return;
2644 
2645 	/* Move offset up to the next cache line */
2646 	desc_cb->page_offset += truesize;
2647 
2648 	if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) {
2649 		desc_cb->reuse_flag = 1;
2650 		/* Bump ref count on page before it is given */
2651 		get_page(desc_cb->priv);
2652 	} else if (page_count(desc_cb->priv) == 1) {
2653 		desc_cb->reuse_flag = 1;
2654 		desc_cb->page_offset = 0;
2655 		get_page(desc_cb->priv);
2656 	}
2657 }
2658 
2659 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
2660 {
2661 	__be16 type = skb->protocol;
2662 	struct tcphdr *th;
2663 	int depth = 0;
2664 
2665 	while (eth_type_vlan(type)) {
2666 		struct vlan_hdr *vh;
2667 
2668 		if ((depth + VLAN_HLEN) > skb_headlen(skb))
2669 			return -EFAULT;
2670 
2671 		vh = (struct vlan_hdr *)(skb->data + depth);
2672 		type = vh->h_vlan_encapsulated_proto;
2673 		depth += VLAN_HLEN;
2674 	}
2675 
2676 	skb_set_network_header(skb, depth);
2677 
2678 	if (type == htons(ETH_P_IP)) {
2679 		const struct iphdr *iph = ip_hdr(skb);
2680 
2681 		depth += sizeof(struct iphdr);
2682 		skb_set_transport_header(skb, depth);
2683 		th = tcp_hdr(skb);
2684 		th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
2685 					  iph->daddr, 0);
2686 	} else if (type == htons(ETH_P_IPV6)) {
2687 		const struct ipv6hdr *iph = ipv6_hdr(skb);
2688 
2689 		depth += sizeof(struct ipv6hdr);
2690 		skb_set_transport_header(skb, depth);
2691 		th = tcp_hdr(skb);
2692 		th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
2693 					  &iph->daddr, 0);
2694 	} else {
2695 		hns3_rl_err(skb->dev,
2696 			    "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2697 			    be16_to_cpu(type), depth);
2698 		return -EFAULT;
2699 	}
2700 
2701 	skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2702 	if (th->cwr)
2703 		skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2704 
2705 	if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
2706 		skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
2707 
2708 	skb->csum_start = (unsigned char *)th - skb->head;
2709 	skb->csum_offset = offsetof(struct tcphdr, check);
2710 	skb->ip_summed = CHECKSUM_PARTIAL;
2711 
2712 	trace_hns3_gro(skb);
2713 
2714 	return 0;
2715 }
2716 
2717 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2718 			     u32 l234info, u32 bd_base_info, u32 ol_info)
2719 {
2720 	struct net_device *netdev = ring_to_netdev(ring);
2721 	int l3_type, l4_type;
2722 	int ol4_type;
2723 
2724 	skb->ip_summed = CHECKSUM_NONE;
2725 
2726 	skb_checksum_none_assert(skb);
2727 
2728 	if (!(netdev->features & NETIF_F_RXCSUM))
2729 		return;
2730 
2731 	/* check if hardware has done checksum */
2732 	if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
2733 		return;
2734 
2735 	if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2736 				 BIT(HNS3_RXD_OL3E_B) |
2737 				 BIT(HNS3_RXD_OL4E_B)))) {
2738 		u64_stats_update_begin(&ring->syncp);
2739 		ring->stats.l3l4_csum_err++;
2740 		u64_stats_update_end(&ring->syncp);
2741 
2742 		return;
2743 	}
2744 
2745 	ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
2746 				   HNS3_RXD_OL4ID_S);
2747 	switch (ol4_type) {
2748 	case HNS3_OL4_TYPE_MAC_IN_UDP:
2749 	case HNS3_OL4_TYPE_NVGRE:
2750 		skb->csum_level = 1;
2751 		/* fall through */
2752 	case HNS3_OL4_TYPE_NO_TUN:
2753 		l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2754 					  HNS3_RXD_L3ID_S);
2755 		l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2756 					  HNS3_RXD_L4ID_S);
2757 
2758 		/* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
2759 		if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2760 		     l3_type == HNS3_L3_TYPE_IPV6) &&
2761 		    (l4_type == HNS3_L4_TYPE_UDP ||
2762 		     l4_type == HNS3_L4_TYPE_TCP ||
2763 		     l4_type == HNS3_L4_TYPE_SCTP))
2764 			skb->ip_summed = CHECKSUM_UNNECESSARY;
2765 		break;
2766 	default:
2767 		break;
2768 	}
2769 }
2770 
2771 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2772 {
2773 	if (skb_has_frag_list(skb))
2774 		napi_gro_flush(&ring->tqp_vector->napi, false);
2775 
2776 	napi_gro_receive(&ring->tqp_vector->napi, skb);
2777 }
2778 
2779 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2780 				struct hns3_desc *desc, u32 l234info,
2781 				u16 *vlan_tag)
2782 {
2783 	struct hnae3_handle *handle = ring->tqp->handle;
2784 	struct pci_dev *pdev = ring->tqp->handle->pdev;
2785 
2786 	if (pdev->revision == 0x20) {
2787 		*vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2788 		if (!(*vlan_tag & VLAN_VID_MASK))
2789 			*vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2790 
2791 		return (*vlan_tag != 0);
2792 	}
2793 
2794 #define HNS3_STRP_OUTER_VLAN	0x1
2795 #define HNS3_STRP_INNER_VLAN	0x2
2796 #define HNS3_STRP_BOTH		0x3
2797 
2798 	/* Hardware always insert VLAN tag into RX descriptor when
2799 	 * remove the tag from packet, driver needs to determine
2800 	 * reporting which tag to stack.
2801 	 */
2802 	switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2803 				HNS3_RXD_STRP_TAGP_S)) {
2804 	case HNS3_STRP_OUTER_VLAN:
2805 		if (handle->port_base_vlan_state !=
2806 				HNAE3_PORT_BASE_VLAN_DISABLE)
2807 			return false;
2808 
2809 		*vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2810 		return true;
2811 	case HNS3_STRP_INNER_VLAN:
2812 		if (handle->port_base_vlan_state !=
2813 				HNAE3_PORT_BASE_VLAN_DISABLE)
2814 			return false;
2815 
2816 		*vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2817 		return true;
2818 	case HNS3_STRP_BOTH:
2819 		if (handle->port_base_vlan_state ==
2820 				HNAE3_PORT_BASE_VLAN_DISABLE)
2821 			*vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2822 		else
2823 			*vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2824 
2825 		return true;
2826 	default:
2827 		return false;
2828 	}
2829 }
2830 
2831 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
2832 			  unsigned char *va)
2833 {
2834 	struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2835 	struct net_device *netdev = ring_to_netdev(ring);
2836 	struct sk_buff *skb;
2837 
2838 	ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2839 	skb = ring->skb;
2840 	if (unlikely(!skb)) {
2841 		hns3_rl_err(netdev, "alloc rx skb fail\n");
2842 
2843 		u64_stats_update_begin(&ring->syncp);
2844 		ring->stats.sw_err_cnt++;
2845 		u64_stats_update_end(&ring->syncp);
2846 
2847 		return -ENOMEM;
2848 	}
2849 
2850 	trace_hns3_rx_desc(ring);
2851 	prefetchw(skb->data);
2852 
2853 	ring->pending_buf = 1;
2854 	ring->frag_num = 0;
2855 	ring->tail_skb = NULL;
2856 	if (length <= HNS3_RX_HEAD_SIZE) {
2857 		memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2858 
2859 		/* We can reuse buffer as-is, just make sure it is local */
2860 		if (likely(hns3_page_is_reusable(desc_cb->priv)))
2861 			desc_cb->reuse_flag = 1;
2862 		else /* This page cannot be reused so discard it */
2863 			put_page(desc_cb->priv);
2864 
2865 		ring_ptr_move_fw(ring, next_to_clean);
2866 		return 0;
2867 	}
2868 	u64_stats_update_begin(&ring->syncp);
2869 	ring->stats.seg_pkt_cnt++;
2870 	u64_stats_update_end(&ring->syncp);
2871 
2872 	ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
2873 	__skb_put(skb, ring->pull_len);
2874 	hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
2875 			    desc_cb);
2876 	ring_ptr_move_fw(ring, next_to_clean);
2877 
2878 	return 0;
2879 }
2880 
2881 static int hns3_add_frag(struct hns3_enet_ring *ring)
2882 {
2883 	struct sk_buff *skb = ring->skb;
2884 	struct sk_buff *head_skb = skb;
2885 	struct sk_buff *new_skb;
2886 	struct hns3_desc_cb *desc_cb;
2887 	struct hns3_desc *desc;
2888 	u32 bd_base_info;
2889 
2890 	do {
2891 		desc = &ring->desc[ring->next_to_clean];
2892 		desc_cb = &ring->desc_cb[ring->next_to_clean];
2893 		bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2894 		/* make sure HW write desc complete */
2895 		dma_rmb();
2896 		if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
2897 			return -ENXIO;
2898 
2899 		if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2900 			new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
2901 			if (unlikely(!new_skb)) {
2902 				hns3_rl_err(ring_to_netdev(ring),
2903 					    "alloc rx fraglist skb fail\n");
2904 				return -ENXIO;
2905 			}
2906 			ring->frag_num = 0;
2907 
2908 			if (ring->tail_skb) {
2909 				ring->tail_skb->next = new_skb;
2910 				ring->tail_skb = new_skb;
2911 			} else {
2912 				skb_shinfo(skb)->frag_list = new_skb;
2913 				ring->tail_skb = new_skb;
2914 			}
2915 		}
2916 
2917 		if (ring->tail_skb) {
2918 			head_skb->truesize += hns3_buf_size(ring);
2919 			head_skb->data_len += le16_to_cpu(desc->rx.size);
2920 			head_skb->len += le16_to_cpu(desc->rx.size);
2921 			skb = ring->tail_skb;
2922 		}
2923 
2924 		hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
2925 		trace_hns3_rx_desc(ring);
2926 		ring_ptr_move_fw(ring, next_to_clean);
2927 		ring->pending_buf++;
2928 	} while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
2929 
2930 	return 0;
2931 }
2932 
2933 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2934 				     struct sk_buff *skb, u32 l234info,
2935 				     u32 bd_base_info, u32 ol_info)
2936 {
2937 	u32 l3_type;
2938 
2939 	skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2940 						    HNS3_RXD_GRO_SIZE_M,
2941 						    HNS3_RXD_GRO_SIZE_S);
2942 	/* if there is no HW GRO, do not set gro params */
2943 	if (!skb_shinfo(skb)->gso_size) {
2944 		hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
2945 		return 0;
2946 	}
2947 
2948 	NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
2949 						  HNS3_RXD_GRO_COUNT_M,
2950 						  HNS3_RXD_GRO_COUNT_S);
2951 
2952 	l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
2953 	if (l3_type == HNS3_L3_TYPE_IPV4)
2954 		skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2955 	else if (l3_type == HNS3_L3_TYPE_IPV6)
2956 		skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2957 	else
2958 		return -EFAULT;
2959 
2960 	return  hns3_gro_complete(skb, l234info);
2961 }
2962 
2963 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2964 				     struct sk_buff *skb, u32 rss_hash)
2965 {
2966 	struct hnae3_handle *handle = ring->tqp->handle;
2967 	enum pkt_hash_types rss_type;
2968 
2969 	if (rss_hash)
2970 		rss_type = handle->kinfo.rss_type;
2971 	else
2972 		rss_type = PKT_HASH_TYPE_NONE;
2973 
2974 	skb_set_hash(skb, rss_hash, rss_type);
2975 }
2976 
2977 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
2978 {
2979 	struct net_device *netdev = ring_to_netdev(ring);
2980 	enum hns3_pkt_l2t_type l2_frame_type;
2981 	u32 bd_base_info, l234info, ol_info;
2982 	struct hns3_desc *desc;
2983 	unsigned int len;
2984 	int pre_ntc, ret;
2985 
2986 	/* bdinfo handled below is only valid on the last BD of the
2987 	 * current packet, and ring->next_to_clean indicates the first
2988 	 * descriptor of next packet, so need - 1 below.
2989 	 */
2990 	pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
2991 					(ring->desc_num - 1);
2992 	desc = &ring->desc[pre_ntc];
2993 	bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2994 	l234info = le32_to_cpu(desc->rx.l234_info);
2995 	ol_info = le32_to_cpu(desc->rx.ol_info);
2996 
2997 	/* Based on hw strategy, the tag offloaded will be stored at
2998 	 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2999 	 * in one layer tag case.
3000 	 */
3001 	if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
3002 		u16 vlan_tag;
3003 
3004 		if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
3005 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3006 					       vlan_tag);
3007 	}
3008 
3009 	if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
3010 				  BIT(HNS3_RXD_L2E_B))))) {
3011 		u64_stats_update_begin(&ring->syncp);
3012 		if (l234info & BIT(HNS3_RXD_L2E_B))
3013 			ring->stats.l2_err++;
3014 		else
3015 			ring->stats.err_pkt_len++;
3016 		u64_stats_update_end(&ring->syncp);
3017 
3018 		return -EFAULT;
3019 	}
3020 
3021 	len = skb->len;
3022 
3023 	/* Do update ip stack process */
3024 	skb->protocol = eth_type_trans(skb, netdev);
3025 
3026 	/* This is needed in order to enable forwarding support */
3027 	ret = hns3_set_gro_and_checksum(ring, skb, l234info,
3028 					bd_base_info, ol_info);
3029 	if (unlikely(ret)) {
3030 		u64_stats_update_begin(&ring->syncp);
3031 		ring->stats.rx_err_cnt++;
3032 		u64_stats_update_end(&ring->syncp);
3033 		return ret;
3034 	}
3035 
3036 	l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
3037 					HNS3_RXD_DMAC_S);
3038 
3039 	u64_stats_update_begin(&ring->syncp);
3040 	ring->stats.rx_pkts++;
3041 	ring->stats.rx_bytes += len;
3042 
3043 	if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
3044 		ring->stats.rx_multicast++;
3045 
3046 	u64_stats_update_end(&ring->syncp);
3047 
3048 	ring->tqp_vector->rx_group.total_bytes += len;
3049 
3050 	hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
3051 	return 0;
3052 }
3053 
3054 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
3055 {
3056 	struct sk_buff *skb = ring->skb;
3057 	struct hns3_desc_cb *desc_cb;
3058 	struct hns3_desc *desc;
3059 	unsigned int length;
3060 	u32 bd_base_info;
3061 	int ret;
3062 
3063 	desc = &ring->desc[ring->next_to_clean];
3064 	desc_cb = &ring->desc_cb[ring->next_to_clean];
3065 
3066 	prefetch(desc);
3067 
3068 	length = le16_to_cpu(desc->rx.size);
3069 	bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
3070 
3071 	/* Check valid BD */
3072 	if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
3073 		return -ENXIO;
3074 
3075 	if (!skb)
3076 		ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
3077 
3078 	/* Prefetch first cache line of first page
3079 	 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
3080 	 * line size is 64B so need to prefetch twice to make it 128B. But in
3081 	 * actual we can have greater size of caches with 128B Level 1 cache
3082 	 * lines. In such a case, single fetch would suffice to cache in the
3083 	 * relevant part of the header.
3084 	 */
3085 	prefetch(ring->va);
3086 #if L1_CACHE_BYTES < 128
3087 	prefetch(ring->va + L1_CACHE_BYTES);
3088 #endif
3089 
3090 	if (!skb) {
3091 		ret = hns3_alloc_skb(ring, length, ring->va);
3092 		skb = ring->skb;
3093 
3094 		if (ret < 0) /* alloc buffer fail */
3095 			return ret;
3096 		if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
3097 			ret = hns3_add_frag(ring);
3098 			if (ret)
3099 				return ret;
3100 		}
3101 	} else {
3102 		ret = hns3_add_frag(ring);
3103 		if (ret)
3104 			return ret;
3105 	}
3106 
3107 	/* As the head data may be changed when GRO enable, copy
3108 	 * the head data in after other data rx completed
3109 	 */
3110 	if (skb->len > HNS3_RX_HEAD_SIZE)
3111 		memcpy(skb->data, ring->va,
3112 		       ALIGN(ring->pull_len, sizeof(long)));
3113 
3114 	ret = hns3_handle_bdinfo(ring, skb);
3115 	if (unlikely(ret)) {
3116 		dev_kfree_skb_any(skb);
3117 		return ret;
3118 	}
3119 
3120 	skb_record_rx_queue(skb, ring->tqp->tqp_index);
3121 	return 0;
3122 }
3123 
3124 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
3125 		       void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
3126 {
3127 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
3128 	int unused_count = hns3_desc_unused(ring);
3129 	int recv_pkts = 0;
3130 	int recv_bds = 0;
3131 	int err, num;
3132 
3133 	num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
3134 	num -= unused_count;
3135 	unused_count -= ring->pending_buf;
3136 
3137 	if (num <= 0)
3138 		goto out;
3139 
3140 	rmb(); /* Make sure num taken effect before the other data is touched */
3141 
3142 	while (recv_pkts < budget && recv_bds < num) {
3143 		/* Reuse or realloc buffers */
3144 		if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
3145 			hns3_nic_alloc_rx_buffers(ring, unused_count);
3146 			unused_count = hns3_desc_unused(ring) -
3147 					ring->pending_buf;
3148 		}
3149 
3150 		/* Poll one pkt */
3151 		err = hns3_handle_rx_bd(ring);
3152 		/* Do not get FE for the packet or failed to alloc skb */
3153 		if (unlikely(!ring->skb || err == -ENXIO)) {
3154 			goto out;
3155 		} else if (likely(!err)) {
3156 			rx_fn(ring, ring->skb);
3157 			recv_pkts++;
3158 		}
3159 
3160 		recv_bds += ring->pending_buf;
3161 		unused_count += ring->pending_buf;
3162 		ring->skb = NULL;
3163 		ring->pending_buf = 0;
3164 	}
3165 
3166 out:
3167 	/* Make all data has been write before submit */
3168 	if (unused_count > 0)
3169 		hns3_nic_alloc_rx_buffers(ring, unused_count);
3170 
3171 	return recv_pkts;
3172 }
3173 
3174 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
3175 {
3176 #define HNS3_RX_LOW_BYTE_RATE 10000
3177 #define HNS3_RX_MID_BYTE_RATE 20000
3178 #define HNS3_RX_ULTRA_PACKET_RATE 40
3179 
3180 	enum hns3_flow_level_range new_flow_level;
3181 	struct hns3_enet_tqp_vector *tqp_vector;
3182 	int packets_per_msecs, bytes_per_msecs;
3183 	u32 time_passed_ms;
3184 
3185 	tqp_vector = ring_group->ring->tqp_vector;
3186 	time_passed_ms =
3187 		jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
3188 	if (!time_passed_ms)
3189 		return false;
3190 
3191 	do_div(ring_group->total_packets, time_passed_ms);
3192 	packets_per_msecs = ring_group->total_packets;
3193 
3194 	do_div(ring_group->total_bytes, time_passed_ms);
3195 	bytes_per_msecs = ring_group->total_bytes;
3196 
3197 	new_flow_level = ring_group->coal.flow_level;
3198 
3199 	/* Simple throttlerate management
3200 	 * 0-10MB/s   lower     (50000 ints/s)
3201 	 * 10-20MB/s   middle    (20000 ints/s)
3202 	 * 20-1249MB/s high      (18000 ints/s)
3203 	 * > 40000pps  ultra     (8000 ints/s)
3204 	 */
3205 	switch (new_flow_level) {
3206 	case HNS3_FLOW_LOW:
3207 		if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
3208 			new_flow_level = HNS3_FLOW_MID;
3209 		break;
3210 	case HNS3_FLOW_MID:
3211 		if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
3212 			new_flow_level = HNS3_FLOW_HIGH;
3213 		else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
3214 			new_flow_level = HNS3_FLOW_LOW;
3215 		break;
3216 	case HNS3_FLOW_HIGH:
3217 	case HNS3_FLOW_ULTRA:
3218 	default:
3219 		if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
3220 			new_flow_level = HNS3_FLOW_MID;
3221 		break;
3222 	}
3223 
3224 	if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
3225 	    &tqp_vector->rx_group == ring_group)
3226 		new_flow_level = HNS3_FLOW_ULTRA;
3227 
3228 	ring_group->total_bytes = 0;
3229 	ring_group->total_packets = 0;
3230 	ring_group->coal.flow_level = new_flow_level;
3231 
3232 	return true;
3233 }
3234 
3235 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
3236 {
3237 	struct hns3_enet_tqp_vector *tqp_vector;
3238 	u16 new_int_gl;
3239 
3240 	if (!ring_group->ring)
3241 		return false;
3242 
3243 	tqp_vector = ring_group->ring->tqp_vector;
3244 	if (!tqp_vector->last_jiffies)
3245 		return false;
3246 
3247 	if (ring_group->total_packets == 0) {
3248 		ring_group->coal.int_gl = HNS3_INT_GL_50K;
3249 		ring_group->coal.flow_level = HNS3_FLOW_LOW;
3250 		return true;
3251 	}
3252 
3253 	if (!hns3_get_new_flow_lvl(ring_group))
3254 		return false;
3255 
3256 	new_int_gl = ring_group->coal.int_gl;
3257 	switch (ring_group->coal.flow_level) {
3258 	case HNS3_FLOW_LOW:
3259 		new_int_gl = HNS3_INT_GL_50K;
3260 		break;
3261 	case HNS3_FLOW_MID:
3262 		new_int_gl = HNS3_INT_GL_20K;
3263 		break;
3264 	case HNS3_FLOW_HIGH:
3265 		new_int_gl = HNS3_INT_GL_18K;
3266 		break;
3267 	case HNS3_FLOW_ULTRA:
3268 		new_int_gl = HNS3_INT_GL_8K;
3269 		break;
3270 	default:
3271 		break;
3272 	}
3273 
3274 	if (new_int_gl != ring_group->coal.int_gl) {
3275 		ring_group->coal.int_gl = new_int_gl;
3276 		return true;
3277 	}
3278 	return false;
3279 }
3280 
3281 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3282 {
3283 	struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3284 	struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3285 	bool rx_update, tx_update;
3286 
3287 	/* update param every 1000ms */
3288 	if (time_before(jiffies,
3289 			tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
3290 		return;
3291 
3292 	if (rx_group->coal.gl_adapt_enable) {
3293 		rx_update = hns3_get_new_int_gl(rx_group);
3294 		if (rx_update)
3295 			hns3_set_vector_coalesce_rx_gl(tqp_vector,
3296 						       rx_group->coal.int_gl);
3297 	}
3298 
3299 	if (tx_group->coal.gl_adapt_enable) {
3300 		tx_update = hns3_get_new_int_gl(tx_group);
3301 		if (tx_update)
3302 			hns3_set_vector_coalesce_tx_gl(tqp_vector,
3303 						       tx_group->coal.int_gl);
3304 	}
3305 
3306 	tqp_vector->last_jiffies = jiffies;
3307 }
3308 
3309 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3310 {
3311 	struct hns3_nic_priv *priv = netdev_priv(napi->dev);
3312 	struct hns3_enet_ring *ring;
3313 	int rx_pkt_total = 0;
3314 
3315 	struct hns3_enet_tqp_vector *tqp_vector =
3316 		container_of(napi, struct hns3_enet_tqp_vector, napi);
3317 	bool clean_complete = true;
3318 	int rx_budget = budget;
3319 
3320 	if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3321 		napi_complete(napi);
3322 		return 0;
3323 	}
3324 
3325 	/* Since the actual Tx work is minimal, we can give the Tx a larger
3326 	 * budget and be more aggressive about cleaning up the Tx descriptors.
3327 	 */
3328 	hns3_for_each_ring(ring, tqp_vector->tx_group)
3329 		hns3_clean_tx_ring(ring);
3330 
3331 	/* make sure rx ring budget not smaller than 1 */
3332 	if (tqp_vector->num_tqps > 1)
3333 		rx_budget = max(budget / tqp_vector->num_tqps, 1);
3334 
3335 	hns3_for_each_ring(ring, tqp_vector->rx_group) {
3336 		int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3337 						    hns3_rx_skb);
3338 
3339 		if (rx_cleaned >= rx_budget)
3340 			clean_complete = false;
3341 
3342 		rx_pkt_total += rx_cleaned;
3343 	}
3344 
3345 	tqp_vector->rx_group.total_packets += rx_pkt_total;
3346 
3347 	if (!clean_complete)
3348 		return budget;
3349 
3350 	if (napi_complete(napi) &&
3351 	    likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3352 		hns3_update_new_int_gl(tqp_vector);
3353 		hns3_mask_vector_irq(tqp_vector, 1);
3354 	}
3355 
3356 	return rx_pkt_total;
3357 }
3358 
3359 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3360 				      struct hnae3_ring_chain_node *head)
3361 {
3362 	struct pci_dev *pdev = tqp_vector->handle->pdev;
3363 	struct hnae3_ring_chain_node *cur_chain = head;
3364 	struct hnae3_ring_chain_node *chain;
3365 	struct hns3_enet_ring *tx_ring;
3366 	struct hns3_enet_ring *rx_ring;
3367 
3368 	tx_ring = tqp_vector->tx_group.ring;
3369 	if (tx_ring) {
3370 		cur_chain->tqp_index = tx_ring->tqp->tqp_index;
3371 		hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3372 			      HNAE3_RING_TYPE_TX);
3373 		hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3374 				HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
3375 
3376 		cur_chain->next = NULL;
3377 
3378 		while (tx_ring->next) {
3379 			tx_ring = tx_ring->next;
3380 
3381 			chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3382 					     GFP_KERNEL);
3383 			if (!chain)
3384 				goto err_free_chain;
3385 
3386 			cur_chain->next = chain;
3387 			chain->tqp_index = tx_ring->tqp->tqp_index;
3388 			hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3389 				      HNAE3_RING_TYPE_TX);
3390 			hnae3_set_field(chain->int_gl_idx,
3391 					HNAE3_RING_GL_IDX_M,
3392 					HNAE3_RING_GL_IDX_S,
3393 					HNAE3_RING_GL_TX);
3394 
3395 			cur_chain = chain;
3396 		}
3397 	}
3398 
3399 	rx_ring = tqp_vector->rx_group.ring;
3400 	if (!tx_ring && rx_ring) {
3401 		cur_chain->next = NULL;
3402 		cur_chain->tqp_index = rx_ring->tqp->tqp_index;
3403 		hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3404 			      HNAE3_RING_TYPE_RX);
3405 		hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3406 				HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3407 
3408 		rx_ring = rx_ring->next;
3409 	}
3410 
3411 	while (rx_ring) {
3412 		chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3413 		if (!chain)
3414 			goto err_free_chain;
3415 
3416 		cur_chain->next = chain;
3417 		chain->tqp_index = rx_ring->tqp->tqp_index;
3418 		hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3419 			      HNAE3_RING_TYPE_RX);
3420 		hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3421 				HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3422 
3423 		cur_chain = chain;
3424 
3425 		rx_ring = rx_ring->next;
3426 	}
3427 
3428 	return 0;
3429 
3430 err_free_chain:
3431 	cur_chain = head->next;
3432 	while (cur_chain) {
3433 		chain = cur_chain->next;
3434 		devm_kfree(&pdev->dev, cur_chain);
3435 		cur_chain = chain;
3436 	}
3437 	head->next = NULL;
3438 
3439 	return -ENOMEM;
3440 }
3441 
3442 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3443 					struct hnae3_ring_chain_node *head)
3444 {
3445 	struct pci_dev *pdev = tqp_vector->handle->pdev;
3446 	struct hnae3_ring_chain_node *chain_tmp, *chain;
3447 
3448 	chain = head->next;
3449 
3450 	while (chain) {
3451 		chain_tmp = chain->next;
3452 		devm_kfree(&pdev->dev, chain);
3453 		chain = chain_tmp;
3454 	}
3455 }
3456 
3457 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3458 				   struct hns3_enet_ring *ring)
3459 {
3460 	ring->next = group->ring;
3461 	group->ring = ring;
3462 
3463 	group->count++;
3464 }
3465 
3466 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3467 {
3468 	struct pci_dev *pdev = priv->ae_handle->pdev;
3469 	struct hns3_enet_tqp_vector *tqp_vector;
3470 	int num_vectors = priv->vector_num;
3471 	int numa_node;
3472 	int vector_i;
3473 
3474 	numa_node = dev_to_node(&pdev->dev);
3475 
3476 	for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3477 		tqp_vector = &priv->tqp_vector[vector_i];
3478 		cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3479 				&tqp_vector->affinity_mask);
3480 	}
3481 }
3482 
3483 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3484 {
3485 	struct hnae3_ring_chain_node vector_ring_chain;
3486 	struct hnae3_handle *h = priv->ae_handle;
3487 	struct hns3_enet_tqp_vector *tqp_vector;
3488 	int ret = 0;
3489 	int i;
3490 
3491 	hns3_nic_set_cpumask(priv);
3492 
3493 	for (i = 0; i < priv->vector_num; i++) {
3494 		tqp_vector = &priv->tqp_vector[i];
3495 		hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3496 		tqp_vector->num_tqps = 0;
3497 	}
3498 
3499 	for (i = 0; i < h->kinfo.num_tqps; i++) {
3500 		u16 vector_i = i % priv->vector_num;
3501 		u16 tqp_num = h->kinfo.num_tqps;
3502 
3503 		tqp_vector = &priv->tqp_vector[vector_i];
3504 
3505 		hns3_add_ring_to_group(&tqp_vector->tx_group,
3506 				       &priv->ring[i]);
3507 
3508 		hns3_add_ring_to_group(&tqp_vector->rx_group,
3509 				       &priv->ring[i + tqp_num]);
3510 
3511 		priv->ring[i].tqp_vector = tqp_vector;
3512 		priv->ring[i + tqp_num].tqp_vector = tqp_vector;
3513 		tqp_vector->num_tqps++;
3514 	}
3515 
3516 	for (i = 0; i < priv->vector_num; i++) {
3517 		tqp_vector = &priv->tqp_vector[i];
3518 
3519 		tqp_vector->rx_group.total_bytes = 0;
3520 		tqp_vector->rx_group.total_packets = 0;
3521 		tqp_vector->tx_group.total_bytes = 0;
3522 		tqp_vector->tx_group.total_packets = 0;
3523 		tqp_vector->handle = h;
3524 
3525 		ret = hns3_get_vector_ring_chain(tqp_vector,
3526 						 &vector_ring_chain);
3527 		if (ret)
3528 			goto map_ring_fail;
3529 
3530 		ret = h->ae_algo->ops->map_ring_to_vector(h,
3531 			tqp_vector->vector_irq, &vector_ring_chain);
3532 
3533 		hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3534 
3535 		if (ret)
3536 			goto map_ring_fail;
3537 
3538 		netif_napi_add(priv->netdev, &tqp_vector->napi,
3539 			       hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3540 	}
3541 
3542 	return 0;
3543 
3544 map_ring_fail:
3545 	while (i--)
3546 		netif_napi_del(&priv->tqp_vector[i].napi);
3547 
3548 	return ret;
3549 }
3550 
3551 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3552 {
3553 #define HNS3_VECTOR_PF_MAX_NUM		64
3554 
3555 	struct hnae3_handle *h = priv->ae_handle;
3556 	struct hns3_enet_tqp_vector *tqp_vector;
3557 	struct hnae3_vector_info *vector;
3558 	struct pci_dev *pdev = h->pdev;
3559 	u16 tqp_num = h->kinfo.num_tqps;
3560 	u16 vector_num;
3561 	int ret = 0;
3562 	u16 i;
3563 
3564 	/* RSS size, cpu online and vector_num should be the same */
3565 	/* Should consider 2p/4p later */
3566 	vector_num = min_t(u16, num_online_cpus(), tqp_num);
3567 	vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3568 
3569 	vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3570 			      GFP_KERNEL);
3571 	if (!vector)
3572 		return -ENOMEM;
3573 
3574 	/* save the actual available vector number */
3575 	vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3576 
3577 	priv->vector_num = vector_num;
3578 	priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3579 		devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3580 			     GFP_KERNEL);
3581 	if (!priv->tqp_vector) {
3582 		ret = -ENOMEM;
3583 		goto out;
3584 	}
3585 
3586 	for (i = 0; i < priv->vector_num; i++) {
3587 		tqp_vector = &priv->tqp_vector[i];
3588 		tqp_vector->idx = i;
3589 		tqp_vector->mask_addr = vector[i].io_addr;
3590 		tqp_vector->vector_irq = vector[i].vector;
3591 		hns3_vector_gl_rl_init(tqp_vector, priv);
3592 	}
3593 
3594 out:
3595 	devm_kfree(&pdev->dev, vector);
3596 	return ret;
3597 }
3598 
3599 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3600 {
3601 	group->ring = NULL;
3602 	group->count = 0;
3603 }
3604 
3605 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
3606 {
3607 	struct hnae3_ring_chain_node vector_ring_chain;
3608 	struct hnae3_handle *h = priv->ae_handle;
3609 	struct hns3_enet_tqp_vector *tqp_vector;
3610 	int i;
3611 
3612 	for (i = 0; i < priv->vector_num; i++) {
3613 		tqp_vector = &priv->tqp_vector[i];
3614 
3615 		if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3616 			continue;
3617 
3618 		/* Since the mapping can be overwritten, when fail to get the
3619 		 * chain between vector and ring, we should go on to deal with
3620 		 * the remaining options.
3621 		 */
3622 		if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain))
3623 			dev_warn(priv->dev, "failed to get ring chain\n");
3624 
3625 		h->ae_algo->ops->unmap_ring_from_vector(h,
3626 			tqp_vector->vector_irq, &vector_ring_chain);
3627 
3628 		hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3629 
3630 		hns3_clear_ring_group(&tqp_vector->rx_group);
3631 		hns3_clear_ring_group(&tqp_vector->tx_group);
3632 		netif_napi_del(&priv->tqp_vector[i].napi);
3633 	}
3634 }
3635 
3636 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3637 {
3638 	struct hnae3_handle *h = priv->ae_handle;
3639 	struct pci_dev *pdev = h->pdev;
3640 	int i, ret;
3641 
3642 	for (i = 0; i < priv->vector_num; i++) {
3643 		struct hns3_enet_tqp_vector *tqp_vector;
3644 
3645 		tqp_vector = &priv->tqp_vector[i];
3646 		ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3647 		if (ret)
3648 			return;
3649 	}
3650 
3651 	devm_kfree(&pdev->dev, priv->tqp_vector);
3652 }
3653 
3654 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3655 			      unsigned int ring_type)
3656 {
3657 	int queue_num = priv->ae_handle->kinfo.num_tqps;
3658 	struct hns3_enet_ring *ring;
3659 	int desc_num;
3660 
3661 	if (ring_type == HNAE3_RING_TYPE_TX) {
3662 		ring = &priv->ring[q->tqp_index];
3663 		desc_num = priv->ae_handle->kinfo.num_tx_desc;
3664 		ring->queue_index = q->tqp_index;
3665 		ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3666 	} else {
3667 		ring = &priv->ring[q->tqp_index + queue_num];
3668 		desc_num = priv->ae_handle->kinfo.num_rx_desc;
3669 		ring->queue_index = q->tqp_index;
3670 		ring->io_base = q->io_base;
3671 	}
3672 
3673 	hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
3674 
3675 	ring->tqp = q;
3676 	ring->desc = NULL;
3677 	ring->desc_cb = NULL;
3678 	ring->dev = priv->dev;
3679 	ring->desc_dma_addr = 0;
3680 	ring->buf_size = q->buf_size;
3681 	ring->desc_num = desc_num;
3682 	ring->next_to_use = 0;
3683 	ring->next_to_clean = 0;
3684 }
3685 
3686 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
3687 			       struct hns3_nic_priv *priv)
3688 {
3689 	hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3690 	hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
3691 }
3692 
3693 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3694 {
3695 	struct hnae3_handle *h = priv->ae_handle;
3696 	struct pci_dev *pdev = h->pdev;
3697 	int i;
3698 
3699 	priv->ring = devm_kzalloc(&pdev->dev,
3700 				  array3_size(h->kinfo.num_tqps,
3701 					      sizeof(*priv->ring), 2),
3702 				  GFP_KERNEL);
3703 	if (!priv->ring)
3704 		return -ENOMEM;
3705 
3706 	for (i = 0; i < h->kinfo.num_tqps; i++)
3707 		hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3708 
3709 	return 0;
3710 }
3711 
3712 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3713 {
3714 	if (!priv->ring)
3715 		return;
3716 
3717 	devm_kfree(priv->dev, priv->ring);
3718 	priv->ring = NULL;
3719 }
3720 
3721 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3722 {
3723 	int ret;
3724 
3725 	if (ring->desc_num <= 0 || ring->buf_size <= 0)
3726 		return -EINVAL;
3727 
3728 	ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3729 				     sizeof(ring->desc_cb[0]), GFP_KERNEL);
3730 	if (!ring->desc_cb) {
3731 		ret = -ENOMEM;
3732 		goto out;
3733 	}
3734 
3735 	ret = hns3_alloc_desc(ring);
3736 	if (ret)
3737 		goto out_with_desc_cb;
3738 
3739 	if (!HNAE3_IS_TX_RING(ring)) {
3740 		ret = hns3_alloc_ring_buffers(ring);
3741 		if (ret)
3742 			goto out_with_desc;
3743 	}
3744 
3745 	return 0;
3746 
3747 out_with_desc:
3748 	hns3_free_desc(ring);
3749 out_with_desc_cb:
3750 	devm_kfree(ring_to_dev(ring), ring->desc_cb);
3751 	ring->desc_cb = NULL;
3752 out:
3753 	return ret;
3754 }
3755 
3756 void hns3_fini_ring(struct hns3_enet_ring *ring)
3757 {
3758 	hns3_free_desc(ring);
3759 	devm_kfree(ring_to_dev(ring), ring->desc_cb);
3760 	ring->desc_cb = NULL;
3761 	ring->next_to_clean = 0;
3762 	ring->next_to_use = 0;
3763 	ring->pending_buf = 0;
3764 	if (ring->skb) {
3765 		dev_kfree_skb_any(ring->skb);
3766 		ring->skb = NULL;
3767 	}
3768 }
3769 
3770 static int hns3_buf_size2type(u32 buf_size)
3771 {
3772 	int bd_size_type;
3773 
3774 	switch (buf_size) {
3775 	case 512:
3776 		bd_size_type = HNS3_BD_SIZE_512_TYPE;
3777 		break;
3778 	case 1024:
3779 		bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3780 		break;
3781 	case 2048:
3782 		bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3783 		break;
3784 	case 4096:
3785 		bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3786 		break;
3787 	default:
3788 		bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3789 	}
3790 
3791 	return bd_size_type;
3792 }
3793 
3794 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3795 {
3796 	dma_addr_t dma = ring->desc_dma_addr;
3797 	struct hnae3_queue *q = ring->tqp;
3798 
3799 	if (!HNAE3_IS_TX_RING(ring)) {
3800 		hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
3801 		hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3802 			       (u32)((dma >> 31) >> 1));
3803 
3804 		hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3805 			       hns3_buf_size2type(ring->buf_size));
3806 		hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3807 			       ring->desc_num / 8 - 1);
3808 
3809 	} else {
3810 		hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3811 			       (u32)dma);
3812 		hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3813 			       (u32)((dma >> 31) >> 1));
3814 
3815 		hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3816 			       ring->desc_num / 8 - 1);
3817 	}
3818 }
3819 
3820 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3821 {
3822 	struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3823 	int i;
3824 
3825 	for (i = 0; i < HNAE3_MAX_TC; i++) {
3826 		struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3827 		int j;
3828 
3829 		if (!tc_info->enable)
3830 			continue;
3831 
3832 		for (j = 0; j < tc_info->tqp_count; j++) {
3833 			struct hnae3_queue *q;
3834 
3835 			q = priv->ring[tc_info->tqp_offset + j].tqp;
3836 			hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3837 				       tc_info->tc);
3838 		}
3839 	}
3840 }
3841 
3842 int hns3_init_all_ring(struct hns3_nic_priv *priv)
3843 {
3844 	struct hnae3_handle *h = priv->ae_handle;
3845 	int ring_num = h->kinfo.num_tqps * 2;
3846 	int i, j;
3847 	int ret;
3848 
3849 	for (i = 0; i < ring_num; i++) {
3850 		ret = hns3_alloc_ring_memory(&priv->ring[i]);
3851 		if (ret) {
3852 			dev_err(priv->dev,
3853 				"Alloc ring memory fail! ret=%d\n", ret);
3854 			goto out_when_alloc_ring_memory;
3855 		}
3856 
3857 		u64_stats_init(&priv->ring[i].syncp);
3858 	}
3859 
3860 	return 0;
3861 
3862 out_when_alloc_ring_memory:
3863 	for (j = i - 1; j >= 0; j--)
3864 		hns3_fini_ring(&priv->ring[j]);
3865 
3866 	return -ENOMEM;
3867 }
3868 
3869 int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
3870 {
3871 	struct hnae3_handle *h = priv->ae_handle;
3872 	int i;
3873 
3874 	for (i = 0; i < h->kinfo.num_tqps; i++) {
3875 		hns3_fini_ring(&priv->ring[i]);
3876 		hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
3877 	}
3878 	return 0;
3879 }
3880 
3881 /* Set mac addr if it is configured. or leave it to the AE driver */
3882 static int hns3_init_mac_addr(struct net_device *netdev)
3883 {
3884 	struct hns3_nic_priv *priv = netdev_priv(netdev);
3885 	struct hnae3_handle *h = priv->ae_handle;
3886 	u8 mac_addr_temp[ETH_ALEN];
3887 	int ret = 0;
3888 
3889 	if (h->ae_algo->ops->get_mac_addr)
3890 		h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3891 
3892 	/* Check if the MAC address is valid, if not get a random one */
3893 	if (!is_valid_ether_addr(mac_addr_temp)) {
3894 		eth_hw_addr_random(netdev);
3895 		dev_warn(priv->dev, "using random MAC address %pM\n",
3896 			 netdev->dev_addr);
3897 	} else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
3898 		ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3899 		ether_addr_copy(netdev->perm_addr, mac_addr_temp);
3900 	} else {
3901 		return 0;
3902 	}
3903 
3904 	if (h->ae_algo->ops->set_mac_addr)
3905 		ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
3906 
3907 	return ret;
3908 }
3909 
3910 static int hns3_init_phy(struct net_device *netdev)
3911 {
3912 	struct hnae3_handle *h = hns3_get_handle(netdev);
3913 	int ret = 0;
3914 
3915 	if (h->ae_algo->ops->mac_connect_phy)
3916 		ret = h->ae_algo->ops->mac_connect_phy(h);
3917 
3918 	return ret;
3919 }
3920 
3921 static void hns3_uninit_phy(struct net_device *netdev)
3922 {
3923 	struct hnae3_handle *h = hns3_get_handle(netdev);
3924 
3925 	if (h->ae_algo->ops->mac_disconnect_phy)
3926 		h->ae_algo->ops->mac_disconnect_phy(h);
3927 }
3928 
3929 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3930 {
3931 	struct hnae3_handle *h = hns3_get_handle(netdev);
3932 
3933 	if (h->ae_algo->ops->del_all_fd_entries)
3934 		h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3935 }
3936 
3937 static int hns3_client_start(struct hnae3_handle *handle)
3938 {
3939 	if (!handle->ae_algo->ops->client_start)
3940 		return 0;
3941 
3942 	return handle->ae_algo->ops->client_start(handle);
3943 }
3944 
3945 static void hns3_client_stop(struct hnae3_handle *handle)
3946 {
3947 	if (!handle->ae_algo->ops->client_stop)
3948 		return;
3949 
3950 	handle->ae_algo->ops->client_stop(handle);
3951 }
3952 
3953 static void hns3_info_show(struct hns3_nic_priv *priv)
3954 {
3955 	struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3956 
3957 	dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
3958 	dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
3959 	dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
3960 	dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
3961 	dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
3962 	dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
3963 	dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
3964 	dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc);
3965 	dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
3966 }
3967 
3968 static int hns3_client_init(struct hnae3_handle *handle)
3969 {
3970 	struct pci_dev *pdev = handle->pdev;
3971 	u16 alloc_tqps, max_rss_size;
3972 	struct hns3_nic_priv *priv;
3973 	struct net_device *netdev;
3974 	int ret;
3975 
3976 	handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3977 						    &max_rss_size);
3978 	netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
3979 	if (!netdev)
3980 		return -ENOMEM;
3981 
3982 	priv = netdev_priv(netdev);
3983 	priv->dev = &pdev->dev;
3984 	priv->netdev = netdev;
3985 	priv->ae_handle = handle;
3986 	priv->tx_timeout_count = 0;
3987 	set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
3988 
3989 	handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
3990 
3991 	handle->kinfo.netdev = netdev;
3992 	handle->priv = (void *)priv;
3993 
3994 	hns3_init_mac_addr(netdev);
3995 
3996 	hns3_set_default_feature(netdev);
3997 
3998 	netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3999 	netdev->priv_flags |= IFF_UNICAST_FLT;
4000 	netdev->netdev_ops = &hns3_nic_netdev_ops;
4001 	SET_NETDEV_DEV(netdev, &pdev->dev);
4002 	hns3_ethtool_set_ops(netdev);
4003 
4004 	/* Carrier off reporting is important to ethtool even BEFORE open */
4005 	netif_carrier_off(netdev);
4006 
4007 	ret = hns3_get_ring_config(priv);
4008 	if (ret) {
4009 		ret = -ENOMEM;
4010 		goto out_get_ring_cfg;
4011 	}
4012 
4013 	ret = hns3_nic_alloc_vector_data(priv);
4014 	if (ret) {
4015 		ret = -ENOMEM;
4016 		goto out_alloc_vector_data;
4017 	}
4018 
4019 	ret = hns3_nic_init_vector_data(priv);
4020 	if (ret) {
4021 		ret = -ENOMEM;
4022 		goto out_init_vector_data;
4023 	}
4024 
4025 	ret = hns3_init_all_ring(priv);
4026 	if (ret) {
4027 		ret = -ENOMEM;
4028 		goto out_init_ring;
4029 	}
4030 
4031 	ret = hns3_init_phy(netdev);
4032 	if (ret)
4033 		goto out_init_phy;
4034 
4035 	ret = register_netdev(netdev);
4036 	if (ret) {
4037 		dev_err(priv->dev, "probe register netdev fail!\n");
4038 		goto out_reg_netdev_fail;
4039 	}
4040 
4041 	/* the device can work without cpu rmap, only aRFS needs it */
4042 	ret = hns3_set_rx_cpu_rmap(netdev);
4043 	if (ret)
4044 		dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4045 
4046 	ret = hns3_nic_init_irq(priv);
4047 	if (ret) {
4048 		dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4049 		hns3_free_rx_cpu_rmap(netdev);
4050 		goto out_init_irq_fail;
4051 	}
4052 
4053 	ret = hns3_client_start(handle);
4054 	if (ret) {
4055 		dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4056 		goto out_client_start;
4057 	}
4058 
4059 	hns3_dcbnl_setup(handle);
4060 
4061 	hns3_dbg_init(handle);
4062 
4063 	/* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
4064 	netdev->max_mtu = HNS3_MAX_MTU;
4065 
4066 	set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4067 
4068 	if (netif_msg_drv(handle))
4069 		hns3_info_show(priv);
4070 
4071 	return ret;
4072 
4073 out_client_start:
4074 	hns3_free_rx_cpu_rmap(netdev);
4075 	hns3_nic_uninit_irq(priv);
4076 out_init_irq_fail:
4077 	unregister_netdev(netdev);
4078 out_reg_netdev_fail:
4079 	hns3_uninit_phy(netdev);
4080 out_init_phy:
4081 	hns3_uninit_all_ring(priv);
4082 out_init_ring:
4083 	hns3_nic_uninit_vector_data(priv);
4084 out_init_vector_data:
4085 	hns3_nic_dealloc_vector_data(priv);
4086 out_alloc_vector_data:
4087 	priv->ring = NULL;
4088 out_get_ring_cfg:
4089 	priv->ae_handle = NULL;
4090 	free_netdev(netdev);
4091 	return ret;
4092 }
4093 
4094 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
4095 {
4096 	struct net_device *netdev = handle->kinfo.netdev;
4097 	struct hns3_nic_priv *priv = netdev_priv(netdev);
4098 	int ret;
4099 
4100 	if (netdev->reg_state != NETREG_UNINITIALIZED)
4101 		unregister_netdev(netdev);
4102 
4103 	hns3_client_stop(handle);
4104 
4105 	hns3_uninit_phy(netdev);
4106 
4107 	if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4108 		netdev_warn(netdev, "already uninitialized\n");
4109 		goto out_netdev_free;
4110 	}
4111 
4112 	hns3_free_rx_cpu_rmap(netdev);
4113 
4114 	hns3_nic_uninit_irq(priv);
4115 
4116 	hns3_del_all_fd_rules(netdev, true);
4117 
4118 	hns3_clear_all_ring(handle, true);
4119 
4120 	hns3_nic_uninit_vector_data(priv);
4121 
4122 	hns3_nic_dealloc_vector_data(priv);
4123 
4124 	ret = hns3_uninit_all_ring(priv);
4125 	if (ret)
4126 		netdev_err(netdev, "uninit ring error\n");
4127 
4128 	hns3_put_ring_config(priv);
4129 
4130 	hns3_dbg_uninit(handle);
4131 
4132 out_netdev_free:
4133 	free_netdev(netdev);
4134 }
4135 
4136 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
4137 {
4138 	struct net_device *netdev = handle->kinfo.netdev;
4139 
4140 	if (!netdev)
4141 		return;
4142 
4143 	if (linkup) {
4144 		netif_carrier_on(netdev);
4145 		netif_tx_wake_all_queues(netdev);
4146 		if (netif_msg_link(handle))
4147 			netdev_info(netdev, "link up\n");
4148 	} else {
4149 		netif_carrier_off(netdev);
4150 		netif_tx_stop_all_queues(netdev);
4151 		if (netif_msg_link(handle))
4152 			netdev_info(netdev, "link down\n");
4153 	}
4154 }
4155 
4156 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
4157 {
4158 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4159 	struct net_device *ndev = kinfo->netdev;
4160 
4161 	if (tc > HNAE3_MAX_TC)
4162 		return -EINVAL;
4163 
4164 	if (!ndev)
4165 		return -ENODEV;
4166 
4167 	return hns3_nic_set_real_num_queue(ndev);
4168 }
4169 
4170 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
4171 {
4172 	while (ring->next_to_clean != ring->next_to_use) {
4173 		ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
4174 		hns3_free_buffer_detach(ring, ring->next_to_clean);
4175 		ring_ptr_move_fw(ring, next_to_clean);
4176 	}
4177 }
4178 
4179 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4180 {
4181 	struct hns3_desc_cb res_cbs;
4182 	int ret;
4183 
4184 	while (ring->next_to_use != ring->next_to_clean) {
4185 		/* When a buffer is not reused, it's memory has been
4186 		 * freed in hns3_handle_rx_bd or will be freed by
4187 		 * stack, so we need to replace the buffer here.
4188 		 */
4189 		if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4190 			ret = hns3_reserve_buffer_map(ring, &res_cbs);
4191 			if (ret) {
4192 				u64_stats_update_begin(&ring->syncp);
4193 				ring->stats.sw_err_cnt++;
4194 				u64_stats_update_end(&ring->syncp);
4195 				/* if alloc new buffer fail, exit directly
4196 				 * and reclear in up flow.
4197 				 */
4198 				netdev_warn(ring_to_netdev(ring),
4199 					    "reserve buffer map failed, ret = %d\n",
4200 					    ret);
4201 				return ret;
4202 			}
4203 			hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
4204 		}
4205 		ring_ptr_move_fw(ring, next_to_use);
4206 	}
4207 
4208 	/* Free the pending skb in rx ring */
4209 	if (ring->skb) {
4210 		dev_kfree_skb_any(ring->skb);
4211 		ring->skb = NULL;
4212 		ring->pending_buf = 0;
4213 	}
4214 
4215 	return 0;
4216 }
4217 
4218 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
4219 {
4220 	while (ring->next_to_use != ring->next_to_clean) {
4221 		/* When a buffer is not reused, it's memory has been
4222 		 * freed in hns3_handle_rx_bd or will be freed by
4223 		 * stack, so only need to unmap the buffer here.
4224 		 */
4225 		if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4226 			hns3_unmap_buffer(ring,
4227 					  &ring->desc_cb[ring->next_to_use]);
4228 			ring->desc_cb[ring->next_to_use].dma = 0;
4229 		}
4230 
4231 		ring_ptr_move_fw(ring, next_to_use);
4232 	}
4233 }
4234 
4235 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
4236 {
4237 	struct net_device *ndev = h->kinfo.netdev;
4238 	struct hns3_nic_priv *priv = netdev_priv(ndev);
4239 	u32 i;
4240 
4241 	for (i = 0; i < h->kinfo.num_tqps; i++) {
4242 		struct hns3_enet_ring *ring;
4243 
4244 		ring = &priv->ring[i];
4245 		hns3_clear_tx_ring(ring);
4246 
4247 		ring = &priv->ring[i + h->kinfo.num_tqps];
4248 		/* Continue to clear other rings even if clearing some
4249 		 * rings failed.
4250 		 */
4251 		if (force)
4252 			hns3_force_clear_rx_ring(ring);
4253 		else
4254 			hns3_clear_rx_ring(ring);
4255 	}
4256 }
4257 
4258 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4259 {
4260 	struct net_device *ndev = h->kinfo.netdev;
4261 	struct hns3_nic_priv *priv = netdev_priv(ndev);
4262 	struct hns3_enet_ring *rx_ring;
4263 	int i, j;
4264 	int ret;
4265 
4266 	for (i = 0; i < h->kinfo.num_tqps; i++) {
4267 		ret = h->ae_algo->ops->reset_queue(h, i);
4268 		if (ret)
4269 			return ret;
4270 
4271 		hns3_init_ring_hw(&priv->ring[i]);
4272 
4273 		/* We need to clear tx ring here because self test will
4274 		 * use the ring and will not run down before up
4275 		 */
4276 		hns3_clear_tx_ring(&priv->ring[i]);
4277 		priv->ring[i].next_to_clean = 0;
4278 		priv->ring[i].next_to_use = 0;
4279 
4280 		rx_ring = &priv->ring[i + h->kinfo.num_tqps];
4281 		hns3_init_ring_hw(rx_ring);
4282 		ret = hns3_clear_rx_ring(rx_ring);
4283 		if (ret)
4284 			return ret;
4285 
4286 		/* We can not know the hardware head and tail when this
4287 		 * function is called in reset flow, so we reuse all desc.
4288 		 */
4289 		for (j = 0; j < rx_ring->desc_num; j++)
4290 			hns3_reuse_buffer(rx_ring, j);
4291 
4292 		rx_ring->next_to_clean = 0;
4293 		rx_ring->next_to_use = 0;
4294 	}
4295 
4296 	hns3_init_tx_ring_tc(priv);
4297 
4298 	return 0;
4299 }
4300 
4301 static void hns3_store_coal(struct hns3_nic_priv *priv)
4302 {
4303 	/* ethtool only support setting and querying one coal
4304 	 * configuration for now, so save the vector 0' coal
4305 	 * configuration here in order to restore it.
4306 	 */
4307 	memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4308 	       sizeof(struct hns3_enet_coalesce));
4309 	memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4310 	       sizeof(struct hns3_enet_coalesce));
4311 }
4312 
4313 static void hns3_restore_coal(struct hns3_nic_priv *priv)
4314 {
4315 	u16 vector_num = priv->vector_num;
4316 	int i;
4317 
4318 	for (i = 0; i < vector_num; i++) {
4319 		memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4320 		       sizeof(struct hns3_enet_coalesce));
4321 		memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4322 		       sizeof(struct hns3_enet_coalesce));
4323 	}
4324 }
4325 
4326 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4327 {
4328 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4329 	struct net_device *ndev = kinfo->netdev;
4330 	struct hns3_nic_priv *priv = netdev_priv(ndev);
4331 
4332 	if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4333 		return 0;
4334 
4335 	if (!netif_running(ndev))
4336 		return 0;
4337 
4338 	return hns3_nic_net_stop(ndev);
4339 }
4340 
4341 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4342 {
4343 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4344 	struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
4345 	int ret = 0;
4346 
4347 	clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4348 
4349 	if (netif_running(kinfo->netdev)) {
4350 		ret = hns3_nic_net_open(kinfo->netdev);
4351 		if (ret) {
4352 			set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4353 			netdev_err(kinfo->netdev,
4354 				   "net up fail, ret=%d!\n", ret);
4355 			return ret;
4356 		}
4357 	}
4358 
4359 	return ret;
4360 }
4361 
4362 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4363 {
4364 	struct net_device *netdev = handle->kinfo.netdev;
4365 	struct hns3_nic_priv *priv = netdev_priv(netdev);
4366 	int ret;
4367 
4368 	/* Carrier off reporting is important to ethtool even BEFORE open */
4369 	netif_carrier_off(netdev);
4370 
4371 	ret = hns3_get_ring_config(priv);
4372 	if (ret)
4373 		return ret;
4374 
4375 	ret = hns3_nic_alloc_vector_data(priv);
4376 	if (ret)
4377 		goto err_put_ring;
4378 
4379 	hns3_restore_coal(priv);
4380 
4381 	ret = hns3_nic_init_vector_data(priv);
4382 	if (ret)
4383 		goto err_dealloc_vector;
4384 
4385 	ret = hns3_init_all_ring(priv);
4386 	if (ret)
4387 		goto err_uninit_vector;
4388 
4389 	/* the device can work without cpu rmap, only aRFS needs it */
4390 	ret = hns3_set_rx_cpu_rmap(netdev);
4391 	if (ret)
4392 		dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4393 
4394 	ret = hns3_nic_init_irq(priv);
4395 	if (ret) {
4396 		dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4397 		hns3_free_rx_cpu_rmap(netdev);
4398 		goto err_init_irq_fail;
4399 	}
4400 
4401 	if (!hns3_is_phys_func(handle->pdev))
4402 		hns3_init_mac_addr(netdev);
4403 
4404 	ret = hns3_client_start(handle);
4405 	if (ret) {
4406 		dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4407 		goto err_client_start_fail;
4408 	}
4409 
4410 	set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4411 
4412 	return ret;
4413 
4414 err_client_start_fail:
4415 	hns3_free_rx_cpu_rmap(netdev);
4416 	hns3_nic_uninit_irq(priv);
4417 err_init_irq_fail:
4418 	hns3_uninit_all_ring(priv);
4419 err_uninit_vector:
4420 	hns3_nic_uninit_vector_data(priv);
4421 err_dealloc_vector:
4422 	hns3_nic_dealloc_vector_data(priv);
4423 err_put_ring:
4424 	hns3_put_ring_config(priv);
4425 
4426 	return ret;
4427 }
4428 
4429 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4430 {
4431 	struct net_device *netdev = handle->kinfo.netdev;
4432 	struct hns3_nic_priv *priv = netdev_priv(netdev);
4433 	int ret;
4434 
4435 	if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4436 		netdev_warn(netdev, "already uninitialized\n");
4437 		return 0;
4438 	}
4439 
4440 	hns3_free_rx_cpu_rmap(netdev);
4441 	hns3_nic_uninit_irq(priv);
4442 	hns3_clear_all_ring(handle, true);
4443 	hns3_reset_tx_queue(priv->ae_handle);
4444 
4445 	hns3_nic_uninit_vector_data(priv);
4446 
4447 	hns3_store_coal(priv);
4448 
4449 	hns3_nic_dealloc_vector_data(priv);
4450 
4451 	ret = hns3_uninit_all_ring(priv);
4452 	if (ret)
4453 		netdev_err(netdev, "uninit ring error\n");
4454 
4455 	hns3_put_ring_config(priv);
4456 
4457 	return ret;
4458 }
4459 
4460 static int hns3_reset_notify(struct hnae3_handle *handle,
4461 			     enum hnae3_reset_notify_type type)
4462 {
4463 	int ret = 0;
4464 
4465 	switch (type) {
4466 	case HNAE3_UP_CLIENT:
4467 		ret = hns3_reset_notify_up_enet(handle);
4468 		break;
4469 	case HNAE3_DOWN_CLIENT:
4470 		ret = hns3_reset_notify_down_enet(handle);
4471 		break;
4472 	case HNAE3_INIT_CLIENT:
4473 		ret = hns3_reset_notify_init_enet(handle);
4474 		break;
4475 	case HNAE3_UNINIT_CLIENT:
4476 		ret = hns3_reset_notify_uninit_enet(handle);
4477 		break;
4478 	default:
4479 		break;
4480 	}
4481 
4482 	return ret;
4483 }
4484 
4485 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
4486 				bool rxfh_configured)
4487 {
4488 	int ret;
4489 
4490 	ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
4491 						 rxfh_configured);
4492 	if (ret) {
4493 		dev_err(&handle->pdev->dev,
4494 			"Change tqp num(%u) fail.\n", new_tqp_num);
4495 		return ret;
4496 	}
4497 
4498 	ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
4499 	if (ret)
4500 		return ret;
4501 
4502 	ret =  hns3_reset_notify(handle, HNAE3_UP_CLIENT);
4503 	if (ret)
4504 		hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
4505 
4506 	return ret;
4507 }
4508 
4509 int hns3_set_channels(struct net_device *netdev,
4510 		      struct ethtool_channels *ch)
4511 {
4512 	struct hnae3_handle *h = hns3_get_handle(netdev);
4513 	struct hnae3_knic_private_info *kinfo = &h->kinfo;
4514 	bool rxfh_configured = netif_is_rxfh_configured(netdev);
4515 	u32 new_tqp_num = ch->combined_count;
4516 	u16 org_tqp_num;
4517 	int ret;
4518 
4519 	if (hns3_nic_resetting(netdev))
4520 		return -EBUSY;
4521 
4522 	if (ch->rx_count || ch->tx_count)
4523 		return -EINVAL;
4524 
4525 	if (new_tqp_num > hns3_get_max_available_channels(h) ||
4526 	    new_tqp_num < 1) {
4527 		dev_err(&netdev->dev,
4528 			"Change tqps fail, the tqp range is from 1 to %u",
4529 			hns3_get_max_available_channels(h));
4530 		return -EINVAL;
4531 	}
4532 
4533 	if (kinfo->rss_size == new_tqp_num)
4534 		return 0;
4535 
4536 	netif_dbg(h, drv, netdev,
4537 		  "set channels: tqp_num=%u, rxfh=%d\n",
4538 		  new_tqp_num, rxfh_configured);
4539 
4540 	ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4541 	if (ret)
4542 		return ret;
4543 
4544 	ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4545 	if (ret)
4546 		return ret;
4547 
4548 	org_tqp_num = h->kinfo.num_tqps;
4549 	ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
4550 	if (ret) {
4551 		int ret1;
4552 
4553 		netdev_warn(netdev,
4554 			    "Change channels fail, revert to old value\n");
4555 		ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
4556 		if (ret1) {
4557 			netdev_err(netdev,
4558 				   "revert to old channel fail\n");
4559 			return ret1;
4560 		}
4561 
4562 		return ret;
4563 	}
4564 
4565 	return 0;
4566 }
4567 
4568 static const struct hns3_hw_error_info hns3_hw_err[] = {
4569 	{ .type = HNAE3_PPU_POISON_ERROR,
4570 	  .msg = "PPU poison" },
4571 	{ .type = HNAE3_CMDQ_ECC_ERROR,
4572 	  .msg = "IMP CMDQ error" },
4573 	{ .type = HNAE3_IMP_RD_POISON_ERROR,
4574 	  .msg = "IMP RD poison" },
4575 };
4576 
4577 static void hns3_process_hw_error(struct hnae3_handle *handle,
4578 				  enum hnae3_hw_error_type type)
4579 {
4580 	int i;
4581 
4582 	for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
4583 		if (hns3_hw_err[i].type == type) {
4584 			dev_err(&handle->pdev->dev, "Detected %s!\n",
4585 				hns3_hw_err[i].msg);
4586 			break;
4587 		}
4588 	}
4589 }
4590 
4591 static const struct hnae3_client_ops client_ops = {
4592 	.init_instance = hns3_client_init,
4593 	.uninit_instance = hns3_client_uninit,
4594 	.link_status_change = hns3_link_status_change,
4595 	.setup_tc = hns3_client_setup_tc,
4596 	.reset_notify = hns3_reset_notify,
4597 	.process_hw_error = hns3_process_hw_error,
4598 };
4599 
4600 /* hns3_init_module - Driver registration routine
4601  * hns3_init_module is the first routine called when the driver is
4602  * loaded. All it does is register with the PCI subsystem.
4603  */
4604 static int __init hns3_init_module(void)
4605 {
4606 	int ret;
4607 
4608 	pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4609 	pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4610 
4611 	client.type = HNAE3_CLIENT_KNIC;
4612 	snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
4613 		 hns3_driver_name);
4614 
4615 	client.ops = &client_ops;
4616 
4617 	INIT_LIST_HEAD(&client.node);
4618 
4619 	hns3_dbg_register_debugfs(hns3_driver_name);
4620 
4621 	ret = hnae3_register_client(&client);
4622 	if (ret)
4623 		goto err_reg_client;
4624 
4625 	ret = pci_register_driver(&hns3_driver);
4626 	if (ret)
4627 		goto err_reg_driver;
4628 
4629 	return ret;
4630 
4631 err_reg_driver:
4632 	hnae3_unregister_client(&client);
4633 err_reg_client:
4634 	hns3_dbg_unregister_debugfs();
4635 	return ret;
4636 }
4637 module_init(hns3_init_module);
4638 
4639 /* hns3_exit_module - Driver exit cleanup routine
4640  * hns3_exit_module is called just before the driver is removed
4641  * from memory.
4642  */
4643 static void __exit hns3_exit_module(void)
4644 {
4645 	pci_unregister_driver(&hns3_driver);
4646 	hnae3_unregister_client(&client);
4647 	hns3_dbg_unregister_debugfs();
4648 }
4649 module_exit(hns3_exit_module);
4650 
4651 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4652 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4653 MODULE_LICENSE("GPL");
4654 MODULE_ALIAS("pci:hns-nic");
4655