1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * amlgoic-core.c - hardware cryptographic offloader for Amlogic GXL SoC
4  *
5  * Copyright (C) 2018-2019 Corentin Labbe <clabbe@baylibre.com>
6  *
7  * Core file which registers crypto algorithms supported by the hardware.
8  */
9 #include <linux/clk.h>
10 #include <linux/crypto.h>
11 #include <linux/io.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <crypto/internal/skcipher.h>
19 #include <linux/dma-mapping.h>
20 
21 #include "amlogic-gxl.h"
22 
23 static irqreturn_t meson_irq_handler(int irq, void *data)
24 {
25 	struct meson_dev *mc = (struct meson_dev *)data;
26 	int flow;
27 	u32 p;
28 
29 	for (flow = 0; flow < MAXFLOW; flow++) {
30 		if (mc->irqs[flow] == irq) {
31 			p = readl(mc->base + ((0x04 + flow) << 2));
32 			if (p) {
33 				writel_relaxed(0xF, mc->base + ((0x4 + flow) << 2));
34 				mc->chanlist[flow].status = 1;
35 				complete(&mc->chanlist[flow].complete);
36 				return IRQ_HANDLED;
37 			}
38 			dev_err(mc->dev, "%s %d Got irq for flow %d but ctrl is empty\n", __func__, irq, flow);
39 		}
40 	}
41 
42 	dev_err(mc->dev, "%s %d from unknown irq\n", __func__, irq);
43 	return IRQ_HANDLED;
44 }
45 
46 static struct meson_alg_template mc_algs[] = {
47 {
48 	.type = CRYPTO_ALG_TYPE_SKCIPHER,
49 	.blockmode = MESON_OPMODE_CBC,
50 	.alg.skcipher = {
51 		.base = {
52 			.cra_name = "cbc(aes)",
53 			.cra_driver_name = "cbc-aes-gxl",
54 			.cra_priority = 400,
55 			.cra_blocksize = AES_BLOCK_SIZE,
56 			.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
57 				CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
58 				CRYPTO_ALG_NEED_FALLBACK,
59 			.cra_ctxsize = sizeof(struct meson_cipher_tfm_ctx),
60 			.cra_module = THIS_MODULE,
61 			.cra_alignmask = 0xf,
62 			.cra_init = meson_cipher_init,
63 			.cra_exit = meson_cipher_exit,
64 		},
65 		.min_keysize	= AES_MIN_KEY_SIZE,
66 		.max_keysize	= AES_MAX_KEY_SIZE,
67 		.ivsize		= AES_BLOCK_SIZE,
68 		.setkey		= meson_aes_setkey,
69 		.encrypt	= meson_skencrypt,
70 		.decrypt	= meson_skdecrypt,
71 	}
72 },
73 {
74 	.type = CRYPTO_ALG_TYPE_SKCIPHER,
75 	.blockmode = MESON_OPMODE_ECB,
76 	.alg.skcipher = {
77 		.base = {
78 			.cra_name = "ecb(aes)",
79 			.cra_driver_name = "ecb-aes-gxl",
80 			.cra_priority = 400,
81 			.cra_blocksize = AES_BLOCK_SIZE,
82 			.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
83 				CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
84 				CRYPTO_ALG_NEED_FALLBACK,
85 			.cra_ctxsize = sizeof(struct meson_cipher_tfm_ctx),
86 			.cra_module = THIS_MODULE,
87 			.cra_alignmask = 0xf,
88 			.cra_init = meson_cipher_init,
89 			.cra_exit = meson_cipher_exit,
90 		},
91 		.min_keysize	= AES_MIN_KEY_SIZE,
92 		.max_keysize	= AES_MAX_KEY_SIZE,
93 		.setkey		= meson_aes_setkey,
94 		.encrypt	= meson_skencrypt,
95 		.decrypt	= meson_skdecrypt,
96 	}
97 },
98 };
99 
100 #ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
101 static int meson_dbgfs_read(struct seq_file *seq, void *v)
102 {
103 	struct meson_dev *mc = seq->private;
104 	int i;
105 
106 	for (i = 0; i < MAXFLOW; i++)
107 		seq_printf(seq, "Channel %d: nreq %lu\n", i, mc->chanlist[i].stat_req);
108 
109 	for (i = 0; i < ARRAY_SIZE(mc_algs); i++) {
110 		switch (mc_algs[i].type) {
111 		case CRYPTO_ALG_TYPE_SKCIPHER:
112 			seq_printf(seq, "%s %s %lu %lu\n",
113 				   mc_algs[i].alg.skcipher.base.cra_driver_name,
114 				   mc_algs[i].alg.skcipher.base.cra_name,
115 				   mc_algs[i].stat_req, mc_algs[i].stat_fb);
116 			break;
117 		}
118 	}
119 	return 0;
120 }
121 
122 static int meson_dbgfs_open(struct inode *inode, struct file *file)
123 {
124 	return single_open(file, meson_dbgfs_read, inode->i_private);
125 }
126 
127 static const struct file_operations meson_debugfs_fops = {
128 	.owner = THIS_MODULE,
129 	.open = meson_dbgfs_open,
130 	.read = seq_read,
131 	.llseek = seq_lseek,
132 	.release = single_release,
133 };
134 #endif
135 
136 static void meson_free_chanlist(struct meson_dev *mc, int i)
137 {
138 	while (i >= 0) {
139 		crypto_engine_exit(mc->chanlist[i].engine);
140 		if (mc->chanlist[i].tl)
141 			dma_free_coherent(mc->dev, sizeof(struct meson_desc) * MAXDESC,
142 					  mc->chanlist[i].tl,
143 					  mc->chanlist[i].t_phy);
144 		i--;
145 	}
146 }
147 
148 /*
149  * Allocate the channel list structure
150  */
151 static int meson_allocate_chanlist(struct meson_dev *mc)
152 {
153 	int i, err;
154 
155 	mc->chanlist = devm_kcalloc(mc->dev, MAXFLOW,
156 				    sizeof(struct meson_flow), GFP_KERNEL);
157 	if (!mc->chanlist)
158 		return -ENOMEM;
159 
160 	for (i = 0; i < MAXFLOW; i++) {
161 		init_completion(&mc->chanlist[i].complete);
162 
163 		mc->chanlist[i].engine = crypto_engine_alloc_init(mc->dev, true);
164 		if (!mc->chanlist[i].engine) {
165 			dev_err(mc->dev, "Cannot allocate engine\n");
166 			i--;
167 			err = -ENOMEM;
168 			goto error_engine;
169 		}
170 		err = crypto_engine_start(mc->chanlist[i].engine);
171 		if (err) {
172 			dev_err(mc->dev, "Cannot start engine\n");
173 			goto error_engine;
174 		}
175 		mc->chanlist[i].tl = dma_alloc_coherent(mc->dev,
176 							sizeof(struct meson_desc) * MAXDESC,
177 							&mc->chanlist[i].t_phy,
178 							GFP_KERNEL);
179 		if (!mc->chanlist[i].tl) {
180 			err = -ENOMEM;
181 			goto error_engine;
182 		}
183 	}
184 	return 0;
185 error_engine:
186 	meson_free_chanlist(mc, i);
187 	return err;
188 }
189 
190 static int meson_register_algs(struct meson_dev *mc)
191 {
192 	int err, i;
193 
194 	for (i = 0; i < ARRAY_SIZE(mc_algs); i++) {
195 		mc_algs[i].mc = mc;
196 		switch (mc_algs[i].type) {
197 		case CRYPTO_ALG_TYPE_SKCIPHER:
198 			err = crypto_register_skcipher(&mc_algs[i].alg.skcipher);
199 			if (err) {
200 				dev_err(mc->dev, "Fail to register %s\n",
201 					mc_algs[i].alg.skcipher.base.cra_name);
202 				mc_algs[i].mc = NULL;
203 				return err;
204 			}
205 			break;
206 		}
207 	}
208 
209 	return 0;
210 }
211 
212 static void meson_unregister_algs(struct meson_dev *mc)
213 {
214 	int i;
215 
216 	for (i = 0; i < ARRAY_SIZE(mc_algs); i++) {
217 		if (!mc_algs[i].mc)
218 			continue;
219 		switch (mc_algs[i].type) {
220 		case CRYPTO_ALG_TYPE_SKCIPHER:
221 			crypto_unregister_skcipher(&mc_algs[i].alg.skcipher);
222 			break;
223 		}
224 	}
225 }
226 
227 static int meson_crypto_probe(struct platform_device *pdev)
228 {
229 	struct meson_dev *mc;
230 	int err, i;
231 
232 	if (!pdev->dev.of_node)
233 		return -ENODEV;
234 
235 	mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
236 	if (!mc)
237 		return -ENOMEM;
238 
239 	mc->dev = &pdev->dev;
240 	platform_set_drvdata(pdev, mc);
241 
242 	mc->base = devm_platform_ioremap_resource(pdev, 0);
243 	if (IS_ERR(mc->base)) {
244 		err = PTR_ERR(mc->base);
245 		dev_err(&pdev->dev, "Cannot request MMIO err=%d\n", err);
246 		return err;
247 	}
248 	mc->busclk = devm_clk_get(&pdev->dev, "blkmv");
249 	if (IS_ERR(mc->busclk)) {
250 		err = PTR_ERR(mc->busclk);
251 		dev_err(&pdev->dev, "Cannot get core clock err=%d\n", err);
252 		return err;
253 	}
254 
255 	mc->irqs = devm_kcalloc(mc->dev, MAXFLOW, sizeof(int), GFP_KERNEL);
256 	for (i = 0; i < MAXFLOW; i++) {
257 		mc->irqs[i] = platform_get_irq(pdev, i);
258 		if (mc->irqs[i] < 0)
259 			return mc->irqs[i];
260 
261 		err = devm_request_irq(&pdev->dev, mc->irqs[i], meson_irq_handler, 0,
262 				       "gxl-crypto", mc);
263 		if (err < 0) {
264 			dev_err(mc->dev, "Cannot request IRQ for flow %d\n", i);
265 			return err;
266 		}
267 	}
268 
269 	err = clk_prepare_enable(mc->busclk);
270 	if (err != 0) {
271 		dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
272 		return err;
273 	}
274 
275 	err = meson_allocate_chanlist(mc);
276 	if (err)
277 		goto error_flow;
278 
279 	err = meson_register_algs(mc);
280 	if (err)
281 		goto error_alg;
282 
283 #ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
284 	mc->dbgfs_dir = debugfs_create_dir("gxl-crypto", NULL);
285 	debugfs_create_file("stats", 0444, mc->dbgfs_dir, mc, &meson_debugfs_fops);
286 #endif
287 
288 	return 0;
289 error_alg:
290 	meson_unregister_algs(mc);
291 error_flow:
292 	meson_free_chanlist(mc, MAXFLOW - 1);
293 	clk_disable_unprepare(mc->busclk);
294 	return err;
295 }
296 
297 static int meson_crypto_remove(struct platform_device *pdev)
298 {
299 	struct meson_dev *mc = platform_get_drvdata(pdev);
300 
301 #ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG
302 	debugfs_remove_recursive(mc->dbgfs_dir);
303 #endif
304 
305 	meson_unregister_algs(mc);
306 
307 	meson_free_chanlist(mc, MAXFLOW - 1);
308 
309 	clk_disable_unprepare(mc->busclk);
310 	return 0;
311 }
312 
313 static const struct of_device_id meson_crypto_of_match_table[] = {
314 	{ .compatible = "amlogic,gxl-crypto", },
315 	{}
316 };
317 MODULE_DEVICE_TABLE(of, meson_crypto_of_match_table);
318 
319 static struct platform_driver meson_crypto_driver = {
320 	.probe		 = meson_crypto_probe,
321 	.remove		 = meson_crypto_remove,
322 	.driver		 = {
323 		.name		   = "gxl-crypto",
324 		.of_match_table	= meson_crypto_of_match_table,
325 	},
326 };
327 
328 module_platform_driver(meson_crypto_driver);
329 
330 MODULE_DESCRIPTION("Amlogic GXL cryptographic offloader");
331 MODULE_LICENSE("GPL");
332 MODULE_AUTHOR("Corentin Labbe <clabbe@baylibre.com>");
333