1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2016 IBM Corporation 4 * 5 * Joel Stanley <joel@jms.id.au> 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/io.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/watchdog.h> 15 16 struct aspeed_wdt { 17 struct watchdog_device wdd; 18 void __iomem *base; 19 u32 ctrl; 20 }; 21 22 struct aspeed_wdt_config { 23 u32 ext_pulse_width_mask; 24 }; 25 26 static const struct aspeed_wdt_config ast2400_config = { 27 .ext_pulse_width_mask = 0xff, 28 }; 29 30 static const struct aspeed_wdt_config ast2500_config = { 31 .ext_pulse_width_mask = 0xfffff, 32 }; 33 34 static const struct of_device_id aspeed_wdt_of_table[] = { 35 { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config }, 36 { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config }, 37 { }, 38 }; 39 MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table); 40 41 #define WDT_STATUS 0x00 42 #define WDT_RELOAD_VALUE 0x04 43 #define WDT_RESTART 0x08 44 #define WDT_CTRL 0x0C 45 #define WDT_CTRL_BOOT_SECONDARY BIT(7) 46 #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) 47 #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) 48 #define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5) 49 #define WDT_CTRL_1MHZ_CLK BIT(4) 50 #define WDT_CTRL_WDT_EXT BIT(3) 51 #define WDT_CTRL_WDT_INTR BIT(2) 52 #define WDT_CTRL_RESET_SYSTEM BIT(1) 53 #define WDT_CTRL_ENABLE BIT(0) 54 #define WDT_TIMEOUT_STATUS 0x10 55 #define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1) 56 57 /* 58 * WDT_RESET_WIDTH controls the characteristics of the external pulse (if 59 * enabled), specifically: 60 * 61 * * Pulse duration 62 * * Drive mode: push-pull vs open-drain 63 * * Polarity: Active high or active low 64 * 65 * Pulse duration configuration is available on both the AST2400 and AST2500, 66 * though the field changes between SoCs: 67 * 68 * AST2400: Bits 7:0 69 * AST2500: Bits 19:0 70 * 71 * This difference is captured in struct aspeed_wdt_config. 72 * 73 * The AST2500 exposes the drive mode and polarity options, but not in a 74 * regular fashion. For read purposes, bit 31 represents active high or low, 75 * and bit 30 represents push-pull or open-drain. With respect to write, magic 76 * values need to be written to the top byte to change the state of the drive 77 * mode and polarity bits. Any other value written to the top byte has no 78 * effect on the state of the drive mode or polarity bits. However, the pulse 79 * width value must be preserved (as desired) if written. 80 */ 81 #define WDT_RESET_WIDTH 0x18 82 #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) 83 #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) 84 #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) 85 #define WDT_RESET_WIDTH_PUSH_PULL BIT(30) 86 #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) 87 #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) 88 89 #define WDT_RESTART_MAGIC 0x4755 90 91 /* 32 bits at 1MHz, in milliseconds */ 92 #define WDT_MAX_TIMEOUT_MS 4294967 93 #define WDT_DEFAULT_TIMEOUT 30 94 #define WDT_RATE_1MHZ 1000000 95 96 static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd) 97 { 98 return container_of(wdd, struct aspeed_wdt, wdd); 99 } 100 101 static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count) 102 { 103 wdt->ctrl |= WDT_CTRL_ENABLE; 104 105 writel(0, wdt->base + WDT_CTRL); 106 writel(count, wdt->base + WDT_RELOAD_VALUE); 107 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); 108 writel(wdt->ctrl, wdt->base + WDT_CTRL); 109 } 110 111 static int aspeed_wdt_start(struct watchdog_device *wdd) 112 { 113 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); 114 115 aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ); 116 117 return 0; 118 } 119 120 static int aspeed_wdt_stop(struct watchdog_device *wdd) 121 { 122 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); 123 124 wdt->ctrl &= ~WDT_CTRL_ENABLE; 125 writel(wdt->ctrl, wdt->base + WDT_CTRL); 126 127 return 0; 128 } 129 130 static int aspeed_wdt_ping(struct watchdog_device *wdd) 131 { 132 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); 133 134 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); 135 136 return 0; 137 } 138 139 static int aspeed_wdt_set_timeout(struct watchdog_device *wdd, 140 unsigned int timeout) 141 { 142 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); 143 u32 actual; 144 145 wdd->timeout = timeout; 146 147 actual = min(timeout, wdd->max_hw_heartbeat_ms * 1000); 148 149 writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE); 150 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); 151 152 return 0; 153 } 154 155 static int aspeed_wdt_restart(struct watchdog_device *wdd, 156 unsigned long action, void *data) 157 { 158 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); 159 160 wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY; 161 aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000); 162 163 mdelay(1000); 164 165 return 0; 166 } 167 168 static const struct watchdog_ops aspeed_wdt_ops = { 169 .start = aspeed_wdt_start, 170 .stop = aspeed_wdt_stop, 171 .ping = aspeed_wdt_ping, 172 .set_timeout = aspeed_wdt_set_timeout, 173 .restart = aspeed_wdt_restart, 174 .owner = THIS_MODULE, 175 }; 176 177 static const struct watchdog_info aspeed_wdt_info = { 178 .options = WDIOF_KEEPALIVEPING 179 | WDIOF_MAGICCLOSE 180 | WDIOF_SETTIMEOUT, 181 .identity = KBUILD_MODNAME, 182 }; 183 184 static int aspeed_wdt_probe(struct platform_device *pdev) 185 { 186 struct device *dev = &pdev->dev; 187 const struct aspeed_wdt_config *config; 188 const struct of_device_id *ofdid; 189 struct aspeed_wdt *wdt; 190 struct device_node *np; 191 const char *reset_type; 192 u32 duration; 193 u32 status; 194 int ret; 195 196 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); 197 if (!wdt) 198 return -ENOMEM; 199 200 wdt->base = devm_platform_ioremap_resource(pdev, 0); 201 if (IS_ERR(wdt->base)) 202 return PTR_ERR(wdt->base); 203 204 /* 205 * The ast2400 wdt can run at PCLK, or 1MHz. The ast2500 only 206 * runs at 1MHz. We chose to always run at 1MHz, as there's no 207 * good reason to have a faster watchdog counter. 208 */ 209 wdt->wdd.info = &aspeed_wdt_info; 210 wdt->wdd.ops = &aspeed_wdt_ops; 211 wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS; 212 wdt->wdd.parent = dev; 213 214 wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT; 215 watchdog_init_timeout(&wdt->wdd, 0, dev); 216 217 np = dev->of_node; 218 219 ofdid = of_match_node(aspeed_wdt_of_table, np); 220 if (!ofdid) 221 return -EINVAL; 222 config = ofdid->data; 223 224 wdt->ctrl = WDT_CTRL_1MHZ_CLK; 225 226 /* 227 * Control reset on a per-device basis to ensure the 228 * host is not affected by a BMC reboot 229 */ 230 ret = of_property_read_string(np, "aspeed,reset-type", &reset_type); 231 if (ret) { 232 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM; 233 } else { 234 if (!strcmp(reset_type, "cpu")) 235 wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU | 236 WDT_CTRL_RESET_SYSTEM; 237 else if (!strcmp(reset_type, "soc")) 238 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | 239 WDT_CTRL_RESET_SYSTEM; 240 else if (!strcmp(reset_type, "system")) 241 wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP | 242 WDT_CTRL_RESET_SYSTEM; 243 else if (strcmp(reset_type, "none")) 244 return -EINVAL; 245 } 246 if (of_property_read_bool(np, "aspeed,external-signal")) 247 wdt->ctrl |= WDT_CTRL_WDT_EXT; 248 if (of_property_read_bool(np, "aspeed,alt-boot")) 249 wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY; 250 251 if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) { 252 /* 253 * The watchdog is running, but invoke aspeed_wdt_start() to 254 * write wdt->ctrl to WDT_CTRL to ensure the watchdog's 255 * configuration conforms to the driver's expectations. 256 * Primarily, ensure we're using the 1MHz clock source. 257 */ 258 aspeed_wdt_start(&wdt->wdd); 259 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); 260 } 261 262 if (of_device_is_compatible(np, "aspeed,ast2500-wdt")) { 263 u32 reg = readl(wdt->base + WDT_RESET_WIDTH); 264 265 reg &= config->ext_pulse_width_mask; 266 if (of_property_read_bool(np, "aspeed,ext-push-pull")) 267 reg |= WDT_PUSH_PULL_MAGIC; 268 else 269 reg |= WDT_OPEN_DRAIN_MAGIC; 270 271 writel(reg, wdt->base + WDT_RESET_WIDTH); 272 273 reg &= config->ext_pulse_width_mask; 274 if (of_property_read_bool(np, "aspeed,ext-active-high")) 275 reg |= WDT_ACTIVE_HIGH_MAGIC; 276 else 277 reg |= WDT_ACTIVE_LOW_MAGIC; 278 279 writel(reg, wdt->base + WDT_RESET_WIDTH); 280 } 281 282 if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) { 283 u32 max_duration = config->ext_pulse_width_mask + 1; 284 285 if (duration == 0 || duration > max_duration) { 286 dev_err(dev, "Invalid pulse duration: %uus\n", 287 duration); 288 duration = max(1U, min(max_duration, duration)); 289 dev_info(dev, "Pulse duration set to %uus\n", 290 duration); 291 } 292 293 /* 294 * The watchdog is always configured with a 1MHz source, so 295 * there is no need to scale the microsecond value. However we 296 * need to offset it - from the datasheet: 297 * 298 * "This register decides the asserting duration of wdt_ext and 299 * wdt_rstarm signal. The default value is 0xFF. It means the 300 * default asserting duration of wdt_ext and wdt_rstarm is 301 * 256us." 302 * 303 * This implies a value of 0 gives a 1us pulse. 304 */ 305 writel(duration - 1, wdt->base + WDT_RESET_WIDTH); 306 } 307 308 status = readl(wdt->base + WDT_TIMEOUT_STATUS); 309 if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) 310 wdt->wdd.bootstatus = WDIOF_CARDRESET; 311 312 return devm_watchdog_register_device(dev, &wdt->wdd); 313 } 314 315 static struct platform_driver aspeed_watchdog_driver = { 316 .probe = aspeed_wdt_probe, 317 .driver = { 318 .name = KBUILD_MODNAME, 319 .of_match_table = of_match_ptr(aspeed_wdt_of_table), 320 }, 321 }; 322 323 static int __init aspeed_wdt_init(void) 324 { 325 return platform_driver_register(&aspeed_watchdog_driver); 326 } 327 arch_initcall(aspeed_wdt_init); 328 329 static void __exit aspeed_wdt_exit(void) 330 { 331 platform_driver_unregister(&aspeed_watchdog_driver); 332 } 333 module_exit(aspeed_wdt_exit); 334 335 MODULE_DESCRIPTION("Aspeed Watchdog Driver"); 336 MODULE_LICENSE("GPL"); 337