1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SMP initialisation and IPI support 4 * Based on arch/arm64/kernel/smp.c 5 * 6 * Copyright (C) 2012 ARM Ltd. 7 * Copyright (C) 2015 Regents of the University of California 8 * Copyright (C) 2017 SiFive 9 */ 10 11 #include <linux/cpu.h> 12 #include <linux/interrupt.h> 13 #include <linux/module.h> 14 #include <linux/profile.h> 15 #include <linux/smp.h> 16 #include <linux/sched.h> 17 #include <linux/seq_file.h> 18 #include <linux/delay.h> 19 20 #include <asm/clint.h> 21 #include <asm/sbi.h> 22 #include <asm/tlbflush.h> 23 #include <asm/cacheflush.h> 24 25 enum ipi_message_type { 26 IPI_RESCHEDULE, 27 IPI_CALL_FUNC, 28 IPI_CPU_STOP, 29 IPI_MAX 30 }; 31 32 unsigned long __cpuid_to_hartid_map[NR_CPUS] = { 33 [0 ... NR_CPUS-1] = INVALID_HARTID 34 }; 35 36 void __init smp_setup_processor_id(void) 37 { 38 cpuid_to_hartid_map(0) = boot_cpu_hartid; 39 } 40 41 /* A collection of single bit ipi messages. */ 42 static struct { 43 unsigned long stats[IPI_MAX] ____cacheline_aligned; 44 unsigned long bits ____cacheline_aligned; 45 } ipi_data[NR_CPUS] __cacheline_aligned; 46 47 int riscv_hartid_to_cpuid(int hartid) 48 { 49 int i; 50 51 for (i = 0; i < NR_CPUS; i++) 52 if (cpuid_to_hartid_map(i) == hartid) 53 return i; 54 55 pr_err("Couldn't find cpu id for hartid [%d]\n", hartid); 56 return i; 57 } 58 59 void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out) 60 { 61 int cpu; 62 63 cpumask_clear(out); 64 for_each_cpu(cpu, in) 65 cpumask_set_cpu(cpuid_to_hartid_map(cpu), out); 66 } 67 EXPORT_SYMBOL_GPL(riscv_cpuid_to_hartid_mask); 68 69 bool arch_match_cpu_phys_id(int cpu, u64 phys_id) 70 { 71 return phys_id == cpuid_to_hartid_map(cpu); 72 } 73 74 /* Unsupported */ 75 int setup_profiling_timer(unsigned int multiplier) 76 { 77 return -EINVAL; 78 } 79 80 static void ipi_stop(void) 81 { 82 set_cpu_online(smp_processor_id(), false); 83 while (1) 84 wait_for_interrupt(); 85 } 86 87 static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op) 88 { 89 struct cpumask hartid_mask; 90 int cpu; 91 92 smp_mb__before_atomic(); 93 for_each_cpu(cpu, mask) 94 set_bit(op, &ipi_data[cpu].bits); 95 smp_mb__after_atomic(); 96 97 riscv_cpuid_to_hartid_mask(mask, &hartid_mask); 98 if (IS_ENABLED(CONFIG_RISCV_SBI)) 99 sbi_send_ipi(cpumask_bits(&hartid_mask)); 100 else 101 clint_send_ipi_mask(mask); 102 } 103 104 static void send_ipi_single(int cpu, enum ipi_message_type op) 105 { 106 int hartid = cpuid_to_hartid_map(cpu); 107 108 smp_mb__before_atomic(); 109 set_bit(op, &ipi_data[cpu].bits); 110 smp_mb__after_atomic(); 111 112 if (IS_ENABLED(CONFIG_RISCV_SBI)) 113 sbi_send_ipi(cpumask_bits(cpumask_of(hartid))); 114 else 115 clint_send_ipi_single(hartid); 116 } 117 118 static inline void clear_ipi(void) 119 { 120 if (IS_ENABLED(CONFIG_RISCV_SBI)) 121 csr_clear(CSR_IP, IE_SIE); 122 else 123 clint_clear_ipi(cpuid_to_hartid_map(smp_processor_id())); 124 } 125 126 void handle_IPI(struct pt_regs *regs) 127 { 128 struct pt_regs *old_regs = set_irq_regs(regs); 129 unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits; 130 unsigned long *stats = ipi_data[smp_processor_id()].stats; 131 132 irq_enter(); 133 134 clear_ipi(); 135 136 while (true) { 137 unsigned long ops; 138 139 /* Order bit clearing and data access. */ 140 mb(); 141 142 ops = xchg(pending_ipis, 0); 143 if (ops == 0) 144 goto done; 145 146 if (ops & (1 << IPI_RESCHEDULE)) { 147 stats[IPI_RESCHEDULE]++; 148 scheduler_ipi(); 149 } 150 151 if (ops & (1 << IPI_CALL_FUNC)) { 152 stats[IPI_CALL_FUNC]++; 153 generic_smp_call_function_interrupt(); 154 } 155 156 if (ops & (1 << IPI_CPU_STOP)) { 157 stats[IPI_CPU_STOP]++; 158 ipi_stop(); 159 } 160 161 BUG_ON((ops >> IPI_MAX) != 0); 162 163 /* Order data access and bit testing. */ 164 mb(); 165 } 166 167 done: 168 irq_exit(); 169 set_irq_regs(old_regs); 170 } 171 172 static const char * const ipi_names[] = { 173 [IPI_RESCHEDULE] = "Rescheduling interrupts", 174 [IPI_CALL_FUNC] = "Function call interrupts", 175 [IPI_CPU_STOP] = "CPU stop interrupts", 176 }; 177 178 void show_ipi_stats(struct seq_file *p, int prec) 179 { 180 unsigned int cpu, i; 181 182 for (i = 0; i < IPI_MAX; i++) { 183 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, 184 prec >= 4 ? " " : ""); 185 for_each_online_cpu(cpu) 186 seq_printf(p, "%10lu ", ipi_data[cpu].stats[i]); 187 seq_printf(p, " %s\n", ipi_names[i]); 188 } 189 } 190 191 void arch_send_call_function_ipi_mask(struct cpumask *mask) 192 { 193 send_ipi_mask(mask, IPI_CALL_FUNC); 194 } 195 196 void arch_send_call_function_single_ipi(int cpu) 197 { 198 send_ipi_single(cpu, IPI_CALL_FUNC); 199 } 200 201 void smp_send_stop(void) 202 { 203 unsigned long timeout; 204 205 if (num_online_cpus() > 1) { 206 cpumask_t mask; 207 208 cpumask_copy(&mask, cpu_online_mask); 209 cpumask_clear_cpu(smp_processor_id(), &mask); 210 211 if (system_state <= SYSTEM_RUNNING) 212 pr_crit("SMP: stopping secondary CPUs\n"); 213 send_ipi_mask(&mask, IPI_CPU_STOP); 214 } 215 216 /* Wait up to one second for other CPUs to stop */ 217 timeout = USEC_PER_SEC; 218 while (num_online_cpus() > 1 && timeout--) 219 udelay(1); 220 221 if (num_online_cpus() > 1) 222 pr_warn("SMP: failed to stop secondary CPUs %*pbl\n", 223 cpumask_pr_args(cpu_online_mask)); 224 } 225 226 void smp_send_reschedule(int cpu) 227 { 228 send_ipi_single(cpu, IPI_RESCHEDULE); 229 } 230 EXPORT_SYMBOL_GPL(smp_send_reschedule); 231