1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM System MMU Architecture Implementation
8
9maintainers:
10  - Will Deacon <will@kernel.org>
11  - Robin Murphy <Robin.Murphy@arm.com>
12
13description: |+
14  ARM SoCs may contain an implementation of the ARM System Memory
15  Management Unit Architecture, which can be used to provide 1 or 2 stages
16  of address translation to bus masters external to the CPU.
17
18  The SMMU may also raise interrupts in response to various fault
19  conditions.
20
21properties:
22  $nodename:
23    pattern: "^iommu@[0-9a-f]*"
24  compatible:
25    oneOf:
26      - description: Qcom SoCs implementing "arm,smmu-v2"
27        items:
28          - enum:
29              - qcom,msm8996-smmu-v2
30              - qcom,msm8998-smmu-v2
31              - qcom,sc7180-smmu-v2
32              - qcom,sdm845-smmu-v2
33          - const: qcom,smmu-v2
34
35      - description: Qcom SoCs implementing "arm,mmu-500"
36        items:
37          - enum:
38              - qcom,sc7180-smmu-500
39              - qcom,sdm845-smmu-500
40          - const: arm,mmu-500
41      - items:
42          - const: arm,mmu-500
43          - const: arm,smmu-v2
44      - items:
45          - enum:
46              - arm,mmu-400
47              - arm,mmu-401
48          - const: arm,smmu-v1
49      - enum:
50          - arm,smmu-v1
51          - arm,smmu-v2
52          - arm,mmu-400
53          - arm,mmu-401
54          - arm,mmu-500
55          - cavium,smmu-v2
56
57  reg:
58    maxItems: 1
59
60  '#global-interrupts':
61    description: The number of global interrupts exposed by the device.
62    $ref: /schemas/types.yaml#/definitions/uint32
63    minimum: 0
64    maximum: 260   # 2 secure, 2 non-secure, and up to 256 perf counters
65
66  '#iommu-cells':
67    enum: [ 1, 2 ]
68    description: |
69      See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
70      value of 1, each IOMMU specifier represents a distinct stream ID emitted
71      by that device into the relevant SMMU.
72
73      SMMUs with stream matching support and complex masters may use a value of
74      2, where the second cell of the IOMMU specifier represents an SMR mask to
75      combine with the ID in the first cell.  Care must be taken to ensure the
76      set of matched IDs does not result in conflicts.
77
78  interrupts:
79    minItems: 1
80    maxItems: 388   # 260 plus 128 contexts
81    description: |
82      Interrupt list, with the first #global-interrupts entries corresponding to
83      the global interrupts and any following entries corresponding to context
84      interrupts, specified in order of their indexing by the SMMU.
85
86      For SMMUv2 implementations, there must be exactly one interrupt per
87      context bank. In the case of a single, combined interrupt, it must be
88      listed multiple times.
89
90  dma-coherent:
91    description: |
92      Present if page table walks made by the SMMU are cache coherent with the
93      CPU.
94
95      NOTE: this only applies to the SMMU itself, not masters connected
96      upstream of the SMMU.
97
98  calxeda,smmu-secure-config-access:
99    type: boolean
100    description:
101      Enable proper handling of buggy implementations that always use secure
102      access to SMMU configuration registers. In this case non-secure aliases of
103      secure registers have to be used during SMMU configuration.
104
105  stream-match-mask:
106    $ref: /schemas/types.yaml#/definitions/uint32
107    description: |
108      For SMMUs supporting stream matching and using #iommu-cells = <1>,
109      specifies a mask of bits to ignore when matching stream IDs (e.g. this may
110      be programmed into the SMRn.MASK field of every stream match register
111      used). For cases where it is desirable to ignore some portion of every
112      Stream ID (e.g. for certain MMU-500 configurations given globally unique
113      input IDs). This property is not valid for SMMUs using stream indexing, or
114      using stream matching with #iommu-cells = <2>, and may be ignored if
115      present in such cases.
116
117  clock-names:
118    items:
119      - const: bus
120      - const: iface
121
122  clocks:
123    items:
124      - description: bus clock required for downstream bus access and for the
125          smmu ptw
126      - description: interface clock required to access smmu's registers
127          through the TCU's programming interface.
128
129  power-domains:
130    maxItems: 1
131
132required:
133  - compatible
134  - reg
135  - '#global-interrupts'
136  - '#iommu-cells'
137  - interrupts
138
139additionalProperties: false
140
141examples:
142  - |+
143    /* SMMU with stream matching or stream indexing */
144    smmu1: iommu@ba5e0000 {
145            compatible = "arm,smmu-v1";
146            reg = <0xba5e0000 0x10000>;
147            #global-interrupts = <2>;
148            interrupts = <0 32 4>,
149                         <0 33 4>,
150                         <0 34 4>, /* This is the first context interrupt */
151                         <0 35 4>,
152                         <0 36 4>,
153                         <0 37 4>;
154            #iommu-cells = <1>;
155    };
156
157    /* device with two stream IDs, 0 and 7 */
158    master1 {
159            iommus = <&smmu1 0>,
160                     <&smmu1 7>;
161    };
162
163
164    /* SMMU with stream matching */
165    smmu2: iommu@ba5f0000 {
166            compatible = "arm,smmu-v1";
167            reg = <0xba5f0000 0x10000>;
168            #global-interrupts = <2>;
169            interrupts = <0 38 4>,
170                         <0 39 4>,
171                         <0 40 4>, /* This is the first context interrupt */
172                         <0 41 4>,
173                         <0 42 4>,
174                         <0 43 4>;
175            #iommu-cells = <2>;
176    };
177
178    /* device with stream IDs 0 and 7 */
179    master2 {
180            iommus = <&smmu2 0 0>,
181                     <&smmu2 7 0>;
182    };
183
184    /* device with stream IDs 1, 17, 33 and 49 */
185    master3 {
186            iommus = <&smmu2 1 0x30>;
187    };
188
189
190    /* ARM MMU-500 with 10-bit stream ID input configuration */
191    smmu3: iommu@ba600000 {
192            compatible = "arm,mmu-500", "arm,smmu-v2";
193            reg = <0xba600000 0x10000>;
194            #global-interrupts = <2>;
195            interrupts = <0 44 4>,
196                         <0 45 4>,
197                         <0 46 4>, /* This is the first context interrupt */
198                         <0 47 4>,
199                         <0 48 4>,
200                         <0 49 4>;
201            #iommu-cells = <1>;
202            /* always ignore appended 5-bit TBU number */
203            stream-match-mask = <0x7c00>;
204    };
205
206    bus {
207            /* bus whose child devices emit one unique 10-bit stream
208               ID each, but may master through multiple SMMU TBUs */
209            iommu-map = <0 &smmu3 0 0x400>;
210
211
212    };
213
214  - |+
215    /* Qcom's arm,smmu-v2 implementation */
216    #include <dt-bindings/interrupt-controller/arm-gic.h>
217    #include <dt-bindings/interrupt-controller/irq.h>
218    smmu4: iommu@d00000 {
219      compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
220      reg = <0xd00000 0x10000>;
221
222      #global-interrupts = <1>;
223      interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
224             <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
225             <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
226      #iommu-cells = <1>;
227      power-domains = <&mmcc 0>;
228
229      clocks = <&mmcc 123>,
230        <&mmcc 124>;
231      clock-names = "bus", "iface";
232    };
233