1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "smuio/smuio_11_0_0_offset.h" 25 #include "smuio/smuio_11_0_0_sh_mask.h" 26 27 #include "smu_v11_0_i2c.h" 28 #include "amdgpu.h" 29 #include "soc15_common.h" 30 #include <drm/drm_fixed.h> 31 #include <drm/drm_drv.h> 32 #include "amdgpu_amdkfd.h" 33 #include <linux/i2c.h> 34 #include <linux/pci.h> 35 36 /* error codes */ 37 #define I2C_OK 0 38 #define I2C_NAK_7B_ADDR_NOACK 1 39 #define I2C_NAK_TXDATA_NOACK 2 40 #define I2C_TIMEOUT 4 41 #define I2C_SW_TIMEOUT 8 42 #define I2C_ABORT 0x10 43 44 /* I2C transaction flags */ 45 #define I2C_NO_STOP 1 46 #define I2C_RESTART 2 47 48 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 49 50 static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en) 51 { 52 struct amdgpu_device *adev = to_amdgpu_device(control); 53 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT); 54 55 reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0); 56 WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg); 57 } 58 59 60 static void smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable) 61 { 62 struct amdgpu_device *adev = to_amdgpu_device(control); 63 64 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0); 65 } 66 67 static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control) 68 { 69 struct amdgpu_device *adev = to_amdgpu_device(control); 70 /* do */ 71 { 72 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR); 73 74 } /* while (reg_CKSVII2C_ic_clr_intr == 0) */ 75 } 76 77 static void smu_v11_0_i2c_configure(struct i2c_adapter *control) 78 { 79 struct amdgpu_device *adev = to_amdgpu_device(control); 80 uint32_t reg = 0; 81 82 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1); 83 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1); 84 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0); 85 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0); 86 /* Standard mode */ 87 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE, 2); 88 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1); 89 90 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg); 91 } 92 93 static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control) 94 { 95 struct amdgpu_device *adev = to_amdgpu_device(control); 96 97 /* 98 * Standard mode speed, These values are taken from SMUIO MAS, 99 * but are different from what is given is 100 * Synopsys spec. The values here are based on assumption 101 * that refclock is 100MHz 102 * 103 * Configuration for standard mode; Speed = 100kbps 104 * Scale linearly, for now only support standard speed clock 105 * This will work only with 100M ref clock 106 * 107 * TBD:Change the calculation to take into account ref clock values also. 108 */ 109 110 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_FS_SPKLEN, 2); 111 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_HCNT, 120); 112 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_LCNT, 130); 113 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SDA_HOLD, 20); 114 } 115 116 static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, uint8_t address) 117 { 118 struct amdgpu_device *adev = to_amdgpu_device(control); 119 120 /* Convert fromr 8-bit to 7-bit address */ 121 address >>= 1; 122 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, (address & 0xFF)); 123 } 124 125 static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control) 126 { 127 struct amdgpu_device *adev = to_amdgpu_device(control); 128 uint32_t ret = I2C_OK; 129 uint32_t reg, reg_c_tx_abrt_source; 130 131 /*Check if transmission is completed */ 132 unsigned long timeout_counter = jiffies + msecs_to_jiffies(20); 133 134 do { 135 if (time_after(jiffies, timeout_counter)) { 136 ret |= I2C_SW_TIMEOUT; 137 break; 138 } 139 140 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); 141 142 } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0); 143 144 if (ret != I2C_OK) 145 return ret; 146 147 /* This only checks if NAK is received and transaction got aborted */ 148 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT); 149 150 if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) { 151 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); 152 DRM_INFO("TX was terminated, IC_TX_ABRT_SOURCE val is:%x", reg_c_tx_abrt_source); 153 154 /* Check for stop due to NACK */ 155 if (REG_GET_FIELD(reg_c_tx_abrt_source, 156 CKSVII2C_IC_TX_ABRT_SOURCE, 157 ABRT_TXDATA_NOACK) == 1) { 158 159 ret |= I2C_NAK_TXDATA_NOACK; 160 161 } else if (REG_GET_FIELD(reg_c_tx_abrt_source, 162 CKSVII2C_IC_TX_ABRT_SOURCE, 163 ABRT_7B_ADDR_NOACK) == 1) { 164 165 ret |= I2C_NAK_7B_ADDR_NOACK; 166 } else { 167 ret |= I2C_ABORT; 168 } 169 170 smu_v11_0_i2c_clear_status(control); 171 } 172 173 return ret; 174 } 175 176 static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control) 177 { 178 struct amdgpu_device *adev = to_amdgpu_device(control); 179 uint32_t ret = I2C_OK; 180 uint32_t reg_ic_status, reg_c_tx_abrt_source; 181 182 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); 183 184 /* If slave is not present */ 185 if (REG_GET_FIELD(reg_c_tx_abrt_source, 186 CKSVII2C_IC_TX_ABRT_SOURCE, 187 ABRT_7B_ADDR_NOACK) == 1) { 188 ret |= I2C_NAK_7B_ADDR_NOACK; 189 190 smu_v11_0_i2c_clear_status(control); 191 } else { /* wait till some data is there in RXFIFO */ 192 /* Poll for some byte in RXFIFO */ 193 unsigned long timeout_counter = jiffies + msecs_to_jiffies(20); 194 195 do { 196 if (time_after(jiffies, timeout_counter)) { 197 ret |= I2C_SW_TIMEOUT; 198 break; 199 } 200 201 reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); 202 203 } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0); 204 } 205 206 return ret; 207 } 208 209 210 211 212 /** 213 * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave device. 214 * 215 * @address: The I2C address of the slave device. 216 * @data: The data to transmit over the bus. 217 * @numbytes: The amount of data to transmit. 218 * @i2c_flag: Flags for transmission 219 * 220 * Returns 0 on success or error. 221 */ 222 static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control, 223 uint8_t address, uint8_t *data, 224 uint32_t numbytes, uint32_t i2c_flag) 225 { 226 struct amdgpu_device *adev = to_amdgpu_device(control); 227 uint32_t bytes_sent, reg, ret = 0; 228 unsigned long timeout_counter; 229 230 bytes_sent = 0; 231 232 DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ", 233 (uint16_t)address, numbytes); 234 235 if (drm_debug_enabled(DRM_UT_DRIVER)) { 236 print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE, 237 16, 1, data, numbytes, false); 238 } 239 240 /* Set the I2C slave address */ 241 smu_v11_0_i2c_set_address(control, address); 242 /* Enable I2C */ 243 smu_v11_0_i2c_enable(control, true); 244 245 /* Clear status bits */ 246 smu_v11_0_i2c_clear_status(control); 247 248 249 timeout_counter = jiffies + msecs_to_jiffies(20); 250 251 while (numbytes > 0) { 252 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); 253 if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) { 254 do { 255 reg = 0; 256 /* 257 * Prepare transaction, no need to set RESTART. I2C engine will send 258 * START as soon as it sees data in TXFIFO 259 */ 260 if (bytes_sent == 0) 261 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART, 262 (i2c_flag & I2C_RESTART) ? 1 : 0); 263 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, data[bytes_sent]); 264 265 /* determine if we need to send STOP bit or not */ 266 if (numbytes == 1) 267 /* Final transaction, so send stop unless I2C_NO_STOP */ 268 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP, 269 (i2c_flag & I2C_NO_STOP) ? 0 : 1); 270 /* Write */ 271 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0); 272 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg); 273 274 /* Record that the bytes were transmitted */ 275 bytes_sent++; 276 numbytes--; 277 278 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); 279 280 } while (numbytes && REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)); 281 } 282 283 /* 284 * We waited too long for the transmission FIFO to become not-full. 285 * Exit the loop with error. 286 */ 287 if (time_after(jiffies, timeout_counter)) { 288 ret |= I2C_SW_TIMEOUT; 289 goto Err; 290 } 291 } 292 293 ret = smu_v11_0_i2c_poll_tx_status(control); 294 295 Err: 296 /* Any error, no point in proceeding */ 297 if (ret != I2C_OK) { 298 if (ret & I2C_SW_TIMEOUT) 299 DRM_ERROR("TIMEOUT ERROR !!!"); 300 301 if (ret & I2C_NAK_7B_ADDR_NOACK) 302 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!"); 303 304 305 if (ret & I2C_NAK_TXDATA_NOACK) 306 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!"); 307 } 308 309 return ret; 310 } 311 312 313 /** 314 * smu_v11_0_i2c_receive - Receive a block of data over the I2C bus from a slave device. 315 * 316 * @address: The I2C address of the slave device. 317 * @numbytes: The amount of data to transmit. 318 * @i2c_flag: Flags for transmission 319 * 320 * Returns 0 on success or error. 321 */ 322 static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control, 323 uint8_t address, uint8_t *data, 324 uint32_t numbytes, uint8_t i2c_flag) 325 { 326 struct amdgpu_device *adev = to_amdgpu_device(control); 327 uint32_t bytes_received, ret = I2C_OK; 328 329 bytes_received = 0; 330 331 /* Set the I2C slave address */ 332 smu_v11_0_i2c_set_address(control, address); 333 334 /* Enable I2C */ 335 smu_v11_0_i2c_enable(control, true); 336 337 while (numbytes > 0) { 338 uint32_t reg = 0; 339 340 smu_v11_0_i2c_clear_status(control); 341 342 343 /* Prepare transaction */ 344 345 /* Each time we disable I2C, so this is not a restart */ 346 if (bytes_received == 0) 347 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART, 348 (i2c_flag & I2C_RESTART) ? 1 : 0); 349 350 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0); 351 /* Read */ 352 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1); 353 354 /* Transmitting last byte */ 355 if (numbytes == 1) 356 /* Final transaction, so send stop if requested */ 357 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP, 358 (i2c_flag & I2C_NO_STOP) ? 0 : 1); 359 360 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg); 361 362 ret = smu_v11_0_i2c_poll_rx_status(control); 363 364 /* Any error, no point in proceeding */ 365 if (ret != I2C_OK) { 366 if (ret & I2C_SW_TIMEOUT) 367 DRM_ERROR("TIMEOUT ERROR !!!"); 368 369 if (ret & I2C_NAK_7B_ADDR_NOACK) 370 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!"); 371 372 if (ret & I2C_NAK_TXDATA_NOACK) 373 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!"); 374 375 break; 376 } 377 378 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD); 379 data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT); 380 381 /* Record that the bytes were received */ 382 bytes_received++; 383 numbytes--; 384 } 385 386 DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :", 387 (uint16_t)address, bytes_received); 388 389 if (drm_debug_enabled(DRM_UT_DRIVER)) { 390 print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE, 391 16, 1, data, bytes_received, false); 392 } 393 394 return ret; 395 } 396 397 static void smu_v11_0_i2c_abort(struct i2c_adapter *control) 398 { 399 struct amdgpu_device *adev = to_amdgpu_device(control); 400 uint32_t reg = 0; 401 402 /* Enable I2C engine; */ 403 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1); 404 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg); 405 406 /* Abort previous transaction */ 407 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1); 408 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg); 409 410 DRM_DEBUG_DRIVER("I2C_Abort() Done."); 411 } 412 413 414 static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control) 415 { 416 struct amdgpu_device *adev = to_amdgpu_device(control); 417 418 const uint32_t IDLE_TIMEOUT = 1024; 419 uint32_t timeout_count = 0; 420 uint32_t reg_ic_enable, reg_ic_enable_status, reg_ic_clr_activity; 421 422 reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS); 423 reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE); 424 425 426 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && 427 (REG_GET_FIELD(reg_ic_enable_status, CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) { 428 /* 429 * Nobody is using I2C engine, but engine remains active because 430 * someone missed to send STOP 431 */ 432 smu_v11_0_i2c_abort(control); 433 } else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) { 434 /* Nobody is using I2C engine */ 435 return true; 436 } 437 438 /* Keep reading activity bit until it's cleared */ 439 do { 440 reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY); 441 442 if (REG_GET_FIELD(reg_ic_clr_activity, 443 CKSVII2C_IC_CLR_ACTIVITY, CLR_ACTIVITY) == 0) 444 return true; 445 446 ++timeout_count; 447 448 } while (timeout_count < IDLE_TIMEOUT); 449 450 return false; 451 } 452 453 static void smu_v11_0_i2c_init(struct i2c_adapter *control) 454 { 455 /* Disable clock gating */ 456 smu_v11_0_i2c_set_clock_gating(control, false); 457 458 if (!smu_v11_0_i2c_activity_done(control)) 459 DRM_WARN("I2C busy !"); 460 461 /* Disable I2C */ 462 smu_v11_0_i2c_enable(control, false); 463 464 /* Configure I2C to operate as master and in standard mode */ 465 smu_v11_0_i2c_configure(control); 466 467 /* Initialize the clock to 50 kHz default */ 468 smu_v11_0_i2c_set_clock(control); 469 470 } 471 472 static void smu_v11_0_i2c_fini(struct i2c_adapter *control) 473 { 474 struct amdgpu_device *adev = to_amdgpu_device(control); 475 uint32_t reg_ic_enable_status, reg_ic_enable; 476 477 smu_v11_0_i2c_enable(control, false); 478 479 /* Double check if disabled, else force abort */ 480 reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS); 481 reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE); 482 483 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && 484 (REG_GET_FIELD(reg_ic_enable_status, 485 CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) { 486 /* 487 * Nobody is using I2C engine, but engine remains active because 488 * someone missed to send STOP 489 */ 490 smu_v11_0_i2c_abort(control); 491 } 492 493 /* Restore clock gating */ 494 495 /* 496 * TODO Reenabling clock gating seems to break subsequent SMU operation 497 * on the I2C bus. My guess is that SMU doesn't disable clock gating like 498 * we do here before working with the bus. So for now just don't restore 499 * it but later work with SMU to see if they have this issue and can 500 * update their code appropriately 501 */ 502 /* smu_v11_0_i2c_set_clock_gating(control, true); */ 503 504 } 505 506 static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control) 507 { 508 struct amdgpu_device *adev = to_amdgpu_device(control); 509 510 /* Send PPSMC_MSG_RequestI2CBus */ 511 if (!adev->powerplay.pp_funcs->smu_i2c_bus_access) 512 goto Fail; 513 514 515 if (!adev->powerplay.pp_funcs->smu_i2c_bus_access(adev->powerplay.pp_handle, true)) 516 return true; 517 518 Fail: 519 return false; 520 } 521 522 static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control) 523 { 524 struct amdgpu_device *adev = to_amdgpu_device(control); 525 526 /* Send PPSMC_MSG_RequestI2CBus */ 527 if (!adev->powerplay.pp_funcs->smu_i2c_bus_access) 528 goto Fail; 529 530 /* Send PPSMC_MSG_ReleaseI2CBus */ 531 if (!adev->powerplay.pp_funcs->smu_i2c_bus_access(adev->powerplay.pp_handle, 532 false)) 533 return true; 534 535 Fail: 536 return false; 537 } 538 539 /***************************** I2C GLUE ****************************/ 540 541 static uint32_t smu_v11_0_i2c_read_data(struct i2c_adapter *control, 542 uint8_t address, 543 uint8_t *data, 544 uint32_t numbytes) 545 { 546 uint32_t ret = 0; 547 548 /* First 2 bytes are dummy write to set EEPROM address */ 549 ret = smu_v11_0_i2c_transmit(control, address, data, 2, I2C_NO_STOP); 550 if (ret != I2C_OK) 551 goto Fail; 552 553 /* Now read data starting with that address */ 554 ret = smu_v11_0_i2c_receive(control, address, data + 2, numbytes - 2, 555 I2C_RESTART); 556 557 Fail: 558 if (ret != I2C_OK) 559 DRM_ERROR("ReadData() - I2C error occurred :%x", ret); 560 561 return ret; 562 } 563 564 static uint32_t smu_v11_0_i2c_write_data(struct i2c_adapter *control, 565 uint8_t address, 566 uint8_t *data, 567 uint32_t numbytes) 568 { 569 uint32_t ret; 570 571 ret = smu_v11_0_i2c_transmit(control, address, data, numbytes, 0); 572 573 if (ret != I2C_OK) 574 DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret); 575 else 576 /* 577 * According to EEPROM spec there is a MAX of 10 ms required for 578 * EEPROM to flush internal RX buffer after STOP was issued at the 579 * end of write transaction. During this time the EEPROM will not be 580 * responsive to any more commands - so wait a bit more. 581 * 582 * TODO Improve to wait for first ACK for slave address after 583 * internal write cycle done. 584 */ 585 msleep(10); 586 587 return ret; 588 589 } 590 591 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) 592 { 593 struct amdgpu_device *adev = to_amdgpu_device(i2c); 594 595 if (!smu_v11_0_i2c_bus_lock(i2c)) { 596 DRM_ERROR("Failed to lock the bus from SMU"); 597 return; 598 } 599 600 adev->pm.bus_locked = true; 601 } 602 603 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) 604 { 605 WARN_ONCE(1, "This operation not supposed to run in atomic context!"); 606 return false; 607 } 608 609 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) 610 { 611 struct amdgpu_device *adev = to_amdgpu_device(i2c); 612 613 if (!smu_v11_0_i2c_bus_unlock(i2c)) { 614 DRM_ERROR("Failed to unlock the bus from SMU"); 615 return; 616 } 617 618 adev->pm.bus_locked = false; 619 } 620 621 static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = { 622 .lock_bus = lock_bus, 623 .trylock_bus = trylock_bus, 624 .unlock_bus = unlock_bus, 625 }; 626 627 static int smu_v11_0_i2c_xfer(struct i2c_adapter *i2c_adap, 628 struct i2c_msg *msgs, int num) 629 { 630 int i, ret; 631 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap); 632 633 if (!adev->pm.bus_locked) { 634 DRM_ERROR("I2C bus unlocked, stopping transaction!"); 635 return -EIO; 636 } 637 638 smu_v11_0_i2c_init(i2c_adap); 639 640 for (i = 0; i < num; i++) { 641 if (msgs[i].flags & I2C_M_RD) 642 ret = smu_v11_0_i2c_read_data(i2c_adap, 643 (uint8_t)msgs[i].addr, 644 msgs[i].buf, msgs[i].len); 645 else 646 ret = smu_v11_0_i2c_write_data(i2c_adap, 647 (uint8_t)msgs[i].addr, 648 msgs[i].buf, msgs[i].len); 649 650 if (ret != I2C_OK) { 651 num = -EIO; 652 break; 653 } 654 } 655 656 smu_v11_0_i2c_fini(i2c_adap); 657 return num; 658 } 659 660 static u32 smu_v11_0_i2c_func(struct i2c_adapter *adap) 661 { 662 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 663 } 664 665 666 static const struct i2c_algorithm smu_v11_0_i2c_algo = { 667 .master_xfer = smu_v11_0_i2c_xfer, 668 .functionality = smu_v11_0_i2c_func, 669 }; 670 671 int smu_v11_0_i2c_control_init(struct i2c_adapter *control) 672 { 673 struct amdgpu_device *adev = to_amdgpu_device(control); 674 int res; 675 676 control->owner = THIS_MODULE; 677 control->class = I2C_CLASS_SPD; 678 control->dev.parent = &adev->pdev->dev; 679 control->algo = &smu_v11_0_i2c_algo; 680 snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); 681 control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops; 682 683 res = i2c_add_adapter(control); 684 if (res) 685 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 686 687 return res; 688 } 689 690 void smu_v11_0_i2c_control_fini(struct i2c_adapter *control) 691 { 692 i2c_del_adapter(control); 693 } 694 695 /* 696 * Keep this for future unit test if bugs arise 697 */ 698 #if 0 699 #define I2C_TARGET_ADDR 0xA0 700 701 bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control) 702 { 703 704 uint32_t ret = I2C_OK; 705 uint8_t data[6] = {0xf, 0, 0xde, 0xad, 0xbe, 0xef}; 706 707 708 DRM_INFO("Begin"); 709 710 if (!smu_v11_0_i2c_bus_lock(control)) { 711 DRM_ERROR("Failed to lock the bus!."); 712 return false; 713 } 714 715 smu_v11_0_i2c_init(control); 716 717 /* Write 0xde to address 0x0000 on the EEPROM */ 718 ret = smu_v11_0_i2c_write_data(control, I2C_TARGET_ADDR, data, 6); 719 720 ret = smu_v11_0_i2c_read_data(control, I2C_TARGET_ADDR, data, 6); 721 722 smu_v11_0_i2c_fini(control); 723 724 smu_v11_0_i2c_bus_unlock(control); 725 726 727 DRM_INFO("End"); 728 return true; 729 } 730 #endif 731