1 // SPDX-License-Identifier: GPL-2.0 2 // TLV320ADCX140 Sound driver 3 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 4 5 #include <linux/module.h> 6 #include <linux/moduleparam.h> 7 #include <linux/init.h> 8 #include <linux/delay.h> 9 #include <linux/pm.h> 10 #include <linux/i2c.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/regulator/consumer.h> 13 #include <linux/acpi.h> 14 #include <linux/of.h> 15 #include <linux/of_gpio.h> 16 #include <linux/slab.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/initval.h> 22 #include <sound/tlv.h> 23 24 #include "tlv320adcx140.h" 25 26 struct adcx140_priv { 27 struct snd_soc_component *component; 28 struct regulator *supply_areg; 29 struct gpio_desc *gpio_reset; 30 struct regmap *regmap; 31 struct device *dev; 32 33 int micbias_vg; 34 35 unsigned int dai_fmt; 36 unsigned int tdm_delay; 37 unsigned int slot_width; 38 }; 39 40 static const struct reg_default adcx140_reg_defaults[] = { 41 { ADCX140_PAGE_SELECT, 0x00 }, 42 { ADCX140_SW_RESET, 0x00 }, 43 { ADCX140_SLEEP_CFG, 0x00 }, 44 { ADCX140_SHDN_CFG, 0x05 }, 45 { ADCX140_ASI_CFG0, 0x30 }, 46 { ADCX140_ASI_CFG1, 0x00 }, 47 { ADCX140_ASI_CFG2, 0x00 }, 48 { ADCX140_ASI_CH1, 0x00 }, 49 { ADCX140_ASI_CH2, 0x01 }, 50 { ADCX140_ASI_CH3, 0x02 }, 51 { ADCX140_ASI_CH4, 0x03 }, 52 { ADCX140_ASI_CH5, 0x04 }, 53 { ADCX140_ASI_CH6, 0x05 }, 54 { ADCX140_ASI_CH7, 0x06 }, 55 { ADCX140_ASI_CH8, 0x07 }, 56 { ADCX140_MST_CFG0, 0x02 }, 57 { ADCX140_MST_CFG1, 0x48 }, 58 { ADCX140_ASI_STS, 0xff }, 59 { ADCX140_CLK_SRC, 0x10 }, 60 { ADCX140_PDMCLK_CFG, 0x40 }, 61 { ADCX140_PDM_CFG, 0x00 }, 62 { ADCX140_GPIO_CFG0, 0x22 }, 63 { ADCX140_GPO_CFG1, 0x00 }, 64 { ADCX140_GPO_CFG2, 0x00 }, 65 { ADCX140_GPO_CFG3, 0x00 }, 66 { ADCX140_GPO_CFG4, 0x00 }, 67 { ADCX140_GPO_VAL, 0x00 }, 68 { ADCX140_GPIO_MON, 0x00 }, 69 { ADCX140_GPI_CFG0, 0x00 }, 70 { ADCX140_GPI_CFG1, 0x00 }, 71 { ADCX140_GPI_MON, 0x00 }, 72 { ADCX140_INT_CFG, 0x00 }, 73 { ADCX140_INT_MASK0, 0xff }, 74 { ADCX140_INT_LTCH0, 0x00 }, 75 { ADCX140_BIAS_CFG, 0x00 }, 76 { ADCX140_CH1_CFG0, 0x00 }, 77 { ADCX140_CH1_CFG1, 0x00 }, 78 { ADCX140_CH1_CFG2, 0xc9 }, 79 { ADCX140_CH1_CFG3, 0x80 }, 80 { ADCX140_CH1_CFG4, 0x00 }, 81 { ADCX140_CH2_CFG0, 0x00 }, 82 { ADCX140_CH2_CFG1, 0x00 }, 83 { ADCX140_CH2_CFG2, 0xc9 }, 84 { ADCX140_CH2_CFG3, 0x80 }, 85 { ADCX140_CH2_CFG4, 0x00 }, 86 { ADCX140_CH3_CFG0, 0x00 }, 87 { ADCX140_CH3_CFG1, 0x00 }, 88 { ADCX140_CH3_CFG2, 0xc9 }, 89 { ADCX140_CH3_CFG3, 0x80 }, 90 { ADCX140_CH3_CFG4, 0x00 }, 91 { ADCX140_CH4_CFG0, 0x00 }, 92 { ADCX140_CH4_CFG1, 0x00 }, 93 { ADCX140_CH4_CFG2, 0xc9 }, 94 { ADCX140_CH4_CFG3, 0x80 }, 95 { ADCX140_CH4_CFG4, 0x00 }, 96 { ADCX140_CH5_CFG2, 0xc9 }, 97 { ADCX140_CH5_CFG3, 0x80 }, 98 { ADCX140_CH5_CFG4, 0x00 }, 99 { ADCX140_CH6_CFG2, 0xc9 }, 100 { ADCX140_CH6_CFG3, 0x80 }, 101 { ADCX140_CH6_CFG4, 0x00 }, 102 { ADCX140_CH7_CFG2, 0xc9 }, 103 { ADCX140_CH7_CFG3, 0x80 }, 104 { ADCX140_CH7_CFG4, 0x00 }, 105 { ADCX140_CH8_CFG2, 0xc9 }, 106 { ADCX140_CH8_CFG3, 0x80 }, 107 { ADCX140_CH8_CFG4, 0x00 }, 108 { ADCX140_DSP_CFG0, 0x01 }, 109 { ADCX140_DSP_CFG1, 0x40 }, 110 { ADCX140_DRE_CFG0, 0x7b }, 111 { ADCX140_AGC_CFG0, 0xe7 }, 112 { ADCX140_IN_CH_EN, 0xf0 }, 113 { ADCX140_ASI_OUT_CH_EN, 0x00 }, 114 { ADCX140_PWR_CFG, 0x00 }, 115 { ADCX140_DEV_STS0, 0x00 }, 116 { ADCX140_DEV_STS1, 0x80 }, 117 }; 118 119 static const struct regmap_range_cfg adcx140_ranges[] = { 120 { 121 .range_min = 0, 122 .range_max = 12 * 128, 123 .selector_reg = ADCX140_PAGE_SELECT, 124 .selector_mask = 0xff, 125 .selector_shift = 0, 126 .window_start = 0, 127 .window_len = 128, 128 }, 129 }; 130 131 static bool adcx140_volatile(struct device *dev, unsigned int reg) 132 { 133 switch (reg) { 134 case ADCX140_SW_RESET: 135 case ADCX140_DEV_STS0: 136 case ADCX140_DEV_STS1: 137 case ADCX140_ASI_STS: 138 return true; 139 default: 140 return false; 141 } 142 } 143 144 static const struct regmap_config adcx140_i2c_regmap = { 145 .reg_bits = 8, 146 .val_bits = 8, 147 .reg_defaults = adcx140_reg_defaults, 148 .num_reg_defaults = ARRAY_SIZE(adcx140_reg_defaults), 149 .cache_type = REGCACHE_FLAT, 150 .ranges = adcx140_ranges, 151 .num_ranges = ARRAY_SIZE(adcx140_ranges), 152 .max_register = 12 * 128, 153 .volatile_reg = adcx140_volatile, 154 }; 155 156 /* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */ 157 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10000, 50, 0); 158 159 /* ADC gain. From 0 to 42 dB in 1 dB steps */ 160 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0); 161 162 /* DRE Level. From -12 dB to -66 dB in 1 dB steps */ 163 static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0); 164 /* DRE Max Gain. From 2 dB to 26 dB in 2 dB steps */ 165 static DECLARE_TLV_DB_SCALE(dre_gain_tlv, 200, 200, 0); 166 167 /* AGC Level. From -6 dB to -36 dB in 2 dB steps */ 168 static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0); 169 /* AGC Max Gain. From 3 dB to 42 dB in 3 dB steps */ 170 static DECLARE_TLV_DB_SCALE(agc_gain_tlv, 300, 300, 0); 171 172 static const char * const decimation_filter_text[] = { 173 "Linear Phase", "Low Latency", "Ultra-low Latency" 174 }; 175 176 static SOC_ENUM_SINGLE_DECL(decimation_filter_enum, ADCX140_DSP_CFG0, 4, 177 decimation_filter_text); 178 179 static const struct snd_kcontrol_new decimation_filter_controls[] = { 180 SOC_DAPM_ENUM("Decimation Filter", decimation_filter_enum), 181 }; 182 183 static const char * const resistor_text[] = { 184 "2.5 kOhm", "10 kOhm", "20 kOhm" 185 }; 186 187 static SOC_ENUM_SINGLE_DECL(in1_resistor_enum, ADCX140_CH1_CFG0, 2, 188 resistor_text); 189 static SOC_ENUM_SINGLE_DECL(in2_resistor_enum, ADCX140_CH2_CFG0, 2, 190 resistor_text); 191 static SOC_ENUM_SINGLE_DECL(in3_resistor_enum, ADCX140_CH3_CFG0, 2, 192 resistor_text); 193 static SOC_ENUM_SINGLE_DECL(in4_resistor_enum, ADCX140_CH4_CFG0, 2, 194 resistor_text); 195 196 static const struct snd_kcontrol_new in1_resistor_controls[] = { 197 SOC_DAPM_ENUM("CH1 Resistor Select", in1_resistor_enum), 198 }; 199 static const struct snd_kcontrol_new in2_resistor_controls[] = { 200 SOC_DAPM_ENUM("CH2 Resistor Select", in2_resistor_enum), 201 }; 202 static const struct snd_kcontrol_new in3_resistor_controls[] = { 203 SOC_DAPM_ENUM("CH3 Resistor Select", in3_resistor_enum), 204 }; 205 static const struct snd_kcontrol_new in4_resistor_controls[] = { 206 SOC_DAPM_ENUM("CH4 Resistor Select", in4_resistor_enum), 207 }; 208 209 /* Analog/Digital Selection */ 210 static const char *adcx140_mic_sel_text[] = {"Analog", "Line In", "Digital"}; 211 static const char *adcx140_analog_sel_text[] = {"Analog", "Line In"}; 212 213 static SOC_ENUM_SINGLE_DECL(adcx140_mic1p_enum, 214 ADCX140_CH1_CFG0, 5, 215 adcx140_mic_sel_text); 216 217 static const struct snd_kcontrol_new adcx140_dapm_mic1p_control = 218 SOC_DAPM_ENUM("MIC1P MUX", adcx140_mic1p_enum); 219 220 static SOC_ENUM_SINGLE_DECL(adcx140_mic1_analog_enum, 221 ADCX140_CH1_CFG0, 7, 222 adcx140_analog_sel_text); 223 224 static const struct snd_kcontrol_new adcx140_dapm_mic1_analog_control = 225 SOC_DAPM_ENUM("MIC1 Analog MUX", adcx140_mic1_analog_enum); 226 227 static SOC_ENUM_SINGLE_DECL(adcx140_mic1m_enum, 228 ADCX140_CH1_CFG0, 5, 229 adcx140_mic_sel_text); 230 231 static const struct snd_kcontrol_new adcx140_dapm_mic1m_control = 232 SOC_DAPM_ENUM("MIC1M MUX", adcx140_mic1m_enum); 233 234 static SOC_ENUM_SINGLE_DECL(adcx140_mic2p_enum, 235 ADCX140_CH2_CFG0, 5, 236 adcx140_mic_sel_text); 237 238 static const struct snd_kcontrol_new adcx140_dapm_mic2p_control = 239 SOC_DAPM_ENUM("MIC2P MUX", adcx140_mic2p_enum); 240 241 static SOC_ENUM_SINGLE_DECL(adcx140_mic2_analog_enum, 242 ADCX140_CH2_CFG0, 7, 243 adcx140_analog_sel_text); 244 245 static const struct snd_kcontrol_new adcx140_dapm_mic2_analog_control = 246 SOC_DAPM_ENUM("MIC2 Analog MUX", adcx140_mic2_analog_enum); 247 248 static SOC_ENUM_SINGLE_DECL(adcx140_mic2m_enum, 249 ADCX140_CH2_CFG0, 5, 250 adcx140_mic_sel_text); 251 252 static const struct snd_kcontrol_new adcx140_dapm_mic2m_control = 253 SOC_DAPM_ENUM("MIC2M MUX", adcx140_mic2m_enum); 254 255 static SOC_ENUM_SINGLE_DECL(adcx140_mic3p_enum, 256 ADCX140_CH3_CFG0, 5, 257 adcx140_mic_sel_text); 258 259 static const struct snd_kcontrol_new adcx140_dapm_mic3p_control = 260 SOC_DAPM_ENUM("MIC3P MUX", adcx140_mic3p_enum); 261 262 static SOC_ENUM_SINGLE_DECL(adcx140_mic3_analog_enum, 263 ADCX140_CH3_CFG0, 7, 264 adcx140_analog_sel_text); 265 266 static const struct snd_kcontrol_new adcx140_dapm_mic3_analog_control = 267 SOC_DAPM_ENUM("MIC3 Analog MUX", adcx140_mic3_analog_enum); 268 269 static SOC_ENUM_SINGLE_DECL(adcx140_mic3m_enum, 270 ADCX140_CH3_CFG0, 5, 271 adcx140_mic_sel_text); 272 273 static const struct snd_kcontrol_new adcx140_dapm_mic3m_control = 274 SOC_DAPM_ENUM("MIC3M MUX", adcx140_mic3m_enum); 275 276 static SOC_ENUM_SINGLE_DECL(adcx140_mic4p_enum, 277 ADCX140_CH4_CFG0, 5, 278 adcx140_mic_sel_text); 279 280 static const struct snd_kcontrol_new adcx140_dapm_mic4p_control = 281 SOC_DAPM_ENUM("MIC4P MUX", adcx140_mic4p_enum); 282 283 static SOC_ENUM_SINGLE_DECL(adcx140_mic4_analog_enum, 284 ADCX140_CH4_CFG0, 7, 285 adcx140_analog_sel_text); 286 287 static const struct snd_kcontrol_new adcx140_dapm_mic4_analog_control = 288 SOC_DAPM_ENUM("MIC4 Analog MUX", adcx140_mic4_analog_enum); 289 290 static SOC_ENUM_SINGLE_DECL(adcx140_mic4m_enum, 291 ADCX140_CH4_CFG0, 5, 292 adcx140_mic_sel_text); 293 294 static const struct snd_kcontrol_new adcx140_dapm_mic4m_control = 295 SOC_DAPM_ENUM("MIC4M MUX", adcx140_mic4m_enum); 296 297 static const struct snd_kcontrol_new adcx140_dapm_ch1_en_switch = 298 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0); 299 static const struct snd_kcontrol_new adcx140_dapm_ch2_en_switch = 300 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0); 301 static const struct snd_kcontrol_new adcx140_dapm_ch3_en_switch = 302 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0); 303 static const struct snd_kcontrol_new adcx140_dapm_ch4_en_switch = 304 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0); 305 306 static const struct snd_kcontrol_new adcx140_dapm_ch1_dre_en_switch = 307 SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0, 0, 1, 0); 308 static const struct snd_kcontrol_new adcx140_dapm_ch2_dre_en_switch = 309 SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0, 0, 1, 0); 310 static const struct snd_kcontrol_new adcx140_dapm_ch3_dre_en_switch = 311 SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0, 0, 1, 0); 312 static const struct snd_kcontrol_new adcx140_dapm_ch4_dre_en_switch = 313 SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0); 314 315 static const struct snd_kcontrol_new adcx140_dapm_dre_en_switch = 316 SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 0); 317 318 /* Output Mixer */ 319 static const struct snd_kcontrol_new adcx140_output_mixer_controls[] = { 320 SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0), 321 SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0), 322 SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0), 323 SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0), 324 }; 325 326 static const struct snd_soc_dapm_widget adcx140_dapm_widgets[] = { 327 /* Analog Differential Inputs */ 328 SND_SOC_DAPM_INPUT("MIC1P"), 329 SND_SOC_DAPM_INPUT("MIC1M"), 330 SND_SOC_DAPM_INPUT("MIC2P"), 331 SND_SOC_DAPM_INPUT("MIC2M"), 332 SND_SOC_DAPM_INPUT("MIC3P"), 333 SND_SOC_DAPM_INPUT("MIC3M"), 334 SND_SOC_DAPM_INPUT("MIC4P"), 335 SND_SOC_DAPM_INPUT("MIC4M"), 336 337 SND_SOC_DAPM_OUTPUT("CH1_OUT"), 338 SND_SOC_DAPM_OUTPUT("CH2_OUT"), 339 SND_SOC_DAPM_OUTPUT("CH3_OUT"), 340 SND_SOC_DAPM_OUTPUT("CH4_OUT"), 341 SND_SOC_DAPM_OUTPUT("CH5_OUT"), 342 SND_SOC_DAPM_OUTPUT("CH6_OUT"), 343 SND_SOC_DAPM_OUTPUT("CH7_OUT"), 344 SND_SOC_DAPM_OUTPUT("CH8_OUT"), 345 346 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0, 347 &adcx140_output_mixer_controls[0], 348 ARRAY_SIZE(adcx140_output_mixer_controls)), 349 350 /* Input Selection to MIC_PGA */ 351 SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM, 0, 0, 352 &adcx140_dapm_mic1p_control), 353 SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM, 0, 0, 354 &adcx140_dapm_mic2p_control), 355 SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM, 0, 0, 356 &adcx140_dapm_mic3p_control), 357 SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM, 0, 0, 358 &adcx140_dapm_mic4p_control), 359 360 /* Input Selection to MIC_PGA */ 361 SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0, 362 &adcx140_dapm_mic1_analog_control), 363 SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0, 364 &adcx140_dapm_mic2_analog_control), 365 SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0, 366 &adcx140_dapm_mic3_analog_control), 367 SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0, 368 &adcx140_dapm_mic4_analog_control), 369 370 SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM, 0, 0, 371 &adcx140_dapm_mic1m_control), 372 SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM, 0, 0, 373 &adcx140_dapm_mic2m_control), 374 SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM, 0, 0, 375 &adcx140_dapm_mic3m_control), 376 SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM, 0, 0, 377 &adcx140_dapm_mic4m_control), 378 379 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM, 0, 0, NULL, 0), 380 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM, 0, 0, NULL, 0), 381 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM, 0, 0, NULL, 0), 382 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM, 0, 0, NULL, 0), 383 384 SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0), 385 SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0), 386 SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0), 387 SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0), 388 389 SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM, 0, 0, 390 &adcx140_dapm_ch1_en_switch), 391 SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM, 0, 0, 392 &adcx140_dapm_ch2_en_switch), 393 SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM, 0, 0, 394 &adcx140_dapm_ch3_en_switch), 395 SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM, 0, 0, 396 &adcx140_dapm_ch4_en_switch), 397 398 SND_SOC_DAPM_SWITCH("DRE_ENABLE", SND_SOC_NOPM, 0, 0, 399 &adcx140_dapm_dre_en_switch), 400 401 SND_SOC_DAPM_SWITCH("CH1_DRE_EN", SND_SOC_NOPM, 0, 0, 402 &adcx140_dapm_ch1_dre_en_switch), 403 SND_SOC_DAPM_SWITCH("CH2_DRE_EN", SND_SOC_NOPM, 0, 0, 404 &adcx140_dapm_ch2_dre_en_switch), 405 SND_SOC_DAPM_SWITCH("CH3_DRE_EN", SND_SOC_NOPM, 0, 0, 406 &adcx140_dapm_ch3_dre_en_switch), 407 SND_SOC_DAPM_SWITCH("CH4_DRE_EN", SND_SOC_NOPM, 0, 0, 408 &adcx140_dapm_ch4_dre_en_switch), 409 410 SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 411 in1_resistor_controls), 412 SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 413 in2_resistor_controls), 414 SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 415 in3_resistor_controls), 416 SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 417 in4_resistor_controls), 418 419 SND_SOC_DAPM_MUX("Decimation Filter", SND_SOC_NOPM, 0, 0, 420 decimation_filter_controls), 421 }; 422 423 static const struct snd_soc_dapm_route adcx140_audio_map[] = { 424 /* Outputs */ 425 {"CH1_OUT", NULL, "Output Mixer"}, 426 {"CH2_OUT", NULL, "Output Mixer"}, 427 {"CH3_OUT", NULL, "Output Mixer"}, 428 {"CH4_OUT", NULL, "Output Mixer"}, 429 430 {"CH1_ASI_EN", "Switch", "CH1_ADC"}, 431 {"CH2_ASI_EN", "Switch", "CH2_ADC"}, 432 {"CH3_ASI_EN", "Switch", "CH3_ADC"}, 433 {"CH4_ASI_EN", "Switch", "CH4_ADC"}, 434 435 {"Decimation Filter", "Linear Phase", "DRE_ENABLE"}, 436 {"Decimation Filter", "Low Latency", "DRE_ENABLE"}, 437 {"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"}, 438 439 {"DRE_ENABLE", "Switch", "CH1_DRE_EN"}, 440 {"DRE_ENABLE", "Switch", "CH2_DRE_EN"}, 441 {"DRE_ENABLE", "Switch", "CH3_DRE_EN"}, 442 {"DRE_ENABLE", "Switch", "CH4_DRE_EN"}, 443 444 {"CH1_DRE_EN", "Switch", "CH1_ADC"}, 445 {"CH2_DRE_EN", "Switch", "CH2_ADC"}, 446 {"CH3_DRE_EN", "Switch", "CH3_ADC"}, 447 {"CH4_DRE_EN", "Switch", "CH4_ADC"}, 448 449 /* Mic input */ 450 {"CH1_ADC", NULL, "MIC_GAIN_CTL_CH1"}, 451 {"CH2_ADC", NULL, "MIC_GAIN_CTL_CH2"}, 452 {"CH3_ADC", NULL, "MIC_GAIN_CTL_CH3"}, 453 {"CH4_ADC", NULL, "MIC_GAIN_CTL_CH4"}, 454 455 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"}, 456 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"}, 457 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"}, 458 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"}, 459 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"}, 460 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"}, 461 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"}, 462 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"}, 463 464 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1P Input Mux"}, 465 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1P Input Mux"}, 466 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1P Input Mux"}, 467 468 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1M Input Mux"}, 469 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1M Input Mux"}, 470 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1M Input Mux"}, 471 472 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2P Input Mux"}, 473 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2P Input Mux"}, 474 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2P Input Mux"}, 475 476 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2M Input Mux"}, 477 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2M Input Mux"}, 478 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2M Input Mux"}, 479 480 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3P Input Mux"}, 481 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3P Input Mux"}, 482 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3P Input Mux"}, 483 484 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3M Input Mux"}, 485 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3M Input Mux"}, 486 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3M Input Mux"}, 487 488 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4P Input Mux"}, 489 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4P Input Mux"}, 490 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4P Input Mux"}, 491 492 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4M Input Mux"}, 493 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4M Input Mux"}, 494 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4M Input Mux"}, 495 496 {"MIC1 Analog Mux", "Line In", "MIC1P"}, 497 {"MIC2 Analog Mux", "Line In", "MIC2P"}, 498 {"MIC3 Analog Mux", "Line In", "MIC3P"}, 499 {"MIC4 Analog Mux", "Line In", "MIC4P"}, 500 501 {"MIC1P Input Mux", "Analog", "MIC1P"}, 502 {"MIC1M Input Mux", "Analog", "MIC1M"}, 503 {"MIC2P Input Mux", "Analog", "MIC2P"}, 504 {"MIC2M Input Mux", "Analog", "MIC2M"}, 505 {"MIC3P Input Mux", "Analog", "MIC3P"}, 506 {"MIC3M Input Mux", "Analog", "MIC3M"}, 507 {"MIC4P Input Mux", "Analog", "MIC4P"}, 508 {"MIC4M Input Mux", "Analog", "MIC4M"}, 509 }; 510 511 static const struct snd_kcontrol_new adcx140_snd_controls[] = { 512 SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0, 513 adc_tlv), 514 SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH1_CFG2, 2, 42, 0, 515 adc_tlv), 516 SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH1_CFG3, 2, 42, 0, 517 adc_tlv), 518 SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH1_CFG4, 2, 42, 0, 519 adc_tlv), 520 521 SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0, 522 dre_thresh_tlv), 523 SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0, 0, 12, 0, 524 dre_gain_tlv), 525 526 SOC_SINGLE_TLV("AGC Threshold", ADCX140_AGC_CFG0, 4, 15, 0, 527 agc_thresh_tlv), 528 SOC_SINGLE_TLV("AGC Max Gain", ADCX140_AGC_CFG0, 0, 13, 0, 529 agc_gain_tlv), 530 531 SOC_SINGLE_TLV("Digital CH1 Out Volume", ADCX140_CH1_CFG2, 532 0, 0xff, 0, dig_vol_tlv), 533 SOC_SINGLE_TLV("Digital CH2 Out Volume", ADCX140_CH2_CFG2, 534 0, 0xff, 0, dig_vol_tlv), 535 SOC_SINGLE_TLV("Digital CH3 Out Volume", ADCX140_CH3_CFG2, 536 0, 0xff, 0, dig_vol_tlv), 537 SOC_SINGLE_TLV("Digital CH4 Out Volume", ADCX140_CH4_CFG2, 538 0, 0xff, 0, dig_vol_tlv), 539 SOC_SINGLE_TLV("Digital CH5 Out Volume", ADCX140_CH5_CFG2, 540 0, 0xff, 0, dig_vol_tlv), 541 SOC_SINGLE_TLV("Digital CH6 Out Volume", ADCX140_CH6_CFG2, 542 0, 0xff, 0, dig_vol_tlv), 543 SOC_SINGLE_TLV("Digital CH7 Out Volume", ADCX140_CH7_CFG2, 544 0, 0xff, 0, dig_vol_tlv), 545 SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2, 546 0, 0xff, 0, dig_vol_tlv), 547 }; 548 549 static int adcx140_reset(struct adcx140_priv *adcx140) 550 { 551 int ret = 0; 552 553 if (adcx140->gpio_reset) { 554 gpiod_direction_output(adcx140->gpio_reset, 0); 555 /* 8.4.1: wait for hw shutdown (25ms) + >= 1ms */ 556 usleep_range(30000, 100000); 557 gpiod_direction_output(adcx140->gpio_reset, 1); 558 } else { 559 ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET, 560 ADCX140_RESET); 561 } 562 563 /* 8.4.2: wait >= 10 ms after entering sleep mode. */ 564 usleep_range(10000, 100000); 565 566 return 0; 567 } 568 569 static int adcx140_hw_params(struct snd_pcm_substream *substream, 570 struct snd_pcm_hw_params *params, 571 struct snd_soc_dai *dai) 572 { 573 struct snd_soc_component *component = dai->component; 574 u8 data = 0; 575 576 switch (params_width(params)) { 577 case 16: 578 data = ADCX140_16_BIT_WORD; 579 break; 580 case 20: 581 data = ADCX140_20_BIT_WORD; 582 break; 583 case 24: 584 data = ADCX140_24_BIT_WORD; 585 break; 586 case 32: 587 data = ADCX140_32_BIT_WORD; 588 break; 589 default: 590 dev_err(component->dev, "%s: Unsupported width %d\n", 591 __func__, params_width(params)); 592 return -EINVAL; 593 } 594 595 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0, 596 ADCX140_WORD_LEN_MSK, data); 597 598 return 0; 599 } 600 601 static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai, 602 unsigned int fmt) 603 { 604 struct snd_soc_component *component = codec_dai->component; 605 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 606 u8 iface_reg1 = 0; 607 u8 iface_reg2 = 0; 608 609 /* set master/slave audio interface */ 610 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 611 case SND_SOC_DAIFMT_CBM_CFM: 612 iface_reg2 |= ADCX140_BCLK_FSYNC_MASTER; 613 break; 614 case SND_SOC_DAIFMT_CBS_CFS: 615 break; 616 case SND_SOC_DAIFMT_CBS_CFM: 617 case SND_SOC_DAIFMT_CBM_CFS: 618 default: 619 dev_err(component->dev, "Invalid DAI master/slave interface\n"); 620 return -EINVAL; 621 } 622 623 /* signal polarity */ 624 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 625 case SND_SOC_DAIFMT_NB_IF: 626 iface_reg1 |= ADCX140_FSYNCINV_BIT; 627 break; 628 case SND_SOC_DAIFMT_IB_IF: 629 iface_reg1 |= ADCX140_BCLKINV_BIT | ADCX140_FSYNCINV_BIT; 630 break; 631 case SND_SOC_DAIFMT_IB_NF: 632 iface_reg1 |= ADCX140_BCLKINV_BIT; 633 break; 634 case SND_SOC_DAIFMT_NB_NF: 635 break; 636 default: 637 dev_err(component->dev, "Invalid DAI clock signal polarity\n"); 638 return -EINVAL; 639 } 640 641 /* interface format */ 642 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 643 case SND_SOC_DAIFMT_I2S: 644 iface_reg1 |= ADCX140_I2S_MODE_BIT; 645 break; 646 case SND_SOC_DAIFMT_LEFT_J: 647 iface_reg1 |= ADCX140_LEFT_JUST_BIT; 648 break; 649 case SND_SOC_DAIFMT_DSP_A: 650 case SND_SOC_DAIFMT_DSP_B: 651 break; 652 default: 653 dev_err(component->dev, "Invalid DAI interface format\n"); 654 return -EINVAL; 655 } 656 657 adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 658 659 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0, 660 ADCX140_FSYNCINV_BIT | 661 ADCX140_BCLKINV_BIT | 662 ADCX140_ASI_FORMAT_MSK, 663 iface_reg1); 664 snd_soc_component_update_bits(component, ADCX140_MST_CFG0, 665 ADCX140_BCLK_FSYNC_MASTER, iface_reg2); 666 667 return 0; 668 } 669 670 static int adcx140_set_dai_tdm_slot(struct snd_soc_dai *codec_dai, 671 unsigned int tx_mask, unsigned int rx_mask, 672 int slots, int slot_width) 673 { 674 struct snd_soc_component *component = codec_dai->component; 675 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 676 unsigned int lsb; 677 678 if (tx_mask != rx_mask) { 679 dev_err(component->dev, "tx and rx masks must be symmetric\n"); 680 return -EINVAL; 681 } 682 683 /* TDM based on DSP mode requires slots to be adjacent */ 684 lsb = __ffs(tx_mask); 685 if ((lsb + 1) != __fls(tx_mask)) { 686 dev_err(component->dev, "Invalid mask, slots must be adjacent\n"); 687 return -EINVAL; 688 } 689 690 switch (slot_width) { 691 case 16: 692 case 20: 693 case 24: 694 case 32: 695 break; 696 default: 697 dev_err(component->dev, "Unsupported slot width %d\n", slot_width); 698 return -EINVAL; 699 } 700 701 adcx140->tdm_delay = lsb; 702 adcx140->slot_width = slot_width; 703 704 return 0; 705 } 706 707 static int adcx140_prepare(struct snd_pcm_substream *substream, 708 struct snd_soc_dai *dai) 709 { 710 struct snd_soc_component *component = dai->component; 711 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 712 int offset = 0; 713 int width = adcx140->slot_width; 714 715 if (!width) 716 width = substream->runtime->sample_bits; 717 718 /* TDM slot selection only valid in DSP_A/_B mode */ 719 if (adcx140->dai_fmt == SND_SOC_DAIFMT_DSP_A) 720 offset += (adcx140->tdm_delay * width + 1); 721 else if (adcx140->dai_fmt == SND_SOC_DAIFMT_DSP_B) 722 offset += adcx140->tdm_delay * width; 723 724 /* Configure data offset */ 725 snd_soc_component_update_bits(component, ADCX140_ASI_CFG1, 726 ADCX140_TX_OFFSET_MASK, offset); 727 728 return 0; 729 } 730 731 static const struct snd_soc_dai_ops adcx140_dai_ops = { 732 .hw_params = adcx140_hw_params, 733 .set_fmt = adcx140_set_dai_fmt, 734 .prepare = adcx140_prepare, 735 .set_tdm_slot = adcx140_set_dai_tdm_slot, 736 }; 737 738 static int adcx140_codec_probe(struct snd_soc_component *component) 739 { 740 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 741 int sleep_cfg_val = ADCX140_WAKE_DEV; 742 u8 bias_source; 743 u8 vref_source; 744 int ret; 745 746 ret = device_property_read_u8(adcx140->dev, "ti,mic-bias-source", 747 &bias_source); 748 if (ret) 749 bias_source = ADCX140_MIC_BIAS_VAL_VREF; 750 751 if (bias_source < ADCX140_MIC_BIAS_VAL_VREF || 752 bias_source > ADCX140_MIC_BIAS_VAL_AVDD) { 753 dev_err(adcx140->dev, "Mic Bias source value is invalid\n"); 754 return -EINVAL; 755 } 756 757 ret = device_property_read_u8(adcx140->dev, "ti,vref-source", 758 &vref_source); 759 if (ret) 760 vref_source = ADCX140_MIC_BIAS_VREF_275V; 761 762 if (vref_source < ADCX140_MIC_BIAS_VREF_275V || 763 vref_source > ADCX140_MIC_BIAS_VREF_1375V) { 764 dev_err(adcx140->dev, "Mic Bias source value is invalid\n"); 765 return -EINVAL; 766 } 767 768 bias_source |= vref_source; 769 770 ret = adcx140_reset(adcx140); 771 if (ret) 772 goto out; 773 774 if(adcx140->supply_areg == NULL) 775 sleep_cfg_val |= ADCX140_AREG_INTERNAL; 776 777 ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val); 778 if (ret) { 779 dev_err(adcx140->dev, "setting sleep config failed %d\n", ret); 780 goto out; 781 } 782 783 /* 8.4.3: Wait >= 1ms after entering active mode. */ 784 usleep_range(1000, 100000); 785 786 ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG, 787 ADCX140_MIC_BIAS_VAL_MSK | 788 ADCX140_MIC_BIAS_VREF_MSK, bias_source); 789 if (ret) 790 dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret); 791 out: 792 return ret; 793 } 794 795 static int adcx140_set_bias_level(struct snd_soc_component *component, 796 enum snd_soc_bias_level level) 797 { 798 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 799 int pwr_cfg = 0; 800 801 switch (level) { 802 case SND_SOC_BIAS_ON: 803 case SND_SOC_BIAS_PREPARE: 804 case SND_SOC_BIAS_STANDBY: 805 pwr_cfg = ADCX140_PWR_CFG_BIAS_PDZ | ADCX140_PWR_CFG_PLL_PDZ | 806 ADCX140_PWR_CFG_ADC_PDZ; 807 break; 808 case SND_SOC_BIAS_OFF: 809 pwr_cfg = 0x0; 810 break; 811 } 812 813 return regmap_write(adcx140->regmap, ADCX140_PWR_CFG, pwr_cfg); 814 } 815 816 static const struct snd_soc_component_driver soc_codec_driver_adcx140 = { 817 .probe = adcx140_codec_probe, 818 .set_bias_level = adcx140_set_bias_level, 819 .controls = adcx140_snd_controls, 820 .num_controls = ARRAY_SIZE(adcx140_snd_controls), 821 .dapm_widgets = adcx140_dapm_widgets, 822 .num_dapm_widgets = ARRAY_SIZE(adcx140_dapm_widgets), 823 .dapm_routes = adcx140_audio_map, 824 .num_dapm_routes = ARRAY_SIZE(adcx140_audio_map), 825 .suspend_bias_off = 1, 826 .idle_bias_on = 0, 827 .use_pmdown_time = 1, 828 .endianness = 1, 829 .non_legacy_dai_naming = 1, 830 }; 831 832 static struct snd_soc_dai_driver adcx140_dai_driver[] = { 833 { 834 .name = "tlv320adcx140-codec", 835 .capture = { 836 .stream_name = "Capture", 837 .channels_min = 2, 838 .channels_max = ADCX140_MAX_CHANNELS, 839 .rates = ADCX140_RATES, 840 .formats = ADCX140_FORMATS, 841 }, 842 .ops = &adcx140_dai_ops, 843 .symmetric_rates = 1, 844 } 845 }; 846 847 static const struct of_device_id tlv320adcx140_of_match[] = { 848 { .compatible = "ti,tlv320adc3140" }, 849 { .compatible = "ti,tlv320adc5140" }, 850 { .compatible = "ti,tlv320adc6140" }, 851 {}, 852 }; 853 MODULE_DEVICE_TABLE(of, tlv320adcx140_of_match); 854 855 static int adcx140_i2c_probe(struct i2c_client *i2c, 856 const struct i2c_device_id *id) 857 { 858 struct adcx140_priv *adcx140; 859 int ret; 860 861 adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL); 862 if (!adcx140) 863 return -ENOMEM; 864 865 adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev, 866 "reset", GPIOD_OUT_LOW); 867 if (IS_ERR(adcx140->gpio_reset)) 868 dev_info(&i2c->dev, "Reset GPIO not defined\n"); 869 870 adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev, 871 "areg"); 872 if (IS_ERR(adcx140->supply_areg)) { 873 if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER) 874 return -EPROBE_DEFER; 875 else 876 adcx140->supply_areg = NULL; 877 } else { 878 ret = regulator_enable(adcx140->supply_areg); 879 if (ret) { 880 dev_err(adcx140->dev, "Failed to enable areg\n"); 881 return ret; 882 } 883 } 884 885 adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap); 886 if (IS_ERR(adcx140->regmap)) { 887 ret = PTR_ERR(adcx140->regmap); 888 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 889 ret); 890 return ret; 891 } 892 adcx140->dev = &i2c->dev; 893 i2c_set_clientdata(i2c, adcx140); 894 895 return devm_snd_soc_register_component(&i2c->dev, 896 &soc_codec_driver_adcx140, 897 adcx140_dai_driver, 1); 898 } 899 900 static const struct i2c_device_id adcx140_i2c_id[] = { 901 { "tlv320adc3140", 0 }, 902 { "tlv320adc5140", 1 }, 903 { "tlv320adc6140", 2 }, 904 {} 905 }; 906 MODULE_DEVICE_TABLE(i2c, adcx140_i2c_id); 907 908 static struct i2c_driver adcx140_i2c_driver = { 909 .driver = { 910 .name = "tlv320adcx140-codec", 911 .of_match_table = of_match_ptr(tlv320adcx140_of_match), 912 }, 913 .probe = adcx140_i2c_probe, 914 .id_table = adcx140_i2c_id, 915 }; 916 module_i2c_driver(adcx140_i2c_driver); 917 918 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>"); 919 MODULE_DESCRIPTION("ASoC TLV320ADCX140 CODEC Driver"); 920 MODULE_LICENSE("GPL v2"); 921