1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV APIC functions (note: not an Intel compatible APIC) 7 * 8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 9 */ 10 #include <linux/crash_dump.h> 11 #include <linux/cpuhotplug.h> 12 #include <linux/cpumask.h> 13 #include <linux/proc_fs.h> 14 #include <linux/memory.h> 15 #include <linux/export.h> 16 #include <linux/pci.h> 17 #include <linux/acpi.h> 18 #include <linux/efi.h> 19 20 #include <asm/e820/api.h> 21 #include <asm/uv/uv_mmrs.h> 22 #include <asm/uv/uv_hub.h> 23 #include <asm/uv/bios.h> 24 #include <asm/uv/uv.h> 25 #include <asm/apic.h> 26 27 static DEFINE_PER_CPU(int, x2apic_extra_bits); 28 29 static enum uv_system_type uv_system_type; 30 static int uv_hubbed_system; 31 static int uv_hubless_system; 32 static u64 gru_start_paddr, gru_end_paddr; 33 static union uvh_apicid uvh_apicid; 34 35 /* Unpack OEM/TABLE ID's to be NULL terminated strings */ 36 static u8 oem_id[ACPI_OEM_ID_SIZE + 1]; 37 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; 38 39 /* Information derived from CPUID: */ 40 static struct { 41 unsigned int apicid_shift; 42 unsigned int apicid_mask; 43 unsigned int socketid_shift; /* aka pnode_shift for UV1/2/3 */ 44 unsigned int pnode_mask; 45 unsigned int gpa_shift; 46 unsigned int gnode_shift; 47 } uv_cpuid; 48 49 static int uv_min_hub_revision_id; 50 51 unsigned int uv_apicid_hibits; 52 53 static struct apic apic_x2apic_uv_x; 54 static struct uv_hub_info_s uv_hub_info_node0; 55 56 /* Set this to use hardware error handler instead of kernel panic: */ 57 static int disable_uv_undefined_panic = 1; 58 59 unsigned long uv_undefined(char *str) 60 { 61 if (likely(!disable_uv_undefined_panic)) 62 panic("UV: error: undefined MMR: %s\n", str); 63 else 64 pr_crit("UV: error: undefined MMR: %s\n", str); 65 66 /* Cause a machine fault: */ 67 return ~0ul; 68 } 69 EXPORT_SYMBOL(uv_undefined); 70 71 static unsigned long __init uv_early_read_mmr(unsigned long addr) 72 { 73 unsigned long val, *mmr; 74 75 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); 76 val = *mmr; 77 early_iounmap(mmr, sizeof(*mmr)); 78 79 return val; 80 } 81 82 static inline bool is_GRU_range(u64 start, u64 end) 83 { 84 return start >= gru_start_paddr && end <= gru_end_paddr; 85 } 86 87 static bool uv_is_untracked_pat_range(u64 start, u64 end) 88 { 89 return is_ISA_range(start, end) || is_GRU_range(start, end); 90 } 91 92 static int __init early_get_pnodeid(void) 93 { 94 union uvh_node_id_u node_id; 95 union uvh_rh_gam_config_mmr_u m_n_config; 96 int pnode; 97 98 /* Currently, all blades have same revision number */ 99 node_id.v = uv_early_read_mmr(UVH_NODE_ID); 100 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR); 101 uv_min_hub_revision_id = node_id.s.revision; 102 103 switch (node_id.s.part_number) { 104 case UV2_HUB_PART_NUMBER: 105 case UV2_HUB_PART_NUMBER_X: 106 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; 107 break; 108 case UV3_HUB_PART_NUMBER: 109 case UV3_HUB_PART_NUMBER_X: 110 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE; 111 break; 112 113 /* Update: UV4A has only a modified revision to indicate HUB fixes */ 114 case UV4_HUB_PART_NUMBER: 115 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1; 116 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */ 117 break; 118 } 119 120 uv_hub_info->hub_revision = uv_min_hub_revision_id; 121 uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1; 122 pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask; 123 uv_cpuid.gpa_shift = 46; /* Default unless changed */ 124 125 pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n", 126 node_id.s.revision, node_id.s.part_number, node_id.s.node_id, 127 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode); 128 return pnode; 129 } 130 131 static void __init uv_tsc_check_sync(void) 132 { 133 u64 mmr; 134 int sync_state; 135 int mmr_shift; 136 char *state; 137 bool valid; 138 139 /* Accommodate different UV arch BIOSes */ 140 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR); 141 mmr_shift = 142 is_uv1_hub() ? 0 : 143 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; 144 if (mmr_shift) 145 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK; 146 else 147 sync_state = 0; 148 149 switch (sync_state) { 150 case UVH_TSC_SYNC_VALID: 151 state = "in sync"; 152 valid = true; 153 break; 154 155 case UVH_TSC_SYNC_INVALID: 156 state = "unstable"; 157 valid = false; 158 break; 159 default: 160 state = "unknown: assuming valid"; 161 valid = true; 162 break; 163 } 164 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state); 165 166 /* Mark flag that says TSC != 0 is valid for socket 0 */ 167 if (valid) 168 mark_tsc_async_resets("UV BIOS"); 169 else 170 mark_tsc_unstable("UV BIOS"); 171 } 172 173 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */ 174 175 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */ 176 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */ 177 #define SMT_TYPE 1 178 #define CORE_TYPE 2 179 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff) 180 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) 181 182 static void set_x2apic_bits(void) 183 { 184 unsigned int eax, ebx, ecx, edx, sub_index; 185 unsigned int sid_shift; 186 187 cpuid(0, &eax, &ebx, &ecx, &edx); 188 if (eax < 0xb) { 189 pr_info("UV: CPU does not have CPUID.11\n"); 190 return; 191 } 192 193 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx); 194 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) { 195 pr_info("UV: CPUID.11 not implemented\n"); 196 return; 197 } 198 199 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 200 sub_index = 1; 201 do { 202 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx); 203 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) { 204 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 205 break; 206 } 207 sub_index++; 208 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE); 209 210 uv_cpuid.apicid_shift = 0; 211 uv_cpuid.apicid_mask = (~(-1 << sid_shift)); 212 uv_cpuid.socketid_shift = sid_shift; 213 } 214 215 static void __init early_get_apic_socketid_shift(void) 216 { 217 if (is_uv2_hub() || is_uv3_hub()) 218 uvh_apicid.v = uv_early_read_mmr(UVH_APICID); 219 220 set_x2apic_bits(); 221 222 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask); 223 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask); 224 } 225 226 /* 227 * Add an extra bit as dictated by bios to the destination apicid of 228 * interrupts potentially passing through the UV HUB. This prevents 229 * a deadlock between interrupts and IO port operations. 230 */ 231 static void __init uv_set_apicid_hibit(void) 232 { 233 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask; 234 235 if (is_uv1_hub()) { 236 apicid_mask.v = uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK); 237 uv_apicid_hibits = apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK; 238 } 239 } 240 241 static void __init uv_stringify(int len, char *to, char *from) 242 { 243 /* Relies on 'to' being NULL chars so result will be NULL terminated */ 244 strncpy(to, from, len-1); 245 } 246 247 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id) 248 { 249 int pnodeid; 250 int uv_apic; 251 252 uv_stringify(sizeof(oem_id), oem_id, _oem_id); 253 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id); 254 255 if (strncmp(oem_id, "SGI", 3) != 0) { 256 if (strncmp(oem_id, "NSGI", 4) != 0) 257 return 0; 258 259 /* UV4 Hubless, CH, (0x11:UV4+Any) */ 260 if (strncmp(oem_id, "NSGI4", 5) == 0) 261 uv_hubless_system = 0x11; 262 263 /* UV3 Hubless, UV300/MC990X w/o hub (0x9:UV3+Any) */ 264 else 265 uv_hubless_system = 0x9; 266 267 pr_info("UV: OEM IDs %s/%s, HUBLESS(0x%x)\n", 268 oem_id, oem_table_id, uv_hubless_system); 269 270 return 0; 271 } 272 273 if (numa_off) { 274 pr_err("UV: NUMA is off, disabling UV support\n"); 275 return 0; 276 } 277 278 /* Set up early hub type field in uv_hub_info for Node 0 */ 279 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0; 280 281 /* 282 * Determine UV arch type. 283 * SGI: UV100/1000 284 * SGI2: UV2000/3000 285 * SGI3: UV300 (truncated to 4 chars because of different varieties) 286 * SGI4: UV400 (truncated to 4 chars because of different varieties) 287 */ 288 uv_hub_info->hub_revision = 289 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE : 290 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE : 291 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE : 292 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0; 293 294 if (uv_hub_info->hub_revision == 0) 295 goto badbios; 296 297 switch (uv_hub_info->hub_revision) { 298 case UV4_HUB_REVISION_BASE: 299 uv_hubbed_system = 0x11; 300 break; 301 302 case UV3_HUB_REVISION_BASE: 303 uv_hubbed_system = 0x9; 304 break; 305 306 case UV2_HUB_REVISION_BASE: 307 uv_hubbed_system = 0x5; 308 break; 309 310 case UV1_HUB_REVISION_BASE: 311 uv_hubbed_system = 0x3; 312 break; 313 } 314 315 pnodeid = early_get_pnodeid(); 316 early_get_apic_socketid_shift(); 317 318 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; 319 x86_platform.nmi_init = uv_nmi_init; 320 321 if (!strcmp(oem_table_id, "UVX")) { 322 /* This is the most common hardware variant: */ 323 uv_system_type = UV_X2APIC; 324 uv_apic = 0; 325 326 } else if (!strcmp(oem_table_id, "UVH")) { 327 /* Only UV1 systems: */ 328 uv_system_type = UV_NON_UNIQUE_APIC; 329 x86_platform.legacy.warm_reset = 0; 330 __this_cpu_write(x2apic_extra_bits, pnodeid << uvh_apicid.s.pnode_shift); 331 uv_set_apicid_hibit(); 332 uv_apic = 1; 333 334 } else if (!strcmp(oem_table_id, "UVL")) { 335 /* Only used for very small systems: */ 336 uv_system_type = UV_LEGACY_APIC; 337 uv_apic = 0; 338 339 } else { 340 goto badbios; 341 } 342 343 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", oem_id, oem_table_id, uv_system_type, uv_min_hub_revision_id, uv_apic); 344 uv_tsc_check_sync(); 345 346 return uv_apic; 347 348 badbios: 349 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id); 350 pr_err("Current BIOS not supported, update kernel and/or BIOS\n"); 351 BUG(); 352 } 353 354 enum uv_system_type get_uv_system_type(void) 355 { 356 return uv_system_type; 357 } 358 359 int is_uv_system(void) 360 { 361 return uv_system_type != UV_NONE; 362 } 363 EXPORT_SYMBOL_GPL(is_uv_system); 364 365 int is_uv_hubbed(int uvtype) 366 { 367 return (uv_hubbed_system & uvtype); 368 } 369 EXPORT_SYMBOL_GPL(is_uv_hubbed); 370 371 static int is_uv_hubless(int uvtype) 372 { 373 return (uv_hubless_system & uvtype); 374 } 375 376 void **__uv_hub_info_list; 377 EXPORT_SYMBOL_GPL(__uv_hub_info_list); 378 379 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 380 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info); 381 382 short uv_possible_blades; 383 EXPORT_SYMBOL_GPL(uv_possible_blades); 384 385 unsigned long sn_rtc_cycles_per_second; 386 EXPORT_SYMBOL(sn_rtc_cycles_per_second); 387 388 /* The following values are used for the per node hub info struct */ 389 static __initdata unsigned short *_node_to_pnode; 390 static __initdata unsigned short _min_socket, _max_socket; 391 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len; 392 static __initdata struct uv_gam_range_entry *uv_gre_table; 393 static __initdata struct uv_gam_parameters *uv_gp_table; 394 static __initdata unsigned short *_socket_to_node; 395 static __initdata unsigned short *_socket_to_pnode; 396 static __initdata unsigned short *_pnode_to_socket; 397 398 static __initdata struct uv_gam_range_s *_gr_table; 399 400 #define SOCK_EMPTY ((unsigned short)~0) 401 402 /* Default UV memory block size is 2GB */ 403 static unsigned long mem_block_size __initdata = (2UL << 30); 404 405 /* Kernel parameter to specify UV mem block size */ 406 static int __init parse_mem_block_size(char *ptr) 407 { 408 unsigned long size = memparse(ptr, NULL); 409 410 /* Size will be rounded down by set_block_size() below */ 411 mem_block_size = size; 412 return 0; 413 } 414 early_param("uv_memblksize", parse_mem_block_size); 415 416 static __init int adj_blksize(u32 lgre) 417 { 418 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT; 419 unsigned long size; 420 421 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1) 422 if (IS_ALIGNED(base, size)) 423 break; 424 425 if (size >= mem_block_size) 426 return 0; 427 428 mem_block_size = size; 429 return 1; 430 } 431 432 static __init void set_block_size(void) 433 { 434 unsigned int order = ffs(mem_block_size); 435 436 if (order) { 437 /* adjust for ffs return of 1..64 */ 438 set_memory_block_size_order(order - 1); 439 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size); 440 } else { 441 /* bad or zero value, default to 1UL << 31 (2GB) */ 442 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size); 443 set_memory_block_size_order(31); 444 } 445 } 446 447 /* Build GAM range lookup table: */ 448 static __init void build_uv_gr_table(void) 449 { 450 struct uv_gam_range_entry *gre = uv_gre_table; 451 struct uv_gam_range_s *grt; 452 unsigned long last_limit = 0, ram_limit = 0; 453 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1; 454 455 if (!gre) 456 return; 457 458 bytes = _gr_table_len * sizeof(struct uv_gam_range_s); 459 grt = kzalloc(bytes, GFP_KERNEL); 460 BUG_ON(!grt); 461 _gr_table = grt; 462 463 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 464 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) { 465 if (!ram_limit) { 466 /* Mark hole between RAM/non-RAM: */ 467 ram_limit = last_limit; 468 last_limit = gre->limit; 469 lsid++; 470 continue; 471 } 472 last_limit = gre->limit; 473 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table)); 474 continue; 475 } 476 if (_max_socket < gre->sockid) { 477 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table)); 478 continue; 479 } 480 sid = gre->sockid - _min_socket; 481 if (lsid < sid) { 482 /* New range: */ 483 grt = &_gr_table[indx]; 484 grt->base = lindx; 485 grt->nasid = gre->nasid; 486 grt->limit = last_limit = gre->limit; 487 lsid = sid; 488 lindx = indx++; 489 continue; 490 } 491 /* Update range: */ 492 if (lsid == sid && !ram_limit) { 493 /* .. if contiguous: */ 494 if (grt->limit == last_limit) { 495 grt->limit = last_limit = gre->limit; 496 continue; 497 } 498 } 499 /* Non-contiguous RAM range: */ 500 if (!ram_limit) { 501 grt++; 502 grt->base = lindx; 503 grt->nasid = gre->nasid; 504 grt->limit = last_limit = gre->limit; 505 continue; 506 } 507 /* Non-contiguous/non-RAM: */ 508 grt++; 509 /* base is this entry */ 510 grt->base = grt - _gr_table; 511 grt->nasid = gre->nasid; 512 grt->limit = last_limit = gre->limit; 513 lsid++; 514 } 515 516 /* Shorten table if possible */ 517 grt++; 518 i = grt - _gr_table; 519 if (i < _gr_table_len) { 520 void *ret; 521 522 bytes = i * sizeof(struct uv_gam_range_s); 523 ret = krealloc(_gr_table, bytes, GFP_KERNEL); 524 if (ret) { 525 _gr_table = ret; 526 _gr_table_len = i; 527 } 528 } 529 530 /* Display resultant GAM range table: */ 531 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) { 532 unsigned long start, end; 533 int gb = grt->base; 534 535 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT; 536 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT; 537 538 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb); 539 } 540 } 541 542 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) 543 { 544 unsigned long val; 545 int pnode; 546 547 pnode = uv_apicid_to_pnode(phys_apicid); 548 phys_apicid |= uv_apicid_hibits; 549 550 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 551 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 552 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 553 APIC_DM_INIT; 554 555 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 556 557 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 558 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 559 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 560 APIC_DM_STARTUP; 561 562 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 563 564 return 0; 565 } 566 567 static void uv_send_IPI_one(int cpu, int vector) 568 { 569 unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu); 570 int pnode = uv_apicid_to_pnode(apicid); 571 unsigned long dmode, val; 572 573 if (vector == NMI_VECTOR) 574 dmode = dest_NMI; 575 else 576 dmode = dest_Fixed; 577 578 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 579 ((apicid | uv_apicid_hibits) << UVH_IPI_INT_APIC_ID_SHFT) | 580 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | 581 (vector << UVH_IPI_INT_VECTOR_SHFT); 582 583 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 584 } 585 586 static void uv_send_IPI_mask(const struct cpumask *mask, int vector) 587 { 588 unsigned int cpu; 589 590 for_each_cpu(cpu, mask) 591 uv_send_IPI_one(cpu, vector); 592 } 593 594 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 595 { 596 unsigned int this_cpu = smp_processor_id(); 597 unsigned int cpu; 598 599 for_each_cpu(cpu, mask) { 600 if (cpu != this_cpu) 601 uv_send_IPI_one(cpu, vector); 602 } 603 } 604 605 static void uv_send_IPI_allbutself(int vector) 606 { 607 unsigned int this_cpu = smp_processor_id(); 608 unsigned int cpu; 609 610 for_each_online_cpu(cpu) { 611 if (cpu != this_cpu) 612 uv_send_IPI_one(cpu, vector); 613 } 614 } 615 616 static void uv_send_IPI_all(int vector) 617 { 618 uv_send_IPI_mask(cpu_online_mask, vector); 619 } 620 621 static int uv_apic_id_valid(u32 apicid) 622 { 623 return 1; 624 } 625 626 static int uv_apic_id_registered(void) 627 { 628 return 1; 629 } 630 631 static void uv_init_apic_ldr(void) 632 { 633 } 634 635 static u32 apic_uv_calc_apicid(unsigned int cpu) 636 { 637 return apic_default_calc_apicid(cpu) | uv_apicid_hibits; 638 } 639 640 static unsigned int x2apic_get_apic_id(unsigned long x) 641 { 642 unsigned int id; 643 644 WARN_ON(preemptible() && num_online_cpus() > 1); 645 id = x | __this_cpu_read(x2apic_extra_bits); 646 647 return id; 648 } 649 650 static u32 set_apic_id(unsigned int id) 651 { 652 /* CHECKME: Do we need to mask out the xapic extra bits? */ 653 return id; 654 } 655 656 static unsigned int uv_read_apic_id(void) 657 { 658 return x2apic_get_apic_id(apic_read(APIC_ID)); 659 } 660 661 static int uv_phys_pkg_id(int initial_apicid, int index_msb) 662 { 663 return uv_read_apic_id() >> index_msb; 664 } 665 666 static void uv_send_IPI_self(int vector) 667 { 668 apic_write(APIC_SELF_IPI, vector); 669 } 670 671 static int uv_probe(void) 672 { 673 return apic == &apic_x2apic_uv_x; 674 } 675 676 static struct apic apic_x2apic_uv_x __ro_after_init = { 677 678 .name = "UV large system", 679 .probe = uv_probe, 680 .acpi_madt_oem_check = uv_acpi_madt_oem_check, 681 .apic_id_valid = uv_apic_id_valid, 682 .apic_id_registered = uv_apic_id_registered, 683 684 .irq_delivery_mode = dest_Fixed, 685 .irq_dest_mode = 0, /* Physical */ 686 687 .disable_esr = 0, 688 .dest_logical = APIC_DEST_LOGICAL, 689 .check_apicid_used = NULL, 690 691 .init_apic_ldr = uv_init_apic_ldr, 692 693 .ioapic_phys_id_map = NULL, 694 .setup_apic_routing = NULL, 695 .cpu_present_to_apicid = default_cpu_present_to_apicid, 696 .apicid_to_cpu_present = NULL, 697 .check_phys_apicid_present = default_check_phys_apicid_present, 698 .phys_pkg_id = uv_phys_pkg_id, 699 700 .get_apic_id = x2apic_get_apic_id, 701 .set_apic_id = set_apic_id, 702 703 .calc_dest_apicid = apic_uv_calc_apicid, 704 705 .send_IPI = uv_send_IPI_one, 706 .send_IPI_mask = uv_send_IPI_mask, 707 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, 708 .send_IPI_allbutself = uv_send_IPI_allbutself, 709 .send_IPI_all = uv_send_IPI_all, 710 .send_IPI_self = uv_send_IPI_self, 711 712 .wakeup_secondary_cpu = uv_wakeup_secondary, 713 .inquire_remote_apic = NULL, 714 715 .read = native_apic_msr_read, 716 .write = native_apic_msr_write, 717 .eoi_write = native_apic_msr_eoi_write, 718 .icr_read = native_x2apic_icr_read, 719 .icr_write = native_x2apic_icr_write, 720 .wait_icr_idle = native_x2apic_wait_icr_idle, 721 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, 722 }; 723 724 static void set_x2apic_extra_bits(int pnode) 725 { 726 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); 727 } 728 729 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 730 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 731 732 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) 733 { 734 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; 735 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; 736 unsigned long m_redirect; 737 unsigned long m_overlay; 738 int i; 739 740 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) { 741 switch (i) { 742 case 0: 743 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR; 744 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR; 745 break; 746 case 1: 747 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR; 748 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR; 749 break; 750 case 2: 751 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR; 752 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR; 753 break; 754 } 755 alias.v = uv_read_local_mmr(m_overlay); 756 if (alias.s.enable && alias.s.base == 0) { 757 *size = (1UL << alias.s.m_alias); 758 redirect.v = uv_read_local_mmr(m_redirect); 759 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; 760 return; 761 } 762 } 763 *base = *size = 0; 764 } 765 766 enum map_type {map_wb, map_uc}; 767 768 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type) 769 { 770 unsigned long bytes, paddr; 771 772 paddr = base << pshift; 773 bytes = (1UL << bshift) * (max_pnode + 1); 774 if (!paddr) { 775 pr_info("UV: Map %s_HI base address NULL\n", id); 776 return; 777 } 778 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes); 779 if (map_type == map_uc) 780 init_extra_mapping_uc(paddr, bytes); 781 else 782 init_extra_mapping_wb(paddr, bytes); 783 } 784 785 static __init void map_gru_high(int max_pnode) 786 { 787 union uvh_rh_gam_gru_overlay_config_mmr_u gru; 788 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; 789 unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK; 790 unsigned long base; 791 792 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); 793 if (!gru.s.enable) { 794 pr_info("UV: GRU disabled\n"); 795 return; 796 } 797 798 base = (gru.v & mask) >> shift; 799 map_high("GRU", base, shift, shift, max_pnode, map_wb); 800 gru_start_paddr = ((u64)base << shift); 801 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); 802 } 803 804 static __init void map_mmr_high(int max_pnode) 805 { 806 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; 807 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; 808 809 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); 810 if (mmr.s.enable) 811 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc); 812 else 813 pr_info("UV: MMR disabled\n"); 814 } 815 816 /* UV3/4 have identical MMIOH overlay configs, UV4A is slightly different */ 817 static __init void map_mmioh_high_uv34(int index, int min_pnode, int max_pnode) 818 { 819 unsigned long overlay; 820 unsigned long mmr; 821 unsigned long base; 822 unsigned long nasid_mask; 823 unsigned long m_overlay; 824 int i, n, shift, m_io, max_io; 825 int nasid, lnasid, fi, li; 826 char *id; 827 828 if (index == 0) { 829 id = "MMIOH0"; 830 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR; 831 overlay = uv_read_local_mmr(m_overlay); 832 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK; 833 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR; 834 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK) 835 >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT; 836 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT; 837 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH; 838 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK; 839 } else { 840 id = "MMIOH1"; 841 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR; 842 overlay = uv_read_local_mmr(m_overlay); 843 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK; 844 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR; 845 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK) 846 >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT; 847 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT; 848 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH; 849 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK; 850 } 851 pr_info("UV: %s overlay 0x%lx base:0x%lx m_io:%d\n", id, overlay, base, m_io); 852 if (!(overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK)) { 853 pr_info("UV: %s disabled\n", id); 854 return; 855 } 856 857 /* Convert to NASID: */ 858 min_pnode *= 2; 859 max_pnode *= 2; 860 max_io = lnasid = fi = li = -1; 861 862 for (i = 0; i < n; i++) { 863 unsigned long m_redirect = mmr + i * 8; 864 unsigned long redirect = uv_read_local_mmr(m_redirect); 865 866 nasid = redirect & nasid_mask; 867 if (i == 0) 868 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n", 869 id, redirect, m_redirect, nasid); 870 871 /* Invalid NASID: */ 872 if (nasid < min_pnode || max_pnode < nasid) 873 nasid = -1; 874 875 if (nasid == lnasid) { 876 li = i; 877 /* Last entry check: */ 878 if (i != n-1) 879 continue; 880 } 881 882 /* Check if we have a cached (or last) redirect to print: */ 883 if (lnasid != -1 || (i == n-1 && nasid != -1)) { 884 unsigned long addr1, addr2; 885 int f, l; 886 887 if (lnasid == -1) { 888 f = l = i; 889 lnasid = nasid; 890 } else { 891 f = fi; 892 l = li; 893 } 894 addr1 = (base << shift) + f * (1ULL << m_io); 895 addr2 = (base << shift) + (l + 1) * (1ULL << m_io); 896 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2); 897 if (max_io < l) 898 max_io = l; 899 } 900 fi = li = i; 901 lnasid = nasid; 902 } 903 904 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io); 905 906 if (max_io >= 0) 907 map_high(id, base, shift, m_io, max_io, map_uc); 908 } 909 910 static __init void map_mmioh_high(int min_pnode, int max_pnode) 911 { 912 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; 913 unsigned long mmr, base; 914 int shift, enable, m_io, n_io; 915 916 if (is_uv3_hub() || is_uv4_hub()) { 917 /* Map both MMIOH regions: */ 918 map_mmioh_high_uv34(0, min_pnode, max_pnode); 919 map_mmioh_high_uv34(1, min_pnode, max_pnode); 920 return; 921 } 922 923 if (is_uv1_hub()) { 924 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; 925 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; 926 mmioh.v = uv_read_local_mmr(mmr); 927 enable = !!mmioh.s1.enable; 928 base = mmioh.s1.base; 929 m_io = mmioh.s1.m_io; 930 n_io = mmioh.s1.n_io; 931 } else if (is_uv2_hub()) { 932 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; 933 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; 934 mmioh.v = uv_read_local_mmr(mmr); 935 enable = !!mmioh.s2.enable; 936 base = mmioh.s2.base; 937 m_io = mmioh.s2.m_io; 938 n_io = mmioh.s2.n_io; 939 } else { 940 return; 941 } 942 943 if (enable) { 944 max_pnode &= (1 << n_io) - 1; 945 pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode); 946 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc); 947 } else { 948 pr_info("UV: MMIOH disabled\n"); 949 } 950 } 951 952 static __init void map_low_mmrs(void) 953 { 954 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); 955 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); 956 } 957 958 static __init void uv_rtc_init(void) 959 { 960 long status; 961 u64 ticks_per_sec; 962 963 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec); 964 965 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { 966 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n"); 967 968 /* BIOS gives wrong value for clock frequency, so guess: */ 969 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; 970 } else { 971 sn_rtc_cycles_per_second = ticks_per_sec; 972 } 973 } 974 975 /* 976 * percpu heartbeat timer 977 */ 978 static void uv_heartbeat(struct timer_list *timer) 979 { 980 unsigned char bits = uv_scir_info->state; 981 982 /* Flip heartbeat bit: */ 983 bits ^= SCIR_CPU_HEARTBEAT; 984 985 /* Is this CPU idle? */ 986 if (idle_cpu(raw_smp_processor_id())) 987 bits &= ~SCIR_CPU_ACTIVITY; 988 else 989 bits |= SCIR_CPU_ACTIVITY; 990 991 /* Update system controller interface reg: */ 992 uv_set_scir_bits(bits); 993 994 /* Enable next timer period: */ 995 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL); 996 } 997 998 static int uv_heartbeat_enable(unsigned int cpu) 999 { 1000 while (!uv_cpu_scir_info(cpu)->enabled) { 1001 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer; 1002 1003 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); 1004 timer_setup(timer, uv_heartbeat, TIMER_PINNED); 1005 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; 1006 add_timer_on(timer, cpu); 1007 uv_cpu_scir_info(cpu)->enabled = 1; 1008 1009 /* Also ensure that boot CPU is enabled: */ 1010 cpu = 0; 1011 } 1012 return 0; 1013 } 1014 1015 #ifdef CONFIG_HOTPLUG_CPU 1016 static int uv_heartbeat_disable(unsigned int cpu) 1017 { 1018 if (uv_cpu_scir_info(cpu)->enabled) { 1019 uv_cpu_scir_info(cpu)->enabled = 0; 1020 del_timer(&uv_cpu_scir_info(cpu)->timer); 1021 } 1022 uv_set_cpu_scir_bits(cpu, 0xff); 1023 return 0; 1024 } 1025 1026 static __init void uv_scir_register_cpu_notifier(void) 1027 { 1028 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online", 1029 uv_heartbeat_enable, uv_heartbeat_disable); 1030 } 1031 1032 #else /* !CONFIG_HOTPLUG_CPU */ 1033 1034 static __init void uv_scir_register_cpu_notifier(void) 1035 { 1036 } 1037 1038 static __init int uv_init_heartbeat(void) 1039 { 1040 int cpu; 1041 1042 if (is_uv_system()) { 1043 for_each_online_cpu(cpu) 1044 uv_heartbeat_enable(cpu); 1045 } 1046 1047 return 0; 1048 } 1049 1050 late_initcall(uv_init_heartbeat); 1051 1052 #endif /* !CONFIG_HOTPLUG_CPU */ 1053 1054 /* Direct Legacy VGA I/O traffic to designated IOH */ 1055 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags) 1056 { 1057 int domain, bus, rc; 1058 1059 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 1060 return 0; 1061 1062 if ((command_bits & PCI_COMMAND_IO) == 0) 1063 return 0; 1064 1065 domain = pci_domain_nr(pdev->bus); 1066 bus = pdev->bus->number; 1067 1068 rc = uv_bios_set_legacy_vga_target(decode, domain, bus); 1069 1070 return rc; 1071 } 1072 1073 /* 1074 * Called on each CPU to initialize the per_cpu UV data area. 1075 * FIXME: hotplug not supported yet 1076 */ 1077 void uv_cpu_init(void) 1078 { 1079 /* CPU 0 initialization will be done via uv_system_init. */ 1080 if (smp_processor_id() == 0) 1081 return; 1082 1083 uv_hub_info->nr_online_cpus++; 1084 1085 if (get_uv_system_type() == UV_NON_UNIQUE_APIC) 1086 set_x2apic_extra_bits(uv_hub_info->pnode); 1087 } 1088 1089 struct mn { 1090 unsigned char m_val; 1091 unsigned char n_val; 1092 unsigned char m_shift; 1093 unsigned char n_lshift; 1094 }; 1095 1096 static void get_mn(struct mn *mnp) 1097 { 1098 union uvh_rh_gam_config_mmr_u m_n_config; 1099 union uv3h_gr0_gam_gr_config_u m_gr_config; 1100 1101 /* Make sure the whole structure is well initialized: */ 1102 memset(mnp, 0, sizeof(*mnp)); 1103 1104 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR); 1105 mnp->n_val = m_n_config.s.n_skt; 1106 1107 if (is_uv4_hub()) { 1108 mnp->m_val = 0; 1109 mnp->n_lshift = 0; 1110 } else if (is_uv3_hub()) { 1111 mnp->m_val = m_n_config.s3.m_skt; 1112 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG); 1113 mnp->n_lshift = m_gr_config.s3.m_skt; 1114 } else if (is_uv2_hub()) { 1115 mnp->m_val = m_n_config.s2.m_skt; 1116 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39; 1117 } else if (is_uv1_hub()) { 1118 mnp->m_val = m_n_config.s1.m_skt; 1119 mnp->n_lshift = mnp->m_val; 1120 } 1121 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0; 1122 } 1123 1124 static void __init uv_init_hub_info(struct uv_hub_info_s *hi) 1125 { 1126 union uvh_node_id_u node_id; 1127 struct mn mn; 1128 1129 get_mn(&mn); 1130 hi->gpa_mask = mn.m_val ? 1131 (1UL << (mn.m_val + mn.n_val)) - 1 : 1132 (1UL << uv_cpuid.gpa_shift) - 1; 1133 1134 hi->m_val = mn.m_val; 1135 hi->n_val = mn.n_val; 1136 hi->m_shift = mn.m_shift; 1137 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0; 1138 hi->hub_revision = uv_hub_info->hub_revision; 1139 hi->pnode_mask = uv_cpuid.pnode_mask; 1140 hi->min_pnode = _min_pnode; 1141 hi->min_socket = _min_socket; 1142 hi->pnode_to_socket = _pnode_to_socket; 1143 hi->socket_to_node = _socket_to_node; 1144 hi->socket_to_pnode = _socket_to_pnode; 1145 hi->gr_table_len = _gr_table_len; 1146 hi->gr_table = _gr_table; 1147 1148 node_id.v = uv_read_local_mmr(UVH_NODE_ID); 1149 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val); 1150 hi->gnode_extra = (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1; 1151 if (mn.m_val) 1152 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val; 1153 1154 if (uv_gp_table) { 1155 hi->global_mmr_base = uv_gp_table->mmr_base; 1156 hi->global_mmr_shift = uv_gp_table->mmr_shift; 1157 hi->global_gru_base = uv_gp_table->gru_base; 1158 hi->global_gru_shift = uv_gp_table->gru_shift; 1159 hi->gpa_shift = uv_gp_table->gpa_shift; 1160 hi->gpa_mask = (1UL << hi->gpa_shift) - 1; 1161 } else { 1162 hi->global_mmr_base = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE; 1163 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT; 1164 } 1165 1166 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top); 1167 1168 hi->apic_pnode_shift = uv_cpuid.socketid_shift; 1169 1170 /* Show system specific info: */ 1171 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift); 1172 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift); 1173 pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift); 1174 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra); 1175 } 1176 1177 static void __init decode_gam_params(unsigned long ptr) 1178 { 1179 uv_gp_table = (struct uv_gam_parameters *)ptr; 1180 1181 pr_info("UV: GAM Params...\n"); 1182 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n", 1183 uv_gp_table->mmr_base, uv_gp_table->mmr_shift, 1184 uv_gp_table->gru_base, uv_gp_table->gru_shift, 1185 uv_gp_table->gpa_shift); 1186 } 1187 1188 static void __init decode_gam_rng_tbl(unsigned long ptr) 1189 { 1190 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr; 1191 unsigned long lgre = 0; 1192 int index = 0; 1193 int sock_min = 999999, pnode_min = 99999; 1194 int sock_max = -1, pnode_max = -1; 1195 1196 uv_gre_table = gre; 1197 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1198 unsigned long size = ((unsigned long)(gre->limit - lgre) 1199 << UV_GAM_RANGE_SHFT); 1200 int order = 0; 1201 char suffix[] = " KMGTPE"; 1202 int flag = ' '; 1203 1204 while (size > 9999 && order < sizeof(suffix)) { 1205 size /= 1024; 1206 order++; 1207 } 1208 1209 /* adjust max block size to current range start */ 1210 if (gre->type == 1 || gre->type == 2) 1211 if (adj_blksize(lgre)) 1212 flag = '*'; 1213 1214 if (!index) { 1215 pr_info("UV: GAM Range Table...\n"); 1216 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN"); 1217 } 1218 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n", 1219 index++, 1220 (unsigned long)lgre << UV_GAM_RANGE_SHFT, 1221 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT, 1222 flag, size, suffix[order], 1223 gre->type, gre->nasid, gre->sockid, gre->pnode); 1224 1225 /* update to next range start */ 1226 lgre = gre->limit; 1227 if (sock_min > gre->sockid) 1228 sock_min = gre->sockid; 1229 if (sock_max < gre->sockid) 1230 sock_max = gre->sockid; 1231 if (pnode_min > gre->pnode) 1232 pnode_min = gre->pnode; 1233 if (pnode_max < gre->pnode) 1234 pnode_max = gre->pnode; 1235 } 1236 _min_socket = sock_min; 1237 _max_socket = sock_max; 1238 _min_pnode = pnode_min; 1239 _max_pnode = pnode_max; 1240 _gr_table_len = index; 1241 1242 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode); 1243 } 1244 1245 static int __init decode_uv_systab(void) 1246 { 1247 struct uv_systab *st; 1248 int i; 1249 1250 /* If system is uv3 or lower, there is no extended UVsystab */ 1251 if (is_uv_hubbed(0xfffffe) < uv(4) && is_uv_hubless(0xfffffe) < uv(4)) 1252 return 0; /* No extended UVsystab required */ 1253 1254 st = uv_systab; 1255 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) { 1256 int rev = st ? st->revision : 0; 1257 1258 pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST); 1259 pr_err("UV: Cannot support UV operations, switching to generic PC\n"); 1260 uv_system_type = UV_NONE; 1261 1262 return -EINVAL; 1263 } 1264 1265 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { 1266 unsigned long ptr = st->entry[i].offset; 1267 1268 if (!ptr) 1269 continue; 1270 1271 ptr = ptr + (unsigned long)st; 1272 1273 switch (st->entry[i].type) { 1274 case UV_SYSTAB_TYPE_GAM_PARAMS: 1275 decode_gam_params(ptr); 1276 break; 1277 1278 case UV_SYSTAB_TYPE_GAM_RNG_TBL: 1279 decode_gam_rng_tbl(ptr); 1280 break; 1281 } 1282 } 1283 return 0; 1284 } 1285 1286 /* 1287 * Set up physical blade translations from UVH_NODE_PRESENT_TABLE 1288 * .. NB: UVH_NODE_PRESENT_TABLE is going away, 1289 * .. being replaced by GAM Range Table 1290 */ 1291 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info) 1292 { 1293 int i, uv_pb = 0; 1294 1295 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH); 1296 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { 1297 unsigned long np; 1298 1299 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); 1300 if (np) 1301 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np); 1302 1303 uv_pb += hweight64(np); 1304 } 1305 if (uv_possible_blades != uv_pb) 1306 uv_possible_blades = uv_pb; 1307 } 1308 1309 static void __init build_socket_tables(void) 1310 { 1311 struct uv_gam_range_entry *gre = uv_gre_table; 1312 int num, nump; 1313 int cpu, i, lnid; 1314 int minsock = _min_socket; 1315 int maxsock = _max_socket; 1316 int minpnode = _min_pnode; 1317 int maxpnode = _max_pnode; 1318 size_t bytes; 1319 1320 if (!gre) { 1321 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) { 1322 pr_info("UV: No UVsystab socket table, ignoring\n"); 1323 return; 1324 } 1325 pr_crit("UV: Error: UVsystab address translations not available!\n"); 1326 BUG(); 1327 } 1328 1329 /* Build socket id -> node id, pnode */ 1330 num = maxsock - minsock + 1; 1331 bytes = num * sizeof(_socket_to_node[0]); 1332 _socket_to_node = kmalloc(bytes, GFP_KERNEL); 1333 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL); 1334 1335 nump = maxpnode - minpnode + 1; 1336 bytes = nump * sizeof(_pnode_to_socket[0]); 1337 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL); 1338 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket); 1339 1340 for (i = 0; i < num; i++) 1341 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY; 1342 1343 for (i = 0; i < nump; i++) 1344 _pnode_to_socket[i] = SOCK_EMPTY; 1345 1346 /* Fill in pnode/node/addr conversion list values: */ 1347 pr_info("UV: GAM Building socket/pnode conversion tables\n"); 1348 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1349 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) 1350 continue; 1351 i = gre->sockid - minsock; 1352 /* Duplicate: */ 1353 if (_socket_to_pnode[i] != SOCK_EMPTY) 1354 continue; 1355 _socket_to_pnode[i] = gre->pnode; 1356 1357 i = gre->pnode - minpnode; 1358 _pnode_to_socket[i] = gre->sockid; 1359 1360 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n", 1361 gre->sockid, gre->type, gre->nasid, 1362 _socket_to_pnode[gre->sockid - minsock], 1363 _pnode_to_socket[gre->pnode - minpnode]); 1364 } 1365 1366 /* Set socket -> node values: */ 1367 lnid = NUMA_NO_NODE; 1368 for_each_present_cpu(cpu) { 1369 int nid = cpu_to_node(cpu); 1370 int apicid, sockid; 1371 1372 if (lnid == nid) 1373 continue; 1374 lnid = nid; 1375 apicid = per_cpu(x86_cpu_to_apicid, cpu); 1376 sockid = apicid >> uv_cpuid.socketid_shift; 1377 _socket_to_node[sockid - minsock] = nid; 1378 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n", 1379 sockid, apicid, nid); 1380 } 1381 1382 /* Set up physical blade to pnode translation from GAM Range Table: */ 1383 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]); 1384 _node_to_pnode = kmalloc(bytes, GFP_KERNEL); 1385 BUG_ON(!_node_to_pnode); 1386 1387 for (lnid = 0; lnid < num_possible_nodes(); lnid++) { 1388 unsigned short sockid; 1389 1390 for (sockid = minsock; sockid <= maxsock; sockid++) { 1391 if (lnid == _socket_to_node[sockid - minsock]) { 1392 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock]; 1393 break; 1394 } 1395 } 1396 if (sockid > maxsock) { 1397 pr_err("UV: socket for node %d not found!\n", lnid); 1398 BUG(); 1399 } 1400 } 1401 1402 /* 1403 * If socket id == pnode or socket id == node for all nodes, 1404 * system runs faster by removing corresponding conversion table. 1405 */ 1406 pr_info("UV: Checking socket->node/pnode for identity maps\n"); 1407 if (minsock == 0) { 1408 for (i = 0; i < num; i++) 1409 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i]) 1410 break; 1411 if (i >= num) { 1412 kfree(_socket_to_node); 1413 _socket_to_node = NULL; 1414 pr_info("UV: 1:1 socket_to_node table removed\n"); 1415 } 1416 } 1417 if (minsock == minpnode) { 1418 for (i = 0; i < num; i++) 1419 if (_socket_to_pnode[i] != SOCK_EMPTY && 1420 _socket_to_pnode[i] != i + minpnode) 1421 break; 1422 if (i >= num) { 1423 kfree(_socket_to_pnode); 1424 _socket_to_pnode = NULL; 1425 pr_info("UV: 1:1 socket_to_pnode table removed\n"); 1426 } 1427 } 1428 } 1429 1430 /* Check which reboot to use */ 1431 static void check_efi_reboot(void) 1432 { 1433 /* If EFI reboot not available, use ACPI reboot */ 1434 if (!efi_enabled(EFI_BOOT)) 1435 reboot_type = BOOT_ACPI; 1436 } 1437 1438 /* Setup user proc fs files */ 1439 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data) 1440 { 1441 seq_printf(file, "0x%x\n", uv_hubbed_system); 1442 return 0; 1443 } 1444 1445 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data) 1446 { 1447 seq_printf(file, "0x%x\n", uv_hubless_system); 1448 return 0; 1449 } 1450 1451 static int __maybe_unused proc_oemid_show(struct seq_file *file, void *data) 1452 { 1453 seq_printf(file, "%s/%s\n", oem_id, oem_table_id); 1454 return 0; 1455 } 1456 1457 static __init void uv_setup_proc_files(int hubless) 1458 { 1459 struct proc_dir_entry *pde; 1460 1461 pde = proc_mkdir(UV_PROC_NODE, NULL); 1462 proc_create_single("oemid", 0, pde, proc_oemid_show); 1463 if (hubless) 1464 proc_create_single("hubless", 0, pde, proc_hubless_show); 1465 else 1466 proc_create_single("hubbed", 0, pde, proc_hubbed_show); 1467 } 1468 1469 /* Initialize UV hubless systems */ 1470 static __init int uv_system_init_hubless(void) 1471 { 1472 int rc; 1473 1474 /* Setup PCH NMI handler */ 1475 uv_nmi_setup_hubless(); 1476 1477 /* Init kernel/BIOS interface */ 1478 rc = uv_bios_init(); 1479 if (rc < 0) 1480 return rc; 1481 1482 /* Process UVsystab */ 1483 rc = decode_uv_systab(); 1484 if (rc < 0) 1485 return rc; 1486 1487 /* Create user access node */ 1488 if (rc >= 0) 1489 uv_setup_proc_files(1); 1490 1491 check_efi_reboot(); 1492 1493 return rc; 1494 } 1495 1496 static void __init uv_system_init_hub(void) 1497 { 1498 struct uv_hub_info_s hub_info = {0}; 1499 int bytes, cpu, nodeid; 1500 unsigned short min_pnode = 9999, max_pnode = 0; 1501 char *hub = is_uv4_hub() ? "UV400" : 1502 is_uv3_hub() ? "UV300" : 1503 is_uv2_hub() ? "UV2000/3000" : 1504 is_uv1_hub() ? "UV100/1000" : NULL; 1505 1506 if (!hub) { 1507 pr_err("UV: Unknown/unsupported UV hub\n"); 1508 return; 1509 } 1510 pr_info("UV: Found %s hub\n", hub); 1511 1512 map_low_mmrs(); 1513 1514 /* Get uv_systab for decoding: */ 1515 uv_bios_init(); 1516 1517 /* If there's an UVsystab problem then abort UV init: */ 1518 if (decode_uv_systab() < 0) 1519 return; 1520 1521 build_socket_tables(); 1522 build_uv_gr_table(); 1523 set_block_size(); 1524 uv_init_hub_info(&hub_info); 1525 uv_possible_blades = num_possible_nodes(); 1526 if (!_node_to_pnode) 1527 boot_init_possible_blades(&hub_info); 1528 1529 /* uv_num_possible_blades() is really the hub count: */ 1530 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus()); 1531 1532 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number); 1533 hub_info.coherency_domain_number = sn_coherency_id; 1534 uv_rtc_init(); 1535 1536 bytes = sizeof(void *) * uv_num_possible_blades(); 1537 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL); 1538 BUG_ON(!__uv_hub_info_list); 1539 1540 bytes = sizeof(struct uv_hub_info_s); 1541 for_each_node(nodeid) { 1542 struct uv_hub_info_s *new_hub; 1543 1544 if (__uv_hub_info_list[nodeid]) { 1545 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid); 1546 BUG(); 1547 } 1548 1549 /* Allocate new per hub info list */ 1550 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid); 1551 BUG_ON(!new_hub); 1552 __uv_hub_info_list[nodeid] = new_hub; 1553 new_hub = uv_hub_info_list(nodeid); 1554 BUG_ON(!new_hub); 1555 *new_hub = hub_info; 1556 1557 /* Use information from GAM table if available: */ 1558 if (_node_to_pnode) 1559 new_hub->pnode = _node_to_pnode[nodeid]; 1560 else /* Or fill in during CPU loop: */ 1561 new_hub->pnode = 0xffff; 1562 1563 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid); 1564 new_hub->memory_nid = NUMA_NO_NODE; 1565 new_hub->nr_possible_cpus = 0; 1566 new_hub->nr_online_cpus = 0; 1567 } 1568 1569 /* Initialize per CPU info: */ 1570 for_each_possible_cpu(cpu) { 1571 int apicid = per_cpu(x86_cpu_to_apicid, cpu); 1572 int numa_node_id; 1573 unsigned short pnode; 1574 1575 nodeid = cpu_to_node(cpu); 1576 numa_node_id = numa_cpu_node(cpu); 1577 pnode = uv_apicid_to_pnode(apicid); 1578 1579 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid); 1580 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++; 1581 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE) 1582 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu); 1583 1584 /* Init memoryless node: */ 1585 if (nodeid != numa_node_id && 1586 uv_hub_info_list(numa_node_id)->pnode == 0xffff) 1587 uv_hub_info_list(numa_node_id)->pnode = pnode; 1588 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff) 1589 uv_cpu_hub_info(cpu)->pnode = pnode; 1590 1591 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid); 1592 } 1593 1594 for_each_node(nodeid) { 1595 unsigned short pnode = uv_hub_info_list(nodeid)->pnode; 1596 1597 /* Add pnode info for pre-GAM list nodes without CPUs: */ 1598 if (pnode == 0xffff) { 1599 unsigned long paddr; 1600 1601 paddr = node_start_pfn(nodeid) << PAGE_SHIFT; 1602 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); 1603 uv_hub_info_list(nodeid)->pnode = pnode; 1604 } 1605 min_pnode = min(pnode, min_pnode); 1606 max_pnode = max(pnode, max_pnode); 1607 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n", 1608 nodeid, 1609 uv_hub_info_list(nodeid)->pnode, 1610 uv_hub_info_list(nodeid)->nr_possible_cpus); 1611 } 1612 1613 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode); 1614 map_gru_high(max_pnode); 1615 map_mmr_high(max_pnode); 1616 map_mmioh_high(min_pnode, max_pnode); 1617 1618 uv_nmi_setup(); 1619 uv_cpu_init(); 1620 uv_scir_register_cpu_notifier(); 1621 uv_setup_proc_files(0); 1622 1623 /* Register Legacy VGA I/O redirection handler: */ 1624 pci_register_set_vga_state(uv_set_vga_state); 1625 1626 check_efi_reboot(); 1627 } 1628 1629 /* 1630 * There is a different code path needed to initialize a UV system that does 1631 * not have a "UV HUB" (referred to as "hubless"). 1632 */ 1633 void __init uv_system_init(void) 1634 { 1635 if (likely(!is_uv_system() && !is_uv_hubless(1))) 1636 return; 1637 1638 if (is_uv_system()) 1639 uv_system_init_hub(); 1640 else 1641 uv_system_init_hubless(); 1642 } 1643 1644 apic_driver(apic_x2apic_uv_x); 1645