1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces 4 * 5 * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>, 6 * Pilo Chambert <pilo.c@wanadoo.fr> 7 * 8 * Thanks to : Anders Torger <torger@ludd.luth.se>, 9 * Henk Hesselink <henk@anda.nl> 10 * for writing the digi96-driver 11 * and RME for all informations. 12 * 13 * **************************************************************************** 14 * 15 * Note #1 "Sek'd models" ................................... martin 2002-12-07 16 * 17 * Identical soundcards by Sek'd were labeled: 18 * RME Digi 32 = Sek'd Prodif 32 19 * RME Digi 32 Pro = Sek'd Prodif 96 20 * RME Digi 32/8 = Sek'd Prodif Gold 21 * 22 * **************************************************************************** 23 * 24 * Note #2 "full duplex mode" ............................... martin 2002-12-07 25 * 26 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical 27 * in this mode. Rec data and play data are using the same buffer therefore. At 28 * first you have got the playing bits in the buffer and then (after playing 29 * them) they were overwitten by the captured sound of the CS8412/14. Both 30 * modes (play/record) are running harmonically hand in hand in the same buffer 31 * and you have only one start bit plus one interrupt bit to control this 32 * paired action. 33 * This is opposite to the latter rme96 where playing and capturing is totally 34 * separated and so their full duplex mode is supported by alsa (using two 35 * start bits and two interrupts for two different buffers). 36 * But due to the wrong sequence of playing and capturing ALSA shows no solved 37 * full duplex support for the rme32 at the moment. That's bad, but I'm not 38 * able to solve it. Are you motivated enough to solve this problem now? Your 39 * patch would be welcome! 40 * 41 * **************************************************************************** 42 * 43 * "The story after the long seeking" -- tiwai 44 * 45 * Ok, the situation regarding the full duplex is now improved a bit. 46 * In the fullduplex mode (given by the module parameter), the hardware buffer 47 * is split to halves for read and write directions at the DMA pointer. 48 * That is, the half above the current DMA pointer is used for write, and 49 * the half below is used for read. To mangle this strange behavior, an 50 * software intermediate buffer is introduced. This is, of course, not good 51 * from the viewpoint of the data transfer efficiency. However, this allows 52 * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size. 53 * 54 * **************************************************************************** 55 */ 56 57 58 #include <linux/delay.h> 59 #include <linux/gfp.h> 60 #include <linux/init.h> 61 #include <linux/interrupt.h> 62 #include <linux/pci.h> 63 #include <linux/module.h> 64 #include <linux/io.h> 65 66 #include <sound/core.h> 67 #include <sound/info.h> 68 #include <sound/control.h> 69 #include <sound/pcm.h> 70 #include <sound/pcm_params.h> 71 #include <sound/pcm-indirect.h> 72 #include <sound/asoundef.h> 73 #include <sound/initval.h> 74 75 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 76 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 77 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 78 static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1}; 79 80 module_param_array(index, int, NULL, 0444); 81 MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard."); 82 module_param_array(id, charp, NULL, 0444); 83 MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard."); 84 module_param_array(enable, bool, NULL, 0444); 85 MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard."); 86 module_param_array(fullduplex, bool, NULL, 0444); 87 MODULE_PARM_DESC(fullduplex, "Support full-duplex mode."); 88 MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>"); 89 MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO"); 90 MODULE_LICENSE("GPL"); 91 MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}"); 92 93 /* Defines for RME Digi32 series */ 94 #define RME32_SPDIF_NCHANNELS 2 95 96 /* Playback and capture buffer size */ 97 #define RME32_BUFFER_SIZE 0x20000 98 99 /* IO area size */ 100 #define RME32_IO_SIZE 0x30000 101 102 /* IO area offsets */ 103 #define RME32_IO_DATA_BUFFER 0x0 104 #define RME32_IO_CONTROL_REGISTER 0x20000 105 #define RME32_IO_GET_POS 0x20000 106 #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004 107 #define RME32_IO_RESET_POS 0x20100 108 109 /* Write control register bits */ 110 #define RME32_WCR_START (1 << 0) /* startbit */ 111 #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono 112 Setting the whole card to mono 113 doesn't seem to be very useful. 114 A software-solution can handle 115 full-duplex with one direction in 116 stereo and the other way in mono. 117 So, the hardware should work all 118 the time in stereo! */ 119 #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */ 120 #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */ 121 #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */ 122 #define RME32_WCR_FREQ_1 (1 << 5) 123 #define RME32_WCR_INP_0 (1 << 6) /* input switch */ 124 #define RME32_WCR_INP_1 (1 << 7) 125 #define RME32_WCR_RESET (1 << 8) /* Reset address */ 126 #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */ 127 #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */ 128 #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */ 129 #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */ 130 #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */ 131 #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */ 132 #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */ 133 134 #define RME32_WCR_BITPOS_FREQ_0 4 135 #define RME32_WCR_BITPOS_FREQ_1 5 136 #define RME32_WCR_BITPOS_INP_0 6 137 #define RME32_WCR_BITPOS_INP_1 7 138 139 /* Read control register bits */ 140 #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff 141 #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */ 142 #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */ 143 #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */ 144 #define RME32_RCR_FREQ_1 (1 << 28) 145 #define RME32_RCR_FREQ_2 (1 << 29) 146 #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */ 147 #define RME32_RCR_IRQ (1 << 31) /* interrupt */ 148 149 #define RME32_RCR_BITPOS_F0 27 150 #define RME32_RCR_BITPOS_F1 28 151 #define RME32_RCR_BITPOS_F2 29 152 153 /* Input types */ 154 #define RME32_INPUT_OPTICAL 0 155 #define RME32_INPUT_COAXIAL 1 156 #define RME32_INPUT_INTERNAL 2 157 #define RME32_INPUT_XLR 3 158 159 /* Clock modes */ 160 #define RME32_CLOCKMODE_SLAVE 0 161 #define RME32_CLOCKMODE_MASTER_32 1 162 #define RME32_CLOCKMODE_MASTER_44 2 163 #define RME32_CLOCKMODE_MASTER_48 3 164 165 /* Block sizes in bytes */ 166 #define RME32_BLOCK_SIZE 8192 167 168 /* Software intermediate buffer (max) size */ 169 #define RME32_MID_BUFFER_SIZE (1024*1024) 170 171 /* Hardware revisions */ 172 #define RME32_32_REVISION 192 173 #define RME32_328_REVISION_OLD 100 174 #define RME32_328_REVISION_NEW 101 175 #define RME32_PRO_REVISION_WITH_8412 192 176 #define RME32_PRO_REVISION_WITH_8414 150 177 178 179 struct rme32 { 180 spinlock_t lock; 181 int irq; 182 unsigned long port; 183 void __iomem *iobase; 184 185 u32 wcreg; /* cached write control register value */ 186 u32 wcreg_spdif; /* S/PDIF setup */ 187 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ 188 u32 rcreg; /* cached read control register value */ 189 190 u8 rev; /* card revision number */ 191 192 struct snd_pcm_substream *playback_substream; 193 struct snd_pcm_substream *capture_substream; 194 195 int playback_frlog; /* log2 of framesize */ 196 int capture_frlog; 197 198 size_t playback_periodsize; /* in bytes, zero if not used */ 199 size_t capture_periodsize; /* in bytes, zero if not used */ 200 201 unsigned int fullduplex_mode; 202 int running; 203 204 struct snd_pcm_indirect playback_pcm; 205 struct snd_pcm_indirect capture_pcm; 206 207 struct snd_card *card; 208 struct snd_pcm *spdif_pcm; 209 struct snd_pcm *adat_pcm; 210 struct pci_dev *pci; 211 struct snd_kcontrol *spdif_ctl; 212 }; 213 214 static const struct pci_device_id snd_rme32_ids[] = { 215 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,}, 216 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,}, 217 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,}, 218 {0,} 219 }; 220 221 MODULE_DEVICE_TABLE(pci, snd_rme32_ids); 222 223 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START) 224 #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414) 225 226 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream); 227 228 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream); 229 230 static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd); 231 232 static void snd_rme32_proc_init(struct rme32 * rme32); 233 234 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32); 235 236 static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32) 237 { 238 return (readl(rme32->iobase + RME32_IO_GET_POS) 239 & RME32_RCR_AUDIO_ADDR_MASK); 240 } 241 242 /* silence callback for halfduplex mode */ 243 static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, 244 int channel, unsigned long pos, 245 unsigned long count) 246 { 247 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 248 249 memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count); 250 return 0; 251 } 252 253 /* copy callback for halfduplex mode */ 254 static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, 255 int channel, unsigned long pos, 256 void __user *src, unsigned long count) 257 { 258 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 259 260 if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 261 src, count)) 262 return -EFAULT; 263 return 0; 264 } 265 266 static int snd_rme32_playback_copy_kernel(struct snd_pcm_substream *substream, 267 int channel, unsigned long pos, 268 void *src, unsigned long count) 269 { 270 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 271 272 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, src, count); 273 return 0; 274 } 275 276 /* copy callback for halfduplex mode */ 277 static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, 278 int channel, unsigned long pos, 279 void __user *dst, unsigned long count) 280 { 281 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 282 283 if (copy_to_user_fromio(dst, 284 rme32->iobase + RME32_IO_DATA_BUFFER + pos, 285 count)) 286 return -EFAULT; 287 return 0; 288 } 289 290 static int snd_rme32_capture_copy_kernel(struct snd_pcm_substream *substream, 291 int channel, unsigned long pos, 292 void *dst, unsigned long count) 293 { 294 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 295 296 memcpy_fromio(dst, rme32->iobase + RME32_IO_DATA_BUFFER + pos, count); 297 return 0; 298 } 299 300 /* 301 * SPDIF I/O capabilities (half-duplex mode) 302 */ 303 static const struct snd_pcm_hardware snd_rme32_spdif_info = { 304 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 305 SNDRV_PCM_INFO_MMAP_VALID | 306 SNDRV_PCM_INFO_INTERLEAVED | 307 SNDRV_PCM_INFO_PAUSE | 308 SNDRV_PCM_INFO_SYNC_START | 309 SNDRV_PCM_INFO_SYNC_APPLPTR), 310 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 311 SNDRV_PCM_FMTBIT_S32_LE), 312 .rates = (SNDRV_PCM_RATE_32000 | 313 SNDRV_PCM_RATE_44100 | 314 SNDRV_PCM_RATE_48000), 315 .rate_min = 32000, 316 .rate_max = 48000, 317 .channels_min = 2, 318 .channels_max = 2, 319 .buffer_bytes_max = RME32_BUFFER_SIZE, 320 .period_bytes_min = RME32_BLOCK_SIZE, 321 .period_bytes_max = RME32_BLOCK_SIZE, 322 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 323 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 324 .fifo_size = 0, 325 }; 326 327 /* 328 * ADAT I/O capabilities (half-duplex mode) 329 */ 330 static const struct snd_pcm_hardware snd_rme32_adat_info = 331 { 332 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 333 SNDRV_PCM_INFO_MMAP_VALID | 334 SNDRV_PCM_INFO_INTERLEAVED | 335 SNDRV_PCM_INFO_PAUSE | 336 SNDRV_PCM_INFO_SYNC_START | 337 SNDRV_PCM_INFO_SYNC_APPLPTR), 338 .formats= SNDRV_PCM_FMTBIT_S16_LE, 339 .rates = (SNDRV_PCM_RATE_44100 | 340 SNDRV_PCM_RATE_48000), 341 .rate_min = 44100, 342 .rate_max = 48000, 343 .channels_min = 8, 344 .channels_max = 8, 345 .buffer_bytes_max = RME32_BUFFER_SIZE, 346 .period_bytes_min = RME32_BLOCK_SIZE, 347 .period_bytes_max = RME32_BLOCK_SIZE, 348 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 349 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 350 .fifo_size = 0, 351 }; 352 353 /* 354 * SPDIF I/O capabilities (full-duplex mode) 355 */ 356 static const struct snd_pcm_hardware snd_rme32_spdif_fd_info = { 357 .info = (SNDRV_PCM_INFO_MMAP | 358 SNDRV_PCM_INFO_MMAP_VALID | 359 SNDRV_PCM_INFO_INTERLEAVED | 360 SNDRV_PCM_INFO_PAUSE | 361 SNDRV_PCM_INFO_SYNC_START | 362 SNDRV_PCM_INFO_SYNC_APPLPTR), 363 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 364 SNDRV_PCM_FMTBIT_S32_LE), 365 .rates = (SNDRV_PCM_RATE_32000 | 366 SNDRV_PCM_RATE_44100 | 367 SNDRV_PCM_RATE_48000), 368 .rate_min = 32000, 369 .rate_max = 48000, 370 .channels_min = 2, 371 .channels_max = 2, 372 .buffer_bytes_max = RME32_MID_BUFFER_SIZE, 373 .period_bytes_min = RME32_BLOCK_SIZE, 374 .period_bytes_max = RME32_BLOCK_SIZE, 375 .periods_min = 2, 376 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE, 377 .fifo_size = 0, 378 }; 379 380 /* 381 * ADAT I/O capabilities (full-duplex mode) 382 */ 383 static const struct snd_pcm_hardware snd_rme32_adat_fd_info = 384 { 385 .info = (SNDRV_PCM_INFO_MMAP | 386 SNDRV_PCM_INFO_MMAP_VALID | 387 SNDRV_PCM_INFO_INTERLEAVED | 388 SNDRV_PCM_INFO_PAUSE | 389 SNDRV_PCM_INFO_SYNC_START | 390 SNDRV_PCM_INFO_SYNC_APPLPTR), 391 .formats= SNDRV_PCM_FMTBIT_S16_LE, 392 .rates = (SNDRV_PCM_RATE_44100 | 393 SNDRV_PCM_RATE_48000), 394 .rate_min = 44100, 395 .rate_max = 48000, 396 .channels_min = 8, 397 .channels_max = 8, 398 .buffer_bytes_max = RME32_MID_BUFFER_SIZE, 399 .period_bytes_min = RME32_BLOCK_SIZE, 400 .period_bytes_max = RME32_BLOCK_SIZE, 401 .periods_min = 2, 402 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE, 403 .fifo_size = 0, 404 }; 405 406 static void snd_rme32_reset_dac(struct rme32 *rme32) 407 { 408 writel(rme32->wcreg | RME32_WCR_PD, 409 rme32->iobase + RME32_IO_CONTROL_REGISTER); 410 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 411 } 412 413 static int snd_rme32_playback_getrate(struct rme32 * rme32) 414 { 415 int rate; 416 417 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + 418 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); 419 switch (rate) { 420 case 1: 421 rate = 32000; 422 break; 423 case 2: 424 rate = 44100; 425 break; 426 case 3: 427 rate = 48000; 428 break; 429 default: 430 return -1; 431 } 432 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate; 433 } 434 435 static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat) 436 { 437 int n; 438 439 *is_adat = 0; 440 if (rme32->rcreg & RME32_RCR_LOCK) { 441 /* ADAT rate */ 442 *is_adat = 1; 443 } 444 if (rme32->rcreg & RME32_RCR_ERF) { 445 return -1; 446 } 447 448 /* S/PDIF rate */ 449 n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) + 450 (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) + 451 (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2); 452 453 if (RME32_PRO_WITH_8414(rme32)) 454 switch (n) { /* supporting the CS8414 */ 455 case 0: 456 case 1: 457 case 2: 458 return -1; 459 case 3: 460 return 96000; 461 case 4: 462 return 88200; 463 case 5: 464 return 48000; 465 case 6: 466 return 44100; 467 case 7: 468 return 32000; 469 default: 470 return -1; 471 break; 472 } 473 else 474 switch (n) { /* supporting the CS8412 */ 475 case 0: 476 return -1; 477 case 1: 478 return 48000; 479 case 2: 480 return 44100; 481 case 3: 482 return 32000; 483 case 4: 484 return 48000; 485 case 5: 486 return 44100; 487 case 6: 488 return 44056; 489 case 7: 490 return 32000; 491 default: 492 break; 493 } 494 return -1; 495 } 496 497 static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate) 498 { 499 int ds; 500 501 ds = rme32->wcreg & RME32_WCR_DS_BM; 502 switch (rate) { 503 case 32000: 504 rme32->wcreg &= ~RME32_WCR_DS_BM; 505 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 506 ~RME32_WCR_FREQ_1; 507 break; 508 case 44100: 509 rme32->wcreg &= ~RME32_WCR_DS_BM; 510 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & 511 ~RME32_WCR_FREQ_0; 512 break; 513 case 48000: 514 rme32->wcreg &= ~RME32_WCR_DS_BM; 515 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 516 RME32_WCR_FREQ_1; 517 break; 518 case 64000: 519 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) 520 return -EINVAL; 521 rme32->wcreg |= RME32_WCR_DS_BM; 522 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 523 ~RME32_WCR_FREQ_1; 524 break; 525 case 88200: 526 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) 527 return -EINVAL; 528 rme32->wcreg |= RME32_WCR_DS_BM; 529 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & 530 ~RME32_WCR_FREQ_0; 531 break; 532 case 96000: 533 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) 534 return -EINVAL; 535 rme32->wcreg |= RME32_WCR_DS_BM; 536 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 537 RME32_WCR_FREQ_1; 538 break; 539 default: 540 return -EINVAL; 541 } 542 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) || 543 (ds && !(rme32->wcreg & RME32_WCR_DS_BM))) 544 { 545 /* change to/from double-speed: reset the DAC (if available) */ 546 snd_rme32_reset_dac(rme32); 547 } else { 548 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 549 } 550 return 0; 551 } 552 553 static int snd_rme32_setclockmode(struct rme32 * rme32, int mode) 554 { 555 switch (mode) { 556 case RME32_CLOCKMODE_SLAVE: 557 /* AutoSync */ 558 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) & 559 ~RME32_WCR_FREQ_1; 560 break; 561 case RME32_CLOCKMODE_MASTER_32: 562 /* Internal 32.0kHz */ 563 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 564 ~RME32_WCR_FREQ_1; 565 break; 566 case RME32_CLOCKMODE_MASTER_44: 567 /* Internal 44.1kHz */ 568 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) | 569 RME32_WCR_FREQ_1; 570 break; 571 case RME32_CLOCKMODE_MASTER_48: 572 /* Internal 48.0kHz */ 573 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 574 RME32_WCR_FREQ_1; 575 break; 576 default: 577 return -EINVAL; 578 } 579 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 580 return 0; 581 } 582 583 static int snd_rme32_getclockmode(struct rme32 * rme32) 584 { 585 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + 586 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); 587 } 588 589 static int snd_rme32_setinputtype(struct rme32 * rme32, int type) 590 { 591 switch (type) { 592 case RME32_INPUT_OPTICAL: 593 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) & 594 ~RME32_WCR_INP_1; 595 break; 596 case RME32_INPUT_COAXIAL: 597 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) & 598 ~RME32_WCR_INP_1; 599 break; 600 case RME32_INPUT_INTERNAL: 601 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) | 602 RME32_WCR_INP_1; 603 break; 604 case RME32_INPUT_XLR: 605 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) | 606 RME32_WCR_INP_1; 607 break; 608 default: 609 return -EINVAL; 610 } 611 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 612 return 0; 613 } 614 615 static int snd_rme32_getinputtype(struct rme32 * rme32) 616 { 617 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) + 618 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1); 619 } 620 621 static void 622 snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback) 623 { 624 int frlog; 625 626 if (n_channels == 2) { 627 frlog = 1; 628 } else { 629 /* assume 8 channels */ 630 frlog = 3; 631 } 632 if (is_playback) { 633 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; 634 rme32->playback_frlog = frlog; 635 } else { 636 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; 637 rme32->capture_frlog = frlog; 638 } 639 } 640 641 static int snd_rme32_setformat(struct rme32 *rme32, snd_pcm_format_t format) 642 { 643 switch (format) { 644 case SNDRV_PCM_FORMAT_S16_LE: 645 rme32->wcreg &= ~RME32_WCR_MODE24; 646 break; 647 case SNDRV_PCM_FORMAT_S32_LE: 648 rme32->wcreg |= RME32_WCR_MODE24; 649 break; 650 default: 651 return -EINVAL; 652 } 653 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 654 return 0; 655 } 656 657 static int 658 snd_rme32_playback_hw_params(struct snd_pcm_substream *substream, 659 struct snd_pcm_hw_params *params) 660 { 661 int err, rate, dummy; 662 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 663 struct snd_pcm_runtime *runtime = substream->runtime; 664 665 if (!rme32->fullduplex_mode) { 666 runtime->dma_area = (void __force *)(rme32->iobase + 667 RME32_IO_DATA_BUFFER); 668 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER; 669 runtime->dma_bytes = RME32_BUFFER_SIZE; 670 } 671 672 spin_lock_irq(&rme32->lock); 673 if ((rme32->rcreg & RME32_RCR_KMODE) && 674 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) { 675 /* AutoSync */ 676 if ((int)params_rate(params) != rate) { 677 spin_unlock_irq(&rme32->lock); 678 return -EIO; 679 } 680 } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) { 681 spin_unlock_irq(&rme32->lock); 682 return err; 683 } 684 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) { 685 spin_unlock_irq(&rme32->lock); 686 return err; 687 } 688 689 snd_rme32_setframelog(rme32, params_channels(params), 1); 690 if (rme32->capture_periodsize != 0) { 691 if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) { 692 spin_unlock_irq(&rme32->lock); 693 return -EBUSY; 694 } 695 } 696 rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog; 697 /* S/PDIF setup */ 698 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) { 699 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); 700 rme32->wcreg |= rme32->wcreg_spdif_stream; 701 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 702 } 703 spin_unlock_irq(&rme32->lock); 704 705 return 0; 706 } 707 708 static int 709 snd_rme32_capture_hw_params(struct snd_pcm_substream *substream, 710 struct snd_pcm_hw_params *params) 711 { 712 int err, isadat, rate; 713 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 714 struct snd_pcm_runtime *runtime = substream->runtime; 715 716 if (!rme32->fullduplex_mode) { 717 runtime->dma_area = (void __force *)rme32->iobase + 718 RME32_IO_DATA_BUFFER; 719 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER; 720 runtime->dma_bytes = RME32_BUFFER_SIZE; 721 } 722 723 spin_lock_irq(&rme32->lock); 724 /* enable AutoSync for record-preparing */ 725 rme32->wcreg |= RME32_WCR_AUTOSYNC; 726 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 727 728 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) { 729 spin_unlock_irq(&rme32->lock); 730 return err; 731 } 732 if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) { 733 spin_unlock_irq(&rme32->lock); 734 return err; 735 } 736 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) { 737 if ((int)params_rate(params) != rate) { 738 spin_unlock_irq(&rme32->lock); 739 return -EIO; 740 } 741 if ((isadat && runtime->hw.channels_min == 2) || 742 (!isadat && runtime->hw.channels_min == 8)) { 743 spin_unlock_irq(&rme32->lock); 744 return -EIO; 745 } 746 } 747 /* AutoSync off for recording */ 748 rme32->wcreg &= ~RME32_WCR_AUTOSYNC; 749 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 750 751 snd_rme32_setframelog(rme32, params_channels(params), 0); 752 if (rme32->playback_periodsize != 0) { 753 if (params_period_size(params) << rme32->capture_frlog != 754 rme32->playback_periodsize) { 755 spin_unlock_irq(&rme32->lock); 756 return -EBUSY; 757 } 758 } 759 rme32->capture_periodsize = 760 params_period_size(params) << rme32->capture_frlog; 761 spin_unlock_irq(&rme32->lock); 762 763 return 0; 764 } 765 766 static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause) 767 { 768 if (!from_pause) { 769 writel(0, rme32->iobase + RME32_IO_RESET_POS); 770 } 771 772 rme32->wcreg |= RME32_WCR_START; 773 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 774 } 775 776 static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause) 777 { 778 /* 779 * Check if there is an unconfirmed IRQ, if so confirm it, or else 780 * the hardware will not stop generating interrupts 781 */ 782 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); 783 if (rme32->rcreg & RME32_RCR_IRQ) { 784 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ); 785 } 786 rme32->wcreg &= ~RME32_WCR_START; 787 if (rme32->wcreg & RME32_WCR_SEL) 788 rme32->wcreg |= RME32_WCR_MUTE; 789 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 790 if (! to_pause) 791 writel(0, rme32->iobase + RME32_IO_RESET_POS); 792 } 793 794 static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id) 795 { 796 struct rme32 *rme32 = (struct rme32 *) dev_id; 797 798 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); 799 if (!(rme32->rcreg & RME32_RCR_IRQ)) { 800 return IRQ_NONE; 801 } else { 802 if (rme32->capture_substream) { 803 snd_pcm_period_elapsed(rme32->capture_substream); 804 } 805 if (rme32->playback_substream) { 806 snd_pcm_period_elapsed(rme32->playback_substream); 807 } 808 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ); 809 } 810 return IRQ_HANDLED; 811 } 812 813 static const unsigned int period_bytes[] = { RME32_BLOCK_SIZE }; 814 815 static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { 816 .count = ARRAY_SIZE(period_bytes), 817 .list = period_bytes, 818 .mask = 0 819 }; 820 821 static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime) 822 { 823 if (! rme32->fullduplex_mode) { 824 snd_pcm_hw_constraint_single(runtime, 825 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 826 RME32_BUFFER_SIZE); 827 snd_pcm_hw_constraint_list(runtime, 0, 828 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 829 &hw_constraints_period_bytes); 830 } 831 } 832 833 static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream) 834 { 835 int rate, dummy; 836 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 837 struct snd_pcm_runtime *runtime = substream->runtime; 838 839 snd_pcm_set_sync(substream); 840 841 spin_lock_irq(&rme32->lock); 842 if (rme32->playback_substream != NULL) { 843 spin_unlock_irq(&rme32->lock); 844 return -EBUSY; 845 } 846 rme32->wcreg &= ~RME32_WCR_ADAT; 847 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 848 rme32->playback_substream = substream; 849 spin_unlock_irq(&rme32->lock); 850 851 if (rme32->fullduplex_mode) 852 runtime->hw = snd_rme32_spdif_fd_info; 853 else 854 runtime->hw = snd_rme32_spdif_info; 855 if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) { 856 runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; 857 runtime->hw.rate_max = 96000; 858 } 859 if ((rme32->rcreg & RME32_RCR_KMODE) && 860 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) { 861 /* AutoSync */ 862 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 863 runtime->hw.rate_min = rate; 864 runtime->hw.rate_max = rate; 865 } 866 867 snd_rme32_set_buffer_constraint(rme32, runtime); 868 869 rme32->wcreg_spdif_stream = rme32->wcreg_spdif; 870 rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 871 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE | 872 SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id); 873 return 0; 874 } 875 876 static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream) 877 { 878 int isadat, rate; 879 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 880 struct snd_pcm_runtime *runtime = substream->runtime; 881 882 snd_pcm_set_sync(substream); 883 884 spin_lock_irq(&rme32->lock); 885 if (rme32->capture_substream != NULL) { 886 spin_unlock_irq(&rme32->lock); 887 return -EBUSY; 888 } 889 rme32->capture_substream = substream; 890 spin_unlock_irq(&rme32->lock); 891 892 if (rme32->fullduplex_mode) 893 runtime->hw = snd_rme32_spdif_fd_info; 894 else 895 runtime->hw = snd_rme32_spdif_info; 896 if (RME32_PRO_WITH_8414(rme32)) { 897 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; 898 runtime->hw.rate_max = 96000; 899 } 900 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) { 901 if (isadat) { 902 return -EIO; 903 } 904 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 905 runtime->hw.rate_min = rate; 906 runtime->hw.rate_max = rate; 907 } 908 909 snd_rme32_set_buffer_constraint(rme32, runtime); 910 911 return 0; 912 } 913 914 static int 915 snd_rme32_playback_adat_open(struct snd_pcm_substream *substream) 916 { 917 int rate, dummy; 918 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 919 struct snd_pcm_runtime *runtime = substream->runtime; 920 921 snd_pcm_set_sync(substream); 922 923 spin_lock_irq(&rme32->lock); 924 if (rme32->playback_substream != NULL) { 925 spin_unlock_irq(&rme32->lock); 926 return -EBUSY; 927 } 928 rme32->wcreg |= RME32_WCR_ADAT; 929 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 930 rme32->playback_substream = substream; 931 spin_unlock_irq(&rme32->lock); 932 933 if (rme32->fullduplex_mode) 934 runtime->hw = snd_rme32_adat_fd_info; 935 else 936 runtime->hw = snd_rme32_adat_info; 937 if ((rme32->rcreg & RME32_RCR_KMODE) && 938 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) { 939 /* AutoSync */ 940 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 941 runtime->hw.rate_min = rate; 942 runtime->hw.rate_max = rate; 943 } 944 945 snd_rme32_set_buffer_constraint(rme32, runtime); 946 return 0; 947 } 948 949 static int 950 snd_rme32_capture_adat_open(struct snd_pcm_substream *substream) 951 { 952 int isadat, rate; 953 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 954 struct snd_pcm_runtime *runtime = substream->runtime; 955 956 if (rme32->fullduplex_mode) 957 runtime->hw = snd_rme32_adat_fd_info; 958 else 959 runtime->hw = snd_rme32_adat_info; 960 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) { 961 if (!isadat) { 962 return -EIO; 963 } 964 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 965 runtime->hw.rate_min = rate; 966 runtime->hw.rate_max = rate; 967 } 968 969 snd_pcm_set_sync(substream); 970 971 spin_lock_irq(&rme32->lock); 972 if (rme32->capture_substream != NULL) { 973 spin_unlock_irq(&rme32->lock); 974 return -EBUSY; 975 } 976 rme32->capture_substream = substream; 977 spin_unlock_irq(&rme32->lock); 978 979 snd_rme32_set_buffer_constraint(rme32, runtime); 980 return 0; 981 } 982 983 static int snd_rme32_playback_close(struct snd_pcm_substream *substream) 984 { 985 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 986 int spdif = 0; 987 988 spin_lock_irq(&rme32->lock); 989 rme32->playback_substream = NULL; 990 rme32->playback_periodsize = 0; 991 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0; 992 spin_unlock_irq(&rme32->lock); 993 if (spdif) { 994 rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 995 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE | 996 SNDRV_CTL_EVENT_MASK_INFO, 997 &rme32->spdif_ctl->id); 998 } 999 return 0; 1000 } 1001 1002 static int snd_rme32_capture_close(struct snd_pcm_substream *substream) 1003 { 1004 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1005 1006 spin_lock_irq(&rme32->lock); 1007 rme32->capture_substream = NULL; 1008 rme32->capture_periodsize = 0; 1009 spin_unlock_irq(&rme32->lock); 1010 return 0; 1011 } 1012 1013 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream) 1014 { 1015 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1016 1017 spin_lock_irq(&rme32->lock); 1018 if (rme32->fullduplex_mode) { 1019 memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm)); 1020 rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE; 1021 rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1022 } else { 1023 writel(0, rme32->iobase + RME32_IO_RESET_POS); 1024 } 1025 if (rme32->wcreg & RME32_WCR_SEL) 1026 rme32->wcreg &= ~RME32_WCR_MUTE; 1027 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1028 spin_unlock_irq(&rme32->lock); 1029 return 0; 1030 } 1031 1032 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream) 1033 { 1034 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1035 1036 spin_lock_irq(&rme32->lock); 1037 if (rme32->fullduplex_mode) { 1038 memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm)); 1039 rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE; 1040 rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2; 1041 rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1042 } else { 1043 writel(0, rme32->iobase + RME32_IO_RESET_POS); 1044 } 1045 spin_unlock_irq(&rme32->lock); 1046 return 0; 1047 } 1048 1049 static int 1050 snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1051 { 1052 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1053 struct snd_pcm_substream *s; 1054 1055 spin_lock(&rme32->lock); 1056 snd_pcm_group_for_each_entry(s, substream) { 1057 if (s != rme32->playback_substream && 1058 s != rme32->capture_substream) 1059 continue; 1060 switch (cmd) { 1061 case SNDRV_PCM_TRIGGER_START: 1062 rme32->running |= (1 << s->stream); 1063 if (rme32->fullduplex_mode) { 1064 /* remember the current DMA position */ 1065 if (s == rme32->playback_substream) { 1066 rme32->playback_pcm.hw_io = 1067 rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); 1068 } else { 1069 rme32->capture_pcm.hw_io = 1070 rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); 1071 } 1072 } 1073 break; 1074 case SNDRV_PCM_TRIGGER_STOP: 1075 rme32->running &= ~(1 << s->stream); 1076 break; 1077 } 1078 snd_pcm_trigger_done(s, substream); 1079 } 1080 1081 switch (cmd) { 1082 case SNDRV_PCM_TRIGGER_START: 1083 if (rme32->running && ! RME32_ISWORKING(rme32)) 1084 snd_rme32_pcm_start(rme32, 0); 1085 break; 1086 case SNDRV_PCM_TRIGGER_STOP: 1087 if (! rme32->running && RME32_ISWORKING(rme32)) 1088 snd_rme32_pcm_stop(rme32, 0); 1089 break; 1090 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1091 if (rme32->running && RME32_ISWORKING(rme32)) 1092 snd_rme32_pcm_stop(rme32, 1); 1093 break; 1094 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1095 if (rme32->running && ! RME32_ISWORKING(rme32)) 1096 snd_rme32_pcm_start(rme32, 1); 1097 break; 1098 } 1099 spin_unlock(&rme32->lock); 1100 return 0; 1101 } 1102 1103 /* pointer callback for halfduplex mode */ 1104 static snd_pcm_uframes_t 1105 snd_rme32_playback_pointer(struct snd_pcm_substream *substream) 1106 { 1107 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1108 return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog; 1109 } 1110 1111 static snd_pcm_uframes_t 1112 snd_rme32_capture_pointer(struct snd_pcm_substream *substream) 1113 { 1114 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1115 return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog; 1116 } 1117 1118 1119 /* ack and pointer callbacks for fullduplex mode */ 1120 static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream, 1121 struct snd_pcm_indirect *rec, size_t bytes) 1122 { 1123 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1124 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, 1125 substream->runtime->dma_area + rec->sw_data, bytes); 1126 } 1127 1128 static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream) 1129 { 1130 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1131 struct snd_pcm_indirect *rec, *cprec; 1132 1133 rec = &rme32->playback_pcm; 1134 cprec = &rme32->capture_pcm; 1135 spin_lock(&rme32->lock); 1136 rec->hw_queue_size = RME32_BUFFER_SIZE; 1137 if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE)) 1138 rec->hw_queue_size -= cprec->hw_ready; 1139 spin_unlock(&rme32->lock); 1140 return snd_pcm_indirect_playback_transfer(substream, rec, 1141 snd_rme32_pb_trans_copy); 1142 } 1143 1144 static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream, 1145 struct snd_pcm_indirect *rec, size_t bytes) 1146 { 1147 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1148 memcpy_fromio(substream->runtime->dma_area + rec->sw_data, 1149 rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, 1150 bytes); 1151 } 1152 1153 static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream) 1154 { 1155 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1156 return snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm, 1157 snd_rme32_cp_trans_copy); 1158 } 1159 1160 static snd_pcm_uframes_t 1161 snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream) 1162 { 1163 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1164 return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm, 1165 snd_rme32_pcm_byteptr(rme32)); 1166 } 1167 1168 static snd_pcm_uframes_t 1169 snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream) 1170 { 1171 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1172 return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm, 1173 snd_rme32_pcm_byteptr(rme32)); 1174 } 1175 1176 /* for halfduplex mode */ 1177 static const struct snd_pcm_ops snd_rme32_playback_spdif_ops = { 1178 .open = snd_rme32_playback_spdif_open, 1179 .close = snd_rme32_playback_close, 1180 .hw_params = snd_rme32_playback_hw_params, 1181 .prepare = snd_rme32_playback_prepare, 1182 .trigger = snd_rme32_pcm_trigger, 1183 .pointer = snd_rme32_playback_pointer, 1184 .copy_user = snd_rme32_playback_copy, 1185 .copy_kernel = snd_rme32_playback_copy_kernel, 1186 .fill_silence = snd_rme32_playback_silence, 1187 .mmap = snd_pcm_lib_mmap_iomem, 1188 }; 1189 1190 static const struct snd_pcm_ops snd_rme32_capture_spdif_ops = { 1191 .open = snd_rme32_capture_spdif_open, 1192 .close = snd_rme32_capture_close, 1193 .hw_params = snd_rme32_capture_hw_params, 1194 .prepare = snd_rme32_capture_prepare, 1195 .trigger = snd_rme32_pcm_trigger, 1196 .pointer = snd_rme32_capture_pointer, 1197 .copy_user = snd_rme32_capture_copy, 1198 .copy_kernel = snd_rme32_capture_copy_kernel, 1199 .mmap = snd_pcm_lib_mmap_iomem, 1200 }; 1201 1202 static const struct snd_pcm_ops snd_rme32_playback_adat_ops = { 1203 .open = snd_rme32_playback_adat_open, 1204 .close = snd_rme32_playback_close, 1205 .hw_params = snd_rme32_playback_hw_params, 1206 .prepare = snd_rme32_playback_prepare, 1207 .trigger = snd_rme32_pcm_trigger, 1208 .pointer = snd_rme32_playback_pointer, 1209 .copy_user = snd_rme32_playback_copy, 1210 .copy_kernel = snd_rme32_playback_copy_kernel, 1211 .fill_silence = snd_rme32_playback_silence, 1212 .mmap = snd_pcm_lib_mmap_iomem, 1213 }; 1214 1215 static const struct snd_pcm_ops snd_rme32_capture_adat_ops = { 1216 .open = snd_rme32_capture_adat_open, 1217 .close = snd_rme32_capture_close, 1218 .hw_params = snd_rme32_capture_hw_params, 1219 .prepare = snd_rme32_capture_prepare, 1220 .trigger = snd_rme32_pcm_trigger, 1221 .pointer = snd_rme32_capture_pointer, 1222 .copy_user = snd_rme32_capture_copy, 1223 .copy_kernel = snd_rme32_capture_copy_kernel, 1224 .mmap = snd_pcm_lib_mmap_iomem, 1225 }; 1226 1227 /* for fullduplex mode */ 1228 static const struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = { 1229 .open = snd_rme32_playback_spdif_open, 1230 .close = snd_rme32_playback_close, 1231 .hw_params = snd_rme32_playback_hw_params, 1232 .prepare = snd_rme32_playback_prepare, 1233 .trigger = snd_rme32_pcm_trigger, 1234 .pointer = snd_rme32_playback_fd_pointer, 1235 .ack = snd_rme32_playback_fd_ack, 1236 }; 1237 1238 static const struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = { 1239 .open = snd_rme32_capture_spdif_open, 1240 .close = snd_rme32_capture_close, 1241 .hw_params = snd_rme32_capture_hw_params, 1242 .prepare = snd_rme32_capture_prepare, 1243 .trigger = snd_rme32_pcm_trigger, 1244 .pointer = snd_rme32_capture_fd_pointer, 1245 .ack = snd_rme32_capture_fd_ack, 1246 }; 1247 1248 static const struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = { 1249 .open = snd_rme32_playback_adat_open, 1250 .close = snd_rme32_playback_close, 1251 .hw_params = snd_rme32_playback_hw_params, 1252 .prepare = snd_rme32_playback_prepare, 1253 .trigger = snd_rme32_pcm_trigger, 1254 .pointer = snd_rme32_playback_fd_pointer, 1255 .ack = snd_rme32_playback_fd_ack, 1256 }; 1257 1258 static const struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = { 1259 .open = snd_rme32_capture_adat_open, 1260 .close = snd_rme32_capture_close, 1261 .hw_params = snd_rme32_capture_hw_params, 1262 .prepare = snd_rme32_capture_prepare, 1263 .trigger = snd_rme32_pcm_trigger, 1264 .pointer = snd_rme32_capture_fd_pointer, 1265 .ack = snd_rme32_capture_fd_ack, 1266 }; 1267 1268 static void snd_rme32_free(void *private_data) 1269 { 1270 struct rme32 *rme32 = (struct rme32 *) private_data; 1271 1272 if (rme32 == NULL) { 1273 return; 1274 } 1275 if (rme32->irq >= 0) { 1276 snd_rme32_pcm_stop(rme32, 0); 1277 free_irq(rme32->irq, (void *) rme32); 1278 rme32->irq = -1; 1279 } 1280 if (rme32->iobase) { 1281 iounmap(rme32->iobase); 1282 rme32->iobase = NULL; 1283 } 1284 if (rme32->port) { 1285 pci_release_regions(rme32->pci); 1286 rme32->port = 0; 1287 } 1288 pci_disable_device(rme32->pci); 1289 } 1290 1291 static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm) 1292 { 1293 struct rme32 *rme32 = (struct rme32 *) pcm->private_data; 1294 rme32->spdif_pcm = NULL; 1295 } 1296 1297 static void 1298 snd_rme32_free_adat_pcm(struct snd_pcm *pcm) 1299 { 1300 struct rme32 *rme32 = (struct rme32 *) pcm->private_data; 1301 rme32->adat_pcm = NULL; 1302 } 1303 1304 static int snd_rme32_create(struct rme32 *rme32) 1305 { 1306 struct pci_dev *pci = rme32->pci; 1307 int err; 1308 1309 rme32->irq = -1; 1310 spin_lock_init(&rme32->lock); 1311 1312 if ((err = pci_enable_device(pci)) < 0) 1313 return err; 1314 1315 if ((err = pci_request_regions(pci, "RME32")) < 0) 1316 return err; 1317 rme32->port = pci_resource_start(rme32->pci, 0); 1318 1319 rme32->iobase = ioremap(rme32->port, RME32_IO_SIZE); 1320 if (!rme32->iobase) { 1321 dev_err(rme32->card->dev, 1322 "unable to remap memory region 0x%lx-0x%lx\n", 1323 rme32->port, rme32->port + RME32_IO_SIZE - 1); 1324 return -ENOMEM; 1325 } 1326 1327 if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_SHARED, 1328 KBUILD_MODNAME, rme32)) { 1329 dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq); 1330 return -EBUSY; 1331 } 1332 rme32->irq = pci->irq; 1333 rme32->card->sync_irq = rme32->irq; 1334 1335 /* read the card's revision number */ 1336 pci_read_config_byte(pci, 8, &rme32->rev); 1337 1338 /* set up ALSA pcm device for S/PDIF */ 1339 if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) { 1340 return err; 1341 } 1342 rme32->spdif_pcm->private_data = rme32; 1343 rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm; 1344 strcpy(rme32->spdif_pcm->name, "Digi32 IEC958"); 1345 if (rme32->fullduplex_mode) { 1346 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1347 &snd_rme32_playback_spdif_fd_ops); 1348 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, 1349 &snd_rme32_capture_spdif_fd_ops); 1350 snd_pcm_set_managed_buffer_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS, 1351 NULL, 0, RME32_MID_BUFFER_SIZE); 1352 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 1353 } else { 1354 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1355 &snd_rme32_playback_spdif_ops); 1356 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, 1357 &snd_rme32_capture_spdif_ops); 1358 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX; 1359 } 1360 1361 /* set up ALSA pcm device for ADAT */ 1362 if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) || 1363 (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) { 1364 /* ADAT is not available on DIGI32 and DIGI32 Pro */ 1365 rme32->adat_pcm = NULL; 1366 } 1367 else { 1368 if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1, 1369 1, 1, &rme32->adat_pcm)) < 0) 1370 { 1371 return err; 1372 } 1373 rme32->adat_pcm->private_data = rme32; 1374 rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm; 1375 strcpy(rme32->adat_pcm->name, "Digi32 ADAT"); 1376 if (rme32->fullduplex_mode) { 1377 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1378 &snd_rme32_playback_adat_fd_ops); 1379 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, 1380 &snd_rme32_capture_adat_fd_ops); 1381 snd_pcm_set_managed_buffer_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS, 1382 NULL, 1383 0, RME32_MID_BUFFER_SIZE); 1384 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 1385 } else { 1386 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1387 &snd_rme32_playback_adat_ops); 1388 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, 1389 &snd_rme32_capture_adat_ops); 1390 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX; 1391 } 1392 } 1393 1394 1395 rme32->playback_periodsize = 0; 1396 rme32->capture_periodsize = 0; 1397 1398 /* make sure playback/capture is stopped, if by some reason active */ 1399 snd_rme32_pcm_stop(rme32, 0); 1400 1401 /* reset DAC */ 1402 snd_rme32_reset_dac(rme32); 1403 1404 /* reset buffer pointer */ 1405 writel(0, rme32->iobase + RME32_IO_RESET_POS); 1406 1407 /* set default values in registers */ 1408 rme32->wcreg = RME32_WCR_SEL | /* normal playback */ 1409 RME32_WCR_INP_0 | /* input select */ 1410 RME32_WCR_MUTE; /* muting on */ 1411 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1412 1413 1414 /* init switch interface */ 1415 if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) { 1416 return err; 1417 } 1418 1419 /* init proc interface */ 1420 snd_rme32_proc_init(rme32); 1421 1422 rme32->capture_substream = NULL; 1423 rme32->playback_substream = NULL; 1424 1425 return 0; 1426 } 1427 1428 /* 1429 * proc interface 1430 */ 1431 1432 static void 1433 snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer) 1434 { 1435 int n; 1436 struct rme32 *rme32 = (struct rme32 *) entry->private_data; 1437 1438 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); 1439 1440 snd_iprintf(buffer, rme32->card->longname); 1441 snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1); 1442 1443 snd_iprintf(buffer, "\nGeneral settings\n"); 1444 if (rme32->fullduplex_mode) 1445 snd_iprintf(buffer, " Full-duplex mode\n"); 1446 else 1447 snd_iprintf(buffer, " Half-duplex mode\n"); 1448 if (RME32_PRO_WITH_8414(rme32)) { 1449 snd_iprintf(buffer, " receiver: CS8414\n"); 1450 } else { 1451 snd_iprintf(buffer, " receiver: CS8412\n"); 1452 } 1453 if (rme32->wcreg & RME32_WCR_MODE24) { 1454 snd_iprintf(buffer, " format: 24 bit"); 1455 } else { 1456 snd_iprintf(buffer, " format: 16 bit"); 1457 } 1458 if (rme32->wcreg & RME32_WCR_MONO) { 1459 snd_iprintf(buffer, ", Mono\n"); 1460 } else { 1461 snd_iprintf(buffer, ", Stereo\n"); 1462 } 1463 1464 snd_iprintf(buffer, "\nInput settings\n"); 1465 switch (snd_rme32_getinputtype(rme32)) { 1466 case RME32_INPUT_OPTICAL: 1467 snd_iprintf(buffer, " input: optical"); 1468 break; 1469 case RME32_INPUT_COAXIAL: 1470 snd_iprintf(buffer, " input: coaxial"); 1471 break; 1472 case RME32_INPUT_INTERNAL: 1473 snd_iprintf(buffer, " input: internal"); 1474 break; 1475 case RME32_INPUT_XLR: 1476 snd_iprintf(buffer, " input: XLR"); 1477 break; 1478 } 1479 if (snd_rme32_capture_getrate(rme32, &n) < 0) { 1480 snd_iprintf(buffer, "\n sample rate: no valid signal\n"); 1481 } else { 1482 if (n) { 1483 snd_iprintf(buffer, " (8 channels)\n"); 1484 } else { 1485 snd_iprintf(buffer, " (2 channels)\n"); 1486 } 1487 snd_iprintf(buffer, " sample rate: %d Hz\n", 1488 snd_rme32_capture_getrate(rme32, &n)); 1489 } 1490 1491 snd_iprintf(buffer, "\nOutput settings\n"); 1492 if (rme32->wcreg & RME32_WCR_SEL) { 1493 snd_iprintf(buffer, " output signal: normal playback"); 1494 } else { 1495 snd_iprintf(buffer, " output signal: same as input"); 1496 } 1497 if (rme32->wcreg & RME32_WCR_MUTE) { 1498 snd_iprintf(buffer, " (muted)\n"); 1499 } else { 1500 snd_iprintf(buffer, "\n"); 1501 } 1502 1503 /* master output frequency */ 1504 if (! 1505 ((!(rme32->wcreg & RME32_WCR_FREQ_0)) 1506 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) { 1507 snd_iprintf(buffer, " sample rate: %d Hz\n", 1508 snd_rme32_playback_getrate(rme32)); 1509 } 1510 if (rme32->rcreg & RME32_RCR_KMODE) { 1511 snd_iprintf(buffer, " sample clock source: AutoSync\n"); 1512 } else { 1513 snd_iprintf(buffer, " sample clock source: Internal\n"); 1514 } 1515 if (rme32->wcreg & RME32_WCR_PRO) { 1516 snd_iprintf(buffer, " format: AES/EBU (professional)\n"); 1517 } else { 1518 snd_iprintf(buffer, " format: IEC958 (consumer)\n"); 1519 } 1520 if (rme32->wcreg & RME32_WCR_EMP) { 1521 snd_iprintf(buffer, " emphasis: on\n"); 1522 } else { 1523 snd_iprintf(buffer, " emphasis: off\n"); 1524 } 1525 } 1526 1527 static void snd_rme32_proc_init(struct rme32 *rme32) 1528 { 1529 snd_card_ro_proc_new(rme32->card, "rme32", rme32, snd_rme32_proc_read); 1530 } 1531 1532 /* 1533 * control interface 1534 */ 1535 1536 #define snd_rme32_info_loopback_control snd_ctl_boolean_mono_info 1537 1538 static int 1539 snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol, 1540 struct snd_ctl_elem_value *ucontrol) 1541 { 1542 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1543 1544 spin_lock_irq(&rme32->lock); 1545 ucontrol->value.integer.value[0] = 1546 rme32->wcreg & RME32_WCR_SEL ? 0 : 1; 1547 spin_unlock_irq(&rme32->lock); 1548 return 0; 1549 } 1550 static int 1551 snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol, 1552 struct snd_ctl_elem_value *ucontrol) 1553 { 1554 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1555 unsigned int val; 1556 int change; 1557 1558 val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL; 1559 spin_lock_irq(&rme32->lock); 1560 val = (rme32->wcreg & ~RME32_WCR_SEL) | val; 1561 change = val != rme32->wcreg; 1562 if (ucontrol->value.integer.value[0]) 1563 val &= ~RME32_WCR_MUTE; 1564 else 1565 val |= RME32_WCR_MUTE; 1566 rme32->wcreg = val; 1567 writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1568 spin_unlock_irq(&rme32->lock); 1569 return change; 1570 } 1571 1572 static int 1573 snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol, 1574 struct snd_ctl_elem_info *uinfo) 1575 { 1576 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1577 static const char * const texts[4] = { 1578 "Optical", "Coaxial", "Internal", "XLR" 1579 }; 1580 int num_items; 1581 1582 switch (rme32->pci->device) { 1583 case PCI_DEVICE_ID_RME_DIGI32: 1584 case PCI_DEVICE_ID_RME_DIGI32_8: 1585 num_items = 3; 1586 break; 1587 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1588 num_items = 4; 1589 break; 1590 default: 1591 snd_BUG(); 1592 return -EINVAL; 1593 } 1594 return snd_ctl_enum_info(uinfo, 1, num_items, texts); 1595 } 1596 static int 1597 snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol, 1598 struct snd_ctl_elem_value *ucontrol) 1599 { 1600 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1601 unsigned int items = 3; 1602 1603 spin_lock_irq(&rme32->lock); 1604 ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32); 1605 1606 switch (rme32->pci->device) { 1607 case PCI_DEVICE_ID_RME_DIGI32: 1608 case PCI_DEVICE_ID_RME_DIGI32_8: 1609 items = 3; 1610 break; 1611 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1612 items = 4; 1613 break; 1614 default: 1615 snd_BUG(); 1616 break; 1617 } 1618 if (ucontrol->value.enumerated.item[0] >= items) { 1619 ucontrol->value.enumerated.item[0] = items - 1; 1620 } 1621 1622 spin_unlock_irq(&rme32->lock); 1623 return 0; 1624 } 1625 static int 1626 snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol, 1627 struct snd_ctl_elem_value *ucontrol) 1628 { 1629 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1630 unsigned int val; 1631 int change, items = 3; 1632 1633 switch (rme32->pci->device) { 1634 case PCI_DEVICE_ID_RME_DIGI32: 1635 case PCI_DEVICE_ID_RME_DIGI32_8: 1636 items = 3; 1637 break; 1638 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1639 items = 4; 1640 break; 1641 default: 1642 snd_BUG(); 1643 break; 1644 } 1645 val = ucontrol->value.enumerated.item[0] % items; 1646 1647 spin_lock_irq(&rme32->lock); 1648 change = val != (unsigned int)snd_rme32_getinputtype(rme32); 1649 snd_rme32_setinputtype(rme32, val); 1650 spin_unlock_irq(&rme32->lock); 1651 return change; 1652 } 1653 1654 static int 1655 snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol, 1656 struct snd_ctl_elem_info *uinfo) 1657 { 1658 static const char * const texts[4] = { "AutoSync", 1659 "Internal 32.0kHz", 1660 "Internal 44.1kHz", 1661 "Internal 48.0kHz" }; 1662 1663 return snd_ctl_enum_info(uinfo, 1, 4, texts); 1664 } 1665 static int 1666 snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol, 1667 struct snd_ctl_elem_value *ucontrol) 1668 { 1669 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1670 1671 spin_lock_irq(&rme32->lock); 1672 ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32); 1673 spin_unlock_irq(&rme32->lock); 1674 return 0; 1675 } 1676 static int 1677 snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol, 1678 struct snd_ctl_elem_value *ucontrol) 1679 { 1680 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1681 unsigned int val; 1682 int change; 1683 1684 val = ucontrol->value.enumerated.item[0] % 3; 1685 spin_lock_irq(&rme32->lock); 1686 change = val != (unsigned int)snd_rme32_getclockmode(rme32); 1687 snd_rme32_setclockmode(rme32, val); 1688 spin_unlock_irq(&rme32->lock); 1689 return change; 1690 } 1691 1692 static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes) 1693 { 1694 u32 val = 0; 1695 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0; 1696 if (val & RME32_WCR_PRO) 1697 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0; 1698 else 1699 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0; 1700 return val; 1701 } 1702 1703 static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val) 1704 { 1705 aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0); 1706 if (val & RME32_WCR_PRO) 1707 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 1708 else 1709 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 1710 } 1711 1712 static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol, 1713 struct snd_ctl_elem_info *uinfo) 1714 { 1715 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1716 uinfo->count = 1; 1717 return 0; 1718 } 1719 1720 static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol, 1721 struct snd_ctl_elem_value *ucontrol) 1722 { 1723 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1724 1725 snd_rme32_convert_to_aes(&ucontrol->value.iec958, 1726 rme32->wcreg_spdif); 1727 return 0; 1728 } 1729 1730 static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol, 1731 struct snd_ctl_elem_value *ucontrol) 1732 { 1733 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1734 int change; 1735 u32 val; 1736 1737 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); 1738 spin_lock_irq(&rme32->lock); 1739 change = val != rme32->wcreg_spdif; 1740 rme32->wcreg_spdif = val; 1741 spin_unlock_irq(&rme32->lock); 1742 return change; 1743 } 1744 1745 static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol, 1746 struct snd_ctl_elem_info *uinfo) 1747 { 1748 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1749 uinfo->count = 1; 1750 return 0; 1751 } 1752 1753 static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol, 1754 struct snd_ctl_elem_value * 1755 ucontrol) 1756 { 1757 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1758 1759 snd_rme32_convert_to_aes(&ucontrol->value.iec958, 1760 rme32->wcreg_spdif_stream); 1761 return 0; 1762 } 1763 1764 static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol, 1765 struct snd_ctl_elem_value * 1766 ucontrol) 1767 { 1768 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1769 int change; 1770 u32 val; 1771 1772 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); 1773 spin_lock_irq(&rme32->lock); 1774 change = val != rme32->wcreg_spdif_stream; 1775 rme32->wcreg_spdif_stream = val; 1776 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); 1777 rme32->wcreg |= val; 1778 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1779 spin_unlock_irq(&rme32->lock); 1780 return change; 1781 } 1782 1783 static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol, 1784 struct snd_ctl_elem_info *uinfo) 1785 { 1786 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1787 uinfo->count = 1; 1788 return 0; 1789 } 1790 1791 static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol, 1792 struct snd_ctl_elem_value * 1793 ucontrol) 1794 { 1795 ucontrol->value.iec958.status[0] = kcontrol->private_value; 1796 return 0; 1797 } 1798 1799 static const struct snd_kcontrol_new snd_rme32_controls[] = { 1800 { 1801 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1802 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1803 .info = snd_rme32_control_spdif_info, 1804 .get = snd_rme32_control_spdif_get, 1805 .put = snd_rme32_control_spdif_put 1806 }, 1807 { 1808 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 1809 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1810 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM), 1811 .info = snd_rme32_control_spdif_stream_info, 1812 .get = snd_rme32_control_spdif_stream_get, 1813 .put = snd_rme32_control_spdif_stream_put 1814 }, 1815 { 1816 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1817 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1818 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), 1819 .info = snd_rme32_control_spdif_mask_info, 1820 .get = snd_rme32_control_spdif_mask_get, 1821 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS 1822 }, 1823 { 1824 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1825 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1826 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK), 1827 .info = snd_rme32_control_spdif_mask_info, 1828 .get = snd_rme32_control_spdif_mask_get, 1829 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS 1830 }, 1831 { 1832 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1833 .name = "Input Connector", 1834 .info = snd_rme32_info_inputtype_control, 1835 .get = snd_rme32_get_inputtype_control, 1836 .put = snd_rme32_put_inputtype_control 1837 }, 1838 { 1839 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1840 .name = "Loopback Input", 1841 .info = snd_rme32_info_loopback_control, 1842 .get = snd_rme32_get_loopback_control, 1843 .put = snd_rme32_put_loopback_control 1844 }, 1845 { 1846 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1847 .name = "Sample Clock Source", 1848 .info = snd_rme32_info_clockmode_control, 1849 .get = snd_rme32_get_clockmode_control, 1850 .put = snd_rme32_put_clockmode_control 1851 } 1852 }; 1853 1854 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32) 1855 { 1856 int idx, err; 1857 struct snd_kcontrol *kctl; 1858 1859 for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) { 1860 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0) 1861 return err; 1862 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 1863 rme32->spdif_ctl = kctl; 1864 } 1865 1866 return 0; 1867 } 1868 1869 /* 1870 * Card initialisation 1871 */ 1872 1873 static void snd_rme32_card_free(struct snd_card *card) 1874 { 1875 snd_rme32_free(card->private_data); 1876 } 1877 1878 static int 1879 snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1880 { 1881 static int dev; 1882 struct rme32 *rme32; 1883 struct snd_card *card; 1884 int err; 1885 1886 if (dev >= SNDRV_CARDS) { 1887 return -ENODEV; 1888 } 1889 if (!enable[dev]) { 1890 dev++; 1891 return -ENOENT; 1892 } 1893 1894 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1895 sizeof(struct rme32), &card); 1896 if (err < 0) 1897 return err; 1898 card->private_free = snd_rme32_card_free; 1899 rme32 = (struct rme32 *) card->private_data; 1900 rme32->card = card; 1901 rme32->pci = pci; 1902 if (fullduplex[dev]) 1903 rme32->fullduplex_mode = 1; 1904 if ((err = snd_rme32_create(rme32)) < 0) { 1905 snd_card_free(card); 1906 return err; 1907 } 1908 1909 strcpy(card->driver, "Digi32"); 1910 switch (rme32->pci->device) { 1911 case PCI_DEVICE_ID_RME_DIGI32: 1912 strcpy(card->shortname, "RME Digi32"); 1913 break; 1914 case PCI_DEVICE_ID_RME_DIGI32_8: 1915 strcpy(card->shortname, "RME Digi32/8"); 1916 break; 1917 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1918 strcpy(card->shortname, "RME Digi32 PRO"); 1919 break; 1920 } 1921 sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d", 1922 card->shortname, rme32->rev, rme32->port, rme32->irq); 1923 1924 if ((err = snd_card_register(card)) < 0) { 1925 snd_card_free(card); 1926 return err; 1927 } 1928 pci_set_drvdata(pci, card); 1929 dev++; 1930 return 0; 1931 } 1932 1933 static void snd_rme32_remove(struct pci_dev *pci) 1934 { 1935 snd_card_free(pci_get_drvdata(pci)); 1936 } 1937 1938 static struct pci_driver rme32_driver = { 1939 .name = KBUILD_MODNAME, 1940 .id_table = snd_rme32_ids, 1941 .probe = snd_rme32_probe, 1942 .remove = snd_rme32_remove, 1943 }; 1944 1945 module_pci_driver(rme32_driver); 1946