1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_CSR_H 7 #define _ASM_RISCV_CSR_H 8 9 #include <asm/asm.h> 10 #include <linux/const.h> 11 12 /* Status register flags */ 13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ 15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ 17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ 19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 20 21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 22 #define SR_FS_OFF _AC(0x00000000, UL) 23 #define SR_FS_INITIAL _AC(0x00002000, UL) 24 #define SR_FS_CLEAN _AC(0x00004000, UL) 25 #define SR_FS_DIRTY _AC(0x00006000, UL) 26 27 #define SR_XS _AC(0x00018000, UL) /* Extension Status */ 28 #define SR_XS_OFF _AC(0x00000000, UL) 29 #define SR_XS_INITIAL _AC(0x00008000, UL) 30 #define SR_XS_CLEAN _AC(0x00010000, UL) 31 #define SR_XS_DIRTY _AC(0x00018000, UL) 32 33 #ifndef CONFIG_64BIT 34 #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ 35 #else 36 #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ 37 #endif 38 39 /* SATP flags */ 40 #ifndef CONFIG_64BIT 41 #define SATP_PPN _AC(0x003FFFFF, UL) 42 #define SATP_MODE_32 _AC(0x80000000, UL) 43 #define SATP_MODE SATP_MODE_32 44 #else 45 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 46 #define SATP_MODE_39 _AC(0x8000000000000000, UL) 47 #define SATP_MODE SATP_MODE_39 48 #endif 49 50 /* Exception cause high bit - is an interrupt if set */ 51 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 52 53 /* Interrupt causes (minus the high bit) */ 54 #define IRQ_U_SOFT 0 55 #define IRQ_S_SOFT 1 56 #define IRQ_M_SOFT 3 57 #define IRQ_U_TIMER 4 58 #define IRQ_S_TIMER 5 59 #define IRQ_M_TIMER 7 60 #define IRQ_U_EXT 8 61 #define IRQ_S_EXT 9 62 #define IRQ_M_EXT 11 63 64 /* Exception causes */ 65 #define EXC_INST_MISALIGNED 0 66 #define EXC_INST_ACCESS 1 67 #define EXC_BREAKPOINT 3 68 #define EXC_LOAD_ACCESS 5 69 #define EXC_STORE_ACCESS 7 70 #define EXC_SYSCALL 8 71 #define EXC_INST_PAGE_FAULT 12 72 #define EXC_LOAD_PAGE_FAULT 13 73 #define EXC_STORE_PAGE_FAULT 15 74 75 /* PMP configuration */ 76 #define PMP_R 0x01 77 #define PMP_W 0x02 78 #define PMP_X 0x04 79 #define PMP_A 0x18 80 #define PMP_A_TOR 0x08 81 #define PMP_A_NA4 0x10 82 #define PMP_A_NAPOT 0x18 83 #define PMP_L 0x80 84 85 /* symbolic CSR names: */ 86 #define CSR_CYCLE 0xc00 87 #define CSR_TIME 0xc01 88 #define CSR_INSTRET 0xc02 89 #define CSR_CYCLEH 0xc80 90 #define CSR_TIMEH 0xc81 91 #define CSR_INSTRETH 0xc82 92 93 #define CSR_SSTATUS 0x100 94 #define CSR_SIE 0x104 95 #define CSR_STVEC 0x105 96 #define CSR_SCOUNTEREN 0x106 97 #define CSR_SSCRATCH 0x140 98 #define CSR_SEPC 0x141 99 #define CSR_SCAUSE 0x142 100 #define CSR_STVAL 0x143 101 #define CSR_SIP 0x144 102 #define CSR_SATP 0x180 103 104 #define CSR_MSTATUS 0x300 105 #define CSR_MISA 0x301 106 #define CSR_MIE 0x304 107 #define CSR_MTVEC 0x305 108 #define CSR_MSCRATCH 0x340 109 #define CSR_MEPC 0x341 110 #define CSR_MCAUSE 0x342 111 #define CSR_MTVAL 0x343 112 #define CSR_MIP 0x344 113 #define CSR_PMPCFG0 0x3a0 114 #define CSR_PMPADDR0 0x3b0 115 #define CSR_MHARTID 0xf14 116 117 #ifdef CONFIG_RISCV_M_MODE 118 # define CSR_STATUS CSR_MSTATUS 119 # define CSR_IE CSR_MIE 120 # define CSR_TVEC CSR_MTVEC 121 # define CSR_SCRATCH CSR_MSCRATCH 122 # define CSR_EPC CSR_MEPC 123 # define CSR_CAUSE CSR_MCAUSE 124 # define CSR_TVAL CSR_MTVAL 125 # define CSR_IP CSR_MIP 126 127 # define SR_IE SR_MIE 128 # define SR_PIE SR_MPIE 129 # define SR_PP SR_MPP 130 131 # define RV_IRQ_SOFT IRQ_M_SOFT 132 # define RV_IRQ_TIMER IRQ_M_TIMER 133 # define RV_IRQ_EXT IRQ_M_EXT 134 #else /* CONFIG_RISCV_M_MODE */ 135 # define CSR_STATUS CSR_SSTATUS 136 # define CSR_IE CSR_SIE 137 # define CSR_TVEC CSR_STVEC 138 # define CSR_SCRATCH CSR_SSCRATCH 139 # define CSR_EPC CSR_SEPC 140 # define CSR_CAUSE CSR_SCAUSE 141 # define CSR_TVAL CSR_STVAL 142 # define CSR_IP CSR_SIP 143 144 # define SR_IE SR_SIE 145 # define SR_PIE SR_SPIE 146 # define SR_PP SR_SPP 147 148 # define RV_IRQ_SOFT IRQ_S_SOFT 149 # define RV_IRQ_TIMER IRQ_S_TIMER 150 # define RV_IRQ_EXT IRQ_S_EXT 151 #endif /* CONFIG_RISCV_M_MODE */ 152 153 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ 154 #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) 155 #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) 156 #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) 157 158 #ifndef __ASSEMBLY__ 159 160 #define csr_swap(csr, val) \ 161 ({ \ 162 unsigned long __v = (unsigned long)(val); \ 163 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 164 : "=r" (__v) : "rK" (__v) \ 165 : "memory"); \ 166 __v; \ 167 }) 168 169 #define csr_read(csr) \ 170 ({ \ 171 register unsigned long __v; \ 172 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 173 : "=r" (__v) : \ 174 : "memory"); \ 175 __v; \ 176 }) 177 178 #define csr_write(csr, val) \ 179 ({ \ 180 unsigned long __v = (unsigned long)(val); \ 181 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 182 : : "rK" (__v) \ 183 : "memory"); \ 184 }) 185 186 #define csr_read_set(csr, val) \ 187 ({ \ 188 unsigned long __v = (unsigned long)(val); \ 189 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 190 : "=r" (__v) : "rK" (__v) \ 191 : "memory"); \ 192 __v; \ 193 }) 194 195 #define csr_set(csr, val) \ 196 ({ \ 197 unsigned long __v = (unsigned long)(val); \ 198 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 199 : : "rK" (__v) \ 200 : "memory"); \ 201 }) 202 203 #define csr_read_clear(csr, val) \ 204 ({ \ 205 unsigned long __v = (unsigned long)(val); \ 206 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 207 : "=r" (__v) : "rK" (__v) \ 208 : "memory"); \ 209 __v; \ 210 }) 211 212 #define csr_clear(csr, val) \ 213 ({ \ 214 unsigned long __v = (unsigned long)(val); \ 215 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 216 : : "rK" (__v) \ 217 : "memory"); \ 218 }) 219 220 #endif /* __ASSEMBLY__ */ 221 222 #endif /* _ASM_RISCV_CSR_H */ 223