1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atmel SDMMC controller driver. 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/mmc/host.h> 15 #include <linux/mmc/slot-gpio.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 22 #include "sdhci-pltfm.h" 23 24 #define SDMMC_MC1R 0x204 25 #define SDMMC_MC1R_DDR BIT(3) 26 #define SDMMC_MC1R_FCD BIT(7) 27 #define SDMMC_CACR 0x230 28 #define SDMMC_CACR_CAPWREN BIT(0) 29 #define SDMMC_CACR_KEY (0x46 << 8) 30 #define SDMMC_CALCR 0x240 31 #define SDMMC_CALCR_EN BIT(0) 32 #define SDMMC_CALCR_ALWYSON BIT(4) 33 34 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ 35 36 struct sdhci_at91_soc_data { 37 const struct sdhci_pltfm_data *pdata; 38 bool baseclk_is_generated_internally; 39 unsigned int divider_for_baseclk; 40 }; 41 42 struct sdhci_at91_priv { 43 const struct sdhci_at91_soc_data *soc_data; 44 struct clk *hclock; 45 struct clk *gck; 46 struct clk *mainck; 47 bool restore_needed; 48 bool cal_always_on; 49 }; 50 51 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host) 52 { 53 u8 mc1r; 54 55 mc1r = readb(host->ioaddr + SDMMC_MC1R); 56 mc1r |= SDMMC_MC1R_FCD; 57 writeb(mc1r, host->ioaddr + SDMMC_MC1R); 58 } 59 60 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) 61 { 62 u16 clk; 63 unsigned long timeout; 64 65 host->mmc->actual_clock = 0; 66 67 /* 68 * There is no requirement to disable the internal clock before 69 * changing the SD clock configuration. Moreover, disabling the 70 * internal clock, changing the configuration and re-enabling the 71 * internal clock causes some bugs. It can prevent to get the internal 72 * clock stable flag ready and an unexpected switch to the base clock 73 * when using presets. 74 */ 75 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 76 clk &= SDHCI_CLOCK_INT_EN; 77 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 78 79 if (clock == 0) 80 return; 81 82 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 83 84 clk |= SDHCI_CLOCK_INT_EN; 85 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 86 87 /* Wait max 20 ms */ 88 timeout = 20; 89 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 90 & SDHCI_CLOCK_INT_STABLE)) { 91 if (timeout == 0) { 92 pr_err("%s: Internal clock never stabilised.\n", 93 mmc_hostname(host->mmc)); 94 return; 95 } 96 timeout--; 97 mdelay(1); 98 } 99 100 clk |= SDHCI_CLOCK_CARD_EN; 101 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 102 } 103 104 /* 105 * In this specific implementation of the SDHCI controller, the power register 106 * needs to have a valid voltage set even when the power supply is managed by 107 * an external regulator. 108 */ 109 static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode, 110 unsigned short vdd) 111 { 112 if (!IS_ERR(host->mmc->supply.vmmc)) { 113 struct mmc_host *mmc = host->mmc; 114 115 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 116 } 117 sdhci_set_power_noreg(host, mode, vdd); 118 } 119 120 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, 121 unsigned int timing) 122 { 123 if (timing == MMC_TIMING_MMC_DDR52) 124 sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R); 125 sdhci_set_uhs_signaling(host, timing); 126 } 127 128 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask) 129 { 130 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 131 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 132 133 sdhci_reset(host, mask); 134 135 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 136 sdhci_at91_set_force_card_detect(host); 137 138 if (priv->cal_always_on && (mask & SDHCI_RESET_ALL)) 139 sdhci_writel(host, SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN, 140 SDMMC_CALCR); 141 } 142 143 static const struct sdhci_ops sdhci_at91_sama5d2_ops = { 144 .set_clock = sdhci_at91_set_clock, 145 .set_bus_width = sdhci_set_bus_width, 146 .reset = sdhci_at91_reset, 147 .set_uhs_signaling = sdhci_at91_set_uhs_signaling, 148 .set_power = sdhci_at91_set_power, 149 }; 150 151 static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = { 152 .ops = &sdhci_at91_sama5d2_ops, 153 }; 154 155 static const struct sdhci_at91_soc_data soc_data_sama5d2 = { 156 .pdata = &sdhci_sama5d2_pdata, 157 .baseclk_is_generated_internally = false, 158 }; 159 160 static const struct sdhci_at91_soc_data soc_data_sam9x60 = { 161 .pdata = &sdhci_sama5d2_pdata, 162 .baseclk_is_generated_internally = true, 163 .divider_for_baseclk = 2, 164 }; 165 166 static const struct of_device_id sdhci_at91_dt_match[] = { 167 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, 168 { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 }, 169 {} 170 }; 171 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); 172 173 static int sdhci_at91_set_clks_presets(struct device *dev) 174 { 175 struct sdhci_host *host = dev_get_drvdata(dev); 176 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 177 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 178 unsigned int caps0, caps1; 179 unsigned int clk_base, clk_mul; 180 unsigned int gck_rate, clk_base_rate; 181 unsigned int preset_div; 182 183 clk_prepare_enable(priv->hclock); 184 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); 185 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); 186 187 gck_rate = clk_get_rate(priv->gck); 188 if (priv->soc_data->baseclk_is_generated_internally) 189 clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk; 190 else 191 clk_base_rate = clk_get_rate(priv->mainck); 192 193 clk_base = clk_base_rate / 1000000; 194 clk_mul = gck_rate / clk_base_rate - 1; 195 196 caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK; 197 caps0 |= (clk_base << SDHCI_CLOCK_BASE_SHIFT) & SDHCI_CLOCK_V3_BASE_MASK; 198 caps1 &= ~SDHCI_CLOCK_MUL_MASK; 199 caps1 |= (clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK; 200 /* Set capabilities in r/w mode. */ 201 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); 202 writel(caps0, host->ioaddr + SDHCI_CAPABILITIES); 203 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); 204 /* Set capabilities in ro mode. */ 205 writel(0, host->ioaddr + SDMMC_CACR); 206 207 dev_info(dev, "update clk mul to %u as gck rate is %u Hz and clk base is %u Hz\n", 208 clk_mul, gck_rate, clk_base_rate); 209 210 /* 211 * We have to set preset values because it depends on the clk_mul 212 * value. Moreover, SDR104 is supported in a degraded mode since the 213 * maximum sd clock value is 120 MHz instead of 208 MHz. For that 214 * reason, we need to use presets to support SDR104. 215 */ 216 preset_div = DIV_ROUND_UP(gck_rate, 24000000) - 1; 217 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 218 host->ioaddr + SDHCI_PRESET_FOR_SDR12); 219 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; 220 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 221 host->ioaddr + SDHCI_PRESET_FOR_SDR25); 222 preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1; 223 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 224 host->ioaddr + SDHCI_PRESET_FOR_SDR50); 225 preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1; 226 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 227 host->ioaddr + SDHCI_PRESET_FOR_SDR104); 228 preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; 229 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, 230 host->ioaddr + SDHCI_PRESET_FOR_DDR50); 231 232 clk_prepare_enable(priv->mainck); 233 clk_prepare_enable(priv->gck); 234 235 return 0; 236 } 237 238 #ifdef CONFIG_PM_SLEEP 239 static int sdhci_at91_suspend(struct device *dev) 240 { 241 struct sdhci_host *host = dev_get_drvdata(dev); 242 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 243 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 244 int ret; 245 246 ret = pm_runtime_force_suspend(dev); 247 248 priv->restore_needed = true; 249 250 return ret; 251 } 252 #endif /* CONFIG_PM_SLEEP */ 253 254 #ifdef CONFIG_PM 255 static int sdhci_at91_runtime_suspend(struct device *dev) 256 { 257 struct sdhci_host *host = dev_get_drvdata(dev); 258 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 259 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 260 int ret; 261 262 ret = sdhci_runtime_suspend_host(host); 263 264 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 265 mmc_retune_needed(host->mmc); 266 267 clk_disable_unprepare(priv->gck); 268 clk_disable_unprepare(priv->hclock); 269 clk_disable_unprepare(priv->mainck); 270 271 return ret; 272 } 273 274 static int sdhci_at91_runtime_resume(struct device *dev) 275 { 276 struct sdhci_host *host = dev_get_drvdata(dev); 277 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 278 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 279 int ret; 280 281 if (priv->restore_needed) { 282 ret = sdhci_at91_set_clks_presets(dev); 283 if (ret) 284 return ret; 285 286 priv->restore_needed = false; 287 goto out; 288 } 289 290 ret = clk_prepare_enable(priv->mainck); 291 if (ret) { 292 dev_err(dev, "can't enable mainck\n"); 293 return ret; 294 } 295 296 ret = clk_prepare_enable(priv->hclock); 297 if (ret) { 298 dev_err(dev, "can't enable hclock\n"); 299 return ret; 300 } 301 302 ret = clk_prepare_enable(priv->gck); 303 if (ret) { 304 dev_err(dev, "can't enable gck\n"); 305 return ret; 306 } 307 308 out: 309 return sdhci_runtime_resume_host(host, 0); 310 } 311 #endif /* CONFIG_PM */ 312 313 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { 314 SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume) 315 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, 316 sdhci_at91_runtime_resume, 317 NULL) 318 }; 319 320 static int sdhci_at91_probe(struct platform_device *pdev) 321 { 322 const struct of_device_id *match; 323 const struct sdhci_at91_soc_data *soc_data; 324 struct sdhci_host *host; 325 struct sdhci_pltfm_host *pltfm_host; 326 struct sdhci_at91_priv *priv; 327 int ret; 328 329 match = of_match_device(sdhci_at91_dt_match, &pdev->dev); 330 if (!match) 331 return -EINVAL; 332 soc_data = match->data; 333 334 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv)); 335 if (IS_ERR(host)) 336 return PTR_ERR(host); 337 338 pltfm_host = sdhci_priv(host); 339 priv = sdhci_pltfm_priv(pltfm_host); 340 priv->soc_data = soc_data; 341 342 priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); 343 if (IS_ERR(priv->mainck)) { 344 if (soc_data->baseclk_is_generated_internally) { 345 priv->mainck = NULL; 346 } else { 347 dev_err(&pdev->dev, "failed to get baseclk\n"); 348 ret = PTR_ERR(priv->mainck); 349 goto sdhci_pltfm_free; 350 } 351 } 352 353 priv->hclock = devm_clk_get(&pdev->dev, "hclock"); 354 if (IS_ERR(priv->hclock)) { 355 dev_err(&pdev->dev, "failed to get hclock\n"); 356 ret = PTR_ERR(priv->hclock); 357 goto sdhci_pltfm_free; 358 } 359 360 priv->gck = devm_clk_get(&pdev->dev, "multclk"); 361 if (IS_ERR(priv->gck)) { 362 dev_err(&pdev->dev, "failed to get multclk\n"); 363 ret = PTR_ERR(priv->gck); 364 goto sdhci_pltfm_free; 365 } 366 367 ret = sdhci_at91_set_clks_presets(&pdev->dev); 368 if (ret) 369 goto sdhci_pltfm_free; 370 371 priv->restore_needed = false; 372 373 /* 374 * if SDCAL pin is wrongly connected, we must enable 375 * the analog calibration cell permanently. 376 */ 377 priv->cal_always_on = 378 device_property_read_bool(&pdev->dev, 379 "microchip,sdcal-inverted"); 380 381 ret = mmc_of_parse(host->mmc); 382 if (ret) 383 goto clocks_disable_unprepare; 384 385 sdhci_get_of_property(pdev); 386 387 pm_runtime_get_noresume(&pdev->dev); 388 pm_runtime_set_active(&pdev->dev); 389 pm_runtime_enable(&pdev->dev); 390 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 391 pm_runtime_use_autosuspend(&pdev->dev); 392 393 /* HS200 is broken at this moment */ 394 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 395 396 ret = sdhci_add_host(host); 397 if (ret) 398 goto pm_runtime_disable; 399 400 /* 401 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes 402 * the assumption that all the clocks of the controller are disabled. 403 * It means we can't get irq from it when it is runtime suspended. 404 * For that reason, it is not planned to wake-up on a card detect irq 405 * from the controller. 406 * If we want to use runtime PM and to be able to wake-up on card 407 * insertion, we have to use a GPIO for the card detection or we can 408 * use polling. Be aware that using polling will resume/suspend the 409 * controller between each attempt. 410 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries 411 * to enable polling via device tree with broken-cd property. 412 */ 413 if (mmc_card_is_removable(host->mmc) && 414 mmc_gpio_get_cd(host->mmc) < 0) { 415 host->mmc->caps |= MMC_CAP_NEEDS_POLL; 416 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 417 } 418 419 /* 420 * If the device attached to the MMC bus is not removable, it is safer 421 * to set the Force Card Detect bit. People often don't connect the 422 * card detect signal and use this pin for another purpose. If the card 423 * detect pin is not muxed to SDHCI controller, a default value is 424 * used. This value can be different from a SoC revision to another 425 * one. Problems come when this default value is not card present. To 426 * avoid this case, if the device is non removable then the card 427 * detection procedure using the SDMCC_CD signal is bypassed. 428 * This bit is reset when a software reset for all command is performed 429 * so we need to implement our own reset function to set back this bit. 430 */ 431 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 432 sdhci_at91_set_force_card_detect(host); 433 434 pm_runtime_put_autosuspend(&pdev->dev); 435 436 return 0; 437 438 pm_runtime_disable: 439 pm_runtime_disable(&pdev->dev); 440 pm_runtime_set_suspended(&pdev->dev); 441 pm_runtime_put_noidle(&pdev->dev); 442 clocks_disable_unprepare: 443 clk_disable_unprepare(priv->gck); 444 clk_disable_unprepare(priv->mainck); 445 clk_disable_unprepare(priv->hclock); 446 sdhci_pltfm_free: 447 sdhci_pltfm_free(pdev); 448 return ret; 449 } 450 451 static int sdhci_at91_remove(struct platform_device *pdev) 452 { 453 struct sdhci_host *host = platform_get_drvdata(pdev); 454 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 455 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); 456 struct clk *gck = priv->gck; 457 struct clk *hclock = priv->hclock; 458 struct clk *mainck = priv->mainck; 459 460 pm_runtime_get_sync(&pdev->dev); 461 pm_runtime_disable(&pdev->dev); 462 pm_runtime_put_noidle(&pdev->dev); 463 464 sdhci_pltfm_unregister(pdev); 465 466 clk_disable_unprepare(gck); 467 clk_disable_unprepare(hclock); 468 clk_disable_unprepare(mainck); 469 470 return 0; 471 } 472 473 static struct platform_driver sdhci_at91_driver = { 474 .driver = { 475 .name = "sdhci-at91", 476 .of_match_table = sdhci_at91_dt_match, 477 .pm = &sdhci_at91_dev_pm_ops, 478 }, 479 .probe = sdhci_at91_probe, 480 .remove = sdhci_at91_remove, 481 }; 482 483 module_platform_driver(sdhci_at91_driver); 484 485 MODULE_DESCRIPTION("SDHCI driver for at91"); 486 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 487 MODULE_LICENSE("GPL v2"); 488