1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/aer.h> 8 #include <linux/async.h> 9 #include <linux/blkdev.h> 10 #include <linux/blk-mq.h> 11 #include <linux/blk-mq-pci.h> 12 #include <linux/dmi.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/mm.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/once.h> 20 #include <linux/pci.h> 21 #include <linux/suspend.h> 22 #include <linux/t10-pi.h> 23 #include <linux/types.h> 24 #include <linux/io-64-nonatomic-lo-hi.h> 25 #include <linux/sed-opal.h> 26 #include <linux/pci-p2pdma.h> 27 28 #include "trace.h" 29 #include "nvme.h" 30 31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 33 34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 35 36 /* 37 * These can be higher, but we need to ensure that any command doesn't 38 * require an sg allocation that needs more than a page of data. 39 */ 40 #define NVME_MAX_KB_SZ 4096 41 #define NVME_MAX_SEGS 127 42 43 static int use_threaded_interrupts; 44 module_param(use_threaded_interrupts, int, 0); 45 46 static bool use_cmb_sqes = true; 47 module_param(use_cmb_sqes, bool, 0444); 48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 49 50 static unsigned int max_host_mem_size_mb = 128; 51 module_param(max_host_mem_size_mb, uint, 0444); 52 MODULE_PARM_DESC(max_host_mem_size_mb, 53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 54 55 static unsigned int sgl_threshold = SZ_32K; 56 module_param(sgl_threshold, uint, 0644); 57 MODULE_PARM_DESC(sgl_threshold, 58 "Use SGLs when average request segment size is larger or equal to " 59 "this size. Use 0 to disable SGLs."); 60 61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 62 static const struct kernel_param_ops io_queue_depth_ops = { 63 .set = io_queue_depth_set, 64 .get = param_get_int, 65 }; 66 67 static int io_queue_depth = 1024; 68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 70 71 static int write_queues; 72 module_param(write_queues, int, 0644); 73 MODULE_PARM_DESC(write_queues, 74 "Number of queues to use for writes. If not set, reads and writes " 75 "will share a queue set."); 76 77 static int poll_queues; 78 module_param(poll_queues, int, 0644); 79 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 80 81 struct nvme_dev; 82 struct nvme_queue; 83 84 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 85 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 86 87 /* 88 * Represents an NVM Express device. Each nvme_dev is a PCI function. 89 */ 90 struct nvme_dev { 91 struct nvme_queue *queues; 92 struct blk_mq_tag_set tagset; 93 struct blk_mq_tag_set admin_tagset; 94 u32 __iomem *dbs; 95 struct device *dev; 96 struct dma_pool *prp_page_pool; 97 struct dma_pool *prp_small_pool; 98 unsigned online_queues; 99 unsigned max_qid; 100 unsigned io_queues[HCTX_MAX_TYPES]; 101 unsigned int num_vecs; 102 int q_depth; 103 int io_sqes; 104 u32 db_stride; 105 void __iomem *bar; 106 unsigned long bar_mapped_size; 107 struct work_struct remove_work; 108 struct mutex shutdown_lock; 109 bool subsystem; 110 u64 cmb_size; 111 bool cmb_use_sqes; 112 u32 cmbsz; 113 u32 cmbloc; 114 struct nvme_ctrl ctrl; 115 u32 last_ps; 116 117 mempool_t *iod_mempool; 118 119 /* shadow doorbell buffer support: */ 120 u32 *dbbuf_dbs; 121 dma_addr_t dbbuf_dbs_dma_addr; 122 u32 *dbbuf_eis; 123 dma_addr_t dbbuf_eis_dma_addr; 124 125 /* host memory buffer support: */ 126 u64 host_mem_size; 127 u32 nr_host_mem_descs; 128 dma_addr_t host_mem_descs_dma; 129 struct nvme_host_mem_buf_desc *host_mem_descs; 130 void **host_mem_desc_bufs; 131 }; 132 133 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 134 { 135 int n = 0, ret; 136 137 ret = kstrtoint(val, 10, &n); 138 if (ret != 0 || n < 2) 139 return -EINVAL; 140 141 return param_set_int(val, kp); 142 } 143 144 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 145 { 146 return qid * 2 * stride; 147 } 148 149 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 150 { 151 return (qid * 2 + 1) * stride; 152 } 153 154 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 155 { 156 return container_of(ctrl, struct nvme_dev, ctrl); 157 } 158 159 /* 160 * An NVM Express queue. Each device has at least two (one for admin 161 * commands and one for I/O commands). 162 */ 163 struct nvme_queue { 164 struct nvme_dev *dev; 165 spinlock_t sq_lock; 166 void *sq_cmds; 167 /* only used for poll queues: */ 168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 169 volatile struct nvme_completion *cqes; 170 struct blk_mq_tags **tags; 171 dma_addr_t sq_dma_addr; 172 dma_addr_t cq_dma_addr; 173 u32 __iomem *q_db; 174 u16 q_depth; 175 u16 cq_vector; 176 u16 sq_tail; 177 u16 last_sq_tail; 178 u16 cq_head; 179 u16 last_cq_head; 180 u16 qid; 181 u8 cq_phase; 182 u8 sqes; 183 unsigned long flags; 184 #define NVMEQ_ENABLED 0 185 #define NVMEQ_SQ_CMB 1 186 #define NVMEQ_DELETE_ERROR 2 187 #define NVMEQ_POLLED 3 188 u32 *dbbuf_sq_db; 189 u32 *dbbuf_cq_db; 190 u32 *dbbuf_sq_ei; 191 u32 *dbbuf_cq_ei; 192 struct completion delete_done; 193 }; 194 195 /* 196 * The nvme_iod describes the data in an I/O. 197 * 198 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 199 * to the actual struct scatterlist. 200 */ 201 struct nvme_iod { 202 struct nvme_request req; 203 struct nvme_queue *nvmeq; 204 bool use_sgl; 205 int aborted; 206 int npages; /* In the PRP list. 0 means small pool in use */ 207 int nents; /* Used in scatterlist */ 208 dma_addr_t first_dma; 209 unsigned int dma_len; /* length of single DMA segment mapping */ 210 dma_addr_t meta_dma; 211 struct scatterlist *sg; 212 }; 213 214 static unsigned int max_io_queues(void) 215 { 216 return num_possible_cpus() + write_queues + poll_queues; 217 } 218 219 static unsigned int max_queue_count(void) 220 { 221 /* IO queues + admin queue */ 222 return 1 + max_io_queues(); 223 } 224 225 static inline unsigned int nvme_dbbuf_size(u32 stride) 226 { 227 return (max_queue_count() * 8 * stride); 228 } 229 230 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 231 { 232 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 233 234 if (dev->dbbuf_dbs) 235 return 0; 236 237 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 238 &dev->dbbuf_dbs_dma_addr, 239 GFP_KERNEL); 240 if (!dev->dbbuf_dbs) 241 return -ENOMEM; 242 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 243 &dev->dbbuf_eis_dma_addr, 244 GFP_KERNEL); 245 if (!dev->dbbuf_eis) { 246 dma_free_coherent(dev->dev, mem_size, 247 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 248 dev->dbbuf_dbs = NULL; 249 return -ENOMEM; 250 } 251 252 return 0; 253 } 254 255 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 256 { 257 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 258 259 if (dev->dbbuf_dbs) { 260 dma_free_coherent(dev->dev, mem_size, 261 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 262 dev->dbbuf_dbs = NULL; 263 } 264 if (dev->dbbuf_eis) { 265 dma_free_coherent(dev->dev, mem_size, 266 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 267 dev->dbbuf_eis = NULL; 268 } 269 } 270 271 static void nvme_dbbuf_init(struct nvme_dev *dev, 272 struct nvme_queue *nvmeq, int qid) 273 { 274 if (!dev->dbbuf_dbs || !qid) 275 return; 276 277 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 278 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 279 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 280 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 281 } 282 283 static void nvme_dbbuf_set(struct nvme_dev *dev) 284 { 285 struct nvme_command c; 286 287 if (!dev->dbbuf_dbs) 288 return; 289 290 memset(&c, 0, sizeof(c)); 291 c.dbbuf.opcode = nvme_admin_dbbuf; 292 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 293 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 294 295 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 296 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 297 /* Free memory and continue on */ 298 nvme_dbbuf_dma_free(dev); 299 } 300 } 301 302 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 303 { 304 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 305 } 306 307 /* Update dbbuf and return true if an MMIO is required */ 308 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 309 volatile u32 *dbbuf_ei) 310 { 311 if (dbbuf_db) { 312 u16 old_value; 313 314 /* 315 * Ensure that the queue is written before updating 316 * the doorbell in memory 317 */ 318 wmb(); 319 320 old_value = *dbbuf_db; 321 *dbbuf_db = value; 322 323 /* 324 * Ensure that the doorbell is updated before reading the event 325 * index from memory. The controller needs to provide similar 326 * ordering to ensure the envent index is updated before reading 327 * the doorbell. 328 */ 329 mb(); 330 331 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 332 return false; 333 } 334 335 return true; 336 } 337 338 /* 339 * Will slightly overestimate the number of pages needed. This is OK 340 * as it only leads to a small amount of wasted memory for the lifetime of 341 * the I/O. 342 */ 343 static int nvme_npages(unsigned size, struct nvme_dev *dev) 344 { 345 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 346 dev->ctrl.page_size); 347 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 348 } 349 350 /* 351 * Calculates the number of pages needed for the SGL segments. For example a 4k 352 * page can accommodate 256 SGL descriptors. 353 */ 354 static int nvme_pci_npages_sgl(unsigned int num_seg) 355 { 356 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 357 } 358 359 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 360 unsigned int size, unsigned int nseg, bool use_sgl) 361 { 362 size_t alloc_size; 363 364 if (use_sgl) 365 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 366 else 367 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 368 369 return alloc_size + sizeof(struct scatterlist) * nseg; 370 } 371 372 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 373 unsigned int hctx_idx) 374 { 375 struct nvme_dev *dev = data; 376 struct nvme_queue *nvmeq = &dev->queues[0]; 377 378 WARN_ON(hctx_idx != 0); 379 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 380 WARN_ON(nvmeq->tags); 381 382 hctx->driver_data = nvmeq; 383 nvmeq->tags = &dev->admin_tagset.tags[0]; 384 return 0; 385 } 386 387 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 388 { 389 struct nvme_queue *nvmeq = hctx->driver_data; 390 391 nvmeq->tags = NULL; 392 } 393 394 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 395 unsigned int hctx_idx) 396 { 397 struct nvme_dev *dev = data; 398 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 399 400 if (!nvmeq->tags) 401 nvmeq->tags = &dev->tagset.tags[hctx_idx]; 402 403 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 404 hctx->driver_data = nvmeq; 405 return 0; 406 } 407 408 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 409 unsigned int hctx_idx, unsigned int numa_node) 410 { 411 struct nvme_dev *dev = set->driver_data; 412 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 413 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 414 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 415 416 BUG_ON(!nvmeq); 417 iod->nvmeq = nvmeq; 418 419 nvme_req(req)->ctrl = &dev->ctrl; 420 return 0; 421 } 422 423 static int queue_irq_offset(struct nvme_dev *dev) 424 { 425 /* if we have more than 1 vec, admin queue offsets us by 1 */ 426 if (dev->num_vecs > 1) 427 return 1; 428 429 return 0; 430 } 431 432 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 433 { 434 struct nvme_dev *dev = set->driver_data; 435 int i, qoff, offset; 436 437 offset = queue_irq_offset(dev); 438 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 439 struct blk_mq_queue_map *map = &set->map[i]; 440 441 map->nr_queues = dev->io_queues[i]; 442 if (!map->nr_queues) { 443 BUG_ON(i == HCTX_TYPE_DEFAULT); 444 continue; 445 } 446 447 /* 448 * The poll queue(s) doesn't have an IRQ (and hence IRQ 449 * affinity), so use the regular blk-mq cpu mapping 450 */ 451 map->queue_offset = qoff; 452 if (i != HCTX_TYPE_POLL && offset) 453 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 454 else 455 blk_mq_map_queues(map); 456 qoff += map->nr_queues; 457 offset += map->nr_queues; 458 } 459 460 return 0; 461 } 462 463 /* 464 * Write sq tail if we are asked to, or if the next command would wrap. 465 */ 466 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 467 { 468 if (!write_sq) { 469 u16 next_tail = nvmeq->sq_tail + 1; 470 471 if (next_tail == nvmeq->q_depth) 472 next_tail = 0; 473 if (next_tail != nvmeq->last_sq_tail) 474 return; 475 } 476 477 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 478 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 479 writel(nvmeq->sq_tail, nvmeq->q_db); 480 nvmeq->last_sq_tail = nvmeq->sq_tail; 481 } 482 483 /** 484 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 485 * @nvmeq: The queue to use 486 * @cmd: The command to send 487 * @write_sq: whether to write to the SQ doorbell 488 */ 489 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 490 bool write_sq) 491 { 492 spin_lock(&nvmeq->sq_lock); 493 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 494 cmd, sizeof(*cmd)); 495 if (++nvmeq->sq_tail == nvmeq->q_depth) 496 nvmeq->sq_tail = 0; 497 nvme_write_sq_db(nvmeq, write_sq); 498 spin_unlock(&nvmeq->sq_lock); 499 } 500 501 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 502 { 503 struct nvme_queue *nvmeq = hctx->driver_data; 504 505 spin_lock(&nvmeq->sq_lock); 506 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 507 nvme_write_sq_db(nvmeq, true); 508 spin_unlock(&nvmeq->sq_lock); 509 } 510 511 static void **nvme_pci_iod_list(struct request *req) 512 { 513 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 514 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 515 } 516 517 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 518 { 519 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 520 int nseg = blk_rq_nr_phys_segments(req); 521 unsigned int avg_seg_size; 522 523 if (nseg == 0) 524 return false; 525 526 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 527 528 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 529 return false; 530 if (!iod->nvmeq->qid) 531 return false; 532 if (!sgl_threshold || avg_seg_size < sgl_threshold) 533 return false; 534 return true; 535 } 536 537 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 538 { 539 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 540 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 541 dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 542 int i; 543 544 if (iod->dma_len) { 545 dma_unmap_page(dev->dev, dma_addr, iod->dma_len, 546 rq_dma_dir(req)); 547 return; 548 } 549 550 WARN_ON_ONCE(!iod->nents); 551 552 if (is_pci_p2pdma_page(sg_page(iod->sg))) 553 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 554 rq_dma_dir(req)); 555 else 556 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 557 558 559 if (iod->npages == 0) 560 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 561 dma_addr); 562 563 for (i = 0; i < iod->npages; i++) { 564 void *addr = nvme_pci_iod_list(req)[i]; 565 566 if (iod->use_sgl) { 567 struct nvme_sgl_desc *sg_list = addr; 568 569 next_dma_addr = 570 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 571 } else { 572 __le64 *prp_list = addr; 573 574 next_dma_addr = le64_to_cpu(prp_list[last_prp]); 575 } 576 577 dma_pool_free(dev->prp_page_pool, addr, dma_addr); 578 dma_addr = next_dma_addr; 579 } 580 581 mempool_free(iod->sg, dev->iod_mempool); 582 } 583 584 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 585 { 586 int i; 587 struct scatterlist *sg; 588 589 for_each_sg(sgl, sg, nents, i) { 590 dma_addr_t phys = sg_phys(sg); 591 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 592 "dma_address:%pad dma_length:%d\n", 593 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 594 sg_dma_len(sg)); 595 } 596 } 597 598 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 599 struct request *req, struct nvme_rw_command *cmnd) 600 { 601 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 602 struct dma_pool *pool; 603 int length = blk_rq_payload_bytes(req); 604 struct scatterlist *sg = iod->sg; 605 int dma_len = sg_dma_len(sg); 606 u64 dma_addr = sg_dma_address(sg); 607 u32 page_size = dev->ctrl.page_size; 608 int offset = dma_addr & (page_size - 1); 609 __le64 *prp_list; 610 void **list = nvme_pci_iod_list(req); 611 dma_addr_t prp_dma; 612 int nprps, i; 613 614 length -= (page_size - offset); 615 if (length <= 0) { 616 iod->first_dma = 0; 617 goto done; 618 } 619 620 dma_len -= (page_size - offset); 621 if (dma_len) { 622 dma_addr += (page_size - offset); 623 } else { 624 sg = sg_next(sg); 625 dma_addr = sg_dma_address(sg); 626 dma_len = sg_dma_len(sg); 627 } 628 629 if (length <= page_size) { 630 iod->first_dma = dma_addr; 631 goto done; 632 } 633 634 nprps = DIV_ROUND_UP(length, page_size); 635 if (nprps <= (256 / 8)) { 636 pool = dev->prp_small_pool; 637 iod->npages = 0; 638 } else { 639 pool = dev->prp_page_pool; 640 iod->npages = 1; 641 } 642 643 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 644 if (!prp_list) { 645 iod->first_dma = dma_addr; 646 iod->npages = -1; 647 return BLK_STS_RESOURCE; 648 } 649 list[0] = prp_list; 650 iod->first_dma = prp_dma; 651 i = 0; 652 for (;;) { 653 if (i == page_size >> 3) { 654 __le64 *old_prp_list = prp_list; 655 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 656 if (!prp_list) 657 return BLK_STS_RESOURCE; 658 list[iod->npages++] = prp_list; 659 prp_list[0] = old_prp_list[i - 1]; 660 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 661 i = 1; 662 } 663 prp_list[i++] = cpu_to_le64(dma_addr); 664 dma_len -= page_size; 665 dma_addr += page_size; 666 length -= page_size; 667 if (length <= 0) 668 break; 669 if (dma_len > 0) 670 continue; 671 if (unlikely(dma_len < 0)) 672 goto bad_sgl; 673 sg = sg_next(sg); 674 dma_addr = sg_dma_address(sg); 675 dma_len = sg_dma_len(sg); 676 } 677 678 done: 679 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 680 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 681 682 return BLK_STS_OK; 683 684 bad_sgl: 685 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 686 "Invalid SGL for payload:%d nents:%d\n", 687 blk_rq_payload_bytes(req), iod->nents); 688 return BLK_STS_IOERR; 689 } 690 691 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 692 struct scatterlist *sg) 693 { 694 sge->addr = cpu_to_le64(sg_dma_address(sg)); 695 sge->length = cpu_to_le32(sg_dma_len(sg)); 696 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 697 } 698 699 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 700 dma_addr_t dma_addr, int entries) 701 { 702 sge->addr = cpu_to_le64(dma_addr); 703 if (entries < SGES_PER_PAGE) { 704 sge->length = cpu_to_le32(entries * sizeof(*sge)); 705 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 706 } else { 707 sge->length = cpu_to_le32(PAGE_SIZE); 708 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 709 } 710 } 711 712 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 713 struct request *req, struct nvme_rw_command *cmd, int entries) 714 { 715 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 716 struct dma_pool *pool; 717 struct nvme_sgl_desc *sg_list; 718 struct scatterlist *sg = iod->sg; 719 dma_addr_t sgl_dma; 720 int i = 0; 721 722 /* setting the transfer type as SGL */ 723 cmd->flags = NVME_CMD_SGL_METABUF; 724 725 if (entries == 1) { 726 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 727 return BLK_STS_OK; 728 } 729 730 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 731 pool = dev->prp_small_pool; 732 iod->npages = 0; 733 } else { 734 pool = dev->prp_page_pool; 735 iod->npages = 1; 736 } 737 738 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 739 if (!sg_list) { 740 iod->npages = -1; 741 return BLK_STS_RESOURCE; 742 } 743 744 nvme_pci_iod_list(req)[0] = sg_list; 745 iod->first_dma = sgl_dma; 746 747 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 748 749 do { 750 if (i == SGES_PER_PAGE) { 751 struct nvme_sgl_desc *old_sg_desc = sg_list; 752 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 753 754 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 755 if (!sg_list) 756 return BLK_STS_RESOURCE; 757 758 i = 0; 759 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 760 sg_list[i++] = *link; 761 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 762 } 763 764 nvme_pci_sgl_set_data(&sg_list[i++], sg); 765 sg = sg_next(sg); 766 } while (--entries > 0); 767 768 return BLK_STS_OK; 769 } 770 771 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 772 struct request *req, struct nvme_rw_command *cmnd, 773 struct bio_vec *bv) 774 { 775 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 776 unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset; 777 778 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 779 if (dma_mapping_error(dev->dev, iod->first_dma)) 780 return BLK_STS_RESOURCE; 781 iod->dma_len = bv->bv_len; 782 783 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 784 if (bv->bv_len > first_prp_len) 785 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 786 return 0; 787 } 788 789 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 790 struct request *req, struct nvme_rw_command *cmnd, 791 struct bio_vec *bv) 792 { 793 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 794 795 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 796 if (dma_mapping_error(dev->dev, iod->first_dma)) 797 return BLK_STS_RESOURCE; 798 iod->dma_len = bv->bv_len; 799 800 cmnd->flags = NVME_CMD_SGL_METABUF; 801 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 802 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 803 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 804 return 0; 805 } 806 807 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 808 struct nvme_command *cmnd) 809 { 810 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 811 blk_status_t ret = BLK_STS_RESOURCE; 812 int nr_mapped; 813 814 if (blk_rq_nr_phys_segments(req) == 1) { 815 struct bio_vec bv = req_bvec(req); 816 817 if (!is_pci_p2pdma_page(bv.bv_page)) { 818 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 819 return nvme_setup_prp_simple(dev, req, 820 &cmnd->rw, &bv); 821 822 if (iod->nvmeq->qid && 823 dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 824 return nvme_setup_sgl_simple(dev, req, 825 &cmnd->rw, &bv); 826 } 827 } 828 829 iod->dma_len = 0; 830 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 831 if (!iod->sg) 832 return BLK_STS_RESOURCE; 833 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 834 iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 835 if (!iod->nents) 836 goto out; 837 838 if (is_pci_p2pdma_page(sg_page(iod->sg))) 839 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 840 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 841 else 842 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 843 rq_dma_dir(req), DMA_ATTR_NO_WARN); 844 if (!nr_mapped) 845 goto out; 846 847 iod->use_sgl = nvme_pci_use_sgls(dev, req); 848 if (iod->use_sgl) 849 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 850 else 851 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 852 out: 853 if (ret != BLK_STS_OK) 854 nvme_unmap_data(dev, req); 855 return ret; 856 } 857 858 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 859 struct nvme_command *cmnd) 860 { 861 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 862 863 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 864 rq_dma_dir(req), 0); 865 if (dma_mapping_error(dev->dev, iod->meta_dma)) 866 return BLK_STS_IOERR; 867 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 868 return 0; 869 } 870 871 /* 872 * NOTE: ns is NULL when called on the admin queue. 873 */ 874 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 875 const struct blk_mq_queue_data *bd) 876 { 877 struct nvme_ns *ns = hctx->queue->queuedata; 878 struct nvme_queue *nvmeq = hctx->driver_data; 879 struct nvme_dev *dev = nvmeq->dev; 880 struct request *req = bd->rq; 881 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 882 struct nvme_command cmnd; 883 blk_status_t ret; 884 885 iod->aborted = 0; 886 iod->npages = -1; 887 iod->nents = 0; 888 889 /* 890 * We should not need to do this, but we're still using this to 891 * ensure we can drain requests on a dying queue. 892 */ 893 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 894 return BLK_STS_IOERR; 895 896 ret = nvme_setup_cmd(ns, req, &cmnd); 897 if (ret) 898 return ret; 899 900 if (blk_rq_nr_phys_segments(req)) { 901 ret = nvme_map_data(dev, req, &cmnd); 902 if (ret) 903 goto out_free_cmd; 904 } 905 906 if (blk_integrity_rq(req)) { 907 ret = nvme_map_metadata(dev, req, &cmnd); 908 if (ret) 909 goto out_unmap_data; 910 } 911 912 blk_mq_start_request(req); 913 nvme_submit_cmd(nvmeq, &cmnd, bd->last); 914 return BLK_STS_OK; 915 out_unmap_data: 916 nvme_unmap_data(dev, req); 917 out_free_cmd: 918 nvme_cleanup_cmd(req); 919 return ret; 920 } 921 922 static void nvme_pci_complete_rq(struct request *req) 923 { 924 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 925 struct nvme_dev *dev = iod->nvmeq->dev; 926 927 nvme_cleanup_cmd(req); 928 if (blk_integrity_rq(req)) 929 dma_unmap_page(dev->dev, iod->meta_dma, 930 rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 931 if (blk_rq_nr_phys_segments(req)) 932 nvme_unmap_data(dev, req); 933 nvme_complete_rq(req); 934 } 935 936 /* We read the CQE phase first to check if the rest of the entry is valid */ 937 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 938 { 939 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 940 nvmeq->cq_phase; 941 } 942 943 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 944 { 945 u16 head = nvmeq->cq_head; 946 947 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 948 nvmeq->dbbuf_cq_ei)) 949 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 950 } 951 952 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 953 { 954 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 955 struct request *req; 956 957 if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 958 dev_warn(nvmeq->dev->ctrl.device, 959 "invalid id %d completed on queue %d\n", 960 cqe->command_id, le16_to_cpu(cqe->sq_id)); 961 return; 962 } 963 964 /* 965 * AEN requests are special as they don't time out and can 966 * survive any kind of queue freeze and often don't respond to 967 * aborts. We don't even bother to allocate a struct request 968 * for them but rather special case them here. 969 */ 970 if (unlikely(nvmeq->qid == 0 && 971 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 972 nvme_complete_async_event(&nvmeq->dev->ctrl, 973 cqe->status, &cqe->result); 974 return; 975 } 976 977 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 978 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 979 nvme_end_request(req, cqe->status, cqe->result); 980 } 981 982 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 983 { 984 while (start != end) { 985 nvme_handle_cqe(nvmeq, start); 986 if (++start == nvmeq->q_depth) 987 start = 0; 988 } 989 } 990 991 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 992 { 993 if (nvmeq->cq_head == nvmeq->q_depth - 1) { 994 nvmeq->cq_head = 0; 995 nvmeq->cq_phase = !nvmeq->cq_phase; 996 } else { 997 nvmeq->cq_head++; 998 } 999 } 1000 1001 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 1002 u16 *end, unsigned int tag) 1003 { 1004 int found = 0; 1005 1006 *start = nvmeq->cq_head; 1007 while (nvme_cqe_pending(nvmeq)) { 1008 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 1009 found++; 1010 nvme_update_cq_head(nvmeq); 1011 } 1012 *end = nvmeq->cq_head; 1013 1014 if (*start != *end) 1015 nvme_ring_cq_doorbell(nvmeq); 1016 return found; 1017 } 1018 1019 static irqreturn_t nvme_irq(int irq, void *data) 1020 { 1021 struct nvme_queue *nvmeq = data; 1022 irqreturn_t ret = IRQ_NONE; 1023 u16 start, end; 1024 1025 /* 1026 * The rmb/wmb pair ensures we see all updates from a previous run of 1027 * the irq handler, even if that was on another CPU. 1028 */ 1029 rmb(); 1030 if (nvmeq->cq_head != nvmeq->last_cq_head) 1031 ret = IRQ_HANDLED; 1032 nvme_process_cq(nvmeq, &start, &end, -1); 1033 nvmeq->last_cq_head = nvmeq->cq_head; 1034 wmb(); 1035 1036 if (start != end) { 1037 nvme_complete_cqes(nvmeq, start, end); 1038 return IRQ_HANDLED; 1039 } 1040 1041 return ret; 1042 } 1043 1044 static irqreturn_t nvme_irq_check(int irq, void *data) 1045 { 1046 struct nvme_queue *nvmeq = data; 1047 if (nvme_cqe_pending(nvmeq)) 1048 return IRQ_WAKE_THREAD; 1049 return IRQ_NONE; 1050 } 1051 1052 /* 1053 * Poll for completions any queue, including those not dedicated to polling. 1054 * Can be called from any context. 1055 */ 1056 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1057 { 1058 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1059 u16 start, end; 1060 int found; 1061 1062 /* 1063 * For a poll queue we need to protect against the polling thread 1064 * using the CQ lock. For normal interrupt driven threads we have 1065 * to disable the interrupt to avoid racing with it. 1066 */ 1067 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 1068 spin_lock(&nvmeq->cq_poll_lock); 1069 found = nvme_process_cq(nvmeq, &start, &end, tag); 1070 spin_unlock(&nvmeq->cq_poll_lock); 1071 } else { 1072 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1073 found = nvme_process_cq(nvmeq, &start, &end, tag); 1074 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1075 } 1076 1077 nvme_complete_cqes(nvmeq, start, end); 1078 return found; 1079 } 1080 1081 static int nvme_poll(struct blk_mq_hw_ctx *hctx) 1082 { 1083 struct nvme_queue *nvmeq = hctx->driver_data; 1084 u16 start, end; 1085 bool found; 1086 1087 if (!nvme_cqe_pending(nvmeq)) 1088 return 0; 1089 1090 spin_lock(&nvmeq->cq_poll_lock); 1091 found = nvme_process_cq(nvmeq, &start, &end, -1); 1092 spin_unlock(&nvmeq->cq_poll_lock); 1093 1094 nvme_complete_cqes(nvmeq, start, end); 1095 return found; 1096 } 1097 1098 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1099 { 1100 struct nvme_dev *dev = to_nvme_dev(ctrl); 1101 struct nvme_queue *nvmeq = &dev->queues[0]; 1102 struct nvme_command c; 1103 1104 memset(&c, 0, sizeof(c)); 1105 c.common.opcode = nvme_admin_async_event; 1106 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1107 nvme_submit_cmd(nvmeq, &c, true); 1108 } 1109 1110 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1111 { 1112 struct nvme_command c; 1113 1114 memset(&c, 0, sizeof(c)); 1115 c.delete_queue.opcode = opcode; 1116 c.delete_queue.qid = cpu_to_le16(id); 1117 1118 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1119 } 1120 1121 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1122 struct nvme_queue *nvmeq, s16 vector) 1123 { 1124 struct nvme_command c; 1125 int flags = NVME_QUEUE_PHYS_CONTIG; 1126 1127 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1128 flags |= NVME_CQ_IRQ_ENABLED; 1129 1130 /* 1131 * Note: we (ab)use the fact that the prp fields survive if no data 1132 * is attached to the request. 1133 */ 1134 memset(&c, 0, sizeof(c)); 1135 c.create_cq.opcode = nvme_admin_create_cq; 1136 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1137 c.create_cq.cqid = cpu_to_le16(qid); 1138 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1139 c.create_cq.cq_flags = cpu_to_le16(flags); 1140 c.create_cq.irq_vector = cpu_to_le16(vector); 1141 1142 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1143 } 1144 1145 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1146 struct nvme_queue *nvmeq) 1147 { 1148 struct nvme_ctrl *ctrl = &dev->ctrl; 1149 struct nvme_command c; 1150 int flags = NVME_QUEUE_PHYS_CONTIG; 1151 1152 /* 1153 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1154 * set. Since URGENT priority is zeroes, it makes all queues 1155 * URGENT. 1156 */ 1157 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1158 flags |= NVME_SQ_PRIO_MEDIUM; 1159 1160 /* 1161 * Note: we (ab)use the fact that the prp fields survive if no data 1162 * is attached to the request. 1163 */ 1164 memset(&c, 0, sizeof(c)); 1165 c.create_sq.opcode = nvme_admin_create_sq; 1166 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1167 c.create_sq.sqid = cpu_to_le16(qid); 1168 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1169 c.create_sq.sq_flags = cpu_to_le16(flags); 1170 c.create_sq.cqid = cpu_to_le16(qid); 1171 1172 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1173 } 1174 1175 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1176 { 1177 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1178 } 1179 1180 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1181 { 1182 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1183 } 1184 1185 static void abort_endio(struct request *req, blk_status_t error) 1186 { 1187 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1188 struct nvme_queue *nvmeq = iod->nvmeq; 1189 1190 dev_warn(nvmeq->dev->ctrl.device, 1191 "Abort status: 0x%x", nvme_req(req)->status); 1192 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1193 blk_mq_free_request(req); 1194 } 1195 1196 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1197 { 1198 1199 /* If true, indicates loss of adapter communication, possibly by a 1200 * NVMe Subsystem reset. 1201 */ 1202 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1203 1204 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1205 switch (dev->ctrl.state) { 1206 case NVME_CTRL_RESETTING: 1207 case NVME_CTRL_CONNECTING: 1208 return false; 1209 default: 1210 break; 1211 } 1212 1213 /* We shouldn't reset unless the controller is on fatal error state 1214 * _or_ if we lost the communication with it. 1215 */ 1216 if (!(csts & NVME_CSTS_CFS) && !nssro) 1217 return false; 1218 1219 return true; 1220 } 1221 1222 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1223 { 1224 /* Read a config register to help see what died. */ 1225 u16 pci_status; 1226 int result; 1227 1228 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1229 &pci_status); 1230 if (result == PCIBIOS_SUCCESSFUL) 1231 dev_warn(dev->ctrl.device, 1232 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1233 csts, pci_status); 1234 else 1235 dev_warn(dev->ctrl.device, 1236 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1237 csts, result); 1238 } 1239 1240 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1241 { 1242 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1243 struct nvme_queue *nvmeq = iod->nvmeq; 1244 struct nvme_dev *dev = nvmeq->dev; 1245 struct request *abort_req; 1246 struct nvme_command cmd; 1247 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1248 1249 /* If PCI error recovery process is happening, we cannot reset or 1250 * the recovery mechanism will surely fail. 1251 */ 1252 mb(); 1253 if (pci_channel_offline(to_pci_dev(dev->dev))) 1254 return BLK_EH_RESET_TIMER; 1255 1256 /* 1257 * Reset immediately if the controller is failed 1258 */ 1259 if (nvme_should_reset(dev, csts)) { 1260 nvme_warn_reset(dev, csts); 1261 nvme_dev_disable(dev, false); 1262 nvme_reset_ctrl(&dev->ctrl); 1263 return BLK_EH_DONE; 1264 } 1265 1266 /* 1267 * Did we miss an interrupt? 1268 */ 1269 if (nvme_poll_irqdisable(nvmeq, req->tag)) { 1270 dev_warn(dev->ctrl.device, 1271 "I/O %d QID %d timeout, completion polled\n", 1272 req->tag, nvmeq->qid); 1273 return BLK_EH_DONE; 1274 } 1275 1276 /* 1277 * Shutdown immediately if controller times out while starting. The 1278 * reset work will see the pci device disabled when it gets the forced 1279 * cancellation error. All outstanding requests are completed on 1280 * shutdown, so we return BLK_EH_DONE. 1281 */ 1282 switch (dev->ctrl.state) { 1283 case NVME_CTRL_CONNECTING: 1284 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1285 /* fall through */ 1286 case NVME_CTRL_DELETING: 1287 dev_warn_ratelimited(dev->ctrl.device, 1288 "I/O %d QID %d timeout, disable controller\n", 1289 req->tag, nvmeq->qid); 1290 nvme_dev_disable(dev, true); 1291 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1292 return BLK_EH_DONE; 1293 case NVME_CTRL_RESETTING: 1294 return BLK_EH_RESET_TIMER; 1295 default: 1296 break; 1297 } 1298 1299 /* 1300 * Shutdown the controller immediately and schedule a reset if the 1301 * command was already aborted once before and still hasn't been 1302 * returned to the driver, or if this is the admin queue. 1303 */ 1304 if (!nvmeq->qid || iod->aborted) { 1305 dev_warn(dev->ctrl.device, 1306 "I/O %d QID %d timeout, reset controller\n", 1307 req->tag, nvmeq->qid); 1308 nvme_dev_disable(dev, false); 1309 nvme_reset_ctrl(&dev->ctrl); 1310 1311 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1312 return BLK_EH_DONE; 1313 } 1314 1315 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1316 atomic_inc(&dev->ctrl.abort_limit); 1317 return BLK_EH_RESET_TIMER; 1318 } 1319 iod->aborted = 1; 1320 1321 memset(&cmd, 0, sizeof(cmd)); 1322 cmd.abort.opcode = nvme_admin_abort_cmd; 1323 cmd.abort.cid = req->tag; 1324 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1325 1326 dev_warn(nvmeq->dev->ctrl.device, 1327 "I/O %d QID %d timeout, aborting\n", 1328 req->tag, nvmeq->qid); 1329 1330 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1331 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1332 if (IS_ERR(abort_req)) { 1333 atomic_inc(&dev->ctrl.abort_limit); 1334 return BLK_EH_RESET_TIMER; 1335 } 1336 1337 abort_req->timeout = ADMIN_TIMEOUT; 1338 abort_req->end_io_data = NULL; 1339 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 1340 1341 /* 1342 * The aborted req will be completed on receiving the abort req. 1343 * We enable the timer again. If hit twice, it'll cause a device reset, 1344 * as the device then is in a faulty state. 1345 */ 1346 return BLK_EH_RESET_TIMER; 1347 } 1348 1349 static void nvme_free_queue(struct nvme_queue *nvmeq) 1350 { 1351 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1352 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1353 if (!nvmeq->sq_cmds) 1354 return; 1355 1356 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1357 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1358 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1359 } else { 1360 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1361 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1362 } 1363 } 1364 1365 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1366 { 1367 int i; 1368 1369 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1370 dev->ctrl.queue_count--; 1371 nvme_free_queue(&dev->queues[i]); 1372 } 1373 } 1374 1375 /** 1376 * nvme_suspend_queue - put queue into suspended state 1377 * @nvmeq: queue to suspend 1378 */ 1379 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1380 { 1381 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1382 return 1; 1383 1384 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1385 mb(); 1386 1387 nvmeq->dev->online_queues--; 1388 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1389 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 1390 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1391 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1392 return 0; 1393 } 1394 1395 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1396 { 1397 int i; 1398 1399 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1400 nvme_suspend_queue(&dev->queues[i]); 1401 } 1402 1403 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1404 { 1405 struct nvme_queue *nvmeq = &dev->queues[0]; 1406 1407 if (shutdown) 1408 nvme_shutdown_ctrl(&dev->ctrl); 1409 else 1410 nvme_disable_ctrl(&dev->ctrl); 1411 1412 nvme_poll_irqdisable(nvmeq, -1); 1413 } 1414 1415 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1416 int entry_size) 1417 { 1418 int q_depth = dev->q_depth; 1419 unsigned q_size_aligned = roundup(q_depth * entry_size, 1420 dev->ctrl.page_size); 1421 1422 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1423 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1424 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1425 q_depth = div_u64(mem_per_q, entry_size); 1426 1427 /* 1428 * Ensure the reduced q_depth is above some threshold where it 1429 * would be better to map queues in system memory with the 1430 * original depth 1431 */ 1432 if (q_depth < 64) 1433 return -ENOMEM; 1434 } 1435 1436 return q_depth; 1437 } 1438 1439 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1440 int qid) 1441 { 1442 struct pci_dev *pdev = to_pci_dev(dev->dev); 1443 1444 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1445 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1446 if (nvmeq->sq_cmds) { 1447 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1448 nvmeq->sq_cmds); 1449 if (nvmeq->sq_dma_addr) { 1450 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1451 return 0; 1452 } 1453 1454 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1455 } 1456 } 1457 1458 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1459 &nvmeq->sq_dma_addr, GFP_KERNEL); 1460 if (!nvmeq->sq_cmds) 1461 return -ENOMEM; 1462 return 0; 1463 } 1464 1465 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1466 { 1467 struct nvme_queue *nvmeq = &dev->queues[qid]; 1468 1469 if (dev->ctrl.queue_count > qid) 1470 return 0; 1471 1472 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1473 nvmeq->q_depth = depth; 1474 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1475 &nvmeq->cq_dma_addr, GFP_KERNEL); 1476 if (!nvmeq->cqes) 1477 goto free_nvmeq; 1478 1479 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1480 goto free_cqdma; 1481 1482 nvmeq->dev = dev; 1483 spin_lock_init(&nvmeq->sq_lock); 1484 spin_lock_init(&nvmeq->cq_poll_lock); 1485 nvmeq->cq_head = 0; 1486 nvmeq->cq_phase = 1; 1487 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1488 nvmeq->qid = qid; 1489 dev->ctrl.queue_count++; 1490 1491 return 0; 1492 1493 free_cqdma: 1494 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1495 nvmeq->cq_dma_addr); 1496 free_nvmeq: 1497 return -ENOMEM; 1498 } 1499 1500 static int queue_request_irq(struct nvme_queue *nvmeq) 1501 { 1502 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1503 int nr = nvmeq->dev->ctrl.instance; 1504 1505 if (use_threaded_interrupts) { 1506 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1507 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1508 } else { 1509 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1510 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1511 } 1512 } 1513 1514 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1515 { 1516 struct nvme_dev *dev = nvmeq->dev; 1517 1518 nvmeq->sq_tail = 0; 1519 nvmeq->last_sq_tail = 0; 1520 nvmeq->cq_head = 0; 1521 nvmeq->cq_phase = 1; 1522 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1523 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1524 nvme_dbbuf_init(dev, nvmeq, qid); 1525 dev->online_queues++; 1526 wmb(); /* ensure the first interrupt sees the initialization */ 1527 } 1528 1529 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1530 { 1531 struct nvme_dev *dev = nvmeq->dev; 1532 int result; 1533 u16 vector = 0; 1534 1535 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1536 1537 /* 1538 * A queue's vector matches the queue identifier unless the controller 1539 * has only one vector available. 1540 */ 1541 if (!polled) 1542 vector = dev->num_vecs == 1 ? 0 : qid; 1543 else 1544 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1545 1546 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1547 if (result) 1548 return result; 1549 1550 result = adapter_alloc_sq(dev, qid, nvmeq); 1551 if (result < 0) 1552 return result; 1553 else if (result) 1554 goto release_cq; 1555 1556 nvmeq->cq_vector = vector; 1557 nvme_init_queue(nvmeq, qid); 1558 1559 if (!polled) { 1560 result = queue_request_irq(nvmeq); 1561 if (result < 0) 1562 goto release_sq; 1563 } 1564 1565 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1566 return result; 1567 1568 release_sq: 1569 dev->online_queues--; 1570 adapter_delete_sq(dev, qid); 1571 release_cq: 1572 adapter_delete_cq(dev, qid); 1573 return result; 1574 } 1575 1576 static const struct blk_mq_ops nvme_mq_admin_ops = { 1577 .queue_rq = nvme_queue_rq, 1578 .complete = nvme_pci_complete_rq, 1579 .init_hctx = nvme_admin_init_hctx, 1580 .exit_hctx = nvme_admin_exit_hctx, 1581 .init_request = nvme_init_request, 1582 .timeout = nvme_timeout, 1583 }; 1584 1585 static const struct blk_mq_ops nvme_mq_ops = { 1586 .queue_rq = nvme_queue_rq, 1587 .complete = nvme_pci_complete_rq, 1588 .commit_rqs = nvme_commit_rqs, 1589 .init_hctx = nvme_init_hctx, 1590 .init_request = nvme_init_request, 1591 .map_queues = nvme_pci_map_queues, 1592 .timeout = nvme_timeout, 1593 .poll = nvme_poll, 1594 }; 1595 1596 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1597 { 1598 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1599 /* 1600 * If the controller was reset during removal, it's possible 1601 * user requests may be waiting on a stopped queue. Start the 1602 * queue to flush these to completion. 1603 */ 1604 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1605 blk_cleanup_queue(dev->ctrl.admin_q); 1606 blk_mq_free_tag_set(&dev->admin_tagset); 1607 } 1608 } 1609 1610 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1611 { 1612 if (!dev->ctrl.admin_q) { 1613 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1614 dev->admin_tagset.nr_hw_queues = 1; 1615 1616 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1617 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1618 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1619 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1620 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1621 dev->admin_tagset.driver_data = dev; 1622 1623 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1624 return -ENOMEM; 1625 dev->ctrl.admin_tagset = &dev->admin_tagset; 1626 1627 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1628 if (IS_ERR(dev->ctrl.admin_q)) { 1629 blk_mq_free_tag_set(&dev->admin_tagset); 1630 return -ENOMEM; 1631 } 1632 if (!blk_get_queue(dev->ctrl.admin_q)) { 1633 nvme_dev_remove_admin(dev); 1634 dev->ctrl.admin_q = NULL; 1635 return -ENODEV; 1636 } 1637 } else 1638 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1639 1640 return 0; 1641 } 1642 1643 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1644 { 1645 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1646 } 1647 1648 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1649 { 1650 struct pci_dev *pdev = to_pci_dev(dev->dev); 1651 1652 if (size <= dev->bar_mapped_size) 1653 return 0; 1654 if (size > pci_resource_len(pdev, 0)) 1655 return -ENOMEM; 1656 if (dev->bar) 1657 iounmap(dev->bar); 1658 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1659 if (!dev->bar) { 1660 dev->bar_mapped_size = 0; 1661 return -ENOMEM; 1662 } 1663 dev->bar_mapped_size = size; 1664 dev->dbs = dev->bar + NVME_REG_DBS; 1665 1666 return 0; 1667 } 1668 1669 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1670 { 1671 int result; 1672 u32 aqa; 1673 struct nvme_queue *nvmeq; 1674 1675 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1676 if (result < 0) 1677 return result; 1678 1679 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1680 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1681 1682 if (dev->subsystem && 1683 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1684 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1685 1686 result = nvme_disable_ctrl(&dev->ctrl); 1687 if (result < 0) 1688 return result; 1689 1690 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1691 if (result) 1692 return result; 1693 1694 nvmeq = &dev->queues[0]; 1695 aqa = nvmeq->q_depth - 1; 1696 aqa |= aqa << 16; 1697 1698 writel(aqa, dev->bar + NVME_REG_AQA); 1699 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1700 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1701 1702 result = nvme_enable_ctrl(&dev->ctrl); 1703 if (result) 1704 return result; 1705 1706 nvmeq->cq_vector = 0; 1707 nvme_init_queue(nvmeq, 0); 1708 result = queue_request_irq(nvmeq); 1709 if (result) { 1710 dev->online_queues--; 1711 return result; 1712 } 1713 1714 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1715 return result; 1716 } 1717 1718 static int nvme_create_io_queues(struct nvme_dev *dev) 1719 { 1720 unsigned i, max, rw_queues; 1721 int ret = 0; 1722 1723 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1724 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1725 ret = -ENOMEM; 1726 break; 1727 } 1728 } 1729 1730 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1731 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1732 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1733 dev->io_queues[HCTX_TYPE_READ]; 1734 } else { 1735 rw_queues = max; 1736 } 1737 1738 for (i = dev->online_queues; i <= max; i++) { 1739 bool polled = i > rw_queues; 1740 1741 ret = nvme_create_queue(&dev->queues[i], i, polled); 1742 if (ret) 1743 break; 1744 } 1745 1746 /* 1747 * Ignore failing Create SQ/CQ commands, we can continue with less 1748 * than the desired amount of queues, and even a controller without 1749 * I/O queues can still be used to issue admin commands. This might 1750 * be useful to upgrade a buggy firmware for example. 1751 */ 1752 return ret >= 0 ? 0 : ret; 1753 } 1754 1755 static ssize_t nvme_cmb_show(struct device *dev, 1756 struct device_attribute *attr, 1757 char *buf) 1758 { 1759 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1760 1761 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1762 ndev->cmbloc, ndev->cmbsz); 1763 } 1764 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1765 1766 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1767 { 1768 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1769 1770 return 1ULL << (12 + 4 * szu); 1771 } 1772 1773 static u32 nvme_cmb_size(struct nvme_dev *dev) 1774 { 1775 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1776 } 1777 1778 static void nvme_map_cmb(struct nvme_dev *dev) 1779 { 1780 u64 size, offset; 1781 resource_size_t bar_size; 1782 struct pci_dev *pdev = to_pci_dev(dev->dev); 1783 int bar; 1784 1785 if (dev->cmb_size) 1786 return; 1787 1788 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1789 if (!dev->cmbsz) 1790 return; 1791 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1792 1793 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1794 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1795 bar = NVME_CMB_BIR(dev->cmbloc); 1796 bar_size = pci_resource_len(pdev, bar); 1797 1798 if (offset > bar_size) 1799 return; 1800 1801 /* 1802 * Controllers may support a CMB size larger than their BAR, 1803 * for example, due to being behind a bridge. Reduce the CMB to 1804 * the reported size of the BAR 1805 */ 1806 if (size > bar_size - offset) 1807 size = bar_size - offset; 1808 1809 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1810 dev_warn(dev->ctrl.device, 1811 "failed to register the CMB\n"); 1812 return; 1813 } 1814 1815 dev->cmb_size = size; 1816 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1817 1818 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1819 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1820 pci_p2pmem_publish(pdev, true); 1821 1822 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1823 &dev_attr_cmb.attr, NULL)) 1824 dev_warn(dev->ctrl.device, 1825 "failed to add sysfs attribute for CMB\n"); 1826 } 1827 1828 static inline void nvme_release_cmb(struct nvme_dev *dev) 1829 { 1830 if (dev->cmb_size) { 1831 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1832 &dev_attr_cmb.attr, NULL); 1833 dev->cmb_size = 0; 1834 } 1835 } 1836 1837 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1838 { 1839 u64 dma_addr = dev->host_mem_descs_dma; 1840 struct nvme_command c; 1841 int ret; 1842 1843 memset(&c, 0, sizeof(c)); 1844 c.features.opcode = nvme_admin_set_features; 1845 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1846 c.features.dword11 = cpu_to_le32(bits); 1847 c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 1848 ilog2(dev->ctrl.page_size)); 1849 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1850 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1851 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1852 1853 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1854 if (ret) { 1855 dev_warn(dev->ctrl.device, 1856 "failed to set host mem (err %d, flags %#x).\n", 1857 ret, bits); 1858 } 1859 return ret; 1860 } 1861 1862 static void nvme_free_host_mem(struct nvme_dev *dev) 1863 { 1864 int i; 1865 1866 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1867 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1868 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 1869 1870 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1871 le64_to_cpu(desc->addr), 1872 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1873 } 1874 1875 kfree(dev->host_mem_desc_bufs); 1876 dev->host_mem_desc_bufs = NULL; 1877 dma_free_coherent(dev->dev, 1878 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1879 dev->host_mem_descs, dev->host_mem_descs_dma); 1880 dev->host_mem_descs = NULL; 1881 dev->nr_host_mem_descs = 0; 1882 } 1883 1884 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1885 u32 chunk_size) 1886 { 1887 struct nvme_host_mem_buf_desc *descs; 1888 u32 max_entries, len; 1889 dma_addr_t descs_dma; 1890 int i = 0; 1891 void **bufs; 1892 u64 size, tmp; 1893 1894 tmp = (preferred + chunk_size - 1); 1895 do_div(tmp, chunk_size); 1896 max_entries = tmp; 1897 1898 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1899 max_entries = dev->ctrl.hmmaxd; 1900 1901 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 1902 &descs_dma, GFP_KERNEL); 1903 if (!descs) 1904 goto out; 1905 1906 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1907 if (!bufs) 1908 goto out_free_descs; 1909 1910 for (size = 0; size < preferred && i < max_entries; size += len) { 1911 dma_addr_t dma_addr; 1912 1913 len = min_t(u64, chunk_size, preferred - size); 1914 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1915 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1916 if (!bufs[i]) 1917 break; 1918 1919 descs[i].addr = cpu_to_le64(dma_addr); 1920 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 1921 i++; 1922 } 1923 1924 if (!size) 1925 goto out_free_bufs; 1926 1927 dev->nr_host_mem_descs = i; 1928 dev->host_mem_size = size; 1929 dev->host_mem_descs = descs; 1930 dev->host_mem_descs_dma = descs_dma; 1931 dev->host_mem_desc_bufs = bufs; 1932 return 0; 1933 1934 out_free_bufs: 1935 while (--i >= 0) { 1936 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 1937 1938 dma_free_attrs(dev->dev, size, bufs[i], 1939 le64_to_cpu(descs[i].addr), 1940 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1941 } 1942 1943 kfree(bufs); 1944 out_free_descs: 1945 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1946 descs_dma); 1947 out: 1948 dev->host_mem_descs = NULL; 1949 return -ENOMEM; 1950 } 1951 1952 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 1953 { 1954 u32 chunk_size; 1955 1956 /* start big and work our way down */ 1957 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1958 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 1959 chunk_size /= 2) { 1960 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 1961 if (!min || dev->host_mem_size >= min) 1962 return 0; 1963 nvme_free_host_mem(dev); 1964 } 1965 } 1966 1967 return -ENOMEM; 1968 } 1969 1970 static int nvme_setup_host_mem(struct nvme_dev *dev) 1971 { 1972 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 1973 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 1974 u64 min = (u64)dev->ctrl.hmmin * 4096; 1975 u32 enable_bits = NVME_HOST_MEM_ENABLE; 1976 int ret; 1977 1978 preferred = min(preferred, max); 1979 if (min > max) { 1980 dev_warn(dev->ctrl.device, 1981 "min host memory (%lld MiB) above limit (%d MiB).\n", 1982 min >> ilog2(SZ_1M), max_host_mem_size_mb); 1983 nvme_free_host_mem(dev); 1984 return 0; 1985 } 1986 1987 /* 1988 * If we already have a buffer allocated check if we can reuse it. 1989 */ 1990 if (dev->host_mem_descs) { 1991 if (dev->host_mem_size >= min) 1992 enable_bits |= NVME_HOST_MEM_RETURN; 1993 else 1994 nvme_free_host_mem(dev); 1995 } 1996 1997 if (!dev->host_mem_descs) { 1998 if (nvme_alloc_host_mem(dev, min, preferred)) { 1999 dev_warn(dev->ctrl.device, 2000 "failed to allocate host memory buffer.\n"); 2001 return 0; /* controller must work without HMB */ 2002 } 2003 2004 dev_info(dev->ctrl.device, 2005 "allocated %lld MiB host memory buffer.\n", 2006 dev->host_mem_size >> ilog2(SZ_1M)); 2007 } 2008 2009 ret = nvme_set_host_mem(dev, enable_bits); 2010 if (ret) 2011 nvme_free_host_mem(dev); 2012 return ret; 2013 } 2014 2015 /* 2016 * nirqs is the number of interrupts available for write and read 2017 * queues. The core already reserved an interrupt for the admin queue. 2018 */ 2019 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2020 { 2021 struct nvme_dev *dev = affd->priv; 2022 unsigned int nr_read_queues; 2023 2024 /* 2025 * If there is no interupt available for queues, ensure that 2026 * the default queue is set to 1. The affinity set size is 2027 * also set to one, but the irq core ignores it for this case. 2028 * 2029 * If only one interrupt is available or 'write_queue' == 0, combine 2030 * write and read queues. 2031 * 2032 * If 'write_queues' > 0, ensure it leaves room for at least one read 2033 * queue. 2034 */ 2035 if (!nrirqs) { 2036 nrirqs = 1; 2037 nr_read_queues = 0; 2038 } else if (nrirqs == 1 || !write_queues) { 2039 nr_read_queues = 0; 2040 } else if (write_queues >= nrirqs) { 2041 nr_read_queues = 1; 2042 } else { 2043 nr_read_queues = nrirqs - write_queues; 2044 } 2045 2046 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2047 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2048 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2049 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2050 affd->nr_sets = nr_read_queues ? 2 : 1; 2051 } 2052 2053 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2054 { 2055 struct pci_dev *pdev = to_pci_dev(dev->dev); 2056 struct irq_affinity affd = { 2057 .pre_vectors = 1, 2058 .calc_sets = nvme_calc_irq_sets, 2059 .priv = dev, 2060 }; 2061 unsigned int irq_queues, this_p_queues; 2062 unsigned int nr_cpus = num_possible_cpus(); 2063 2064 /* 2065 * Poll queues don't need interrupts, but we need at least one IO 2066 * queue left over for non-polled IO. 2067 */ 2068 this_p_queues = poll_queues; 2069 if (this_p_queues >= nr_io_queues) { 2070 this_p_queues = nr_io_queues - 1; 2071 irq_queues = 1; 2072 } else { 2073 if (nr_cpus < nr_io_queues - this_p_queues) 2074 irq_queues = nr_cpus + 1; 2075 else 2076 irq_queues = nr_io_queues - this_p_queues + 1; 2077 } 2078 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 2079 2080 /* Initialize for the single interrupt case */ 2081 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2082 dev->io_queues[HCTX_TYPE_READ] = 0; 2083 2084 /* 2085 * Some Apple controllers require all queues to use the 2086 * first vector. 2087 */ 2088 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR) 2089 irq_queues = 1; 2090 2091 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2092 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2093 } 2094 2095 static void nvme_disable_io_queues(struct nvme_dev *dev) 2096 { 2097 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2098 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2099 } 2100 2101 static int nvme_setup_io_queues(struct nvme_dev *dev) 2102 { 2103 struct nvme_queue *adminq = &dev->queues[0]; 2104 struct pci_dev *pdev = to_pci_dev(dev->dev); 2105 int result, nr_io_queues; 2106 unsigned long size; 2107 2108 nr_io_queues = max_io_queues(); 2109 2110 /* 2111 * If tags are shared with admin queue (Apple bug), then 2112 * make sure we only use one IO queue. 2113 */ 2114 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2115 nr_io_queues = 1; 2116 2117 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2118 if (result < 0) 2119 return result; 2120 2121 if (nr_io_queues == 0) 2122 return 0; 2123 2124 clear_bit(NVMEQ_ENABLED, &adminq->flags); 2125 2126 if (dev->cmb_use_sqes) { 2127 result = nvme_cmb_qdepth(dev, nr_io_queues, 2128 sizeof(struct nvme_command)); 2129 if (result > 0) 2130 dev->q_depth = result; 2131 else 2132 dev->cmb_use_sqes = false; 2133 } 2134 2135 do { 2136 size = db_bar_size(dev, nr_io_queues); 2137 result = nvme_remap_bar(dev, size); 2138 if (!result) 2139 break; 2140 if (!--nr_io_queues) 2141 return -ENOMEM; 2142 } while (1); 2143 adminq->q_db = dev->dbs; 2144 2145 retry: 2146 /* Deregister the admin queue's interrupt */ 2147 pci_free_irq(pdev, 0, adminq); 2148 2149 /* 2150 * If we enable msix early due to not intx, disable it again before 2151 * setting up the full range we need. 2152 */ 2153 pci_free_irq_vectors(pdev); 2154 2155 result = nvme_setup_irqs(dev, nr_io_queues); 2156 if (result <= 0) 2157 return -EIO; 2158 2159 dev->num_vecs = result; 2160 result = max(result - 1, 1); 2161 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2162 2163 /* 2164 * Should investigate if there's a performance win from allocating 2165 * more queues than interrupt vectors; it might allow the submission 2166 * path to scale better, even if the receive path is limited by the 2167 * number of interrupts. 2168 */ 2169 result = queue_request_irq(adminq); 2170 if (result) 2171 return result; 2172 set_bit(NVMEQ_ENABLED, &adminq->flags); 2173 2174 result = nvme_create_io_queues(dev); 2175 if (result || dev->online_queues < 2) 2176 return result; 2177 2178 if (dev->online_queues - 1 < dev->max_qid) { 2179 nr_io_queues = dev->online_queues - 1; 2180 nvme_disable_io_queues(dev); 2181 nvme_suspend_io_queues(dev); 2182 goto retry; 2183 } 2184 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2185 dev->io_queues[HCTX_TYPE_DEFAULT], 2186 dev->io_queues[HCTX_TYPE_READ], 2187 dev->io_queues[HCTX_TYPE_POLL]); 2188 return 0; 2189 } 2190 2191 static void nvme_del_queue_end(struct request *req, blk_status_t error) 2192 { 2193 struct nvme_queue *nvmeq = req->end_io_data; 2194 2195 blk_mq_free_request(req); 2196 complete(&nvmeq->delete_done); 2197 } 2198 2199 static void nvme_del_cq_end(struct request *req, blk_status_t error) 2200 { 2201 struct nvme_queue *nvmeq = req->end_io_data; 2202 2203 if (error) 2204 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2205 2206 nvme_del_queue_end(req, error); 2207 } 2208 2209 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2210 { 2211 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2212 struct request *req; 2213 struct nvme_command cmd; 2214 2215 memset(&cmd, 0, sizeof(cmd)); 2216 cmd.delete_queue.opcode = opcode; 2217 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2218 2219 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2220 if (IS_ERR(req)) 2221 return PTR_ERR(req); 2222 2223 req->timeout = ADMIN_TIMEOUT; 2224 req->end_io_data = nvmeq; 2225 2226 init_completion(&nvmeq->delete_done); 2227 blk_execute_rq_nowait(q, NULL, req, false, 2228 opcode == nvme_admin_delete_cq ? 2229 nvme_del_cq_end : nvme_del_queue_end); 2230 return 0; 2231 } 2232 2233 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2234 { 2235 int nr_queues = dev->online_queues - 1, sent = 0; 2236 unsigned long timeout; 2237 2238 retry: 2239 timeout = ADMIN_TIMEOUT; 2240 while (nr_queues > 0) { 2241 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2242 break; 2243 nr_queues--; 2244 sent++; 2245 } 2246 while (sent) { 2247 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2248 2249 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2250 timeout); 2251 if (timeout == 0) 2252 return false; 2253 2254 /* handle any remaining CQEs */ 2255 if (opcode == nvme_admin_delete_cq && 2256 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2257 nvme_poll_irqdisable(nvmeq, -1); 2258 2259 sent--; 2260 if (nr_queues) 2261 goto retry; 2262 } 2263 return true; 2264 } 2265 2266 /* 2267 * return error value only when tagset allocation failed 2268 */ 2269 static int nvme_dev_add(struct nvme_dev *dev) 2270 { 2271 int ret; 2272 2273 if (!dev->ctrl.tagset) { 2274 dev->tagset.ops = &nvme_mq_ops; 2275 dev->tagset.nr_hw_queues = dev->online_queues - 1; 2276 dev->tagset.nr_maps = 2; /* default + read */ 2277 if (dev->io_queues[HCTX_TYPE_POLL]) 2278 dev->tagset.nr_maps++; 2279 dev->tagset.timeout = NVME_IO_TIMEOUT; 2280 dev->tagset.numa_node = dev_to_node(dev->dev); 2281 dev->tagset.queue_depth = 2282 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2283 dev->tagset.cmd_size = sizeof(struct nvme_iod); 2284 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 2285 dev->tagset.driver_data = dev; 2286 2287 /* 2288 * Some Apple controllers requires tags to be unique 2289 * across admin and IO queue, so reserve the first 32 2290 * tags of the IO queue. 2291 */ 2292 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2293 dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2294 2295 ret = blk_mq_alloc_tag_set(&dev->tagset); 2296 if (ret) { 2297 dev_warn(dev->ctrl.device, 2298 "IO queues tagset allocation failed %d\n", ret); 2299 return ret; 2300 } 2301 dev->ctrl.tagset = &dev->tagset; 2302 } else { 2303 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2304 2305 /* Free previously allocated queues that are no longer usable */ 2306 nvme_free_queues(dev, dev->online_queues); 2307 } 2308 2309 nvme_dbbuf_set(dev); 2310 return 0; 2311 } 2312 2313 static int nvme_pci_enable(struct nvme_dev *dev) 2314 { 2315 int result = -ENOMEM; 2316 struct pci_dev *pdev = to_pci_dev(dev->dev); 2317 2318 if (pci_enable_device_mem(pdev)) 2319 return result; 2320 2321 pci_set_master(pdev); 2322 2323 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 2324 goto disable; 2325 2326 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2327 result = -ENODEV; 2328 goto disable; 2329 } 2330 2331 /* 2332 * Some devices and/or platforms don't advertise or work with INTx 2333 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2334 * adjust this later. 2335 */ 2336 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2337 if (result < 0) 2338 return result; 2339 2340 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2341 2342 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2343 io_queue_depth); 2344 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2345 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2346 dev->dbs = dev->bar + 4096; 2347 2348 /* 2349 * Some Apple controllers require a non-standard SQE size. 2350 * Interestingly they also seem to ignore the CC:IOSQES register 2351 * so we don't bother updating it here. 2352 */ 2353 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2354 dev->io_sqes = 7; 2355 else 2356 dev->io_sqes = NVME_NVM_IOSQES; 2357 2358 /* 2359 * Temporary fix for the Apple controller found in the MacBook8,1 and 2360 * some MacBook7,1 to avoid controller resets and data loss. 2361 */ 2362 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2363 dev->q_depth = 2; 2364 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2365 "set queue depth=%u to work around controller resets\n", 2366 dev->q_depth); 2367 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2368 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2369 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2370 dev->q_depth = 64; 2371 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2372 "set queue depth=%u\n", dev->q_depth); 2373 } 2374 2375 /* 2376 * Controllers with the shared tags quirk need the IO queue to be 2377 * big enough so that we get 32 tags for the admin queue 2378 */ 2379 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2380 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2381 dev->q_depth = NVME_AQ_DEPTH + 2; 2382 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2383 dev->q_depth); 2384 } 2385 2386 2387 nvme_map_cmb(dev); 2388 2389 pci_enable_pcie_error_reporting(pdev); 2390 pci_save_state(pdev); 2391 return 0; 2392 2393 disable: 2394 pci_disable_device(pdev); 2395 return result; 2396 } 2397 2398 static void nvme_dev_unmap(struct nvme_dev *dev) 2399 { 2400 if (dev->bar) 2401 iounmap(dev->bar); 2402 pci_release_mem_regions(to_pci_dev(dev->dev)); 2403 } 2404 2405 static void nvme_pci_disable(struct nvme_dev *dev) 2406 { 2407 struct pci_dev *pdev = to_pci_dev(dev->dev); 2408 2409 pci_free_irq_vectors(pdev); 2410 2411 if (pci_is_enabled(pdev)) { 2412 pci_disable_pcie_error_reporting(pdev); 2413 pci_disable_device(pdev); 2414 } 2415 } 2416 2417 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2418 { 2419 bool dead = true, freeze = false; 2420 struct pci_dev *pdev = to_pci_dev(dev->dev); 2421 2422 mutex_lock(&dev->shutdown_lock); 2423 if (pci_is_enabled(pdev)) { 2424 u32 csts = readl(dev->bar + NVME_REG_CSTS); 2425 2426 if (dev->ctrl.state == NVME_CTRL_LIVE || 2427 dev->ctrl.state == NVME_CTRL_RESETTING) { 2428 freeze = true; 2429 nvme_start_freeze(&dev->ctrl); 2430 } 2431 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2432 pdev->error_state != pci_channel_io_normal); 2433 } 2434 2435 /* 2436 * Give the controller a chance to complete all entered requests if 2437 * doing a safe shutdown. 2438 */ 2439 if (!dead && shutdown && freeze) 2440 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2441 2442 nvme_stop_queues(&dev->ctrl); 2443 2444 if (!dead && dev->ctrl.queue_count > 0) { 2445 nvme_disable_io_queues(dev); 2446 nvme_disable_admin_queue(dev, shutdown); 2447 } 2448 nvme_suspend_io_queues(dev); 2449 nvme_suspend_queue(&dev->queues[0]); 2450 nvme_pci_disable(dev); 2451 2452 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2453 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2454 blk_mq_tagset_wait_completed_request(&dev->tagset); 2455 blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2456 2457 /* 2458 * The driver will not be starting up queues again if shutting down so 2459 * must flush all entered requests to their failed completion to avoid 2460 * deadlocking blk-mq hot-cpu notifier. 2461 */ 2462 if (shutdown) { 2463 nvme_start_queues(&dev->ctrl); 2464 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2465 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2466 } 2467 mutex_unlock(&dev->shutdown_lock); 2468 } 2469 2470 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2471 { 2472 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2473 PAGE_SIZE, PAGE_SIZE, 0); 2474 if (!dev->prp_page_pool) 2475 return -ENOMEM; 2476 2477 /* Optimisation for I/Os between 4k and 128k */ 2478 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2479 256, 256, 0); 2480 if (!dev->prp_small_pool) { 2481 dma_pool_destroy(dev->prp_page_pool); 2482 return -ENOMEM; 2483 } 2484 return 0; 2485 } 2486 2487 static void nvme_release_prp_pools(struct nvme_dev *dev) 2488 { 2489 dma_pool_destroy(dev->prp_page_pool); 2490 dma_pool_destroy(dev->prp_small_pool); 2491 } 2492 2493 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2494 { 2495 struct nvme_dev *dev = to_nvme_dev(ctrl); 2496 2497 nvme_dbbuf_dma_free(dev); 2498 put_device(dev->dev); 2499 if (dev->tagset.tags) 2500 blk_mq_free_tag_set(&dev->tagset); 2501 if (dev->ctrl.admin_q) 2502 blk_put_queue(dev->ctrl.admin_q); 2503 kfree(dev->queues); 2504 free_opal_dev(dev->ctrl.opal_dev); 2505 mempool_destroy(dev->iod_mempool); 2506 kfree(dev); 2507 } 2508 2509 static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2510 { 2511 nvme_get_ctrl(&dev->ctrl); 2512 nvme_dev_disable(dev, false); 2513 nvme_kill_queues(&dev->ctrl); 2514 if (!queue_work(nvme_wq, &dev->remove_work)) 2515 nvme_put_ctrl(&dev->ctrl); 2516 } 2517 2518 static void nvme_reset_work(struct work_struct *work) 2519 { 2520 struct nvme_dev *dev = 2521 container_of(work, struct nvme_dev, ctrl.reset_work); 2522 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2523 int result; 2524 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 2525 2526 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2527 result = -ENODEV; 2528 goto out; 2529 } 2530 2531 /* 2532 * If we're called to reset a live controller first shut it down before 2533 * moving on. 2534 */ 2535 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2536 nvme_dev_disable(dev, false); 2537 nvme_sync_queues(&dev->ctrl); 2538 2539 mutex_lock(&dev->shutdown_lock); 2540 result = nvme_pci_enable(dev); 2541 if (result) 2542 goto out_unlock; 2543 2544 result = nvme_pci_configure_admin_queue(dev); 2545 if (result) 2546 goto out_unlock; 2547 2548 result = nvme_alloc_admin_tags(dev); 2549 if (result) 2550 goto out_unlock; 2551 2552 /* 2553 * Limit the max command size to prevent iod->sg allocations going 2554 * over a single page. 2555 */ 2556 dev->ctrl.max_hw_sectors = min_t(u32, 2557 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2558 dev->ctrl.max_segments = NVME_MAX_SEGS; 2559 2560 /* 2561 * Don't limit the IOMMU merged segment size. 2562 */ 2563 dma_set_max_seg_size(dev->dev, 0xffffffff); 2564 2565 mutex_unlock(&dev->shutdown_lock); 2566 2567 /* 2568 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2569 * initializing procedure here. 2570 */ 2571 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2572 dev_warn(dev->ctrl.device, 2573 "failed to mark controller CONNECTING\n"); 2574 result = -EBUSY; 2575 goto out; 2576 } 2577 2578 result = nvme_init_identify(&dev->ctrl); 2579 if (result) 2580 goto out; 2581 2582 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2583 if (!dev->ctrl.opal_dev) 2584 dev->ctrl.opal_dev = 2585 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2586 else if (was_suspend) 2587 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2588 } else { 2589 free_opal_dev(dev->ctrl.opal_dev); 2590 dev->ctrl.opal_dev = NULL; 2591 } 2592 2593 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2594 result = nvme_dbbuf_dma_alloc(dev); 2595 if (result) 2596 dev_warn(dev->dev, 2597 "unable to allocate dma for dbbuf\n"); 2598 } 2599 2600 if (dev->ctrl.hmpre) { 2601 result = nvme_setup_host_mem(dev); 2602 if (result < 0) 2603 goto out; 2604 } 2605 2606 result = nvme_setup_io_queues(dev); 2607 if (result) 2608 goto out; 2609 2610 /* 2611 * Keep the controller around but remove all namespaces if we don't have 2612 * any working I/O queue. 2613 */ 2614 if (dev->online_queues < 2) { 2615 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2616 nvme_kill_queues(&dev->ctrl); 2617 nvme_remove_namespaces(&dev->ctrl); 2618 new_state = NVME_CTRL_ADMIN_ONLY; 2619 } else { 2620 nvme_start_queues(&dev->ctrl); 2621 nvme_wait_freeze(&dev->ctrl); 2622 /* hit this only when allocate tagset fails */ 2623 if (nvme_dev_add(dev)) 2624 new_state = NVME_CTRL_ADMIN_ONLY; 2625 nvme_unfreeze(&dev->ctrl); 2626 } 2627 2628 /* 2629 * If only admin queue live, keep it to do further investigation or 2630 * recovery. 2631 */ 2632 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 2633 dev_warn(dev->ctrl.device, 2634 "failed to mark controller state %d\n", new_state); 2635 result = -ENODEV; 2636 goto out; 2637 } 2638 2639 nvme_start_ctrl(&dev->ctrl); 2640 return; 2641 2642 out_unlock: 2643 mutex_unlock(&dev->shutdown_lock); 2644 out: 2645 if (result) 2646 dev_warn(dev->ctrl.device, 2647 "Removing after probe failure status: %d\n", result); 2648 nvme_remove_dead_ctrl(dev); 2649 } 2650 2651 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2652 { 2653 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2654 struct pci_dev *pdev = to_pci_dev(dev->dev); 2655 2656 if (pci_get_drvdata(pdev)) 2657 device_release_driver(&pdev->dev); 2658 nvme_put_ctrl(&dev->ctrl); 2659 } 2660 2661 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2662 { 2663 *val = readl(to_nvme_dev(ctrl)->bar + off); 2664 return 0; 2665 } 2666 2667 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2668 { 2669 writel(val, to_nvme_dev(ctrl)->bar + off); 2670 return 0; 2671 } 2672 2673 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2674 { 2675 *val = readq(to_nvme_dev(ctrl)->bar + off); 2676 return 0; 2677 } 2678 2679 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2680 { 2681 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2682 2683 return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 2684 } 2685 2686 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2687 .name = "pcie", 2688 .module = THIS_MODULE, 2689 .flags = NVME_F_METADATA_SUPPORTED | 2690 NVME_F_PCI_P2PDMA, 2691 .reg_read32 = nvme_pci_reg_read32, 2692 .reg_write32 = nvme_pci_reg_write32, 2693 .reg_read64 = nvme_pci_reg_read64, 2694 .free_ctrl = nvme_pci_free_ctrl, 2695 .submit_async_event = nvme_pci_submit_async_event, 2696 .get_address = nvme_pci_get_address, 2697 }; 2698 2699 static int nvme_dev_map(struct nvme_dev *dev) 2700 { 2701 struct pci_dev *pdev = to_pci_dev(dev->dev); 2702 2703 if (pci_request_mem_regions(pdev, "nvme")) 2704 return -ENODEV; 2705 2706 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2707 goto release; 2708 2709 return 0; 2710 release: 2711 pci_release_mem_regions(pdev); 2712 return -ENODEV; 2713 } 2714 2715 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2716 { 2717 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2718 /* 2719 * Several Samsung devices seem to drop off the PCIe bus 2720 * randomly when APST is on and uses the deepest sleep state. 2721 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2722 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2723 * 950 PRO 256GB", but it seems to be restricted to two Dell 2724 * laptops. 2725 */ 2726 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2727 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2728 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2729 return NVME_QUIRK_NO_DEEPEST_PS; 2730 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2731 /* 2732 * Samsung SSD 960 EVO drops off the PCIe bus after system 2733 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2734 * within few minutes after bootup on a Coffee Lake board - 2735 * ASUS PRIME Z370-A 2736 */ 2737 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2738 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2739 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2740 return NVME_QUIRK_NO_APST; 2741 } 2742 2743 return 0; 2744 } 2745 2746 static void nvme_async_probe(void *data, async_cookie_t cookie) 2747 { 2748 struct nvme_dev *dev = data; 2749 2750 flush_work(&dev->ctrl.reset_work); 2751 flush_work(&dev->ctrl.scan_work); 2752 nvme_put_ctrl(&dev->ctrl); 2753 } 2754 2755 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2756 { 2757 int node, result = -ENOMEM; 2758 struct nvme_dev *dev; 2759 unsigned long quirks = id->driver_data; 2760 size_t alloc_size; 2761 2762 node = dev_to_node(&pdev->dev); 2763 if (node == NUMA_NO_NODE) 2764 set_dev_node(&pdev->dev, first_memory_node); 2765 2766 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2767 if (!dev) 2768 return -ENOMEM; 2769 2770 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 2771 GFP_KERNEL, node); 2772 if (!dev->queues) 2773 goto free; 2774 2775 dev->dev = get_device(&pdev->dev); 2776 pci_set_drvdata(pdev, dev); 2777 2778 result = nvme_dev_map(dev); 2779 if (result) 2780 goto put_pci; 2781 2782 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2783 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2784 mutex_init(&dev->shutdown_lock); 2785 2786 result = nvme_setup_prp_pools(dev); 2787 if (result) 2788 goto unmap; 2789 2790 quirks |= check_vendor_combination_bug(pdev); 2791 2792 /* 2793 * Double check that our mempool alloc size will cover the biggest 2794 * command we support. 2795 */ 2796 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2797 NVME_MAX_SEGS, true); 2798 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2799 2800 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2801 mempool_kfree, 2802 (void *) alloc_size, 2803 GFP_KERNEL, node); 2804 if (!dev->iod_mempool) { 2805 result = -ENOMEM; 2806 goto release_pools; 2807 } 2808 2809 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2810 quirks); 2811 if (result) 2812 goto release_mempool; 2813 2814 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2815 2816 nvme_reset_ctrl(&dev->ctrl); 2817 nvme_get_ctrl(&dev->ctrl); 2818 async_schedule(nvme_async_probe, dev); 2819 2820 return 0; 2821 2822 release_mempool: 2823 mempool_destroy(dev->iod_mempool); 2824 release_pools: 2825 nvme_release_prp_pools(dev); 2826 unmap: 2827 nvme_dev_unmap(dev); 2828 put_pci: 2829 put_device(dev->dev); 2830 free: 2831 kfree(dev->queues); 2832 kfree(dev); 2833 return result; 2834 } 2835 2836 static void nvme_reset_prepare(struct pci_dev *pdev) 2837 { 2838 struct nvme_dev *dev = pci_get_drvdata(pdev); 2839 nvme_dev_disable(dev, false); 2840 } 2841 2842 static void nvme_reset_done(struct pci_dev *pdev) 2843 { 2844 struct nvme_dev *dev = pci_get_drvdata(pdev); 2845 nvme_reset_ctrl_sync(&dev->ctrl); 2846 } 2847 2848 static void nvme_shutdown(struct pci_dev *pdev) 2849 { 2850 struct nvme_dev *dev = pci_get_drvdata(pdev); 2851 nvme_dev_disable(dev, true); 2852 } 2853 2854 /* 2855 * The driver's remove may be called on a device in a partially initialized 2856 * state. This function must not have any dependencies on the device state in 2857 * order to proceed. 2858 */ 2859 static void nvme_remove(struct pci_dev *pdev) 2860 { 2861 struct nvme_dev *dev = pci_get_drvdata(pdev); 2862 2863 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2864 pci_set_drvdata(pdev, NULL); 2865 2866 if (!pci_device_is_present(pdev)) { 2867 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2868 nvme_dev_disable(dev, true); 2869 nvme_dev_remove_admin(dev); 2870 } 2871 2872 flush_work(&dev->ctrl.reset_work); 2873 nvme_stop_ctrl(&dev->ctrl); 2874 nvme_remove_namespaces(&dev->ctrl); 2875 nvme_dev_disable(dev, true); 2876 nvme_release_cmb(dev); 2877 nvme_free_host_mem(dev); 2878 nvme_dev_remove_admin(dev); 2879 nvme_free_queues(dev, 0); 2880 nvme_uninit_ctrl(&dev->ctrl); 2881 nvme_release_prp_pools(dev); 2882 nvme_dev_unmap(dev); 2883 nvme_put_ctrl(&dev->ctrl); 2884 } 2885 2886 #ifdef CONFIG_PM_SLEEP 2887 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2888 { 2889 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2890 } 2891 2892 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2893 { 2894 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2895 } 2896 2897 static int nvme_resume(struct device *dev) 2898 { 2899 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2900 struct nvme_ctrl *ctrl = &ndev->ctrl; 2901 2902 if (ndev->last_ps == U32_MAX || 2903 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2904 nvme_reset_ctrl(ctrl); 2905 return 0; 2906 } 2907 2908 static int nvme_suspend(struct device *dev) 2909 { 2910 struct pci_dev *pdev = to_pci_dev(dev); 2911 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2912 struct nvme_ctrl *ctrl = &ndev->ctrl; 2913 int ret = -EBUSY; 2914 2915 ndev->last_ps = U32_MAX; 2916 2917 /* 2918 * The platform does not remove power for a kernel managed suspend so 2919 * use host managed nvme power settings for lowest idle power if 2920 * possible. This should have quicker resume latency than a full device 2921 * shutdown. But if the firmware is involved after the suspend or the 2922 * device does not support any non-default power states, shut down the 2923 * device fully. 2924 * 2925 * If ASPM is not enabled for the device, shut down the device and allow 2926 * the PCI bus layer to put it into D3 in order to take the PCIe link 2927 * down, so as to allow the platform to achieve its minimum low-power 2928 * state (which may not be possible if the link is up). 2929 */ 2930 if (pm_suspend_via_firmware() || !ctrl->npss || 2931 !pcie_aspm_enabled(pdev) || 2932 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) { 2933 nvme_dev_disable(ndev, true); 2934 return 0; 2935 } 2936 2937 nvme_start_freeze(ctrl); 2938 nvme_wait_freeze(ctrl); 2939 nvme_sync_queues(ctrl); 2940 2941 if (ctrl->state != NVME_CTRL_LIVE && 2942 ctrl->state != NVME_CTRL_ADMIN_ONLY) 2943 goto unfreeze; 2944 2945 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 2946 if (ret < 0) 2947 goto unfreeze; 2948 2949 ret = nvme_set_power_state(ctrl, ctrl->npss); 2950 if (ret < 0) 2951 goto unfreeze; 2952 2953 if (ret) { 2954 /* 2955 * Clearing npss forces a controller reset on resume. The 2956 * correct value will be resdicovered then. 2957 */ 2958 nvme_dev_disable(ndev, true); 2959 ctrl->npss = 0; 2960 ret = 0; 2961 goto unfreeze; 2962 } 2963 /* 2964 * A saved state prevents pci pm from generically controlling the 2965 * device's power. If we're using protocol specific settings, we don't 2966 * want pci interfering. 2967 */ 2968 pci_save_state(pdev); 2969 unfreeze: 2970 nvme_unfreeze(ctrl); 2971 return ret; 2972 } 2973 2974 static int nvme_simple_suspend(struct device *dev) 2975 { 2976 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2977 2978 nvme_dev_disable(ndev, true); 2979 return 0; 2980 } 2981 2982 static int nvme_simple_resume(struct device *dev) 2983 { 2984 struct pci_dev *pdev = to_pci_dev(dev); 2985 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2986 2987 nvme_reset_ctrl(&ndev->ctrl); 2988 return 0; 2989 } 2990 2991 static const struct dev_pm_ops nvme_dev_pm_ops = { 2992 .suspend = nvme_suspend, 2993 .resume = nvme_resume, 2994 .freeze = nvme_simple_suspend, 2995 .thaw = nvme_simple_resume, 2996 .poweroff = nvme_simple_suspend, 2997 .restore = nvme_simple_resume, 2998 }; 2999 #endif /* CONFIG_PM_SLEEP */ 3000 3001 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3002 pci_channel_state_t state) 3003 { 3004 struct nvme_dev *dev = pci_get_drvdata(pdev); 3005 3006 /* 3007 * A frozen channel requires a reset. When detected, this method will 3008 * shutdown the controller to quiesce. The controller will be restarted 3009 * after the slot reset through driver's slot_reset callback. 3010 */ 3011 switch (state) { 3012 case pci_channel_io_normal: 3013 return PCI_ERS_RESULT_CAN_RECOVER; 3014 case pci_channel_io_frozen: 3015 dev_warn(dev->ctrl.device, 3016 "frozen state error detected, reset controller\n"); 3017 nvme_dev_disable(dev, false); 3018 return PCI_ERS_RESULT_NEED_RESET; 3019 case pci_channel_io_perm_failure: 3020 dev_warn(dev->ctrl.device, 3021 "failure state error detected, request disconnect\n"); 3022 return PCI_ERS_RESULT_DISCONNECT; 3023 } 3024 return PCI_ERS_RESULT_NEED_RESET; 3025 } 3026 3027 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3028 { 3029 struct nvme_dev *dev = pci_get_drvdata(pdev); 3030 3031 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3032 pci_restore_state(pdev); 3033 nvme_reset_ctrl(&dev->ctrl); 3034 return PCI_ERS_RESULT_RECOVERED; 3035 } 3036 3037 static void nvme_error_resume(struct pci_dev *pdev) 3038 { 3039 struct nvme_dev *dev = pci_get_drvdata(pdev); 3040 3041 flush_work(&dev->ctrl.reset_work); 3042 } 3043 3044 static const struct pci_error_handlers nvme_err_handler = { 3045 .error_detected = nvme_error_detected, 3046 .slot_reset = nvme_slot_reset, 3047 .resume = nvme_error_resume, 3048 .reset_prepare = nvme_reset_prepare, 3049 .reset_done = nvme_reset_done, 3050 }; 3051 3052 static const struct pci_device_id nvme_id_table[] = { 3053 { PCI_VDEVICE(INTEL, 0x0953), 3054 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3055 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3056 { PCI_VDEVICE(INTEL, 0x0a53), 3057 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3058 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3059 { PCI_VDEVICE(INTEL, 0x0a54), 3060 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3061 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3062 { PCI_VDEVICE(INTEL, 0x0a55), 3063 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3064 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3065 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3066 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3067 NVME_QUIRK_MEDIUM_PRIO_SQ }, 3068 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3069 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3070 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3071 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3072 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3073 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3074 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3075 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3076 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3077 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3078 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3079 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3080 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3081 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3082 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3083 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3084 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3085 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3086 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3087 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3088 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3089 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3090 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3091 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3092 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3093 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3094 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 3095 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3096 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3097 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3098 NVME_QUIRK_128_BYTES_SQES | 3099 NVME_QUIRK_SHARED_TAGS }, 3100 { 0, } 3101 }; 3102 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3103 3104 static struct pci_driver nvme_driver = { 3105 .name = "nvme", 3106 .id_table = nvme_id_table, 3107 .probe = nvme_probe, 3108 .remove = nvme_remove, 3109 .shutdown = nvme_shutdown, 3110 #ifdef CONFIG_PM_SLEEP 3111 .driver = { 3112 .pm = &nvme_dev_pm_ops, 3113 }, 3114 #endif 3115 .sriov_configure = pci_sriov_configure_simple, 3116 .err_handler = &nvme_err_handler, 3117 }; 3118 3119 static int __init nvme_init(void) 3120 { 3121 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3122 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3123 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3124 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3125 return pci_register_driver(&nvme_driver); 3126 } 3127 3128 static void __exit nvme_exit(void) 3129 { 3130 pci_unregister_driver(&nvme_driver); 3131 flush_workqueue(nvme_wq); 3132 } 3133 3134 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3135 MODULE_LICENSE("GPL"); 3136 MODULE_VERSION("1.0"); 3137 module_init(nvme_init); 3138 module_exit(nvme_exit); 3139