1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/module.h> 30 #include <linux/pagemap.h> 31 #include <linux/pci.h> 32 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_debugfs.h> 35 36 #include "amdgpu.h" 37 #include "amdgpu_display.h" 38 #include "amdgpu_xgmi.h" 39 40 void amdgpu_gem_object_free(struct drm_gem_object *gobj) 41 { 42 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 43 44 if (robj) { 45 amdgpu_mn_unregister(robj); 46 amdgpu_bo_unref(&robj); 47 } 48 } 49 50 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 51 int alignment, u32 initial_domain, 52 u64 flags, enum ttm_bo_type type, 53 struct dma_resv *resv, 54 struct drm_gem_object **obj) 55 { 56 struct amdgpu_bo *bo; 57 struct amdgpu_bo_param bp; 58 int r; 59 60 memset(&bp, 0, sizeof(bp)); 61 *obj = NULL; 62 63 bp.size = size; 64 bp.byte_align = alignment; 65 bp.type = type; 66 bp.resv = resv; 67 bp.preferred_domain = initial_domain; 68 retry: 69 bp.flags = flags; 70 bp.domain = initial_domain; 71 r = amdgpu_bo_create(adev, &bp, &bo); 72 if (r) { 73 if (r != -ERESTARTSYS) { 74 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 75 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 76 goto retry; 77 } 78 79 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 80 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 81 goto retry; 82 } 83 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 84 size, initial_domain, alignment, r); 85 } 86 return r; 87 } 88 *obj = &bo->tbo.base; 89 90 return 0; 91 } 92 93 void amdgpu_gem_force_release(struct amdgpu_device *adev) 94 { 95 struct drm_device *ddev = adev->ddev; 96 struct drm_file *file; 97 98 mutex_lock(&ddev->filelist_mutex); 99 100 list_for_each_entry(file, &ddev->filelist, lhead) { 101 struct drm_gem_object *gobj; 102 int handle; 103 104 WARN_ONCE(1, "Still active user space clients!\n"); 105 spin_lock(&file->table_lock); 106 idr_for_each_entry(&file->object_idr, gobj, handle) { 107 WARN_ONCE(1, "And also active allocations!\n"); 108 drm_gem_object_put_unlocked(gobj); 109 } 110 idr_destroy(&file->object_idr); 111 spin_unlock(&file->table_lock); 112 } 113 114 mutex_unlock(&ddev->filelist_mutex); 115 } 116 117 /* 118 * Call from drm_gem_handle_create which appear in both new and open ioctl 119 * case. 120 */ 121 int amdgpu_gem_object_open(struct drm_gem_object *obj, 122 struct drm_file *file_priv) 123 { 124 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 125 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 126 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 127 struct amdgpu_vm *vm = &fpriv->vm; 128 struct amdgpu_bo_va *bo_va; 129 struct mm_struct *mm; 130 int r; 131 132 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 133 if (mm && mm != current->mm) 134 return -EPERM; 135 136 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 137 abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) 138 return -EPERM; 139 140 r = amdgpu_bo_reserve(abo, false); 141 if (r) 142 return r; 143 144 bo_va = amdgpu_vm_bo_find(vm, abo); 145 if (!bo_va) { 146 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 147 } else { 148 ++bo_va->ref_count; 149 } 150 amdgpu_bo_unreserve(abo); 151 return 0; 152 } 153 154 void amdgpu_gem_object_close(struct drm_gem_object *obj, 155 struct drm_file *file_priv) 156 { 157 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 158 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 159 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 160 struct amdgpu_vm *vm = &fpriv->vm; 161 162 struct amdgpu_bo_list_entry vm_pd; 163 struct list_head list, duplicates; 164 struct ttm_validate_buffer tv; 165 struct ww_acquire_ctx ticket; 166 struct amdgpu_bo_va *bo_va; 167 int r; 168 169 INIT_LIST_HEAD(&list); 170 INIT_LIST_HEAD(&duplicates); 171 172 tv.bo = &bo->tbo; 173 tv.num_shared = 1; 174 list_add(&tv.head, &list); 175 176 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 177 178 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 179 if (r) { 180 dev_err(adev->dev, "leaking bo va because " 181 "we fail to reserve bo (%d)\n", r); 182 return; 183 } 184 bo_va = amdgpu_vm_bo_find(vm, bo); 185 if (bo_va && --bo_va->ref_count == 0) { 186 amdgpu_vm_bo_rmv(adev, bo_va); 187 188 if (amdgpu_vm_ready(vm)) { 189 struct dma_fence *fence = NULL; 190 191 r = amdgpu_vm_clear_freed(adev, vm, &fence); 192 if (unlikely(r)) { 193 dev_err(adev->dev, "failed to clear page " 194 "tables on GEM object close (%d)\n", r); 195 } 196 197 if (fence) { 198 amdgpu_bo_fence(bo, fence, true); 199 dma_fence_put(fence); 200 } 201 } 202 } 203 ttm_eu_backoff_reservation(&ticket, &list); 204 } 205 206 /* 207 * GEM ioctls. 208 */ 209 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 210 struct drm_file *filp) 211 { 212 struct amdgpu_device *adev = dev->dev_private; 213 struct amdgpu_fpriv *fpriv = filp->driver_priv; 214 struct amdgpu_vm *vm = &fpriv->vm; 215 union drm_amdgpu_gem_create *args = data; 216 uint64_t flags = args->in.domain_flags; 217 uint64_t size = args->in.bo_size; 218 struct dma_resv *resv = NULL; 219 struct drm_gem_object *gobj; 220 uint32_t handle; 221 int r; 222 223 /* reject invalid gem flags */ 224 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 225 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 226 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 227 AMDGPU_GEM_CREATE_VRAM_CLEARED | 228 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 229 AMDGPU_GEM_CREATE_EXPLICIT_SYNC)) 230 231 return -EINVAL; 232 233 /* reject invalid gem domains */ 234 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 235 return -EINVAL; 236 237 /* create a gem object to contain this object in */ 238 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 239 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 240 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 241 /* if gds bo is created from user space, it must be 242 * passed to bo list 243 */ 244 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 245 return -EINVAL; 246 } 247 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 248 } 249 250 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 251 r = amdgpu_bo_reserve(vm->root.base.bo, false); 252 if (r) 253 return r; 254 255 resv = vm->root.base.bo->tbo.base.resv; 256 } 257 258 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 259 (u32)(0xffffffff & args->in.domains), 260 flags, ttm_bo_type_device, resv, &gobj); 261 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 262 if (!r) { 263 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 264 265 abo->parent = amdgpu_bo_ref(vm->root.base.bo); 266 } 267 amdgpu_bo_unreserve(vm->root.base.bo); 268 } 269 if (r) 270 return r; 271 272 r = drm_gem_handle_create(filp, gobj, &handle); 273 /* drop reference from allocate - handle holds it now */ 274 drm_gem_object_put_unlocked(gobj); 275 if (r) 276 return r; 277 278 memset(args, 0, sizeof(*args)); 279 args->out.handle = handle; 280 return 0; 281 } 282 283 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 284 struct drm_file *filp) 285 { 286 struct ttm_operation_ctx ctx = { true, false }; 287 struct amdgpu_device *adev = dev->dev_private; 288 struct drm_amdgpu_gem_userptr *args = data; 289 struct drm_gem_object *gobj; 290 struct amdgpu_bo *bo; 291 uint32_t handle; 292 int r; 293 294 args->addr = untagged_addr(args->addr); 295 296 if (offset_in_page(args->addr | args->size)) 297 return -EINVAL; 298 299 /* reject unknown flag values */ 300 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 301 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 302 AMDGPU_GEM_USERPTR_REGISTER)) 303 return -EINVAL; 304 305 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 306 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 307 308 /* if we want to write to it we must install a MMU notifier */ 309 return -EACCES; 310 } 311 312 /* create a gem object to contain this object in */ 313 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 314 0, ttm_bo_type_device, NULL, &gobj); 315 if (r) 316 return r; 317 318 bo = gem_to_amdgpu_bo(gobj); 319 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 320 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 321 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); 322 if (r) 323 goto release_object; 324 325 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 326 r = amdgpu_mn_register(bo, args->addr); 327 if (r) 328 goto release_object; 329 } 330 331 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 332 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); 333 if (r) 334 goto release_object; 335 336 r = amdgpu_bo_reserve(bo, true); 337 if (r) 338 goto user_pages_done; 339 340 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 341 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 342 amdgpu_bo_unreserve(bo); 343 if (r) 344 goto user_pages_done; 345 } 346 347 r = drm_gem_handle_create(filp, gobj, &handle); 348 if (r) 349 goto user_pages_done; 350 351 args->handle = handle; 352 353 user_pages_done: 354 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) 355 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm); 356 357 release_object: 358 drm_gem_object_put_unlocked(gobj); 359 360 return r; 361 } 362 363 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 364 struct drm_device *dev, 365 uint32_t handle, uint64_t *offset_p) 366 { 367 struct drm_gem_object *gobj; 368 struct amdgpu_bo *robj; 369 370 gobj = drm_gem_object_lookup(filp, handle); 371 if (gobj == NULL) { 372 return -ENOENT; 373 } 374 robj = gem_to_amdgpu_bo(gobj); 375 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 376 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 377 drm_gem_object_put_unlocked(gobj); 378 return -EPERM; 379 } 380 *offset_p = amdgpu_bo_mmap_offset(robj); 381 drm_gem_object_put_unlocked(gobj); 382 return 0; 383 } 384 385 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 386 struct drm_file *filp) 387 { 388 union drm_amdgpu_gem_mmap *args = data; 389 uint32_t handle = args->in.handle; 390 memset(args, 0, sizeof(*args)); 391 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 392 } 393 394 /** 395 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 396 * 397 * @timeout_ns: timeout in ns 398 * 399 * Calculate the timeout in jiffies from an absolute timeout in ns. 400 */ 401 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 402 { 403 unsigned long timeout_jiffies; 404 ktime_t timeout; 405 406 /* clamp timeout if it's to large */ 407 if (((int64_t)timeout_ns) < 0) 408 return MAX_SCHEDULE_TIMEOUT; 409 410 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 411 if (ktime_to_ns(timeout) < 0) 412 return 0; 413 414 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 415 /* clamp timeout to avoid unsigned-> signed overflow */ 416 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 417 return MAX_SCHEDULE_TIMEOUT - 1; 418 419 return timeout_jiffies; 420 } 421 422 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 423 struct drm_file *filp) 424 { 425 union drm_amdgpu_gem_wait_idle *args = data; 426 struct drm_gem_object *gobj; 427 struct amdgpu_bo *robj; 428 uint32_t handle = args->in.handle; 429 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 430 int r = 0; 431 long ret; 432 433 gobj = drm_gem_object_lookup(filp, handle); 434 if (gobj == NULL) { 435 return -ENOENT; 436 } 437 robj = gem_to_amdgpu_bo(gobj); 438 ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, 439 timeout); 440 441 /* ret == 0 means not signaled, 442 * ret > 0 means signaled 443 * ret < 0 means interrupted before timeout 444 */ 445 if (ret >= 0) { 446 memset(args, 0, sizeof(*args)); 447 args->out.status = (ret == 0); 448 } else 449 r = ret; 450 451 drm_gem_object_put_unlocked(gobj); 452 return r; 453 } 454 455 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 456 struct drm_file *filp) 457 { 458 struct drm_amdgpu_gem_metadata *args = data; 459 struct drm_gem_object *gobj; 460 struct amdgpu_bo *robj; 461 int r = -1; 462 463 DRM_DEBUG("%d \n", args->handle); 464 gobj = drm_gem_object_lookup(filp, args->handle); 465 if (gobj == NULL) 466 return -ENOENT; 467 robj = gem_to_amdgpu_bo(gobj); 468 469 r = amdgpu_bo_reserve(robj, false); 470 if (unlikely(r != 0)) 471 goto out; 472 473 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 474 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 475 r = amdgpu_bo_get_metadata(robj, args->data.data, 476 sizeof(args->data.data), 477 &args->data.data_size_bytes, 478 &args->data.flags); 479 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 480 if (args->data.data_size_bytes > sizeof(args->data.data)) { 481 r = -EINVAL; 482 goto unreserve; 483 } 484 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 485 if (!r) 486 r = amdgpu_bo_set_metadata(robj, args->data.data, 487 args->data.data_size_bytes, 488 args->data.flags); 489 } 490 491 unreserve: 492 amdgpu_bo_unreserve(robj); 493 out: 494 drm_gem_object_put_unlocked(gobj); 495 return r; 496 } 497 498 /** 499 * amdgpu_gem_va_update_vm -update the bo_va in its VM 500 * 501 * @adev: amdgpu_device pointer 502 * @vm: vm to update 503 * @bo_va: bo_va to update 504 * @operation: map, unmap or clear 505 * 506 * Update the bo_va directly after setting its address. Errors are not 507 * vital here, so they are not reported back to userspace. 508 */ 509 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 510 struct amdgpu_vm *vm, 511 struct amdgpu_bo_va *bo_va, 512 uint32_t operation) 513 { 514 int r; 515 516 if (!amdgpu_vm_ready(vm)) 517 return; 518 519 r = amdgpu_vm_clear_freed(adev, vm, NULL); 520 if (r) 521 goto error; 522 523 if (operation == AMDGPU_VA_OP_MAP || 524 operation == AMDGPU_VA_OP_REPLACE) { 525 r = amdgpu_vm_bo_update(adev, bo_va, false); 526 if (r) 527 goto error; 528 } 529 530 r = amdgpu_vm_update_pdes(adev, vm, false); 531 532 error: 533 if (r && r != -ERESTARTSYS) 534 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 535 } 536 537 /** 538 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags 539 * 540 * @adev: amdgpu_device pointer 541 * @flags: GEM UAPI flags 542 * 543 * Returns the GEM UAPI flags mapped into hardware for the ASIC. 544 */ 545 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags) 546 { 547 uint64_t pte_flag = 0; 548 549 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 550 pte_flag |= AMDGPU_PTE_EXECUTABLE; 551 if (flags & AMDGPU_VM_PAGE_READABLE) 552 pte_flag |= AMDGPU_PTE_READABLE; 553 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 554 pte_flag |= AMDGPU_PTE_WRITEABLE; 555 if (flags & AMDGPU_VM_PAGE_PRT) 556 pte_flag |= AMDGPU_PTE_PRT; 557 558 if (adev->gmc.gmc_funcs->map_mtype) 559 pte_flag |= amdgpu_gmc_map_mtype(adev, 560 flags & AMDGPU_VM_MTYPE_MASK); 561 562 return pte_flag; 563 } 564 565 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 566 struct drm_file *filp) 567 { 568 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 569 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 570 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 571 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 572 AMDGPU_VM_PAGE_PRT; 573 574 struct drm_amdgpu_gem_va *args = data; 575 struct drm_gem_object *gobj; 576 struct amdgpu_device *adev = dev->dev_private; 577 struct amdgpu_fpriv *fpriv = filp->driver_priv; 578 struct amdgpu_bo *abo; 579 struct amdgpu_bo_va *bo_va; 580 struct amdgpu_bo_list_entry vm_pd; 581 struct ttm_validate_buffer tv; 582 struct ww_acquire_ctx ticket; 583 struct list_head list, duplicates; 584 uint64_t va_flags; 585 int r = 0; 586 587 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 588 dev_dbg(&dev->pdev->dev, 589 "va_address 0x%LX is in reserved area 0x%LX\n", 590 args->va_address, AMDGPU_VA_RESERVED_SIZE); 591 return -EINVAL; 592 } 593 594 if (args->va_address >= AMDGPU_GMC_HOLE_START && 595 args->va_address < AMDGPU_GMC_HOLE_END) { 596 dev_dbg(&dev->pdev->dev, 597 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 598 args->va_address, AMDGPU_GMC_HOLE_START, 599 AMDGPU_GMC_HOLE_END); 600 return -EINVAL; 601 } 602 603 args->va_address &= AMDGPU_GMC_HOLE_MASK; 604 605 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 606 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", 607 args->flags); 608 return -EINVAL; 609 } 610 611 switch (args->operation) { 612 case AMDGPU_VA_OP_MAP: 613 case AMDGPU_VA_OP_UNMAP: 614 case AMDGPU_VA_OP_CLEAR: 615 case AMDGPU_VA_OP_REPLACE: 616 break; 617 default: 618 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", 619 args->operation); 620 return -EINVAL; 621 } 622 623 INIT_LIST_HEAD(&list); 624 INIT_LIST_HEAD(&duplicates); 625 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 626 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 627 gobj = drm_gem_object_lookup(filp, args->handle); 628 if (gobj == NULL) 629 return -ENOENT; 630 abo = gem_to_amdgpu_bo(gobj); 631 tv.bo = &abo->tbo; 632 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 633 tv.num_shared = 1; 634 else 635 tv.num_shared = 0; 636 list_add(&tv.head, &list); 637 } else { 638 gobj = NULL; 639 abo = NULL; 640 } 641 642 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 643 644 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 645 if (r) 646 goto error_unref; 647 648 if (abo) { 649 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 650 if (!bo_va) { 651 r = -ENOENT; 652 goto error_backoff; 653 } 654 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 655 bo_va = fpriv->prt_va; 656 } else { 657 bo_va = NULL; 658 } 659 660 switch (args->operation) { 661 case AMDGPU_VA_OP_MAP: 662 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 663 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 664 args->offset_in_bo, args->map_size, 665 va_flags); 666 break; 667 case AMDGPU_VA_OP_UNMAP: 668 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 669 break; 670 671 case AMDGPU_VA_OP_CLEAR: 672 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 673 args->va_address, 674 args->map_size); 675 break; 676 case AMDGPU_VA_OP_REPLACE: 677 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 678 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 679 args->offset_in_bo, args->map_size, 680 va_flags); 681 break; 682 default: 683 break; 684 } 685 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 686 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 687 args->operation); 688 689 error_backoff: 690 ttm_eu_backoff_reservation(&ticket, &list); 691 692 error_unref: 693 drm_gem_object_put_unlocked(gobj); 694 return r; 695 } 696 697 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 698 struct drm_file *filp) 699 { 700 struct amdgpu_device *adev = dev->dev_private; 701 struct drm_amdgpu_gem_op *args = data; 702 struct drm_gem_object *gobj; 703 struct amdgpu_vm_bo_base *base; 704 struct amdgpu_bo *robj; 705 int r; 706 707 gobj = drm_gem_object_lookup(filp, args->handle); 708 if (gobj == NULL) { 709 return -ENOENT; 710 } 711 robj = gem_to_amdgpu_bo(gobj); 712 713 r = amdgpu_bo_reserve(robj, false); 714 if (unlikely(r)) 715 goto out; 716 717 switch (args->op) { 718 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 719 struct drm_amdgpu_gem_create_in info; 720 void __user *out = u64_to_user_ptr(args->value); 721 722 info.bo_size = robj->tbo.base.size; 723 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 724 info.domains = robj->preferred_domains; 725 info.domain_flags = robj->flags; 726 amdgpu_bo_unreserve(robj); 727 if (copy_to_user(out, &info, sizeof(info))) 728 r = -EFAULT; 729 break; 730 } 731 case AMDGPU_GEM_OP_SET_PLACEMENT: 732 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { 733 r = -EINVAL; 734 amdgpu_bo_unreserve(robj); 735 break; 736 } 737 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 738 r = -EPERM; 739 amdgpu_bo_unreserve(robj); 740 break; 741 } 742 for (base = robj->vm_bo; base; base = base->next) 743 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), 744 amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) { 745 r = -EINVAL; 746 amdgpu_bo_unreserve(robj); 747 goto out; 748 } 749 750 751 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 752 AMDGPU_GEM_DOMAIN_GTT | 753 AMDGPU_GEM_DOMAIN_CPU); 754 robj->allowed_domains = robj->preferred_domains; 755 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 756 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 757 758 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 759 amdgpu_vm_bo_invalidate(adev, robj, true); 760 761 amdgpu_bo_unreserve(robj); 762 break; 763 default: 764 amdgpu_bo_unreserve(robj); 765 r = -EINVAL; 766 } 767 768 out: 769 drm_gem_object_put_unlocked(gobj); 770 return r; 771 } 772 773 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 774 struct drm_device *dev, 775 struct drm_mode_create_dumb *args) 776 { 777 struct amdgpu_device *adev = dev->dev_private; 778 struct drm_gem_object *gobj; 779 uint32_t handle; 780 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 781 AMDGPU_GEM_CREATE_CPU_GTT_USWC; 782 u32 domain; 783 int r; 784 785 /* 786 * The buffer returned from this function should be cleared, but 787 * it can only be done if the ring is enabled or we'll fail to 788 * create the buffer. 789 */ 790 if (adev->mman.buffer_funcs_enabled) 791 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 792 793 args->pitch = amdgpu_align_pitch(adev, args->width, 794 DIV_ROUND_UP(args->bpp, 8), 0); 795 args->size = (u64)args->pitch * args->height; 796 args->size = ALIGN(args->size, PAGE_SIZE); 797 domain = amdgpu_bo_get_preferred_pin_domain(adev, 798 amdgpu_display_supported_domains(adev, flags)); 799 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, 800 ttm_bo_type_device, NULL, &gobj); 801 if (r) 802 return -ENOMEM; 803 804 r = drm_gem_handle_create(file_priv, gobj, &handle); 805 /* drop reference from allocate - handle holds it now */ 806 drm_gem_object_put_unlocked(gobj); 807 if (r) { 808 return r; 809 } 810 args->handle = handle; 811 return 0; 812 } 813 814 #if defined(CONFIG_DEBUG_FS) 815 816 #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \ 817 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 818 seq_printf((m), " " #flag); \ 819 } 820 821 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) 822 { 823 struct drm_gem_object *gobj = ptr; 824 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 825 struct seq_file *m = data; 826 827 struct dma_buf_attachment *attachment; 828 struct dma_buf *dma_buf; 829 unsigned domain; 830 const char *placement; 831 unsigned pin_count; 832 833 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 834 switch (domain) { 835 case AMDGPU_GEM_DOMAIN_VRAM: 836 placement = "VRAM"; 837 break; 838 case AMDGPU_GEM_DOMAIN_GTT: 839 placement = " GTT"; 840 break; 841 case AMDGPU_GEM_DOMAIN_CPU: 842 default: 843 placement = " CPU"; 844 break; 845 } 846 seq_printf(m, "\t0x%08x: %12ld byte %s", 847 id, amdgpu_bo_size(bo), placement); 848 849 pin_count = READ_ONCE(bo->pin_count); 850 if (pin_count) 851 seq_printf(m, " pin count %d", pin_count); 852 853 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 854 attachment = READ_ONCE(bo->tbo.base.import_attach); 855 856 if (attachment) 857 seq_printf(m, " imported from %p", dma_buf); 858 else if (dma_buf) 859 seq_printf(m, " exported as %p", dma_buf); 860 861 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 862 amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS); 863 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC); 864 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED); 865 amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW); 866 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 867 amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID); 868 amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC); 869 870 seq_printf(m, "\n"); 871 872 return 0; 873 } 874 875 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 876 { 877 struct drm_info_node *node = (struct drm_info_node *)m->private; 878 struct drm_device *dev = node->minor->dev; 879 struct drm_file *file; 880 int r; 881 882 r = mutex_lock_interruptible(&dev->filelist_mutex); 883 if (r) 884 return r; 885 886 list_for_each_entry(file, &dev->filelist, lhead) { 887 struct task_struct *task; 888 889 /* 890 * Although we have a valid reference on file->pid, that does 891 * not guarantee that the task_struct who called get_pid() is 892 * still alive (e.g. get_pid(current) => fork() => exit()). 893 * Therefore, we need to protect this ->comm access using RCU. 894 */ 895 rcu_read_lock(); 896 task = pid_task(file->pid, PIDTYPE_PID); 897 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 898 task ? task->comm : "<unknown>"); 899 rcu_read_unlock(); 900 901 spin_lock(&file->table_lock); 902 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); 903 spin_unlock(&file->table_lock); 904 } 905 906 mutex_unlock(&dev->filelist_mutex); 907 return 0; 908 } 909 910 static const struct drm_info_list amdgpu_debugfs_gem_list[] = { 911 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 912 }; 913 #endif 914 915 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 916 { 917 #if defined(CONFIG_DEBUG_FS) 918 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); 919 #endif 920 return 0; 921 } 922