1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
8
9maintainers:
10  - Wen He <wen.he_1@nxp.com>
11
12description: |
13  NXP LS1028A has a clock domain PXLCLK0 used for the Display output
14  interface in the display core, as implemented in TSMC CLN28HPM PLL.
15  which generate and offers pixel clocks to Display.
16
17properties:
18  compatible:
19    const: fsl,ls1028a-plldig
20
21  reg:
22    maxItems: 1
23
24  '#clock-cells':
25    const: 0
26
27  fsl,vco-hz:
28     description: Optional for VCO frequency of the PLL in Hertz.
29        The VCO frequency of this PLL cannot be changed during runtime
30        only at startup. Therefore, the output frequencies are very
31        limited and might not even closely match the requested frequency.
32        To work around this restriction the user may specify its own
33        desired VCO frequency for the PLL.
34     minimum: 650000000
35     maximum: 1300000000
36     default: 1188000000
37
38required:
39  - compatible
40  - reg
41  - clocks
42  - '#clock-cells'
43
44examples:
45  # Display PIXEL Clock node:
46  - |
47    dpclk: clock-display@f1f0000 {
48        compatible = "fsl,ls1028a-plldig";
49        reg = <0x0 0xf1f0000 0x0 0xffff>;
50        #clock-cells = <0>;
51        clocks = <&osc_27m>;
52    };
53
54...
55