1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ARM Ltd. 4 * 5 * ARMv8 Foundation model DTS 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/memreserve/ 0x80000000 0x00010000; 13 14/ { 15 model = "Foundation-v8A"; 16 compatible = "arm,foundation-aarch64", "arm,vexpress"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 aliases { 24 serial0 = &v2m_serial0; 25 serial1 = &v2m_serial1; 26 serial2 = &v2m_serial2; 27 serial3 = &v2m_serial3; 28 }; 29 30 cpus { 31 #address-cells = <2>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,armv8"; 37 reg = <0x0 0x0>; 38 next-level-cache = <&L2_0>; 39 }; 40 cpu1: cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,armv8"; 43 reg = <0x0 0x1>; 44 next-level-cache = <&L2_0>; 45 }; 46 cpu2: cpu@2 { 47 device_type = "cpu"; 48 compatible = "arm,armv8"; 49 reg = <0x0 0x2>; 50 next-level-cache = <&L2_0>; 51 }; 52 cpu3: cpu@3 { 53 device_type = "cpu"; 54 compatible = "arm,armv8"; 55 reg = <0x0 0x3>; 56 next-level-cache = <&L2_0>; 57 }; 58 59 L2_0: l2-cache0 { 60 compatible = "cache"; 61 }; 62 }; 63 64 memory@80000000 { 65 device_type = "memory"; 66 reg = <0x00000000 0x80000000 0 0x80000000>, 67 <0x00000008 0x80000000 0 0x80000000>; 68 }; 69 70 timer { 71 compatible = "arm,armv8-timer"; 72 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 73 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 74 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 75 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 76 clock-frequency = <100000000>; 77 }; 78 79 pmu { 80 compatible = "arm,armv8-pmuv3"; 81 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 85 }; 86 87 watchdog@2a440000 { 88 compatible = "arm,sbsa-gwdt"; 89 reg = <0x0 0x2a440000 0 0x1000>, 90 <0x0 0x2a450000 0 0x1000>; 91 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 92 timeout-sec = <30>; 93 }; 94 95 bus@8000000 { 96 compatible = "arm,vexpress,v2m-p1", "simple-bus"; 97 arm,v2m-memory-map = "rs1"; 98 #address-cells = <2>; /* SMB chipselect number and offset */ 99 #size-cells = <1>; 100 101 ranges = <0 0 0 0x08000000 0x04000000>, 102 <1 0 0 0x14000000 0x04000000>, 103 <2 0 0 0x18000000 0x04000000>, 104 <3 0 0 0x1c000000 0x04000000>, 105 <4 0 0 0x0c000000 0x04000000>, 106 <5 0 0 0x10000000 0x04000000>; 107 108 #interrupt-cells = <1>; 109 interrupt-map-mask = <0 0 63>; 110 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 111 <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 112 <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 113 <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 114 <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 115 <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 116 <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 117 <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 118 <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 119 <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 120 <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 121 <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 122 <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 123 <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 124 <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 125 <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 126 <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 127 <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 128 <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 129 <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 130 <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 131 <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 132 <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 133 <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 134 <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 135 <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 136 <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 137 <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 138 <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 139 <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 140 <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 141 <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 142 <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 143 <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 144 <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 145 <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 146 <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 147 <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 148 <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 149 <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 150 <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 151 <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 152 <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 153 154 ethernet@2,02000000 { 155 compatible = "smsc,lan91c111"; 156 reg = <2 0x02000000 0x10000>; 157 interrupts = <15>; 158 }; 159 160 v2m_clk24mhz: clk24mhz { 161 compatible = "fixed-clock"; 162 #clock-cells = <0>; 163 clock-frequency = <24000000>; 164 clock-output-names = "v2m:clk24mhz"; 165 }; 166 167 v2m_refclk1mhz: refclk1mhz { 168 compatible = "fixed-clock"; 169 #clock-cells = <0>; 170 clock-frequency = <1000000>; 171 clock-output-names = "v2m:refclk1mhz"; 172 }; 173 174 v2m_refclk32khz: refclk32khz { 175 compatible = "fixed-clock"; 176 #clock-cells = <0>; 177 clock-frequency = <32768>; 178 clock-output-names = "v2m:refclk32khz"; 179 }; 180 181 iofpga@3,00000000 { 182 compatible = "simple-bus"; 183 #address-cells = <1>; 184 #size-cells = <1>; 185 ranges = <0 3 0 0x200000>; 186 187 v2m_sysreg: sysreg@10000 { 188 compatible = "arm,vexpress-sysreg"; 189 reg = <0x010000 0x1000>; 190 }; 191 192 v2m_serial0: uart@90000 { 193 compatible = "arm,pl011", "arm,primecell"; 194 reg = <0x090000 0x1000>; 195 interrupts = <5>; 196 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 197 clock-names = "uartclk", "apb_pclk"; 198 }; 199 200 v2m_serial1: uart@a0000 { 201 compatible = "arm,pl011", "arm,primecell"; 202 reg = <0x0a0000 0x1000>; 203 interrupts = <6>; 204 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 205 clock-names = "uartclk", "apb_pclk"; 206 }; 207 208 v2m_serial2: uart@b0000 { 209 compatible = "arm,pl011", "arm,primecell"; 210 reg = <0x0b0000 0x1000>; 211 interrupts = <7>; 212 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 213 clock-names = "uartclk", "apb_pclk"; 214 }; 215 216 v2m_serial3: uart@c0000 { 217 compatible = "arm,pl011", "arm,primecell"; 218 reg = <0x0c0000 0x1000>; 219 interrupts = <8>; 220 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 221 clock-names = "uartclk", "apb_pclk"; 222 }; 223 224 virtio-block@130000 { 225 compatible = "virtio,mmio"; 226 reg = <0x130000 0x200>; 227 interrupts = <42>; 228 }; 229 }; 230 }; 231}; 232