1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * I2C bus driver for the Cadence I2C controller. 4 * 5 * Copyright (C) 2009 - 2014 Xilinx, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/of.h> 16 #include <linux/pm_runtime.h> 17 18 /* Register offsets for the I2C device. */ 19 #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */ 20 #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */ 21 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */ 22 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */ 23 #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */ 24 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */ 25 #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */ 26 #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */ 27 #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */ 28 29 /* Control Register Bit mask definitions */ 30 #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */ 31 #define CDNS_I2C_CR_ACK_EN BIT(3) 32 #define CDNS_I2C_CR_NEA BIT(2) 33 #define CDNS_I2C_CR_MS BIT(1) 34 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */ 35 #define CDNS_I2C_CR_RW BIT(0) 36 /* 1 = Auto init FIFO to zeroes */ 37 #define CDNS_I2C_CR_CLR_FIFO BIT(6) 38 #define CDNS_I2C_CR_DIVA_SHIFT 14 39 #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT) 40 #define CDNS_I2C_CR_DIVB_SHIFT 8 41 #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT) 42 43 /* Status Register Bit mask definitions */ 44 #define CDNS_I2C_SR_BA BIT(8) 45 #define CDNS_I2C_SR_RXDV BIT(5) 46 47 /* 48 * I2C Address Register Bit mask definitions 49 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0] 50 * bits. A write access to this register always initiates a transfer if the I2C 51 * is in master mode. 52 */ 53 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */ 54 55 /* 56 * I2C Interrupt Registers Bit mask definitions 57 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same 58 * bit definitions. 59 */ 60 #define CDNS_I2C_IXR_ARB_LOST BIT(9) 61 #define CDNS_I2C_IXR_RX_UNF BIT(7) 62 #define CDNS_I2C_IXR_TX_OVF BIT(6) 63 #define CDNS_I2C_IXR_RX_OVF BIT(5) 64 #define CDNS_I2C_IXR_SLV_RDY BIT(4) 65 #define CDNS_I2C_IXR_TO BIT(3) 66 #define CDNS_I2C_IXR_NACK BIT(2) 67 #define CDNS_I2C_IXR_DATA BIT(1) 68 #define CDNS_I2C_IXR_COMP BIT(0) 69 70 #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 71 CDNS_I2C_IXR_RX_UNF | \ 72 CDNS_I2C_IXR_TX_OVF | \ 73 CDNS_I2C_IXR_RX_OVF | \ 74 CDNS_I2C_IXR_SLV_RDY | \ 75 CDNS_I2C_IXR_TO | \ 76 CDNS_I2C_IXR_NACK | \ 77 CDNS_I2C_IXR_DATA | \ 78 CDNS_I2C_IXR_COMP) 79 80 #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 81 CDNS_I2C_IXR_RX_UNF | \ 82 CDNS_I2C_IXR_TX_OVF | \ 83 CDNS_I2C_IXR_RX_OVF | \ 84 CDNS_I2C_IXR_NACK) 85 86 #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 87 CDNS_I2C_IXR_RX_UNF | \ 88 CDNS_I2C_IXR_TX_OVF | \ 89 CDNS_I2C_IXR_RX_OVF | \ 90 CDNS_I2C_IXR_NACK | \ 91 CDNS_I2C_IXR_DATA | \ 92 CDNS_I2C_IXR_COMP) 93 94 #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000) 95 /* timeout for pm runtime autosuspend */ 96 #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */ 97 98 #define CDNS_I2C_FIFO_DEPTH 16 99 /* FIFO depth at which the DATA interrupt occurs */ 100 #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2) 101 #define CDNS_I2C_MAX_TRANSFER_SIZE 255 102 /* Transfer size in multiples of data interrupt depth */ 103 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3) 104 105 #define DRIVER_NAME "cdns-i2c" 106 107 #define CDNS_I2C_SPEED_MAX 400000 108 #define CDNS_I2C_SPEED_DEFAULT 100000 109 110 #define CDNS_I2C_DIVA_MAX 4 111 #define CDNS_I2C_DIVB_MAX 64 112 113 #define CDNS_I2C_TIMEOUT_MAX 0xFF 114 115 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0) 116 117 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset) 118 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset) 119 120 /** 121 * struct cdns_i2c - I2C device private data structure 122 * 123 * @dev: Pointer to device structure 124 * @membase: Base address of the I2C device 125 * @adap: I2C adapter instance 126 * @p_msg: Message pointer 127 * @err_status: Error status in Interrupt Status Register 128 * @xfer_done: Transfer complete status 129 * @p_send_buf: Pointer to transmit buffer 130 * @p_recv_buf: Pointer to receive buffer 131 * @send_count: Number of bytes still expected to send 132 * @recv_count: Number of bytes still expected to receive 133 * @curr_recv_count: Number of bytes to be received in current transfer 134 * @irq: IRQ number 135 * @input_clk: Input clock to I2C controller 136 * @i2c_clk: Maximum I2C clock speed 137 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit 138 * @clk: Pointer to struct clk 139 * @clk_rate_change_nb: Notifier block for clock rate changes 140 * @quirks: flag for broken hold bit usage in r1p10 141 */ 142 struct cdns_i2c { 143 struct device *dev; 144 void __iomem *membase; 145 struct i2c_adapter adap; 146 struct i2c_msg *p_msg; 147 int err_status; 148 struct completion xfer_done; 149 unsigned char *p_send_buf; 150 unsigned char *p_recv_buf; 151 unsigned int send_count; 152 unsigned int recv_count; 153 unsigned int curr_recv_count; 154 int irq; 155 unsigned long input_clk; 156 unsigned int i2c_clk; 157 unsigned int bus_hold_flag; 158 struct clk *clk; 159 struct notifier_block clk_rate_change_nb; 160 u32 quirks; 161 }; 162 163 struct cdns_platform_data { 164 u32 quirks; 165 }; 166 167 #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \ 168 clk_rate_change_nb) 169 170 /** 171 * cdns_i2c_clear_bus_hold - Clear bus hold bit 172 * @id: Pointer to driver data struct 173 * 174 * Helper to clear the controller's bus hold bit. 175 */ 176 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) 177 { 178 u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 179 if (reg & CDNS_I2C_CR_HOLD) 180 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET); 181 } 182 183 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) 184 { 185 return (hold_wrkaround && 186 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)); 187 } 188 189 /** 190 * cdns_i2c_isr - Interrupt handler for the I2C device 191 * @irq: irq number for the I2C device 192 * @ptr: void pointer to cdns_i2c structure 193 * 194 * This function handles the data interrupt, transfer complete interrupt and 195 * the error interrupts of the I2C device. 196 * 197 * Return: IRQ_HANDLED always 198 */ 199 static irqreturn_t cdns_i2c_isr(int irq, void *ptr) 200 { 201 unsigned int isr_status, avail_bytes, updatetx; 202 unsigned int bytes_to_send; 203 bool hold_quirk; 204 struct cdns_i2c *id = ptr; 205 /* Signal completion only after everything is updated */ 206 int done_flag = 0; 207 irqreturn_t status = IRQ_NONE; 208 209 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 210 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 211 id->err_status = 0; 212 213 /* Handling nack and arbitration lost interrupt */ 214 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) { 215 done_flag = 1; 216 status = IRQ_HANDLED; 217 } 218 219 /* 220 * Check if transfer size register needs to be updated again for a 221 * large data receive operation. 222 */ 223 updatetx = 0; 224 if (id->recv_count > id->curr_recv_count) 225 updatetx = 1; 226 227 hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx; 228 229 /* When receiving, handle data interrupt and completion interrupt */ 230 if (id->p_recv_buf && 231 ((isr_status & CDNS_I2C_IXR_COMP) || 232 (isr_status & CDNS_I2C_IXR_DATA))) { 233 /* Read data if receive data valid is set */ 234 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & 235 CDNS_I2C_SR_RXDV) { 236 /* 237 * Clear hold bit that was set for FIFO control if 238 * RX data left is less than FIFO depth, unless 239 * repeated start is selected. 240 */ 241 if ((id->recv_count < CDNS_I2C_FIFO_DEPTH) && 242 !id->bus_hold_flag) 243 cdns_i2c_clear_bus_hold(id); 244 245 if (id->recv_count > 0) { 246 *(id->p_recv_buf)++ = 247 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 248 id->recv_count--; 249 id->curr_recv_count--; 250 } else { 251 dev_err(id->adap.dev.parent, 252 "xfer_size reg rollover. xfer aborted!\n"); 253 id->err_status |= CDNS_I2C_IXR_TO; 254 break; 255 } 256 257 if (cdns_is_holdquirk(id, hold_quirk)) 258 break; 259 } 260 261 /* 262 * The controller sends NACK to the slave when transfer size 263 * register reaches zero without considering the HOLD bit. 264 * This workaround is implemented for large data transfers to 265 * maintain transfer size non-zero while performing a large 266 * receive operation. 267 */ 268 if (cdns_is_holdquirk(id, hold_quirk)) { 269 /* wait while fifo is full */ 270 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) != 271 (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH)) 272 ; 273 274 /* 275 * Check number of bytes to be received against maximum 276 * transfer size and update register accordingly. 277 */ 278 if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) > 279 CDNS_I2C_TRANSFER_SIZE) { 280 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 281 CDNS_I2C_XFER_SIZE_OFFSET); 282 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE + 283 CDNS_I2C_FIFO_DEPTH; 284 } else { 285 cdns_i2c_writereg(id->recv_count - 286 CDNS_I2C_FIFO_DEPTH, 287 CDNS_I2C_XFER_SIZE_OFFSET); 288 id->curr_recv_count = id->recv_count; 289 } 290 } else if (id->recv_count && !hold_quirk && 291 !id->curr_recv_count) { 292 293 /* Set the slave address in address register*/ 294 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, 295 CDNS_I2C_ADDR_OFFSET); 296 297 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) { 298 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 299 CDNS_I2C_XFER_SIZE_OFFSET); 300 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE; 301 } else { 302 cdns_i2c_writereg(id->recv_count, 303 CDNS_I2C_XFER_SIZE_OFFSET); 304 id->curr_recv_count = id->recv_count; 305 } 306 } 307 308 /* Clear hold (if not repeated start) and signal completion */ 309 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) { 310 if (!id->bus_hold_flag) 311 cdns_i2c_clear_bus_hold(id); 312 done_flag = 1; 313 } 314 315 status = IRQ_HANDLED; 316 } 317 318 /* When sending, handle transfer complete interrupt */ 319 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) { 320 /* 321 * If there is more data to be sent, calculate the 322 * space available in FIFO and fill with that many bytes. 323 */ 324 if (id->send_count) { 325 avail_bytes = CDNS_I2C_FIFO_DEPTH - 326 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 327 if (id->send_count > avail_bytes) 328 bytes_to_send = avail_bytes; 329 else 330 bytes_to_send = id->send_count; 331 332 while (bytes_to_send--) { 333 cdns_i2c_writereg( 334 (*(id->p_send_buf)++), 335 CDNS_I2C_DATA_OFFSET); 336 id->send_count--; 337 } 338 } else { 339 /* 340 * Signal the completion of transaction and 341 * clear the hold bus bit if there are no 342 * further messages to be processed. 343 */ 344 done_flag = 1; 345 } 346 if (!id->send_count && !id->bus_hold_flag) 347 cdns_i2c_clear_bus_hold(id); 348 349 status = IRQ_HANDLED; 350 } 351 352 /* Update the status for errors */ 353 id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK; 354 if (id->err_status) 355 status = IRQ_HANDLED; 356 357 if (done_flag) 358 complete(&id->xfer_done); 359 360 return status; 361 } 362 363 /** 364 * cdns_i2c_mrecv - Prepare and start a master receive operation 365 * @id: pointer to the i2c device structure 366 */ 367 static void cdns_i2c_mrecv(struct cdns_i2c *id) 368 { 369 unsigned int ctrl_reg; 370 unsigned int isr_status; 371 372 id->p_recv_buf = id->p_msg->buf; 373 id->recv_count = id->p_msg->len; 374 375 /* Put the controller in master receive mode and clear the FIFO */ 376 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 377 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO; 378 379 if (id->p_msg->flags & I2C_M_RECV_LEN) 380 id->recv_count = I2C_SMBUS_BLOCK_MAX + 1; 381 382 id->curr_recv_count = id->recv_count; 383 384 /* 385 * Check for the message size against FIFO depth and set the 386 * 'hold bus' bit if it is greater than FIFO depth. 387 */ 388 if ((id->recv_count > CDNS_I2C_FIFO_DEPTH) || id->bus_hold_flag) 389 ctrl_reg |= CDNS_I2C_CR_HOLD; 390 else 391 ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD; 392 393 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 394 395 /* Clear the interrupts in interrupt status register */ 396 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 397 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 398 399 /* 400 * The no. of bytes to receive is checked against the limit of 401 * max transfer size. Set transfer size register with no of bytes 402 * receive if it is less than transfer size and transfer size if 403 * it is more. Enable the interrupts. 404 */ 405 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) { 406 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 407 CDNS_I2C_XFER_SIZE_OFFSET); 408 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE; 409 } else { 410 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET); 411 } 412 413 /* Set the slave address in address register - triggers operation */ 414 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, 415 CDNS_I2C_ADDR_OFFSET); 416 /* Clear the bus hold flag if bytes to receive is less than FIFO size */ 417 if (!id->bus_hold_flag && 418 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) && 419 (id->recv_count <= CDNS_I2C_FIFO_DEPTH)) 420 cdns_i2c_clear_bus_hold(id); 421 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); 422 } 423 424 /** 425 * cdns_i2c_msend - Prepare and start a master send operation 426 * @id: pointer to the i2c device 427 */ 428 static void cdns_i2c_msend(struct cdns_i2c *id) 429 { 430 unsigned int avail_bytes; 431 unsigned int bytes_to_send; 432 unsigned int ctrl_reg; 433 unsigned int isr_status; 434 435 id->p_recv_buf = NULL; 436 id->p_send_buf = id->p_msg->buf; 437 id->send_count = id->p_msg->len; 438 439 /* Set the controller in Master transmit mode and clear the FIFO. */ 440 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 441 ctrl_reg &= ~CDNS_I2C_CR_RW; 442 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO; 443 444 /* 445 * Check for the message size against FIFO depth and set the 446 * 'hold bus' bit if it is greater than FIFO depth. 447 */ 448 if ((id->send_count > CDNS_I2C_FIFO_DEPTH) || id->bus_hold_flag) 449 ctrl_reg |= CDNS_I2C_CR_HOLD; 450 else 451 ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD; 452 453 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 454 455 /* Clear the interrupts in interrupt status register. */ 456 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 457 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 458 459 /* 460 * Calculate the space available in FIFO. Check the message length 461 * against the space available, and fill the FIFO accordingly. 462 * Enable the interrupts. 463 */ 464 avail_bytes = CDNS_I2C_FIFO_DEPTH - 465 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 466 467 if (id->send_count > avail_bytes) 468 bytes_to_send = avail_bytes; 469 else 470 bytes_to_send = id->send_count; 471 472 while (bytes_to_send--) { 473 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET); 474 id->send_count--; 475 } 476 477 /* 478 * Clear the bus hold flag if there is no more data 479 * and if it is the last message. 480 */ 481 if (!id->bus_hold_flag && !id->send_count) 482 cdns_i2c_clear_bus_hold(id); 483 /* Set the slave address in address register - triggers operation. */ 484 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, 485 CDNS_I2C_ADDR_OFFSET); 486 487 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); 488 } 489 490 /** 491 * cdns_i2c_master_reset - Reset the interface 492 * @adap: pointer to the i2c adapter driver instance 493 * 494 * This function cleanup the fifos, clear the hold bit and status 495 * and disable the interrupts. 496 */ 497 static void cdns_i2c_master_reset(struct i2c_adapter *adap) 498 { 499 struct cdns_i2c *id = adap->algo_data; 500 u32 regval; 501 502 /* Disable the interrupts */ 503 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET); 504 /* Clear the hold bit and fifos */ 505 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 506 regval &= ~CDNS_I2C_CR_HOLD; 507 regval |= CDNS_I2C_CR_CLR_FIFO; 508 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET); 509 /* Update the transfercount register to zero */ 510 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET); 511 /* Clear the interrupt status register */ 512 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 513 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET); 514 /* Clear the status register */ 515 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); 516 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET); 517 } 518 519 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg, 520 struct i2c_adapter *adap) 521 { 522 unsigned long time_left; 523 u32 reg; 524 525 id->p_msg = msg; 526 id->err_status = 0; 527 reinit_completion(&id->xfer_done); 528 529 /* Check for the TEN Bit mode on each msg */ 530 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 531 if (msg->flags & I2C_M_TEN) { 532 if (reg & CDNS_I2C_CR_NEA) 533 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA, 534 CDNS_I2C_CR_OFFSET); 535 } else { 536 if (!(reg & CDNS_I2C_CR_NEA)) 537 cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA, 538 CDNS_I2C_CR_OFFSET); 539 } 540 541 /* Check for the R/W flag on each msg */ 542 if (msg->flags & I2C_M_RD) 543 cdns_i2c_mrecv(id); 544 else 545 cdns_i2c_msend(id); 546 547 /* Wait for the signal of completion */ 548 time_left = wait_for_completion_timeout(&id->xfer_done, adap->timeout); 549 if (time_left == 0) { 550 cdns_i2c_master_reset(adap); 551 dev_err(id->adap.dev.parent, 552 "timeout waiting on completion\n"); 553 return -ETIMEDOUT; 554 } 555 556 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, 557 CDNS_I2C_IDR_OFFSET); 558 559 /* If it is bus arbitration error, try again */ 560 if (id->err_status & CDNS_I2C_IXR_ARB_LOST) 561 return -EAGAIN; 562 563 return 0; 564 } 565 566 /** 567 * cdns_i2c_master_xfer - The main i2c transfer function 568 * @adap: pointer to the i2c adapter driver instance 569 * @msgs: pointer to the i2c message structure 570 * @num: the number of messages to transfer 571 * 572 * Initiates the send/recv activity based on the transfer message received. 573 * 574 * Return: number of msgs processed on success, negative error otherwise 575 */ 576 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 577 int num) 578 { 579 int ret, count; 580 u32 reg; 581 struct cdns_i2c *id = adap->algo_data; 582 bool hold_quirk; 583 584 ret = pm_runtime_get_sync(id->dev); 585 if (ret < 0) 586 return ret; 587 /* Check if the bus is free */ 588 if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) { 589 ret = -EAGAIN; 590 goto out; 591 } 592 593 hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT); 594 /* 595 * Set the flag to one when multiple messages are to be 596 * processed with a repeated start. 597 */ 598 if (num > 1) { 599 /* 600 * This controller does not give completion interrupt after a 601 * master receive message if HOLD bit is set (repeated start), 602 * resulting in SW timeout. Hence, if a receive message is 603 * followed by any other message, an error is returned 604 * indicating that this sequence is not supported. 605 */ 606 for (count = 0; (count < num - 1 && hold_quirk); count++) { 607 if (msgs[count].flags & I2C_M_RD) { 608 dev_warn(adap->dev.parent, 609 "Can't do repeated start after a receive message\n"); 610 ret = -EOPNOTSUPP; 611 goto out; 612 } 613 } 614 id->bus_hold_flag = 1; 615 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 616 reg |= CDNS_I2C_CR_HOLD; 617 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET); 618 } else { 619 id->bus_hold_flag = 0; 620 } 621 622 /* Process the msg one by one */ 623 for (count = 0; count < num; count++, msgs++) { 624 if (count == (num - 1)) 625 id->bus_hold_flag = 0; 626 627 ret = cdns_i2c_process_msg(id, msgs, adap); 628 if (ret) 629 goto out; 630 631 /* Report the other error interrupts to application */ 632 if (id->err_status) { 633 cdns_i2c_master_reset(adap); 634 635 if (id->err_status & CDNS_I2C_IXR_NACK) { 636 ret = -ENXIO; 637 goto out; 638 } 639 ret = -EIO; 640 goto out; 641 } 642 } 643 644 ret = num; 645 out: 646 pm_runtime_mark_last_busy(id->dev); 647 pm_runtime_put_autosuspend(id->dev); 648 return ret; 649 } 650 651 /** 652 * cdns_i2c_func - Returns the supported features of the I2C driver 653 * @adap: pointer to the i2c adapter structure 654 * 655 * Return: 32 bit value, each bit corresponding to a feature 656 */ 657 static u32 cdns_i2c_func(struct i2c_adapter *adap) 658 { 659 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | 660 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 661 I2C_FUNC_SMBUS_BLOCK_DATA; 662 } 663 664 static const struct i2c_algorithm cdns_i2c_algo = { 665 .master_xfer = cdns_i2c_master_xfer, 666 .functionality = cdns_i2c_func, 667 }; 668 669 /** 670 * cdns_i2c_calc_divs - Calculate clock dividers 671 * @f: I2C clock frequency 672 * @input_clk: Input clock frequency 673 * @a: First divider (return value) 674 * @b: Second divider (return value) 675 * 676 * f is used as input and output variable. As input it is used as target I2C 677 * frequency. On function exit f holds the actually resulting I2C frequency. 678 * 679 * Return: 0 on success, negative errno otherwise. 680 */ 681 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, 682 unsigned int *a, unsigned int *b) 683 { 684 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp; 685 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0; 686 unsigned int last_error, current_error; 687 688 /* calculate (divisor_a+1) x (divisor_b+1) */ 689 temp = input_clk / (22 * fscl); 690 691 /* 692 * If the calculated value is negative or 0, the fscl input is out of 693 * range. Return error. 694 */ 695 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX))) 696 return -EINVAL; 697 698 last_error = -1; 699 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) { 700 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); 701 702 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX)) 703 continue; 704 div_b--; 705 706 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); 707 708 if (actual_fscl > fscl) 709 continue; 710 711 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) : 712 (fscl - actual_fscl)); 713 714 if (last_error > current_error) { 715 calc_div_a = div_a; 716 calc_div_b = div_b; 717 best_fscl = actual_fscl; 718 last_error = current_error; 719 } 720 } 721 722 *a = calc_div_a; 723 *b = calc_div_b; 724 *f = best_fscl; 725 726 return 0; 727 } 728 729 /** 730 * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device 731 * @clk_in: I2C clock input frequency in Hz 732 * @id: Pointer to the I2C device structure 733 * 734 * The device must be idle rather than busy transferring data before setting 735 * these device options. 736 * The data rate is set by values in the control register. 737 * The formula for determining the correct register values is 738 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) 739 * See the hardware data sheet for a full explanation of setting the serial 740 * clock rate. The clock can not be faster than the input clock divide by 22. 741 * The two most common clock rates are 100KHz and 400KHz. 742 * 743 * Return: 0 on success, negative error otherwise 744 */ 745 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id) 746 { 747 unsigned int div_a, div_b; 748 unsigned int ctrl_reg; 749 int ret = 0; 750 unsigned long fscl = id->i2c_clk; 751 752 ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b); 753 if (ret) 754 return ret; 755 756 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 757 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK); 758 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) | 759 (div_b << CDNS_I2C_CR_DIVB_SHIFT)); 760 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 761 762 return 0; 763 } 764 765 /** 766 * cdns_i2c_clk_notifier_cb - Clock rate change callback 767 * @nb: Pointer to notifier block 768 * @event: Notification reason 769 * @data: Pointer to notification data object 770 * 771 * This function is called when the cdns_i2c input clock frequency changes. 772 * The callback checks whether a valid bus frequency can be generated after the 773 * change. If so, the change is acknowledged, otherwise the change is aborted. 774 * New dividers are written to the HW in the pre- or post change notification 775 * depending on the scaling direction. 776 * 777 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK 778 * to acknowledge the change, NOTIFY_DONE if the notification is 779 * considered irrelevant. 780 */ 781 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long 782 event, void *data) 783 { 784 struct clk_notifier_data *ndata = data; 785 struct cdns_i2c *id = to_cdns_i2c(nb); 786 787 if (pm_runtime_suspended(id->dev)) 788 return NOTIFY_OK; 789 790 switch (event) { 791 case PRE_RATE_CHANGE: 792 { 793 unsigned long input_clk = ndata->new_rate; 794 unsigned long fscl = id->i2c_clk; 795 unsigned int div_a, div_b; 796 int ret; 797 798 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b); 799 if (ret) { 800 dev_warn(id->adap.dev.parent, 801 "clock rate change rejected\n"); 802 return NOTIFY_STOP; 803 } 804 805 /* scale up */ 806 if (ndata->new_rate > ndata->old_rate) 807 cdns_i2c_setclk(ndata->new_rate, id); 808 809 return NOTIFY_OK; 810 } 811 case POST_RATE_CHANGE: 812 id->input_clk = ndata->new_rate; 813 /* scale down */ 814 if (ndata->new_rate < ndata->old_rate) 815 cdns_i2c_setclk(ndata->new_rate, id); 816 return NOTIFY_OK; 817 case ABORT_RATE_CHANGE: 818 /* scale up */ 819 if (ndata->new_rate > ndata->old_rate) 820 cdns_i2c_setclk(ndata->old_rate, id); 821 return NOTIFY_OK; 822 default: 823 return NOTIFY_DONE; 824 } 825 } 826 827 /** 828 * cdns_i2c_runtime_suspend - Runtime suspend method for the driver 829 * @dev: Address of the platform_device structure 830 * 831 * Put the driver into low power mode. 832 * 833 * Return: 0 always 834 */ 835 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) 836 { 837 struct cdns_i2c *xi2c = dev_get_drvdata(dev); 838 839 clk_disable(xi2c->clk); 840 841 return 0; 842 } 843 844 /** 845 * cdns_i2c_runtime_resume - Runtime resume 846 * @dev: Address of the platform_device structure 847 * 848 * Runtime resume callback. 849 * 850 * Return: 0 on success and error value on error 851 */ 852 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) 853 { 854 struct cdns_i2c *xi2c = dev_get_drvdata(dev); 855 int ret; 856 857 ret = clk_enable(xi2c->clk); 858 if (ret) { 859 dev_err(dev, "Cannot enable clock.\n"); 860 return ret; 861 } 862 863 return 0; 864 } 865 866 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = { 867 SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend, 868 cdns_i2c_runtime_resume, NULL) 869 }; 870 871 static const struct cdns_platform_data r1p10_i2c_def = { 872 .quirks = CDNS_I2C_BROKEN_HOLD_BIT, 873 }; 874 875 static const struct of_device_id cdns_i2c_of_match[] = { 876 { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def }, 877 { .compatible = "cdns,i2c-r1p14",}, 878 { /* end of table */ } 879 }; 880 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match); 881 882 /** 883 * cdns_i2c_probe - Platform registration call 884 * @pdev: Handle to the platform device structure 885 * 886 * This function does all the memory allocation and registration for the i2c 887 * device. User can modify the address mode to 10 bit address mode using the 888 * ioctl call with option I2C_TENBIT. 889 * 890 * Return: 0 on success, negative error otherwise 891 */ 892 static int cdns_i2c_probe(struct platform_device *pdev) 893 { 894 struct resource *r_mem; 895 struct cdns_i2c *id; 896 int ret; 897 const struct of_device_id *match; 898 899 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL); 900 if (!id) 901 return -ENOMEM; 902 903 id->dev = &pdev->dev; 904 platform_set_drvdata(pdev, id); 905 906 match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node); 907 if (match && match->data) { 908 const struct cdns_platform_data *data = match->data; 909 id->quirks = data->quirks; 910 } 911 912 r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 913 id->membase = devm_ioremap_resource(&pdev->dev, r_mem); 914 if (IS_ERR(id->membase)) 915 return PTR_ERR(id->membase); 916 917 id->irq = platform_get_irq(pdev, 0); 918 919 id->adap.owner = THIS_MODULE; 920 id->adap.dev.of_node = pdev->dev.of_node; 921 id->adap.algo = &cdns_i2c_algo; 922 id->adap.timeout = CDNS_I2C_TIMEOUT; 923 id->adap.retries = 3; /* Default retry value. */ 924 id->adap.algo_data = id; 925 id->adap.dev.parent = &pdev->dev; 926 init_completion(&id->xfer_done); 927 snprintf(id->adap.name, sizeof(id->adap.name), 928 "Cadence I2C at %08lx", (unsigned long)r_mem->start); 929 930 id->clk = devm_clk_get(&pdev->dev, NULL); 931 if (IS_ERR(id->clk)) { 932 if (PTR_ERR(id->clk) != -EPROBE_DEFER) 933 dev_err(&pdev->dev, "input clock not found.\n"); 934 return PTR_ERR(id->clk); 935 } 936 ret = clk_prepare_enable(id->clk); 937 if (ret) 938 dev_err(&pdev->dev, "Unable to enable clock.\n"); 939 940 pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT); 941 pm_runtime_use_autosuspend(id->dev); 942 pm_runtime_set_active(id->dev); 943 pm_runtime_enable(id->dev); 944 945 id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb; 946 if (clk_notifier_register(id->clk, &id->clk_rate_change_nb)) 947 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 948 id->input_clk = clk_get_rate(id->clk); 949 950 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", 951 &id->i2c_clk); 952 if (ret || (id->i2c_clk > CDNS_I2C_SPEED_MAX)) 953 id->i2c_clk = CDNS_I2C_SPEED_DEFAULT; 954 955 cdns_i2c_writereg(CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS, 956 CDNS_I2C_CR_OFFSET); 957 958 ret = cdns_i2c_setclk(id->input_clk, id); 959 if (ret) { 960 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk); 961 ret = -EINVAL; 962 goto err_clk_dis; 963 } 964 965 ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0, 966 DRIVER_NAME, id); 967 if (ret) { 968 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq); 969 goto err_clk_dis; 970 } 971 972 /* 973 * Cadence I2C controller has a bug wherein it generates 974 * invalid read transaction after HW timeout in master receiver mode. 975 * HW timeout is not used by this driver and the interrupt is disabled. 976 * But the feature itself cannot be disabled. Hence maximum value 977 * is written to this register to reduce the chances of error. 978 */ 979 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET); 980 981 ret = i2c_add_adapter(&id->adap); 982 if (ret < 0) 983 goto err_clk_dis; 984 985 dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n", 986 id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq); 987 988 return 0; 989 990 err_clk_dis: 991 clk_disable_unprepare(id->clk); 992 pm_runtime_disable(&pdev->dev); 993 pm_runtime_set_suspended(&pdev->dev); 994 return ret; 995 } 996 997 /** 998 * cdns_i2c_remove - Unregister the device after releasing the resources 999 * @pdev: Handle to the platform device structure 1000 * 1001 * This function frees all the resources allocated to the device. 1002 * 1003 * Return: 0 always 1004 */ 1005 static int cdns_i2c_remove(struct platform_device *pdev) 1006 { 1007 struct cdns_i2c *id = platform_get_drvdata(pdev); 1008 1009 pm_runtime_disable(&pdev->dev); 1010 pm_runtime_set_suspended(&pdev->dev); 1011 pm_runtime_dont_use_autosuspend(&pdev->dev); 1012 1013 i2c_del_adapter(&id->adap); 1014 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb); 1015 clk_disable_unprepare(id->clk); 1016 1017 return 0; 1018 } 1019 1020 static struct platform_driver cdns_i2c_drv = { 1021 .driver = { 1022 .name = DRIVER_NAME, 1023 .of_match_table = cdns_i2c_of_match, 1024 .pm = &cdns_i2c_dev_pm_ops, 1025 }, 1026 .probe = cdns_i2c_probe, 1027 .remove = cdns_i2c_remove, 1028 }; 1029 1030 module_platform_driver(cdns_i2c_drv); 1031 1032 MODULE_AUTHOR("Xilinx Inc."); 1033 MODULE_DESCRIPTION("Cadence I2C bus driver"); 1034 MODULE_LICENSE("GPL"); 1035