1 /* 2 * Allwinner EMAC Fast Ethernet driver for Linux. 3 * 4 * Copyright 2012-2013 Stefan Roese <sr@denx.de> 5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com> 6 * 7 * Based on the Linux driver provided by Allwinner: 8 * Copyright (C) 1997 Sten Wang 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/gpio.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/mii.h> 22 #include <linux/module.h> 23 #include <linux/netdevice.h> 24 #include <linux/of_address.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/phy.h> 31 #include <linux/soc/sunxi/sunxi_sram.h> 32 33 #include "sun4i-emac.h" 34 35 #define DRV_NAME "sun4i-emac" 36 #define DRV_VERSION "1.02" 37 38 #define EMAC_MAX_FRAME_LEN 0x0600 39 40 #define EMAC_DEFAULT_MSG_ENABLE 0x0000 41 static int debug = -1; /* defaults above */; 42 module_param(debug, int, 0); 43 MODULE_PARM_DESC(debug, "debug message flags"); 44 45 /* Transmit timeout, default 5 seconds. */ 46 static int watchdog = 5000; 47 module_param(watchdog, int, 0400); 48 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); 49 50 /* EMAC register address locking. 51 * 52 * The EMAC uses an address register to control where data written 53 * to the data register goes. This means that the address register 54 * must be preserved over interrupts or similar calls. 55 * 56 * During interrupt and other critical calls, a spinlock is used to 57 * protect the system, but the calls themselves save the address 58 * in the address register in case they are interrupting another 59 * access to the device. 60 * 61 * For general accesses a lock is provided so that calls which are 62 * allowed to sleep are serialised so that the address register does 63 * not need to be saved. This lock also serves to serialise access 64 * to the EEPROM and PHY access registers which are shared between 65 * these two devices. 66 */ 67 68 /* The driver supports the original EMACE, and now the two newer 69 * devices, EMACA and EMACB. 70 */ 71 72 struct emac_board_info { 73 struct clk *clk; 74 struct device *dev; 75 struct platform_device *pdev; 76 spinlock_t lock; 77 void __iomem *membase; 78 u32 msg_enable; 79 struct net_device *ndev; 80 struct sk_buff *skb_last; 81 u16 tx_fifo_stat; 82 83 int emacrx_completed_flag; 84 85 struct device_node *phy_node; 86 unsigned int link; 87 unsigned int speed; 88 unsigned int duplex; 89 90 phy_interface_t phy_interface; 91 }; 92 93 static void emac_update_speed(struct net_device *dev) 94 { 95 struct emac_board_info *db = netdev_priv(dev); 96 unsigned int reg_val; 97 98 /* set EMAC SPEED, depend on PHY */ 99 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); 100 reg_val &= ~(0x1 << 8); 101 if (db->speed == SPEED_100) 102 reg_val |= 1 << 8; 103 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); 104 } 105 106 static void emac_update_duplex(struct net_device *dev) 107 { 108 struct emac_board_info *db = netdev_priv(dev); 109 unsigned int reg_val; 110 111 /* set duplex depend on phy */ 112 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); 113 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; 114 if (db->duplex) 115 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; 116 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); 117 } 118 119 static void emac_handle_link_change(struct net_device *dev) 120 { 121 struct emac_board_info *db = netdev_priv(dev); 122 struct phy_device *phydev = dev->phydev; 123 unsigned long flags; 124 int status_change = 0; 125 126 if (phydev->link) { 127 if (db->speed != phydev->speed) { 128 spin_lock_irqsave(&db->lock, flags); 129 db->speed = phydev->speed; 130 emac_update_speed(dev); 131 spin_unlock_irqrestore(&db->lock, flags); 132 status_change = 1; 133 } 134 135 if (db->duplex != phydev->duplex) { 136 spin_lock_irqsave(&db->lock, flags); 137 db->duplex = phydev->duplex; 138 emac_update_duplex(dev); 139 spin_unlock_irqrestore(&db->lock, flags); 140 status_change = 1; 141 } 142 } 143 144 if (phydev->link != db->link) { 145 if (!phydev->link) { 146 db->speed = 0; 147 db->duplex = -1; 148 } 149 db->link = phydev->link; 150 151 status_change = 1; 152 } 153 154 if (status_change) 155 phy_print_status(phydev); 156 } 157 158 static int emac_mdio_probe(struct net_device *dev) 159 { 160 struct emac_board_info *db = netdev_priv(dev); 161 struct phy_device *phydev; 162 163 /* to-do: PHY interrupts are currently not supported */ 164 165 /* attach the mac to the phy */ 166 phydev = of_phy_connect(db->ndev, db->phy_node, 167 &emac_handle_link_change, 0, 168 db->phy_interface); 169 if (!phydev) { 170 netdev_err(db->ndev, "could not find the PHY\n"); 171 return -ENODEV; 172 } 173 174 /* mask with MAC supported features */ 175 phy_set_max_speed(phydev, SPEED_100); 176 177 db->link = 0; 178 db->speed = 0; 179 db->duplex = -1; 180 181 return 0; 182 } 183 184 static void emac_mdio_remove(struct net_device *dev) 185 { 186 phy_disconnect(dev->phydev); 187 } 188 189 static void emac_reset(struct emac_board_info *db) 190 { 191 dev_dbg(db->dev, "resetting device\n"); 192 193 /* RESET device */ 194 writel(0, db->membase + EMAC_CTL_REG); 195 udelay(200); 196 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); 197 udelay(200); 198 } 199 200 static void emac_outblk_32bit(void __iomem *reg, void *data, int count) 201 { 202 writesl(reg, data, round_up(count, 4) / 4); 203 } 204 205 static void emac_inblk_32bit(void __iomem *reg, void *data, int count) 206 { 207 readsl(reg, data, round_up(count, 4) / 4); 208 } 209 210 /* ethtool ops */ 211 static void emac_get_drvinfo(struct net_device *dev, 212 struct ethtool_drvinfo *info) 213 { 214 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 215 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 216 strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info)); 217 } 218 219 static u32 emac_get_msglevel(struct net_device *dev) 220 { 221 struct emac_board_info *db = netdev_priv(dev); 222 223 return db->msg_enable; 224 } 225 226 static void emac_set_msglevel(struct net_device *dev, u32 value) 227 { 228 struct emac_board_info *db = netdev_priv(dev); 229 230 db->msg_enable = value; 231 } 232 233 static const struct ethtool_ops emac_ethtool_ops = { 234 .get_drvinfo = emac_get_drvinfo, 235 .get_link = ethtool_op_get_link, 236 .get_link_ksettings = phy_ethtool_get_link_ksettings, 237 .set_link_ksettings = phy_ethtool_set_link_ksettings, 238 .get_msglevel = emac_get_msglevel, 239 .set_msglevel = emac_set_msglevel, 240 }; 241 242 static unsigned int emac_setup(struct net_device *ndev) 243 { 244 struct emac_board_info *db = netdev_priv(ndev); 245 unsigned int reg_val; 246 247 /* set up TX */ 248 reg_val = readl(db->membase + EMAC_TX_MODE_REG); 249 250 writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN, 251 db->membase + EMAC_TX_MODE_REG); 252 253 /* set MAC */ 254 /* set MAC CTL0 */ 255 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); 256 writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN | 257 EMAC_MAC_CTL0_TX_FLOW_CTL_EN, 258 db->membase + EMAC_MAC_CTL0_REG); 259 260 /* set MAC CTL1 */ 261 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); 262 reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN; 263 reg_val |= EMAC_MAC_CTL1_CRC_EN; 264 reg_val |= EMAC_MAC_CTL1_PAD_EN; 265 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); 266 267 /* set up IPGT */ 268 writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG); 269 270 /* set up IPGR */ 271 writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2, 272 db->membase + EMAC_MAC_IPGR_REG); 273 274 /* set up Collison window */ 275 writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM, 276 db->membase + EMAC_MAC_CLRT_REG); 277 278 /* set up Max Frame Length */ 279 writel(EMAC_MAX_FRAME_LEN, 280 db->membase + EMAC_MAC_MAXF_REG); 281 282 return 0; 283 } 284 285 static void emac_set_rx_mode(struct net_device *ndev) 286 { 287 struct emac_board_info *db = netdev_priv(ndev); 288 unsigned int reg_val; 289 290 /* set up RX */ 291 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 292 293 if (ndev->flags & IFF_PROMISC) 294 reg_val |= EMAC_RX_CTL_PASS_ALL_EN; 295 else 296 reg_val &= ~EMAC_RX_CTL_PASS_ALL_EN; 297 298 writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN | 299 EMAC_RX_CTL_ACCEPT_UNICAST_EN | EMAC_RX_CTL_DA_FILTER_EN | 300 EMAC_RX_CTL_ACCEPT_MULTICAST_EN | 301 EMAC_RX_CTL_ACCEPT_BROADCAST_EN, 302 db->membase + EMAC_RX_CTL_REG); 303 } 304 305 static unsigned int emac_powerup(struct net_device *ndev) 306 { 307 struct emac_board_info *db = netdev_priv(ndev); 308 unsigned int reg_val; 309 310 /* initial EMAC */ 311 /* flush RX FIFO */ 312 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 313 reg_val |= 0x8; 314 writel(reg_val, db->membase + EMAC_RX_CTL_REG); 315 udelay(1); 316 317 /* initial MAC */ 318 /* soft reset MAC */ 319 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); 320 reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET; 321 writel(reg_val, db->membase + EMAC_MAC_CTL0_REG); 322 323 /* set MII clock */ 324 reg_val = readl(db->membase + EMAC_MAC_MCFG_REG); 325 reg_val &= (~(0xf << 2)); 326 reg_val |= (0xD << 2); 327 writel(reg_val, db->membase + EMAC_MAC_MCFG_REG); 328 329 /* clear RX counter */ 330 writel(0x0, db->membase + EMAC_RX_FBC_REG); 331 332 /* disable all interrupt and clear interrupt status */ 333 writel(0, db->membase + EMAC_INT_CTL_REG); 334 reg_val = readl(db->membase + EMAC_INT_STA_REG); 335 writel(reg_val, db->membase + EMAC_INT_STA_REG); 336 337 udelay(1); 338 339 /* set up EMAC */ 340 emac_setup(ndev); 341 342 /* set mac_address to chip */ 343 writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev-> 344 dev_addr[2], db->membase + EMAC_MAC_A1_REG); 345 writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev-> 346 dev_addr[5], db->membase + EMAC_MAC_A0_REG); 347 348 mdelay(1); 349 350 return 0; 351 } 352 353 static int emac_set_mac_address(struct net_device *dev, void *p) 354 { 355 struct sockaddr *addr = p; 356 struct emac_board_info *db = netdev_priv(dev); 357 358 if (netif_running(dev)) 359 return -EBUSY; 360 361 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 362 363 writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev-> 364 dev_addr[2], db->membase + EMAC_MAC_A1_REG); 365 writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev-> 366 dev_addr[5], db->membase + EMAC_MAC_A0_REG); 367 368 return 0; 369 } 370 371 /* Initialize emac board */ 372 static void emac_init_device(struct net_device *dev) 373 { 374 struct emac_board_info *db = netdev_priv(dev); 375 unsigned long flags; 376 unsigned int reg_val; 377 378 spin_lock_irqsave(&db->lock, flags); 379 380 emac_update_speed(dev); 381 emac_update_duplex(dev); 382 383 /* enable RX/TX */ 384 reg_val = readl(db->membase + EMAC_CTL_REG); 385 writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN, 386 db->membase + EMAC_CTL_REG); 387 388 /* enable RX/TX0/RX Hlevel interrup */ 389 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 390 reg_val |= (0xf << 0) | (0x01 << 8); 391 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 392 393 spin_unlock_irqrestore(&db->lock, flags); 394 } 395 396 /* Our watchdog timed out. Called by the networking layer */ 397 static void emac_timeout(struct net_device *dev, unsigned int txqueue) 398 { 399 struct emac_board_info *db = netdev_priv(dev); 400 unsigned long flags; 401 402 if (netif_msg_timer(db)) 403 dev_err(db->dev, "tx time out.\n"); 404 405 /* Save previous register address */ 406 spin_lock_irqsave(&db->lock, flags); 407 408 netif_stop_queue(dev); 409 emac_reset(db); 410 emac_init_device(dev); 411 /* We can accept TX packets again */ 412 netif_trans_update(dev); 413 netif_wake_queue(dev); 414 415 /* Restore previous register address */ 416 spin_unlock_irqrestore(&db->lock, flags); 417 } 418 419 /* Hardware start transmission. 420 * Send a packet to media from the upper layer. 421 */ 422 static int emac_start_xmit(struct sk_buff *skb, struct net_device *dev) 423 { 424 struct emac_board_info *db = netdev_priv(dev); 425 unsigned long channel; 426 unsigned long flags; 427 428 channel = db->tx_fifo_stat & 3; 429 if (channel == 3) 430 return 1; 431 432 channel = (channel == 1 ? 1 : 0); 433 434 spin_lock_irqsave(&db->lock, flags); 435 436 writel(channel, db->membase + EMAC_TX_INS_REG); 437 438 emac_outblk_32bit(db->membase + EMAC_TX_IO_DATA_REG, 439 skb->data, skb->len); 440 dev->stats.tx_bytes += skb->len; 441 442 db->tx_fifo_stat |= 1 << channel; 443 /* TX control: First packet immediately send, second packet queue */ 444 if (channel == 0) { 445 /* set TX len */ 446 writel(skb->len, db->membase + EMAC_TX_PL0_REG); 447 /* start translate from fifo to phy */ 448 writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1, 449 db->membase + EMAC_TX_CTL0_REG); 450 451 /* save the time stamp */ 452 netif_trans_update(dev); 453 } else if (channel == 1) { 454 /* set TX len */ 455 writel(skb->len, db->membase + EMAC_TX_PL1_REG); 456 /* start translate from fifo to phy */ 457 writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1, 458 db->membase + EMAC_TX_CTL1_REG); 459 460 /* save the time stamp */ 461 netif_trans_update(dev); 462 } 463 464 if ((db->tx_fifo_stat & 3) == 3) { 465 /* Second packet */ 466 netif_stop_queue(dev); 467 } 468 469 spin_unlock_irqrestore(&db->lock, flags); 470 471 /* free this SKB */ 472 dev_consume_skb_any(skb); 473 474 return NETDEV_TX_OK; 475 } 476 477 /* EMAC interrupt handler 478 * receive the packet to upper layer, free the transmitted packet 479 */ 480 static void emac_tx_done(struct net_device *dev, struct emac_board_info *db, 481 unsigned int tx_status) 482 { 483 /* One packet sent complete */ 484 db->tx_fifo_stat &= ~(tx_status & 3); 485 if (3 == (tx_status & 3)) 486 dev->stats.tx_packets += 2; 487 else 488 dev->stats.tx_packets++; 489 490 if (netif_msg_tx_done(db)) 491 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); 492 493 netif_wake_queue(dev); 494 } 495 496 /* Received a packet and pass to upper layer 497 */ 498 static void emac_rx(struct net_device *dev) 499 { 500 struct emac_board_info *db = netdev_priv(dev); 501 struct sk_buff *skb; 502 u8 *rdptr; 503 bool good_packet; 504 static int rxlen_last; 505 unsigned int reg_val; 506 u32 rxhdr, rxstatus, rxcount, rxlen; 507 508 /* Check packet ready or not */ 509 while (1) { 510 /* race warning: the first packet might arrive with 511 * the interrupts disabled, but the second will fix 512 * it 513 */ 514 rxcount = readl(db->membase + EMAC_RX_FBC_REG); 515 516 if (netif_msg_rx_status(db)) 517 dev_dbg(db->dev, "RXCount: %x\n", rxcount); 518 519 if ((db->skb_last != NULL) && (rxlen_last > 0)) { 520 dev->stats.rx_bytes += rxlen_last; 521 522 /* Pass to upper layer */ 523 db->skb_last->protocol = eth_type_trans(db->skb_last, 524 dev); 525 netif_rx(db->skb_last); 526 dev->stats.rx_packets++; 527 db->skb_last = NULL; 528 rxlen_last = 0; 529 530 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 531 reg_val &= ~EMAC_RX_CTL_DMA_EN; 532 writel(reg_val, db->membase + EMAC_RX_CTL_REG); 533 } 534 535 if (!rxcount) { 536 db->emacrx_completed_flag = 1; 537 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 538 reg_val |= (0xf << 0) | (0x01 << 8); 539 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 540 541 /* had one stuck? */ 542 rxcount = readl(db->membase + EMAC_RX_FBC_REG); 543 if (!rxcount) 544 return; 545 } 546 547 reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG); 548 if (netif_msg_rx_status(db)) 549 dev_dbg(db->dev, "receive header: %x\n", reg_val); 550 if (reg_val != EMAC_UNDOCUMENTED_MAGIC) { 551 /* disable RX */ 552 reg_val = readl(db->membase + EMAC_CTL_REG); 553 writel(reg_val & ~EMAC_CTL_RX_EN, 554 db->membase + EMAC_CTL_REG); 555 556 /* Flush RX FIFO */ 557 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 558 writel(reg_val | (1 << 3), 559 db->membase + EMAC_RX_CTL_REG); 560 561 do { 562 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 563 } while (reg_val & (1 << 3)); 564 565 /* enable RX */ 566 reg_val = readl(db->membase + EMAC_CTL_REG); 567 writel(reg_val | EMAC_CTL_RX_EN, 568 db->membase + EMAC_CTL_REG); 569 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 570 reg_val |= (0xf << 0) | (0x01 << 8); 571 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 572 573 db->emacrx_completed_flag = 1; 574 575 return; 576 } 577 578 /* A packet ready now & Get status/length */ 579 good_packet = true; 580 581 rxhdr = readl(db->membase + EMAC_RX_IO_DATA_REG); 582 583 if (netif_msg_rx_status(db)) 584 dev_dbg(db->dev, "rxhdr: %x\n", *((int *)(&rxhdr))); 585 586 rxlen = EMAC_RX_IO_DATA_LEN(rxhdr); 587 rxstatus = EMAC_RX_IO_DATA_STATUS(rxhdr); 588 589 if (netif_msg_rx_status(db)) 590 dev_dbg(db->dev, "RX: status %02x, length %04x\n", 591 rxstatus, rxlen); 592 593 /* Packet Status check */ 594 if (rxlen < 0x40) { 595 good_packet = false; 596 if (netif_msg_rx_err(db)) 597 dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); 598 } 599 600 if (unlikely(!(rxstatus & EMAC_RX_IO_DATA_STATUS_OK))) { 601 good_packet = false; 602 603 if (rxstatus & EMAC_RX_IO_DATA_STATUS_CRC_ERR) { 604 if (netif_msg_rx_err(db)) 605 dev_dbg(db->dev, "crc error\n"); 606 dev->stats.rx_crc_errors++; 607 } 608 609 if (rxstatus & EMAC_RX_IO_DATA_STATUS_LEN_ERR) { 610 if (netif_msg_rx_err(db)) 611 dev_dbg(db->dev, "length error\n"); 612 dev->stats.rx_length_errors++; 613 } 614 } 615 616 /* Move data from EMAC */ 617 if (good_packet) { 618 skb = netdev_alloc_skb(dev, rxlen + 4); 619 if (!skb) 620 continue; 621 skb_reserve(skb, 2); 622 rdptr = skb_put(skb, rxlen - 4); 623 624 /* Read received packet from RX SRAM */ 625 if (netif_msg_rx_status(db)) 626 dev_dbg(db->dev, "RxLen %x\n", rxlen); 627 628 emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG, 629 rdptr, rxlen); 630 dev->stats.rx_bytes += rxlen; 631 632 /* Pass to upper layer */ 633 skb->protocol = eth_type_trans(skb, dev); 634 netif_rx(skb); 635 dev->stats.rx_packets++; 636 } 637 } 638 } 639 640 static irqreturn_t emac_interrupt(int irq, void *dev_id) 641 { 642 struct net_device *dev = dev_id; 643 struct emac_board_info *db = netdev_priv(dev); 644 int int_status; 645 unsigned long flags; 646 unsigned int reg_val; 647 648 /* A real interrupt coming */ 649 650 /* holders of db->lock must always block IRQs */ 651 spin_lock_irqsave(&db->lock, flags); 652 653 /* Disable all interrupts */ 654 writel(0, db->membase + EMAC_INT_CTL_REG); 655 656 /* Got EMAC interrupt status */ 657 /* Got ISR */ 658 int_status = readl(db->membase + EMAC_INT_STA_REG); 659 /* Clear ISR status */ 660 writel(int_status, db->membase + EMAC_INT_STA_REG); 661 662 if (netif_msg_intr(db)) 663 dev_dbg(db->dev, "emac interrupt %02x\n", int_status); 664 665 /* Received the coming packet */ 666 if ((int_status & 0x100) && (db->emacrx_completed_flag == 1)) { 667 /* carrier lost */ 668 db->emacrx_completed_flag = 0; 669 emac_rx(dev); 670 } 671 672 /* Transmit Interrupt check */ 673 if (int_status & (0x01 | 0x02)) 674 emac_tx_done(dev, db, int_status); 675 676 if (int_status & (0x04 | 0x08)) 677 netdev_info(dev, " ab : %x\n", int_status); 678 679 /* Re-enable interrupt mask */ 680 if (db->emacrx_completed_flag == 1) { 681 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 682 reg_val |= (0xf << 0) | (0x01 << 8); 683 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 684 } 685 spin_unlock_irqrestore(&db->lock, flags); 686 687 return IRQ_HANDLED; 688 } 689 690 #ifdef CONFIG_NET_POLL_CONTROLLER 691 /* 692 * Used by netconsole 693 */ 694 static void emac_poll_controller(struct net_device *dev) 695 { 696 disable_irq(dev->irq); 697 emac_interrupt(dev->irq, dev); 698 enable_irq(dev->irq); 699 } 700 #endif 701 702 /* Open the interface. 703 * The interface is opened whenever "ifconfig" actives it. 704 */ 705 static int emac_open(struct net_device *dev) 706 { 707 struct emac_board_info *db = netdev_priv(dev); 708 int ret; 709 710 if (netif_msg_ifup(db)) 711 dev_dbg(db->dev, "enabling %s\n", dev->name); 712 713 if (request_irq(dev->irq, &emac_interrupt, 0, dev->name, dev)) 714 return -EAGAIN; 715 716 /* Initialize EMAC board */ 717 emac_reset(db); 718 emac_init_device(dev); 719 720 ret = emac_mdio_probe(dev); 721 if (ret < 0) { 722 free_irq(dev->irq, dev); 723 netdev_err(dev, "cannot probe MDIO bus\n"); 724 return ret; 725 } 726 727 phy_start(dev->phydev); 728 netif_start_queue(dev); 729 730 return 0; 731 } 732 733 static void emac_shutdown(struct net_device *dev) 734 { 735 unsigned int reg_val; 736 struct emac_board_info *db = netdev_priv(dev); 737 738 /* Disable all interrupt */ 739 writel(0, db->membase + EMAC_INT_CTL_REG); 740 741 /* clear interrupt status */ 742 reg_val = readl(db->membase + EMAC_INT_STA_REG); 743 writel(reg_val, db->membase + EMAC_INT_STA_REG); 744 745 /* Disable RX/TX */ 746 reg_val = readl(db->membase + EMAC_CTL_REG); 747 reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET); 748 writel(reg_val, db->membase + EMAC_CTL_REG); 749 } 750 751 /* Stop the interface. 752 * The interface is stopped when it is brought. 753 */ 754 static int emac_stop(struct net_device *ndev) 755 { 756 struct emac_board_info *db = netdev_priv(ndev); 757 758 if (netif_msg_ifdown(db)) 759 dev_dbg(db->dev, "shutting down %s\n", ndev->name); 760 761 netif_stop_queue(ndev); 762 netif_carrier_off(ndev); 763 764 phy_stop(ndev->phydev); 765 766 emac_mdio_remove(ndev); 767 768 emac_shutdown(ndev); 769 770 free_irq(ndev->irq, ndev); 771 772 return 0; 773 } 774 775 static const struct net_device_ops emac_netdev_ops = { 776 .ndo_open = emac_open, 777 .ndo_stop = emac_stop, 778 .ndo_start_xmit = emac_start_xmit, 779 .ndo_tx_timeout = emac_timeout, 780 .ndo_set_rx_mode = emac_set_rx_mode, 781 .ndo_do_ioctl = phy_do_ioctl_running, 782 .ndo_validate_addr = eth_validate_addr, 783 .ndo_set_mac_address = emac_set_mac_address, 784 #ifdef CONFIG_NET_POLL_CONTROLLER 785 .ndo_poll_controller = emac_poll_controller, 786 #endif 787 }; 788 789 /* Search EMAC board, allocate space and register it 790 */ 791 static int emac_probe(struct platform_device *pdev) 792 { 793 struct device_node *np = pdev->dev.of_node; 794 struct emac_board_info *db; 795 struct net_device *ndev; 796 int ret = 0; 797 const char *mac_addr; 798 799 ndev = alloc_etherdev(sizeof(struct emac_board_info)); 800 if (!ndev) { 801 dev_err(&pdev->dev, "could not allocate device.\n"); 802 return -ENOMEM; 803 } 804 805 SET_NETDEV_DEV(ndev, &pdev->dev); 806 807 db = netdev_priv(ndev); 808 809 db->dev = &pdev->dev; 810 db->ndev = ndev; 811 db->pdev = pdev; 812 db->msg_enable = netif_msg_init(debug, EMAC_DEFAULT_MSG_ENABLE); 813 814 spin_lock_init(&db->lock); 815 816 db->membase = of_iomap(np, 0); 817 if (!db->membase) { 818 dev_err(&pdev->dev, "failed to remap registers\n"); 819 ret = -ENOMEM; 820 goto out; 821 } 822 823 /* fill in parameters for net-dev structure */ 824 ndev->base_addr = (unsigned long)db->membase; 825 ndev->irq = irq_of_parse_and_map(np, 0); 826 if (ndev->irq == -ENXIO) { 827 netdev_err(ndev, "No irq resource\n"); 828 ret = ndev->irq; 829 goto out_iounmap; 830 } 831 832 db->clk = devm_clk_get(&pdev->dev, NULL); 833 if (IS_ERR(db->clk)) { 834 ret = PTR_ERR(db->clk); 835 goto out_iounmap; 836 } 837 838 ret = clk_prepare_enable(db->clk); 839 if (ret) { 840 dev_err(&pdev->dev, "Error couldn't enable clock (%d)\n", ret); 841 goto out_iounmap; 842 } 843 844 ret = sunxi_sram_claim(&pdev->dev); 845 if (ret) { 846 dev_err(&pdev->dev, "Error couldn't map SRAM to device\n"); 847 goto out_clk_disable_unprepare; 848 } 849 850 db->phy_node = of_parse_phandle(np, "phy-handle", 0); 851 if (!db->phy_node) 852 db->phy_node = of_parse_phandle(np, "phy", 0); 853 if (!db->phy_node) { 854 dev_err(&pdev->dev, "no associated PHY\n"); 855 ret = -ENODEV; 856 goto out_release_sram; 857 } 858 859 /* Read MAC-address from DT */ 860 mac_addr = of_get_mac_address(np); 861 if (!IS_ERR(mac_addr)) 862 ether_addr_copy(ndev->dev_addr, mac_addr); 863 864 /* Check if the MAC address is valid, if not get a random one */ 865 if (!is_valid_ether_addr(ndev->dev_addr)) { 866 eth_hw_addr_random(ndev); 867 dev_warn(&pdev->dev, "using random MAC address %pM\n", 868 ndev->dev_addr); 869 } 870 871 db->emacrx_completed_flag = 1; 872 emac_powerup(ndev); 873 emac_reset(db); 874 875 ndev->netdev_ops = &emac_netdev_ops; 876 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 877 ndev->ethtool_ops = &emac_ethtool_ops; 878 879 platform_set_drvdata(pdev, ndev); 880 881 /* Carrier starts down, phylib will bring it up */ 882 netif_carrier_off(ndev); 883 884 ret = register_netdev(ndev); 885 if (ret) { 886 dev_err(&pdev->dev, "Registering netdev failed!\n"); 887 ret = -ENODEV; 888 goto out_release_sram; 889 } 890 891 dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n", 892 ndev->name, db->membase, ndev->irq, ndev->dev_addr); 893 894 return 0; 895 896 out_release_sram: 897 sunxi_sram_release(&pdev->dev); 898 out_clk_disable_unprepare: 899 clk_disable_unprepare(db->clk); 900 out_iounmap: 901 iounmap(db->membase); 902 out: 903 dev_err(db->dev, "not found (%d).\n", ret); 904 905 free_netdev(ndev); 906 907 return ret; 908 } 909 910 static int emac_remove(struct platform_device *pdev) 911 { 912 struct net_device *ndev = platform_get_drvdata(pdev); 913 struct emac_board_info *db = netdev_priv(ndev); 914 915 unregister_netdev(ndev); 916 sunxi_sram_release(&pdev->dev); 917 clk_disable_unprepare(db->clk); 918 iounmap(db->membase); 919 free_netdev(ndev); 920 921 dev_dbg(&pdev->dev, "released and freed device\n"); 922 return 0; 923 } 924 925 static int emac_suspend(struct platform_device *dev, pm_message_t state) 926 { 927 struct net_device *ndev = platform_get_drvdata(dev); 928 929 netif_carrier_off(ndev); 930 netif_device_detach(ndev); 931 emac_shutdown(ndev); 932 933 return 0; 934 } 935 936 static int emac_resume(struct platform_device *dev) 937 { 938 struct net_device *ndev = platform_get_drvdata(dev); 939 struct emac_board_info *db = netdev_priv(ndev); 940 941 emac_reset(db); 942 emac_init_device(ndev); 943 netif_device_attach(ndev); 944 945 return 0; 946 } 947 948 static const struct of_device_id emac_of_match[] = { 949 {.compatible = "allwinner,sun4i-a10-emac",}, 950 951 /* Deprecated */ 952 {.compatible = "allwinner,sun4i-emac",}, 953 {}, 954 }; 955 956 MODULE_DEVICE_TABLE(of, emac_of_match); 957 958 static struct platform_driver emac_driver = { 959 .driver = { 960 .name = "sun4i-emac", 961 .of_match_table = emac_of_match, 962 }, 963 .probe = emac_probe, 964 .remove = emac_remove, 965 .suspend = emac_suspend, 966 .resume = emac_resume, 967 }; 968 969 module_platform_driver(emac_driver); 970 971 MODULE_AUTHOR("Stefan Roese <sr@denx.de>"); 972 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 973 MODULE_DESCRIPTION("Allwinner A10 emac network driver"); 974 MODULE_LICENSE("GPL"); 975