1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l42.c -- CS42L42 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/version.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/i2c.h> 19 #include <linux/gpio.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <linux/platform_device.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/gpio/consumer.h> 25 #include <linux/of.h> 26 #include <linux/of_gpio.h> 27 #include <linux/of_device.h> 28 #include <sound/core.h> 29 #include <sound/pcm.h> 30 #include <sound/pcm_params.h> 31 #include <sound/soc.h> 32 #include <sound/soc-dapm.h> 33 #include <sound/initval.h> 34 #include <sound/tlv.h> 35 #include <dt-bindings/sound/cs42l42.h> 36 37 #include "cs42l42.h" 38 39 static const struct reg_default cs42l42_reg_defaults[] = { 40 { CS42L42_FRZ_CTL, 0x00 }, 41 { CS42L42_SRC_CTL, 0x10 }, 42 { CS42L42_MCLK_STATUS, 0x02 }, 43 { CS42L42_MCLK_CTL, 0x02 }, 44 { CS42L42_SFTRAMP_RATE, 0xA4 }, 45 { CS42L42_I2C_DEBOUNCE, 0x88 }, 46 { CS42L42_I2C_STRETCH, 0x03 }, 47 { CS42L42_I2C_TIMEOUT, 0xB7 }, 48 { CS42L42_PWR_CTL1, 0xFF }, 49 { CS42L42_PWR_CTL2, 0x84 }, 50 { CS42L42_PWR_CTL3, 0x20 }, 51 { CS42L42_RSENSE_CTL1, 0x40 }, 52 { CS42L42_RSENSE_CTL2, 0x00 }, 53 { CS42L42_OSC_SWITCH, 0x00 }, 54 { CS42L42_OSC_SWITCH_STATUS, 0x05 }, 55 { CS42L42_RSENSE_CTL3, 0x1B }, 56 { CS42L42_TSENSE_CTL, 0x1B }, 57 { CS42L42_TSRS_INT_DISABLE, 0x00 }, 58 { CS42L42_TRSENSE_STATUS, 0x00 }, 59 { CS42L42_HSDET_CTL1, 0x77 }, 60 { CS42L42_HSDET_CTL2, 0x00 }, 61 { CS42L42_HS_SWITCH_CTL, 0xF3 }, 62 { CS42L42_HS_DET_STATUS, 0x00 }, 63 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 64 { CS42L42_MCLK_SRC_SEL, 0x00 }, 65 { CS42L42_SPDIF_CLK_CFG, 0x00 }, 66 { CS42L42_FSYNC_PW_LOWER, 0x00 }, 67 { CS42L42_FSYNC_PW_UPPER, 0x00 }, 68 { CS42L42_FSYNC_P_LOWER, 0xF9 }, 69 { CS42L42_FSYNC_P_UPPER, 0x00 }, 70 { CS42L42_ASP_CLK_CFG, 0x00 }, 71 { CS42L42_ASP_FRM_CFG, 0x10 }, 72 { CS42L42_FS_RATE_EN, 0x00 }, 73 { CS42L42_IN_ASRC_CLK, 0x00 }, 74 { CS42L42_OUT_ASRC_CLK, 0x00 }, 75 { CS42L42_PLL_DIV_CFG1, 0x00 }, 76 { CS42L42_ADC_OVFL_STATUS, 0x00 }, 77 { CS42L42_MIXER_STATUS, 0x00 }, 78 { CS42L42_SRC_STATUS, 0x00 }, 79 { CS42L42_ASP_RX_STATUS, 0x00 }, 80 { CS42L42_ASP_TX_STATUS, 0x00 }, 81 { CS42L42_CODEC_STATUS, 0x00 }, 82 { CS42L42_DET_INT_STATUS1, 0x00 }, 83 { CS42L42_DET_INT_STATUS2, 0x00 }, 84 { CS42L42_SRCPL_INT_STATUS, 0x00 }, 85 { CS42L42_VPMON_STATUS, 0x00 }, 86 { CS42L42_PLL_LOCK_STATUS, 0x00 }, 87 { CS42L42_TSRS_PLUG_STATUS, 0x00 }, 88 { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, 89 { CS42L42_MIXER_INT_MASK, 0x0F }, 90 { CS42L42_SRC_INT_MASK, 0x0F }, 91 { CS42L42_ASP_RX_INT_MASK, 0x1F }, 92 { CS42L42_ASP_TX_INT_MASK, 0x0F }, 93 { CS42L42_CODEC_INT_MASK, 0x03 }, 94 { CS42L42_SRCPL_INT_MASK, 0xFF }, 95 { CS42L42_VPMON_INT_MASK, 0x01 }, 96 { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, 97 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, 98 { CS42L42_PLL_CTL1, 0x00 }, 99 { CS42L42_PLL_DIV_FRAC0, 0x00 }, 100 { CS42L42_PLL_DIV_FRAC1, 0x00 }, 101 { CS42L42_PLL_DIV_FRAC2, 0x00 }, 102 { CS42L42_PLL_DIV_INT, 0x40 }, 103 { CS42L42_PLL_CTL3, 0x10 }, 104 { CS42L42_PLL_CAL_RATIO, 0x80 }, 105 { CS42L42_PLL_CTL4, 0x03 }, 106 { CS42L42_LOAD_DET_RCSTAT, 0x00 }, 107 { CS42L42_LOAD_DET_DONE, 0x00 }, 108 { CS42L42_LOAD_DET_EN, 0x00 }, 109 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, 110 { CS42L42_WAKE_CTL, 0xC0 }, 111 { CS42L42_ADC_DISABLE_MUTE, 0x00 }, 112 { CS42L42_TIPSENSE_CTL, 0x02 }, 113 { CS42L42_MISC_DET_CTL, 0x03 }, 114 { CS42L42_MIC_DET_CTL1, 0x1F }, 115 { CS42L42_MIC_DET_CTL2, 0x2F }, 116 { CS42L42_DET_STATUS1, 0x00 }, 117 { CS42L42_DET_STATUS2, 0x00 }, 118 { CS42L42_DET_INT1_MASK, 0xE0 }, 119 { CS42L42_DET_INT2_MASK, 0xFF }, 120 { CS42L42_HS_BIAS_CTL, 0xC2 }, 121 { CS42L42_ADC_CTL, 0x00 }, 122 { CS42L42_ADC_VOLUME, 0x00 }, 123 { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, 124 { CS42L42_DAC_CTL1, 0x00 }, 125 { CS42L42_DAC_CTL2, 0x02 }, 126 { CS42L42_HP_CTL, 0x0D }, 127 { CS42L42_CLASSH_CTL, 0x07 }, 128 { CS42L42_MIXER_CHA_VOL, 0x3F }, 129 { CS42L42_MIXER_ADC_VOL, 0x3F }, 130 { CS42L42_MIXER_CHB_VOL, 0x3F }, 131 { CS42L42_EQ_COEF_IN0, 0x22 }, 132 { CS42L42_EQ_COEF_IN1, 0x00 }, 133 { CS42L42_EQ_COEF_IN2, 0x00 }, 134 { CS42L42_EQ_COEF_IN3, 0x00 }, 135 { CS42L42_EQ_COEF_RW, 0x00 }, 136 { CS42L42_EQ_COEF_OUT0, 0x00 }, 137 { CS42L42_EQ_COEF_OUT1, 0x00 }, 138 { CS42L42_EQ_COEF_OUT2, 0x00 }, 139 { CS42L42_EQ_COEF_OUT3, 0x00 }, 140 { CS42L42_EQ_INIT_STAT, 0x00 }, 141 { CS42L42_EQ_START_FILT, 0x00 }, 142 { CS42L42_EQ_MUTE_CTL, 0x00 }, 143 { CS42L42_SP_RX_CH_SEL, 0x04 }, 144 { CS42L42_SP_RX_ISOC_CTL, 0x04 }, 145 { CS42L42_SP_RX_FS, 0x8C }, 146 { CS42l42_SPDIF_CH_SEL, 0x0E }, 147 { CS42L42_SP_TX_ISOC_CTL, 0x04 }, 148 { CS42L42_SP_TX_FS, 0xCC }, 149 { CS42L42_SPDIF_SW_CTL1, 0x3F }, 150 { CS42L42_SRC_SDIN_FS, 0x40 }, 151 { CS42L42_SRC_SDOUT_FS, 0x40 }, 152 { CS42L42_SPDIF_CTL1, 0x01 }, 153 { CS42L42_SPDIF_CTL2, 0x00 }, 154 { CS42L42_SPDIF_CTL3, 0x00 }, 155 { CS42L42_SPDIF_CTL4, 0x42 }, 156 { CS42L42_ASP_TX_SZ_EN, 0x00 }, 157 { CS42L42_ASP_TX_CH_EN, 0x00 }, 158 { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, 159 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, 160 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, 161 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, 162 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, 163 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, 164 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 165 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, 166 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, 167 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, 168 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, 169 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, 170 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, 171 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, 172 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, 173 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, 174 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, 175 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, 176 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, 177 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, 178 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, 179 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, 180 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, 181 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, 182 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, 183 { CS42L42_SUB_REVID, 0x03 }, 184 }; 185 186 static bool cs42l42_readable_register(struct device *dev, unsigned int reg) 187 { 188 switch (reg) { 189 case CS42L42_PAGE_REGISTER: 190 case CS42L42_DEVID_AB: 191 case CS42L42_DEVID_CD: 192 case CS42L42_DEVID_E: 193 case CS42L42_FABID: 194 case CS42L42_REVID: 195 case CS42L42_FRZ_CTL: 196 case CS42L42_SRC_CTL: 197 case CS42L42_MCLK_STATUS: 198 case CS42L42_MCLK_CTL: 199 case CS42L42_SFTRAMP_RATE: 200 case CS42L42_I2C_DEBOUNCE: 201 case CS42L42_I2C_STRETCH: 202 case CS42L42_I2C_TIMEOUT: 203 case CS42L42_PWR_CTL1: 204 case CS42L42_PWR_CTL2: 205 case CS42L42_PWR_CTL3: 206 case CS42L42_RSENSE_CTL1: 207 case CS42L42_RSENSE_CTL2: 208 case CS42L42_OSC_SWITCH: 209 case CS42L42_OSC_SWITCH_STATUS: 210 case CS42L42_RSENSE_CTL3: 211 case CS42L42_TSENSE_CTL: 212 case CS42L42_TSRS_INT_DISABLE: 213 case CS42L42_TRSENSE_STATUS: 214 case CS42L42_HSDET_CTL1: 215 case CS42L42_HSDET_CTL2: 216 case CS42L42_HS_SWITCH_CTL: 217 case CS42L42_HS_DET_STATUS: 218 case CS42L42_HS_CLAMP_DISABLE: 219 case CS42L42_MCLK_SRC_SEL: 220 case CS42L42_SPDIF_CLK_CFG: 221 case CS42L42_FSYNC_PW_LOWER: 222 case CS42L42_FSYNC_PW_UPPER: 223 case CS42L42_FSYNC_P_LOWER: 224 case CS42L42_FSYNC_P_UPPER: 225 case CS42L42_ASP_CLK_CFG: 226 case CS42L42_ASP_FRM_CFG: 227 case CS42L42_FS_RATE_EN: 228 case CS42L42_IN_ASRC_CLK: 229 case CS42L42_OUT_ASRC_CLK: 230 case CS42L42_PLL_DIV_CFG1: 231 case CS42L42_ADC_OVFL_STATUS: 232 case CS42L42_MIXER_STATUS: 233 case CS42L42_SRC_STATUS: 234 case CS42L42_ASP_RX_STATUS: 235 case CS42L42_ASP_TX_STATUS: 236 case CS42L42_CODEC_STATUS: 237 case CS42L42_DET_INT_STATUS1: 238 case CS42L42_DET_INT_STATUS2: 239 case CS42L42_SRCPL_INT_STATUS: 240 case CS42L42_VPMON_STATUS: 241 case CS42L42_PLL_LOCK_STATUS: 242 case CS42L42_TSRS_PLUG_STATUS: 243 case CS42L42_ADC_OVFL_INT_MASK: 244 case CS42L42_MIXER_INT_MASK: 245 case CS42L42_SRC_INT_MASK: 246 case CS42L42_ASP_RX_INT_MASK: 247 case CS42L42_ASP_TX_INT_MASK: 248 case CS42L42_CODEC_INT_MASK: 249 case CS42L42_SRCPL_INT_MASK: 250 case CS42L42_VPMON_INT_MASK: 251 case CS42L42_PLL_LOCK_INT_MASK: 252 case CS42L42_TSRS_PLUG_INT_MASK: 253 case CS42L42_PLL_CTL1: 254 case CS42L42_PLL_DIV_FRAC0: 255 case CS42L42_PLL_DIV_FRAC1: 256 case CS42L42_PLL_DIV_FRAC2: 257 case CS42L42_PLL_DIV_INT: 258 case CS42L42_PLL_CTL3: 259 case CS42L42_PLL_CAL_RATIO: 260 case CS42L42_PLL_CTL4: 261 case CS42L42_LOAD_DET_RCSTAT: 262 case CS42L42_LOAD_DET_DONE: 263 case CS42L42_LOAD_DET_EN: 264 case CS42L42_HSBIAS_SC_AUTOCTL: 265 case CS42L42_WAKE_CTL: 266 case CS42L42_ADC_DISABLE_MUTE: 267 case CS42L42_TIPSENSE_CTL: 268 case CS42L42_MISC_DET_CTL: 269 case CS42L42_MIC_DET_CTL1: 270 case CS42L42_MIC_DET_CTL2: 271 case CS42L42_DET_STATUS1: 272 case CS42L42_DET_STATUS2: 273 case CS42L42_DET_INT1_MASK: 274 case CS42L42_DET_INT2_MASK: 275 case CS42L42_HS_BIAS_CTL: 276 case CS42L42_ADC_CTL: 277 case CS42L42_ADC_VOLUME: 278 case CS42L42_ADC_WNF_HPF_CTL: 279 case CS42L42_DAC_CTL1: 280 case CS42L42_DAC_CTL2: 281 case CS42L42_HP_CTL: 282 case CS42L42_CLASSH_CTL: 283 case CS42L42_MIXER_CHA_VOL: 284 case CS42L42_MIXER_ADC_VOL: 285 case CS42L42_MIXER_CHB_VOL: 286 case CS42L42_EQ_COEF_IN0: 287 case CS42L42_EQ_COEF_IN1: 288 case CS42L42_EQ_COEF_IN2: 289 case CS42L42_EQ_COEF_IN3: 290 case CS42L42_EQ_COEF_RW: 291 case CS42L42_EQ_COEF_OUT0: 292 case CS42L42_EQ_COEF_OUT1: 293 case CS42L42_EQ_COEF_OUT2: 294 case CS42L42_EQ_COEF_OUT3: 295 case CS42L42_EQ_INIT_STAT: 296 case CS42L42_EQ_START_FILT: 297 case CS42L42_EQ_MUTE_CTL: 298 case CS42L42_SP_RX_CH_SEL: 299 case CS42L42_SP_RX_ISOC_CTL: 300 case CS42L42_SP_RX_FS: 301 case CS42l42_SPDIF_CH_SEL: 302 case CS42L42_SP_TX_ISOC_CTL: 303 case CS42L42_SP_TX_FS: 304 case CS42L42_SPDIF_SW_CTL1: 305 case CS42L42_SRC_SDIN_FS: 306 case CS42L42_SRC_SDOUT_FS: 307 case CS42L42_SPDIF_CTL1: 308 case CS42L42_SPDIF_CTL2: 309 case CS42L42_SPDIF_CTL3: 310 case CS42L42_SPDIF_CTL4: 311 case CS42L42_ASP_TX_SZ_EN: 312 case CS42L42_ASP_TX_CH_EN: 313 case CS42L42_ASP_TX_CH_AP_RES: 314 case CS42L42_ASP_TX_CH1_BIT_MSB: 315 case CS42L42_ASP_TX_CH1_BIT_LSB: 316 case CS42L42_ASP_TX_HIZ_DLY_CFG: 317 case CS42L42_ASP_TX_CH2_BIT_MSB: 318 case CS42L42_ASP_TX_CH2_BIT_LSB: 319 case CS42L42_ASP_RX_DAI0_EN: 320 case CS42L42_ASP_RX_DAI0_CH1_AP_RES: 321 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: 322 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: 323 case CS42L42_ASP_RX_DAI0_CH2_AP_RES: 324 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: 325 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: 326 case CS42L42_ASP_RX_DAI0_CH3_AP_RES: 327 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: 328 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: 329 case CS42L42_ASP_RX_DAI0_CH4_AP_RES: 330 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: 331 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: 332 case CS42L42_ASP_RX_DAI1_CH1_AP_RES: 333 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: 334 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: 335 case CS42L42_ASP_RX_DAI1_CH2_AP_RES: 336 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: 337 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: 338 case CS42L42_SUB_REVID: 339 return true; 340 default: 341 return false; 342 } 343 } 344 345 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 346 { 347 switch (reg) { 348 case CS42L42_DEVID_AB: 349 case CS42L42_DEVID_CD: 350 case CS42L42_DEVID_E: 351 case CS42L42_MCLK_STATUS: 352 case CS42L42_TRSENSE_STATUS: 353 case CS42L42_HS_DET_STATUS: 354 case CS42L42_ADC_OVFL_STATUS: 355 case CS42L42_MIXER_STATUS: 356 case CS42L42_SRC_STATUS: 357 case CS42L42_ASP_RX_STATUS: 358 case CS42L42_ASP_TX_STATUS: 359 case CS42L42_CODEC_STATUS: 360 case CS42L42_DET_INT_STATUS1: 361 case CS42L42_DET_INT_STATUS2: 362 case CS42L42_SRCPL_INT_STATUS: 363 case CS42L42_VPMON_STATUS: 364 case CS42L42_PLL_LOCK_STATUS: 365 case CS42L42_TSRS_PLUG_STATUS: 366 case CS42L42_LOAD_DET_RCSTAT: 367 case CS42L42_LOAD_DET_DONE: 368 case CS42L42_DET_STATUS1: 369 case CS42L42_DET_STATUS2: 370 return true; 371 default: 372 return false; 373 } 374 } 375 376 static const struct regmap_range_cfg cs42l42_page_range = { 377 .name = "Pages", 378 .range_min = 0, 379 .range_max = CS42L42_MAX_REGISTER, 380 .selector_reg = CS42L42_PAGE_REGISTER, 381 .selector_mask = 0xff, 382 .selector_shift = 0, 383 .window_start = 0, 384 .window_len = 256, 385 }; 386 387 static const struct regmap_config cs42l42_regmap = { 388 .reg_bits = 8, 389 .val_bits = 8, 390 391 .readable_reg = cs42l42_readable_register, 392 .volatile_reg = cs42l42_volatile_register, 393 394 .ranges = &cs42l42_page_range, 395 .num_ranges = 1, 396 397 .max_register = CS42L42_MAX_REGISTER, 398 .reg_defaults = cs42l42_reg_defaults, 399 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), 400 .cache_type = REGCACHE_RBTREE, 401 }; 402 403 static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, false); 404 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6200, 100, false); 405 406 static const char * const cs42l42_hpf_freq_text[] = { 407 "1.86Hz", "120Hz", "235Hz", "466Hz" 408 }; 409 410 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 411 CS42L42_ADC_HPF_CF_SHIFT, 412 cs42l42_hpf_freq_text); 413 414 static const char * const cs42l42_wnf3_freq_text[] = { 415 "160Hz", "180Hz", "200Hz", "220Hz", 416 "240Hz", "260Hz", "280Hz", "300Hz" 417 }; 418 419 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 420 CS42L42_ADC_WNF_CF_SHIFT, 421 cs42l42_wnf3_freq_text); 422 423 static const char * const cs42l42_wnf05_freq_text[] = { 424 "280Hz", "315Hz", "350Hz", "385Hz", 425 "420Hz", "455Hz", "490Hz", "525Hz" 426 }; 427 428 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf05_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 429 CS42L42_ADC_WNF_CF_SHIFT, 430 cs42l42_wnf05_freq_text); 431 432 static const struct snd_kcontrol_new cs42l42_snd_controls[] = { 433 /* ADC Volume and Filter Controls */ 434 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL, 435 CS42L42_ADC_NOTCH_DIS_SHIFT, true, false), 436 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL, 437 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), 438 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL, 439 CS42L42_ADC_INV_SHIFT, true, false), 440 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL, 441 CS42L42_ADC_DIG_BOOST_SHIFT, true, false), 442 SOC_SINGLE_SX_TLV("ADC Volume", CS42L42_ADC_VOLUME, 443 CS42L42_ADC_VOL_SHIFT, 0xA0, 0x6C, adc_tlv), 444 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL, 445 CS42L42_ADC_WNF_EN_SHIFT, true, false), 446 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL, 447 CS42L42_ADC_HPF_EN_SHIFT, true, false), 448 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum), 449 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum), 450 SOC_ENUM("WNF 05dB Freq", cs42l42_wnf05_freq_enum), 451 452 /* DAC Volume and Filter Controls */ 453 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1, 454 CS42L42_DACA_INV_SHIFT, true, false), 455 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1, 456 CS42L42_DACB_INV_SHIFT, true, false), 457 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2, 458 CS42L42_DAC_HPF_EN_SHIFT, true, false), 459 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL, 460 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, 461 0x3e, 1, mixer_tlv) 462 }; 463 464 static int cs42l42_hpdrv_evt(struct snd_soc_dapm_widget *w, 465 struct snd_kcontrol *kcontrol, int event) 466 { 467 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 468 469 if (event & SND_SOC_DAPM_POST_PMU) { 470 /* Enable the channels */ 471 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN, 472 CS42L42_ASP_RX0_CH_EN_MASK, 473 (CS42L42_ASP_RX0_CH1_EN | 474 CS42L42_ASP_RX0_CH2_EN) << 475 CS42L42_ASP_RX0_CH_EN_SHIFT); 476 477 /* Power up */ 478 snd_soc_component_update_bits(component, CS42L42_PWR_CTL1, 479 CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK | 480 CS42L42_HP_PDN_MASK, 0); 481 } else if (event & SND_SOC_DAPM_PRE_PMD) { 482 /* Disable the channels */ 483 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN, 484 CS42L42_ASP_RX0_CH_EN_MASK, 0); 485 486 /* Power down */ 487 snd_soc_component_update_bits(component, CS42L42_PWR_CTL1, 488 CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK | 489 CS42L42_HP_PDN_MASK, 490 CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK | 491 CS42L42_HP_PDN_MASK); 492 } else { 493 dev_err(component->dev, "Invalid event 0x%x\n", event); 494 } 495 return 0; 496 } 497 498 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { 499 SND_SOC_DAPM_OUTPUT("HP"), 500 SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS42L42_ASP_CLK_CFG, 501 CS42L42_ASP_SCLK_EN_SHIFT, false), 502 SND_SOC_DAPM_OUT_DRV_E("HPDRV", SND_SOC_NOPM, 0, 503 0, NULL, 0, cs42l42_hpdrv_evt, 504 SND_SOC_DAPM_POST_PMU | 505 SND_SOC_DAPM_PRE_PMD) 506 }; 507 508 static const struct snd_soc_dapm_route cs42l42_audio_map[] = { 509 {"SDIN", NULL, "Playback"}, 510 {"HPDRV", NULL, "SDIN"}, 511 {"HP", NULL, "HPDRV"} 512 }; 513 514 static int cs42l42_set_bias_level(struct snd_soc_component *component, 515 enum snd_soc_bias_level level) 516 { 517 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 518 int ret; 519 520 switch (level) { 521 case SND_SOC_BIAS_ON: 522 break; 523 case SND_SOC_BIAS_PREPARE: 524 break; 525 case SND_SOC_BIAS_STANDBY: 526 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 527 regcache_cache_only(cs42l42->regmap, false); 528 regcache_sync(cs42l42->regmap); 529 ret = regulator_bulk_enable( 530 ARRAY_SIZE(cs42l42->supplies), 531 cs42l42->supplies); 532 if (ret != 0) { 533 dev_err(component->dev, 534 "Failed to enable regulators: %d\n", 535 ret); 536 return ret; 537 } 538 } 539 break; 540 case SND_SOC_BIAS_OFF: 541 542 regcache_cache_only(cs42l42->regmap, true); 543 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 544 cs42l42->supplies); 545 break; 546 } 547 548 return 0; 549 } 550 551 static int cs42l42_component_probe(struct snd_soc_component *component) 552 { 553 struct cs42l42_private *cs42l42 = 554 (struct cs42l42_private *)snd_soc_component_get_drvdata(component); 555 556 cs42l42->component = component; 557 558 return 0; 559 } 560 561 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = { 562 .probe = cs42l42_component_probe, 563 .set_bias_level = cs42l42_set_bias_level, 564 .dapm_widgets = cs42l42_dapm_widgets, 565 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), 566 .dapm_routes = cs42l42_audio_map, 567 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), 568 .controls = cs42l42_snd_controls, 569 .num_controls = ARRAY_SIZE(cs42l42_snd_controls), 570 .idle_bias_on = 1, 571 .endianness = 1, 572 .non_legacy_dai_naming = 1, 573 }; 574 575 struct cs42l42_pll_params { 576 u32 sclk; 577 u8 mclk_div; 578 u8 mclk_src_sel; 579 u8 sclk_prediv; 580 u8 pll_div_int; 581 u32 pll_div_frac; 582 u8 pll_mode; 583 u8 pll_divout; 584 u32 mclk_int; 585 u8 pll_cal_ratio; 586 }; 587 588 /* 589 * Common PLL Settings for given SCLK 590 * Table 4-5 from the Datasheet 591 */ 592 static const struct cs42l42_pll_params pll_ratio_table[] = { 593 { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 }, 594 { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 }, 595 { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 }, 596 { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 }, 597 { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 }, 598 { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 }, 599 { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 }, 600 { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 }, 601 { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 }, 602 { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 }, 603 { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 }, 604 { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 }, 605 { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 }, 606 { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 }, 607 { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 } 608 }; 609 610 static int cs42l42_pll_config(struct snd_soc_component *component) 611 { 612 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 613 int i; 614 u32 fsync; 615 616 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 617 if (pll_ratio_table[i].sclk == cs42l42->sclk) { 618 /* Configure the internal sample rate */ 619 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, 620 CS42L42_INTERNAL_FS_MASK, 621 ((pll_ratio_table[i].mclk_int != 622 12000000) && 623 (pll_ratio_table[i].mclk_int != 624 24000000)) << 625 CS42L42_INTERNAL_FS_SHIFT); 626 /* Set the MCLK src (PLL or SCLK) and the divide 627 * ratio 628 */ 629 snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL, 630 CS42L42_MCLK_SRC_SEL_MASK | 631 CS42L42_MCLKDIV_MASK, 632 (pll_ratio_table[i].mclk_src_sel 633 << CS42L42_MCLK_SRC_SEL_SHIFT) | 634 (pll_ratio_table[i].mclk_div << 635 CS42L42_MCLKDIV_SHIFT)); 636 /* Set up the LRCLK */ 637 fsync = cs42l42->sclk / cs42l42->srate; 638 if (((fsync * cs42l42->srate) != cs42l42->sclk) 639 || ((fsync % 2) != 0)) { 640 dev_err(component->dev, 641 "Unsupported sclk %d/sample rate %d\n", 642 cs42l42->sclk, 643 cs42l42->srate); 644 return -EINVAL; 645 } 646 /* Set the LRCLK period */ 647 snd_soc_component_update_bits(component, 648 CS42L42_FSYNC_P_LOWER, 649 CS42L42_FSYNC_PERIOD_MASK, 650 CS42L42_FRAC0_VAL(fsync - 1) << 651 CS42L42_FSYNC_PERIOD_SHIFT); 652 snd_soc_component_update_bits(component, 653 CS42L42_FSYNC_P_UPPER, 654 CS42L42_FSYNC_PERIOD_MASK, 655 CS42L42_FRAC1_VAL(fsync - 1) << 656 CS42L42_FSYNC_PERIOD_SHIFT); 657 /* Set the LRCLK to 50% duty cycle */ 658 fsync = fsync / 2; 659 snd_soc_component_update_bits(component, 660 CS42L42_FSYNC_PW_LOWER, 661 CS42L42_FSYNC_PULSE_WIDTH_MASK, 662 CS42L42_FRAC0_VAL(fsync - 1) << 663 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 664 snd_soc_component_update_bits(component, 665 CS42L42_FSYNC_PW_UPPER, 666 CS42L42_FSYNC_PULSE_WIDTH_MASK, 667 CS42L42_FRAC1_VAL(fsync - 1) << 668 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 669 snd_soc_component_update_bits(component, 670 CS42L42_ASP_FRM_CFG, 671 CS42L42_ASP_5050_MASK, 672 CS42L42_ASP_5050_MASK); 673 /* Set the frame delay to 1.0 SCLK clocks */ 674 snd_soc_component_update_bits(component, CS42L42_ASP_FRM_CFG, 675 CS42L42_ASP_FSD_MASK, 676 CS42L42_ASP_FSD_1_0 << 677 CS42L42_ASP_FSD_SHIFT); 678 /* Set the sample rates (96k or lower) */ 679 snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN, 680 CS42L42_FS_EN_MASK, 681 (CS42L42_FS_EN_IASRC_96K | 682 CS42L42_FS_EN_OASRC_96K) << 683 CS42L42_FS_EN_SHIFT); 684 /* Set the input/output internal MCLK clock ~12 MHz */ 685 snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK, 686 CS42L42_CLK_IASRC_SEL_MASK, 687 CS42L42_CLK_IASRC_SEL_12 << 688 CS42L42_CLK_IASRC_SEL_SHIFT); 689 snd_soc_component_update_bits(component, 690 CS42L42_OUT_ASRC_CLK, 691 CS42L42_CLK_OASRC_SEL_MASK, 692 CS42L42_CLK_OASRC_SEL_12 << 693 CS42L42_CLK_OASRC_SEL_SHIFT); 694 /* channel 1 on low LRCLK, 32 bit */ 695 snd_soc_component_update_bits(component, 696 CS42L42_ASP_RX_DAI0_CH1_AP_RES, 697 CS42L42_ASP_RX_CH_AP_MASK | 698 CS42L42_ASP_RX_CH_RES_MASK, 699 (CS42L42_ASP_RX_CH_AP_LOW << 700 CS42L42_ASP_RX_CH_AP_SHIFT) | 701 (CS42L42_ASP_RX_CH_RES_32 << 702 CS42L42_ASP_RX_CH_RES_SHIFT)); 703 /* Channel 2 on high LRCLK, 32 bit */ 704 snd_soc_component_update_bits(component, 705 CS42L42_ASP_RX_DAI0_CH2_AP_RES, 706 CS42L42_ASP_RX_CH_AP_MASK | 707 CS42L42_ASP_RX_CH_RES_MASK, 708 (CS42L42_ASP_RX_CH_AP_HI << 709 CS42L42_ASP_RX_CH_AP_SHIFT) | 710 (CS42L42_ASP_RX_CH_RES_32 << 711 CS42L42_ASP_RX_CH_RES_SHIFT)); 712 if (pll_ratio_table[i].mclk_src_sel == 0) { 713 /* Pass the clock straight through */ 714 snd_soc_component_update_bits(component, 715 CS42L42_PLL_CTL1, 716 CS42L42_PLL_START_MASK, 0); 717 } else { 718 /* Configure PLL per table 4-5 */ 719 snd_soc_component_update_bits(component, 720 CS42L42_PLL_DIV_CFG1, 721 CS42L42_SCLK_PREDIV_MASK, 722 pll_ratio_table[i].sclk_prediv 723 << CS42L42_SCLK_PREDIV_SHIFT); 724 snd_soc_component_update_bits(component, 725 CS42L42_PLL_DIV_INT, 726 CS42L42_PLL_DIV_INT_MASK, 727 pll_ratio_table[i].pll_div_int 728 << CS42L42_PLL_DIV_INT_SHIFT); 729 snd_soc_component_update_bits(component, 730 CS42L42_PLL_DIV_FRAC0, 731 CS42L42_PLL_DIV_FRAC_MASK, 732 CS42L42_FRAC0_VAL( 733 pll_ratio_table[i].pll_div_frac) 734 << CS42L42_PLL_DIV_FRAC_SHIFT); 735 snd_soc_component_update_bits(component, 736 CS42L42_PLL_DIV_FRAC1, 737 CS42L42_PLL_DIV_FRAC_MASK, 738 CS42L42_FRAC1_VAL( 739 pll_ratio_table[i].pll_div_frac) 740 << CS42L42_PLL_DIV_FRAC_SHIFT); 741 snd_soc_component_update_bits(component, 742 CS42L42_PLL_DIV_FRAC2, 743 CS42L42_PLL_DIV_FRAC_MASK, 744 CS42L42_FRAC2_VAL( 745 pll_ratio_table[i].pll_div_frac) 746 << CS42L42_PLL_DIV_FRAC_SHIFT); 747 snd_soc_component_update_bits(component, 748 CS42L42_PLL_CTL4, 749 CS42L42_PLL_MODE_MASK, 750 pll_ratio_table[i].pll_mode 751 << CS42L42_PLL_MODE_SHIFT); 752 snd_soc_component_update_bits(component, 753 CS42L42_PLL_CTL3, 754 CS42L42_PLL_DIVOUT_MASK, 755 pll_ratio_table[i].pll_divout 756 << CS42L42_PLL_DIVOUT_SHIFT); 757 snd_soc_component_update_bits(component, 758 CS42L42_PLL_CAL_RATIO, 759 CS42L42_PLL_CAL_RATIO_MASK, 760 pll_ratio_table[i].pll_cal_ratio 761 << CS42L42_PLL_CAL_RATIO_SHIFT); 762 } 763 return 0; 764 } 765 } 766 767 return -EINVAL; 768 } 769 770 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 771 { 772 struct snd_soc_component *component = codec_dai->component; 773 u32 asp_cfg_val = 0; 774 775 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 776 case SND_SOC_DAIFMT_CBS_CFM: 777 asp_cfg_val |= CS42L42_ASP_MASTER_MODE << 778 CS42L42_ASP_MODE_SHIFT; 779 break; 780 case SND_SOC_DAIFMT_CBS_CFS: 781 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << 782 CS42L42_ASP_MODE_SHIFT; 783 break; 784 default: 785 return -EINVAL; 786 } 787 788 /* interface format */ 789 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 790 case SND_SOC_DAIFMT_I2S: 791 case SND_SOC_DAIFMT_LEFT_J: 792 break; 793 default: 794 return -EINVAL; 795 } 796 797 /* Bitclock/frame inversion */ 798 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 799 case SND_SOC_DAIFMT_NB_NF: 800 break; 801 case SND_SOC_DAIFMT_NB_IF: 802 asp_cfg_val |= CS42L42_ASP_POL_INV << 803 CS42L42_ASP_LCPOL_IN_SHIFT; 804 break; 805 case SND_SOC_DAIFMT_IB_NF: 806 asp_cfg_val |= CS42L42_ASP_POL_INV << 807 CS42L42_ASP_SCPOL_IN_DAC_SHIFT; 808 break; 809 case SND_SOC_DAIFMT_IB_IF: 810 asp_cfg_val |= CS42L42_ASP_POL_INV << 811 CS42L42_ASP_LCPOL_IN_SHIFT; 812 asp_cfg_val |= CS42L42_ASP_POL_INV << 813 CS42L42_ASP_SCPOL_IN_DAC_SHIFT; 814 break; 815 } 816 817 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, 818 CS42L42_ASP_MODE_MASK | 819 CS42L42_ASP_SCPOL_IN_DAC_MASK | 820 CS42L42_ASP_LCPOL_IN_MASK, asp_cfg_val); 821 822 return 0; 823 } 824 825 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, 826 struct snd_pcm_hw_params *params, 827 struct snd_soc_dai *dai) 828 { 829 struct snd_soc_component *component = dai->component; 830 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 831 int retval; 832 833 cs42l42->srate = params_rate(params); 834 cs42l42->swidth = params_width(params); 835 836 retval = cs42l42_pll_config(component); 837 838 return retval; 839 } 840 841 static int cs42l42_set_sysclk(struct snd_soc_dai *dai, 842 int clk_id, unsigned int freq, int dir) 843 { 844 struct snd_soc_component *component = dai->component; 845 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 846 847 cs42l42->sclk = freq; 848 849 return 0; 850 } 851 852 static int cs42l42_mute(struct snd_soc_dai *dai, int mute, int direction) 853 { 854 struct snd_soc_component *component = dai->component; 855 unsigned int regval; 856 u8 fullScaleVol; 857 858 if (mute) { 859 /* Mark SCLK as not present to turn on the internal 860 * oscillator. 861 */ 862 snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH, 863 CS42L42_SCLK_PRESENT_MASK, 0); 864 865 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 866 CS42L42_PLL_START_MASK, 867 0 << CS42L42_PLL_START_SHIFT); 868 869 /* Mute the headphone */ 870 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 871 CS42L42_HP_ANA_AMUTE_MASK | 872 CS42L42_HP_ANA_BMUTE_MASK, 873 CS42L42_HP_ANA_AMUTE_MASK | 874 CS42L42_HP_ANA_BMUTE_MASK); 875 } else { 876 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 877 CS42L42_PLL_START_MASK, 878 1 << CS42L42_PLL_START_SHIFT); 879 /* Read the headphone load */ 880 regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT); 881 if (((regval & CS42L42_RLA_STAT_MASK) >> 882 CS42L42_RLA_STAT_SHIFT) == CS42L42_RLA_STAT_15_OHM) { 883 fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK; 884 } else { 885 fullScaleVol = 0; 886 } 887 888 /* Un-mute the headphone, set the full scale volume flag */ 889 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 890 CS42L42_HP_ANA_AMUTE_MASK | 891 CS42L42_HP_ANA_BMUTE_MASK | 892 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol); 893 894 /* Mark SCLK as present, turn off internal oscillator */ 895 snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH, 896 CS42L42_SCLK_PRESENT_MASK, 897 CS42L42_SCLK_PRESENT_MASK); 898 } 899 900 return 0; 901 } 902 903 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \ 904 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | \ 905 SNDRV_PCM_FMTBIT_S32_LE) 906 907 908 static const struct snd_soc_dai_ops cs42l42_ops = { 909 .hw_params = cs42l42_pcm_hw_params, 910 .set_fmt = cs42l42_set_dai_fmt, 911 .set_sysclk = cs42l42_set_sysclk, 912 .mute_stream = cs42l42_mute, 913 .no_capture_mute = 1, 914 }; 915 916 static struct snd_soc_dai_driver cs42l42_dai = { 917 .name = "cs42l42", 918 .playback = { 919 .stream_name = "Playback", 920 .channels_min = 1, 921 .channels_max = 2, 922 .rates = SNDRV_PCM_RATE_8000_192000, 923 .formats = CS42L42_FORMATS, 924 }, 925 .capture = { 926 .stream_name = "Capture", 927 .channels_min = 1, 928 .channels_max = 2, 929 .rates = SNDRV_PCM_RATE_8000_192000, 930 .formats = CS42L42_FORMATS, 931 }, 932 .ops = &cs42l42_ops, 933 }; 934 935 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) 936 { 937 unsigned int hs_det_status; 938 unsigned int int_status; 939 940 /* Mask the auto detect interrupt */ 941 regmap_update_bits(cs42l42->regmap, 942 CS42L42_CODEC_INT_MASK, 943 CS42L42_PDN_DONE_MASK | 944 CS42L42_HSDET_AUTO_DONE_MASK, 945 (1 << CS42L42_PDN_DONE_SHIFT) | 946 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 947 948 /* Set hs detect to automatic, disabled mode */ 949 regmap_update_bits(cs42l42->regmap, 950 CS42L42_HSDET_CTL2, 951 CS42L42_HSDET_CTRL_MASK | 952 CS42L42_HSDET_SET_MASK | 953 CS42L42_HSBIAS_REF_MASK | 954 CS42L42_HSDET_AUTO_TIME_MASK, 955 (2 << CS42L42_HSDET_CTRL_SHIFT) | 956 (2 << CS42L42_HSDET_SET_SHIFT) | 957 (0 << CS42L42_HSBIAS_REF_SHIFT) | 958 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 959 960 /* Read and save the hs detection result */ 961 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 962 963 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> 964 CS42L42_HSDET_TYPE_SHIFT; 965 966 /* Set up button detection */ 967 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || 968 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { 969 /* Set auto HS bias settings to default */ 970 regmap_update_bits(cs42l42->regmap, 971 CS42L42_HSBIAS_SC_AUTOCTL, 972 CS42L42_HSBIAS_SENSE_EN_MASK | 973 CS42L42_AUTO_HSBIAS_HIZ_MASK | 974 CS42L42_TIP_SENSE_EN_MASK | 975 CS42L42_HSBIAS_SENSE_TRIP_MASK, 976 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 977 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 978 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 979 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 980 981 /* Set up hs detect level sensitivity */ 982 regmap_update_bits(cs42l42->regmap, 983 CS42L42_MIC_DET_CTL1, 984 CS42L42_LATCH_TO_VP_MASK | 985 CS42L42_EVENT_STAT_SEL_MASK | 986 CS42L42_HS_DET_LEVEL_MASK, 987 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 988 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 989 (cs42l42->bias_thresholds[0] << 990 CS42L42_HS_DET_LEVEL_SHIFT)); 991 992 /* Set auto HS bias settings to default */ 993 regmap_update_bits(cs42l42->regmap, 994 CS42L42_HSBIAS_SC_AUTOCTL, 995 CS42L42_HSBIAS_SENSE_EN_MASK | 996 CS42L42_AUTO_HSBIAS_HIZ_MASK | 997 CS42L42_TIP_SENSE_EN_MASK | 998 CS42L42_HSBIAS_SENSE_TRIP_MASK, 999 (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1000 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1001 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1002 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1003 1004 /* Turn on level detect circuitry */ 1005 regmap_update_bits(cs42l42->regmap, 1006 CS42L42_MISC_DET_CTL, 1007 CS42L42_DETECT_MODE_MASK | 1008 CS42L42_HSBIAS_CTL_MASK | 1009 CS42L42_PDN_MIC_LVL_DET_MASK, 1010 (0 << CS42L42_DETECT_MODE_SHIFT) | 1011 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1012 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1013 1014 msleep(cs42l42->btn_det_init_dbnce); 1015 1016 /* Clear any button interrupts before unmasking them */ 1017 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1018 &int_status); 1019 1020 /* Unmask button detect interrupts */ 1021 regmap_update_bits(cs42l42->regmap, 1022 CS42L42_DET_INT2_MASK, 1023 CS42L42_M_DETECT_TF_MASK | 1024 CS42L42_M_DETECT_FT_MASK | 1025 CS42L42_M_HSBIAS_HIZ_MASK | 1026 CS42L42_M_SHORT_RLS_MASK | 1027 CS42L42_M_SHORT_DET_MASK, 1028 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1029 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1030 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1031 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1032 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1033 } else { 1034 /* Make sure button detect and HS bias circuits are off */ 1035 regmap_update_bits(cs42l42->regmap, 1036 CS42L42_MISC_DET_CTL, 1037 CS42L42_DETECT_MODE_MASK | 1038 CS42L42_HSBIAS_CTL_MASK | 1039 CS42L42_PDN_MIC_LVL_DET_MASK, 1040 (0 << CS42L42_DETECT_MODE_SHIFT) | 1041 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1042 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1043 } 1044 1045 regmap_update_bits(cs42l42->regmap, 1046 CS42L42_DAC_CTL2, 1047 CS42L42_HPOUT_PULLDOWN_MASK | 1048 CS42L42_HPOUT_LOAD_MASK | 1049 CS42L42_HPOUT_CLAMP_MASK | 1050 CS42L42_DAC_HPF_EN_MASK | 1051 CS42L42_DAC_MON_EN_MASK, 1052 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1053 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1054 (0 << CS42L42_HPOUT_CLAMP_SHIFT) | 1055 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1056 (0 << CS42L42_DAC_MON_EN_SHIFT)); 1057 1058 /* Unmask tip sense interrupts */ 1059 regmap_update_bits(cs42l42->regmap, 1060 CS42L42_TSRS_PLUG_INT_MASK, 1061 CS42L42_RS_PLUG_MASK | 1062 CS42L42_RS_UNPLUG_MASK | 1063 CS42L42_TS_PLUG_MASK | 1064 CS42L42_TS_UNPLUG_MASK, 1065 (1 << CS42L42_RS_PLUG_SHIFT) | 1066 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1067 (0 << CS42L42_TS_PLUG_SHIFT) | 1068 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1069 } 1070 1071 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) 1072 { 1073 /* Mask tip sense interrupts */ 1074 regmap_update_bits(cs42l42->regmap, 1075 CS42L42_TSRS_PLUG_INT_MASK, 1076 CS42L42_RS_PLUG_MASK | 1077 CS42L42_RS_UNPLUG_MASK | 1078 CS42L42_TS_PLUG_MASK | 1079 CS42L42_TS_UNPLUG_MASK, 1080 (1 << CS42L42_RS_PLUG_SHIFT) | 1081 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1082 (1 << CS42L42_TS_PLUG_SHIFT) | 1083 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1084 1085 /* Make sure button detect and HS bias circuits are off */ 1086 regmap_update_bits(cs42l42->regmap, 1087 CS42L42_MISC_DET_CTL, 1088 CS42L42_DETECT_MODE_MASK | 1089 CS42L42_HSBIAS_CTL_MASK | 1090 CS42L42_PDN_MIC_LVL_DET_MASK, 1091 (0 << CS42L42_DETECT_MODE_SHIFT) | 1092 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1093 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1094 1095 /* Set auto HS bias settings to default */ 1096 regmap_update_bits(cs42l42->regmap, 1097 CS42L42_HSBIAS_SC_AUTOCTL, 1098 CS42L42_HSBIAS_SENSE_EN_MASK | 1099 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1100 CS42L42_TIP_SENSE_EN_MASK | 1101 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1102 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1103 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1104 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1105 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1106 1107 /* Set hs detect to manual, disabled mode */ 1108 regmap_update_bits(cs42l42->regmap, 1109 CS42L42_HSDET_CTL2, 1110 CS42L42_HSDET_CTRL_MASK | 1111 CS42L42_HSDET_SET_MASK | 1112 CS42L42_HSBIAS_REF_MASK | 1113 CS42L42_HSDET_AUTO_TIME_MASK, 1114 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1115 (2 << CS42L42_HSDET_SET_SHIFT) | 1116 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1117 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1118 1119 regmap_update_bits(cs42l42->regmap, 1120 CS42L42_DAC_CTL2, 1121 CS42L42_HPOUT_PULLDOWN_MASK | 1122 CS42L42_HPOUT_LOAD_MASK | 1123 CS42L42_HPOUT_CLAMP_MASK | 1124 CS42L42_DAC_HPF_EN_MASK | 1125 CS42L42_DAC_MON_EN_MASK, 1126 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1127 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1128 (1 << CS42L42_HPOUT_CLAMP_SHIFT) | 1129 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1130 (1 << CS42L42_DAC_MON_EN_SHIFT)); 1131 1132 /* Power up HS bias to 2.7V */ 1133 regmap_update_bits(cs42l42->regmap, 1134 CS42L42_MISC_DET_CTL, 1135 CS42L42_DETECT_MODE_MASK | 1136 CS42L42_HSBIAS_CTL_MASK | 1137 CS42L42_PDN_MIC_LVL_DET_MASK, 1138 (0 << CS42L42_DETECT_MODE_SHIFT) | 1139 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1140 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1141 1142 /* Wait for HS bias to ramp up */ 1143 msleep(cs42l42->hs_bias_ramp_time); 1144 1145 /* Unmask auto detect interrupt */ 1146 regmap_update_bits(cs42l42->regmap, 1147 CS42L42_CODEC_INT_MASK, 1148 CS42L42_PDN_DONE_MASK | 1149 CS42L42_HSDET_AUTO_DONE_MASK, 1150 (1 << CS42L42_PDN_DONE_SHIFT) | 1151 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1152 1153 /* Set hs detect to automatic, enabled mode */ 1154 regmap_update_bits(cs42l42->regmap, 1155 CS42L42_HSDET_CTL2, 1156 CS42L42_HSDET_CTRL_MASK | 1157 CS42L42_HSDET_SET_MASK | 1158 CS42L42_HSBIAS_REF_MASK | 1159 CS42L42_HSDET_AUTO_TIME_MASK, 1160 (3 << CS42L42_HSDET_CTRL_SHIFT) | 1161 (2 << CS42L42_HSDET_SET_SHIFT) | 1162 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1163 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1164 } 1165 1166 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) 1167 { 1168 /* Mask button detect interrupts */ 1169 regmap_update_bits(cs42l42->regmap, 1170 CS42L42_DET_INT2_MASK, 1171 CS42L42_M_DETECT_TF_MASK | 1172 CS42L42_M_DETECT_FT_MASK | 1173 CS42L42_M_HSBIAS_HIZ_MASK | 1174 CS42L42_M_SHORT_RLS_MASK | 1175 CS42L42_M_SHORT_DET_MASK, 1176 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1177 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1178 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1179 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1180 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1181 1182 /* Ground HS bias */ 1183 regmap_update_bits(cs42l42->regmap, 1184 CS42L42_MISC_DET_CTL, 1185 CS42L42_DETECT_MODE_MASK | 1186 CS42L42_HSBIAS_CTL_MASK | 1187 CS42L42_PDN_MIC_LVL_DET_MASK, 1188 (0 << CS42L42_DETECT_MODE_SHIFT) | 1189 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1190 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1191 1192 /* Set auto HS bias settings to default */ 1193 regmap_update_bits(cs42l42->regmap, 1194 CS42L42_HSBIAS_SC_AUTOCTL, 1195 CS42L42_HSBIAS_SENSE_EN_MASK | 1196 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1197 CS42L42_TIP_SENSE_EN_MASK | 1198 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1199 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1200 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1201 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1202 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1203 1204 /* Set hs detect to manual, disabled mode */ 1205 regmap_update_bits(cs42l42->regmap, 1206 CS42L42_HSDET_CTL2, 1207 CS42L42_HSDET_CTRL_MASK | 1208 CS42L42_HSDET_SET_MASK | 1209 CS42L42_HSBIAS_REF_MASK | 1210 CS42L42_HSDET_AUTO_TIME_MASK, 1211 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1212 (2 << CS42L42_HSDET_SET_SHIFT) | 1213 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1214 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1215 } 1216 1217 static void cs42l42_handle_button_press(struct cs42l42_private *cs42l42) 1218 { 1219 int bias_level; 1220 unsigned int detect_status; 1221 1222 /* Mask button detect interrupts */ 1223 regmap_update_bits(cs42l42->regmap, 1224 CS42L42_DET_INT2_MASK, 1225 CS42L42_M_DETECT_TF_MASK | 1226 CS42L42_M_DETECT_FT_MASK | 1227 CS42L42_M_HSBIAS_HIZ_MASK | 1228 CS42L42_M_SHORT_RLS_MASK | 1229 CS42L42_M_SHORT_DET_MASK, 1230 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1231 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1232 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1233 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1234 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1235 1236 usleep_range(cs42l42->btn_det_event_dbnce * 1000, 1237 cs42l42->btn_det_event_dbnce * 2000); 1238 1239 /* Test all 4 level detect biases */ 1240 bias_level = 1; 1241 do { 1242 /* Adjust button detect level sensitivity */ 1243 regmap_update_bits(cs42l42->regmap, 1244 CS42L42_MIC_DET_CTL1, 1245 CS42L42_LATCH_TO_VP_MASK | 1246 CS42L42_EVENT_STAT_SEL_MASK | 1247 CS42L42_HS_DET_LEVEL_MASK, 1248 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1249 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1250 (cs42l42->bias_thresholds[bias_level] << 1251 CS42L42_HS_DET_LEVEL_SHIFT)); 1252 1253 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2, 1254 &detect_status); 1255 } while ((detect_status & CS42L42_HS_TRUE_MASK) && 1256 (++bias_level < CS42L42_NUM_BIASES)); 1257 1258 switch (bias_level) { 1259 case 1: /* Function C button press */ 1260 dev_dbg(cs42l42->component->dev, "Function C button press\n"); 1261 break; 1262 case 2: /* Function B button press */ 1263 dev_dbg(cs42l42->component->dev, "Function B button press\n"); 1264 break; 1265 case 3: /* Function D button press */ 1266 dev_dbg(cs42l42->component->dev, "Function D button press\n"); 1267 break; 1268 case 4: /* Function A button press */ 1269 dev_dbg(cs42l42->component->dev, "Function A button press\n"); 1270 break; 1271 } 1272 1273 /* Set button detect level sensitivity back to default */ 1274 regmap_update_bits(cs42l42->regmap, 1275 CS42L42_MIC_DET_CTL1, 1276 CS42L42_LATCH_TO_VP_MASK | 1277 CS42L42_EVENT_STAT_SEL_MASK | 1278 CS42L42_HS_DET_LEVEL_MASK, 1279 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1280 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1281 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); 1282 1283 /* Clear any button interrupts before unmasking them */ 1284 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1285 &detect_status); 1286 1287 /* Unmask button detect interrupts */ 1288 regmap_update_bits(cs42l42->regmap, 1289 CS42L42_DET_INT2_MASK, 1290 CS42L42_M_DETECT_TF_MASK | 1291 CS42L42_M_DETECT_FT_MASK | 1292 CS42L42_M_HSBIAS_HIZ_MASK | 1293 CS42L42_M_SHORT_RLS_MASK | 1294 CS42L42_M_SHORT_DET_MASK, 1295 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1296 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1297 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1298 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1299 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1300 } 1301 1302 struct cs42l42_irq_params { 1303 u16 status_addr; 1304 u16 mask_addr; 1305 u8 mask; 1306 }; 1307 1308 static const struct cs42l42_irq_params irq_params_table[] = { 1309 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, 1310 CS42L42_ADC_OVFL_VAL_MASK}, 1311 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, 1312 CS42L42_MIXER_VAL_MASK}, 1313 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, 1314 CS42L42_SRC_VAL_MASK}, 1315 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, 1316 CS42L42_ASP_RX_VAL_MASK}, 1317 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, 1318 CS42L42_ASP_TX_VAL_MASK}, 1319 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, 1320 CS42L42_CODEC_VAL_MASK}, 1321 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, 1322 CS42L42_DET_INT_VAL1_MASK}, 1323 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, 1324 CS42L42_DET_INT_VAL2_MASK}, 1325 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, 1326 CS42L42_SRCPL_VAL_MASK}, 1327 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, 1328 CS42L42_VPMON_VAL_MASK}, 1329 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, 1330 CS42L42_PLL_LOCK_VAL_MASK}, 1331 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, 1332 CS42L42_TSRS_PLUG_VAL_MASK} 1333 }; 1334 1335 static irqreturn_t cs42l42_irq_thread(int irq, void *data) 1336 { 1337 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; 1338 struct snd_soc_component *component = cs42l42->component; 1339 unsigned int stickies[12]; 1340 unsigned int masks[12]; 1341 unsigned int current_plug_status; 1342 unsigned int current_button_status; 1343 unsigned int i; 1344 1345 /* Read sticky registers to clear interurpt */ 1346 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 1347 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr, 1348 &(stickies[i])); 1349 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr, 1350 &(masks[i])); 1351 stickies[i] = stickies[i] & (~masks[i]) & 1352 irq_params_table[i].mask; 1353 } 1354 1355 /* Read tip sense status before handling type detect */ 1356 current_plug_status = (stickies[11] & 1357 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1358 CS42L42_TS_PLUG_SHIFT; 1359 1360 /* Read button sense status */ 1361 current_button_status = stickies[7] & 1362 (CS42L42_M_DETECT_TF_MASK | 1363 CS42L42_M_DETECT_FT_MASK | 1364 CS42L42_M_HSBIAS_HIZ_MASK); 1365 1366 /* Check auto-detect status */ 1367 if ((~masks[5]) & irq_params_table[5].mask) { 1368 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { 1369 cs42l42_process_hs_type_detect(cs42l42); 1370 dev_dbg(component->dev, 1371 "Auto detect done (%d)\n", 1372 cs42l42->hs_type); 1373 } 1374 } 1375 1376 /* Check tip sense status */ 1377 if ((~masks[11]) & irq_params_table[11].mask) { 1378 switch (current_plug_status) { 1379 case CS42L42_TS_PLUG: 1380 if (cs42l42->plug_state != CS42L42_TS_PLUG) { 1381 cs42l42->plug_state = CS42L42_TS_PLUG; 1382 cs42l42_init_hs_type_detect(cs42l42); 1383 } 1384 break; 1385 1386 case CS42L42_TS_UNPLUG: 1387 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { 1388 cs42l42->plug_state = CS42L42_TS_UNPLUG; 1389 cs42l42_cancel_hs_type_detect(cs42l42); 1390 dev_dbg(component->dev, 1391 "Unplug event\n"); 1392 } 1393 break; 1394 1395 default: 1396 if (cs42l42->plug_state != CS42L42_TS_TRANS) 1397 cs42l42->plug_state = CS42L42_TS_TRANS; 1398 } 1399 } 1400 1401 /* Check button detect status */ 1402 if ((~masks[7]) & irq_params_table[7].mask) { 1403 if (!(current_button_status & 1404 CS42L42_M_HSBIAS_HIZ_MASK)) { 1405 1406 if (current_button_status & 1407 CS42L42_M_DETECT_TF_MASK) { 1408 dev_dbg(component->dev, 1409 "Button released\n"); 1410 } else if (current_button_status & 1411 CS42L42_M_DETECT_FT_MASK) { 1412 cs42l42_handle_button_press(cs42l42); 1413 } 1414 } 1415 } 1416 1417 return IRQ_HANDLED; 1418 } 1419 1420 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) 1421 { 1422 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, 1423 CS42L42_ADC_OVFL_MASK, 1424 (1 << CS42L42_ADC_OVFL_SHIFT)); 1425 1426 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK, 1427 CS42L42_MIX_CHB_OVFL_MASK | 1428 CS42L42_MIX_CHA_OVFL_MASK | 1429 CS42L42_EQ_OVFL_MASK | 1430 CS42L42_EQ_BIQUAD_OVFL_MASK, 1431 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | 1432 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | 1433 (1 << CS42L42_EQ_OVFL_SHIFT) | 1434 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); 1435 1436 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK, 1437 CS42L42_SRC_ILK_MASK | 1438 CS42L42_SRC_OLK_MASK | 1439 CS42L42_SRC_IUNLK_MASK | 1440 CS42L42_SRC_OUNLK_MASK, 1441 (1 << CS42L42_SRC_ILK_SHIFT) | 1442 (1 << CS42L42_SRC_OLK_SHIFT) | 1443 (1 << CS42L42_SRC_IUNLK_SHIFT) | 1444 (1 << CS42L42_SRC_OUNLK_SHIFT)); 1445 1446 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, 1447 CS42L42_ASPRX_NOLRCK_MASK | 1448 CS42L42_ASPRX_EARLY_MASK | 1449 CS42L42_ASPRX_LATE_MASK | 1450 CS42L42_ASPRX_ERROR_MASK | 1451 CS42L42_ASPRX_OVLD_MASK, 1452 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | 1453 (1 << CS42L42_ASPRX_EARLY_SHIFT) | 1454 (1 << CS42L42_ASPRX_LATE_SHIFT) | 1455 (1 << CS42L42_ASPRX_ERROR_SHIFT) | 1456 (1 << CS42L42_ASPRX_OVLD_SHIFT)); 1457 1458 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, 1459 CS42L42_ASPTX_NOLRCK_MASK | 1460 CS42L42_ASPTX_EARLY_MASK | 1461 CS42L42_ASPTX_LATE_MASK | 1462 CS42L42_ASPTX_SMERROR_MASK, 1463 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | 1464 (1 << CS42L42_ASPTX_EARLY_SHIFT) | 1465 (1 << CS42L42_ASPTX_LATE_SHIFT) | 1466 (1 << CS42L42_ASPTX_SMERROR_SHIFT)); 1467 1468 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 1469 CS42L42_PDN_DONE_MASK | 1470 CS42L42_HSDET_AUTO_DONE_MASK, 1471 (1 << CS42L42_PDN_DONE_SHIFT) | 1472 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1473 1474 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK, 1475 CS42L42_SRCPL_ADC_LK_MASK | 1476 CS42L42_SRCPL_DAC_LK_MASK | 1477 CS42L42_SRCPL_ADC_UNLK_MASK | 1478 CS42L42_SRCPL_DAC_UNLK_MASK, 1479 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | 1480 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | 1481 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | 1482 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); 1483 1484 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK, 1485 CS42L42_TIP_SENSE_UNPLUG_MASK | 1486 CS42L42_TIP_SENSE_PLUG_MASK | 1487 CS42L42_HSBIAS_SENSE_MASK, 1488 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | 1489 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | 1490 (1 << CS42L42_HSBIAS_SENSE_SHIFT)); 1491 1492 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK, 1493 CS42L42_M_DETECT_TF_MASK | 1494 CS42L42_M_DETECT_FT_MASK | 1495 CS42L42_M_HSBIAS_HIZ_MASK | 1496 CS42L42_M_SHORT_RLS_MASK | 1497 CS42L42_M_SHORT_DET_MASK, 1498 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1499 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1500 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1501 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1502 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1503 1504 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK, 1505 CS42L42_VPMON_MASK, 1506 (1 << CS42L42_VPMON_SHIFT)); 1507 1508 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, 1509 CS42L42_PLL_LOCK_MASK, 1510 (1 << CS42L42_PLL_LOCK_SHIFT)); 1511 1512 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 1513 CS42L42_RS_PLUG_MASK | 1514 CS42L42_RS_UNPLUG_MASK | 1515 CS42L42_TS_PLUG_MASK | 1516 CS42L42_TS_UNPLUG_MASK, 1517 (1 << CS42L42_RS_PLUG_SHIFT) | 1518 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1519 (0 << CS42L42_TS_PLUG_SHIFT) | 1520 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1521 } 1522 1523 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) 1524 { 1525 unsigned int reg; 1526 1527 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1528 1529 /* Latch analog controls to VP power domain */ 1530 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1, 1531 CS42L42_LATCH_TO_VP_MASK | 1532 CS42L42_EVENT_STAT_SEL_MASK | 1533 CS42L42_HS_DET_LEVEL_MASK, 1534 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1535 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1536 (cs42l42->bias_thresholds[0] << 1537 CS42L42_HS_DET_LEVEL_SHIFT)); 1538 1539 /* Remove ground noise-suppression clamps */ 1540 regmap_update_bits(cs42l42->regmap, 1541 CS42L42_HS_CLAMP_DISABLE, 1542 CS42L42_HS_CLAMP_DISABLE_MASK, 1543 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); 1544 1545 /* Enable the tip sense circuit */ 1546 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL, 1547 CS42L42_TIP_SENSE_CTRL_MASK | 1548 CS42L42_TIP_SENSE_INV_MASK | 1549 CS42L42_TIP_SENSE_DEBOUNCE_MASK, 1550 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | 1551 (0 << CS42L42_TIP_SENSE_INV_SHIFT) | 1552 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); 1553 1554 /* Save the initial status of the tip sense */ 1555 regmap_read(cs42l42->regmap, 1556 CS42L42_TSRS_PLUG_STATUS, 1557 ®); 1558 cs42l42->plug_state = (((char) reg) & 1559 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1560 CS42L42_TS_PLUG_SHIFT; 1561 } 1562 1563 static const unsigned int threshold_defaults[] = { 1564 CS42L42_HS_DET_LEVEL_15, 1565 CS42L42_HS_DET_LEVEL_8, 1566 CS42L42_HS_DET_LEVEL_4, 1567 CS42L42_HS_DET_LEVEL_1 1568 }; 1569 1570 static int cs42l42_handle_device_data(struct i2c_client *i2c_client, 1571 struct cs42l42_private *cs42l42) 1572 { 1573 struct device_node *np = i2c_client->dev.of_node; 1574 unsigned int val; 1575 unsigned int thresholds[CS42L42_NUM_BIASES]; 1576 int ret; 1577 int i; 1578 1579 ret = of_property_read_u32(np, "cirrus,ts-inv", &val); 1580 1581 if (!ret) { 1582 switch (val) { 1583 case CS42L42_TS_INV_EN: 1584 case CS42L42_TS_INV_DIS: 1585 cs42l42->ts_inv = val; 1586 break; 1587 default: 1588 dev_err(&i2c_client->dev, 1589 "Wrong cirrus,ts-inv DT value %d\n", 1590 val); 1591 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1592 } 1593 } else { 1594 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1595 } 1596 1597 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1598 CS42L42_TS_INV_MASK, 1599 (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT)); 1600 1601 ret = of_property_read_u32(np, "cirrus,ts-dbnc-rise", &val); 1602 1603 if (!ret) { 1604 switch (val) { 1605 case CS42L42_TS_DBNCE_0: 1606 case CS42L42_TS_DBNCE_125: 1607 case CS42L42_TS_DBNCE_250: 1608 case CS42L42_TS_DBNCE_500: 1609 case CS42L42_TS_DBNCE_750: 1610 case CS42L42_TS_DBNCE_1000: 1611 case CS42L42_TS_DBNCE_1250: 1612 case CS42L42_TS_DBNCE_1500: 1613 cs42l42->ts_dbnc_rise = val; 1614 break; 1615 default: 1616 dev_err(&i2c_client->dev, 1617 "Wrong cirrus,ts-dbnc-rise DT value %d\n", 1618 val); 1619 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1620 } 1621 } else { 1622 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1623 } 1624 1625 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1626 CS42L42_TS_RISE_DBNCE_TIME_MASK, 1627 (cs42l42->ts_dbnc_rise << 1628 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); 1629 1630 ret = of_property_read_u32(np, "cirrus,ts-dbnc-fall", &val); 1631 1632 if (!ret) { 1633 switch (val) { 1634 case CS42L42_TS_DBNCE_0: 1635 case CS42L42_TS_DBNCE_125: 1636 case CS42L42_TS_DBNCE_250: 1637 case CS42L42_TS_DBNCE_500: 1638 case CS42L42_TS_DBNCE_750: 1639 case CS42L42_TS_DBNCE_1000: 1640 case CS42L42_TS_DBNCE_1250: 1641 case CS42L42_TS_DBNCE_1500: 1642 cs42l42->ts_dbnc_fall = val; 1643 break; 1644 default: 1645 dev_err(&i2c_client->dev, 1646 "Wrong cirrus,ts-dbnc-fall DT value %d\n", 1647 val); 1648 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1649 } 1650 } else { 1651 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1652 } 1653 1654 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1655 CS42L42_TS_FALL_DBNCE_TIME_MASK, 1656 (cs42l42->ts_dbnc_fall << 1657 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); 1658 1659 ret = of_property_read_u32(np, "cirrus,btn-det-init-dbnce", &val); 1660 1661 if (!ret) { 1662 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) 1663 cs42l42->btn_det_init_dbnce = val; 1664 else { 1665 dev_err(&i2c_client->dev, 1666 "Wrong cirrus,btn-det-init-dbnce DT value %d\n", 1667 val); 1668 cs42l42->btn_det_init_dbnce = 1669 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1670 } 1671 } else { 1672 cs42l42->btn_det_init_dbnce = 1673 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1674 } 1675 1676 ret = of_property_read_u32(np, "cirrus,btn-det-event-dbnce", &val); 1677 1678 if (!ret) { 1679 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) 1680 cs42l42->btn_det_event_dbnce = val; 1681 else { 1682 dev_err(&i2c_client->dev, 1683 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); 1684 cs42l42->btn_det_event_dbnce = 1685 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1686 } 1687 } else { 1688 cs42l42->btn_det_event_dbnce = 1689 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1690 } 1691 1692 ret = of_property_read_u32_array(np, "cirrus,bias-lvls", 1693 (u32 *)thresholds, CS42L42_NUM_BIASES); 1694 1695 if (!ret) { 1696 for (i = 0; i < CS42L42_NUM_BIASES; i++) { 1697 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) 1698 cs42l42->bias_thresholds[i] = thresholds[i]; 1699 else { 1700 dev_err(&i2c_client->dev, 1701 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i, 1702 thresholds[i]); 1703 cs42l42->bias_thresholds[i] = 1704 threshold_defaults[i]; 1705 } 1706 } 1707 } else { 1708 for (i = 0; i < CS42L42_NUM_BIASES; i++) 1709 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 1710 } 1711 1712 ret = of_property_read_u32(np, "cirrus,hs-bias-ramp-rate", &val); 1713 1714 if (!ret) { 1715 switch (val) { 1716 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: 1717 cs42l42->hs_bias_ramp_rate = val; 1718 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; 1719 break; 1720 case CS42L42_HSBIAS_RAMP_FAST: 1721 cs42l42->hs_bias_ramp_rate = val; 1722 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; 1723 break; 1724 case CS42L42_HSBIAS_RAMP_SLOW: 1725 cs42l42->hs_bias_ramp_rate = val; 1726 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1727 break; 1728 case CS42L42_HSBIAS_RAMP_SLOWEST: 1729 cs42l42->hs_bias_ramp_rate = val; 1730 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; 1731 break; 1732 default: 1733 dev_err(&i2c_client->dev, 1734 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n", 1735 val); 1736 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 1737 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1738 } 1739 } else { 1740 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 1741 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1742 } 1743 1744 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL, 1745 CS42L42_HSBIAS_RAMP_MASK, 1746 (cs42l42->hs_bias_ramp_rate << 1747 CS42L42_HSBIAS_RAMP_SHIFT)); 1748 1749 return 0; 1750 } 1751 1752 static int cs42l42_i2c_probe(struct i2c_client *i2c_client, 1753 const struct i2c_device_id *id) 1754 { 1755 struct cs42l42_private *cs42l42; 1756 int ret, i; 1757 unsigned int devid = 0; 1758 unsigned int reg; 1759 1760 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private), 1761 GFP_KERNEL); 1762 if (!cs42l42) 1763 return -ENOMEM; 1764 1765 i2c_set_clientdata(i2c_client, cs42l42); 1766 1767 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap); 1768 if (IS_ERR(cs42l42->regmap)) { 1769 ret = PTR_ERR(cs42l42->regmap); 1770 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 1771 return ret; 1772 } 1773 1774 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) 1775 cs42l42->supplies[i].supply = cs42l42_supply_names[i]; 1776 1777 ret = devm_regulator_bulk_get(&i2c_client->dev, 1778 ARRAY_SIZE(cs42l42->supplies), 1779 cs42l42->supplies); 1780 if (ret != 0) { 1781 dev_err(&i2c_client->dev, 1782 "Failed to request supplies: %d\n", ret); 1783 return ret; 1784 } 1785 1786 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 1787 cs42l42->supplies); 1788 if (ret != 0) { 1789 dev_err(&i2c_client->dev, 1790 "Failed to enable supplies: %d\n", ret); 1791 return ret; 1792 } 1793 1794 /* Reset the Device */ 1795 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, 1796 "reset", GPIOD_OUT_LOW); 1797 if (IS_ERR(cs42l42->reset_gpio)) 1798 return PTR_ERR(cs42l42->reset_gpio); 1799 1800 if (cs42l42->reset_gpio) { 1801 dev_dbg(&i2c_client->dev, "Found reset GPIO\n"); 1802 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 1803 } 1804 mdelay(3); 1805 1806 /* Request IRQ */ 1807 ret = devm_request_threaded_irq(&i2c_client->dev, 1808 i2c_client->irq, 1809 NULL, cs42l42_irq_thread, 1810 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 1811 "cs42l42", cs42l42); 1812 1813 if (ret != 0) 1814 dev_err(&i2c_client->dev, 1815 "Failed to request IRQ: %d\n", ret); 1816 1817 /* initialize codec */ 1818 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_AB, ®); 1819 devid = (reg & 0xFF) << 12; 1820 1821 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_CD, ®); 1822 devid |= (reg & 0xFF) << 4; 1823 1824 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_E, ®); 1825 devid |= (reg & 0xF0) >> 4; 1826 1827 if (devid != CS42L42_CHIP_ID) { 1828 ret = -ENODEV; 1829 dev_err(&i2c_client->dev, 1830 "CS42L42 Device ID (%X). Expected %X\n", 1831 devid, CS42L42_CHIP_ID); 1832 return ret; 1833 } 1834 1835 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); 1836 if (ret < 0) { 1837 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 1838 return ret; 1839 } 1840 1841 dev_info(&i2c_client->dev, 1842 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF); 1843 1844 /* Power up the codec */ 1845 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1, 1846 CS42L42_ASP_DAO_PDN_MASK | 1847 CS42L42_ASP_DAI_PDN_MASK | 1848 CS42L42_MIXER_PDN_MASK | 1849 CS42L42_EQ_PDN_MASK | 1850 CS42L42_HP_PDN_MASK | 1851 CS42L42_ADC_PDN_MASK | 1852 CS42L42_PDN_ALL_MASK, 1853 (1 << CS42L42_ASP_DAO_PDN_SHIFT) | 1854 (1 << CS42L42_ASP_DAI_PDN_SHIFT) | 1855 (1 << CS42L42_MIXER_PDN_SHIFT) | 1856 (1 << CS42L42_EQ_PDN_SHIFT) | 1857 (1 << CS42L42_HP_PDN_SHIFT) | 1858 (1 << CS42L42_ADC_PDN_SHIFT) | 1859 (0 << CS42L42_PDN_ALL_SHIFT)); 1860 1861 if (i2c_client->dev.of_node) { 1862 ret = cs42l42_handle_device_data(i2c_client, cs42l42); 1863 if (ret != 0) 1864 return ret; 1865 } 1866 1867 /* Setup headset detection */ 1868 cs42l42_setup_hs_type_detect(cs42l42); 1869 1870 /* Mask/Unmask Interrupts */ 1871 cs42l42_set_interrupt_masks(cs42l42); 1872 1873 /* Register codec for machine driver */ 1874 ret = devm_snd_soc_register_component(&i2c_client->dev, 1875 &soc_component_dev_cs42l42, &cs42l42_dai, 1); 1876 if (ret < 0) 1877 goto err_disable; 1878 return 0; 1879 1880 err_disable: 1881 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 1882 cs42l42->supplies); 1883 return ret; 1884 } 1885 1886 static int cs42l42_i2c_remove(struct i2c_client *i2c_client) 1887 { 1888 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client); 1889 1890 /* Hold down reset */ 1891 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 1892 1893 return 0; 1894 } 1895 1896 #ifdef CONFIG_PM 1897 static int cs42l42_runtime_suspend(struct device *dev) 1898 { 1899 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 1900 1901 regcache_cache_only(cs42l42->regmap, true); 1902 regcache_mark_dirty(cs42l42->regmap); 1903 1904 /* Hold down reset */ 1905 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 1906 1907 /* remove power */ 1908 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 1909 cs42l42->supplies); 1910 1911 return 0; 1912 } 1913 1914 static int cs42l42_runtime_resume(struct device *dev) 1915 { 1916 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 1917 int ret; 1918 1919 /* Enable power */ 1920 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 1921 cs42l42->supplies); 1922 if (ret != 0) { 1923 dev_err(dev, "Failed to enable supplies: %d\n", 1924 ret); 1925 return ret; 1926 } 1927 1928 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 1929 1930 regcache_cache_only(cs42l42->regmap, false); 1931 regcache_sync(cs42l42->regmap); 1932 1933 return 0; 1934 } 1935 #endif 1936 1937 static const struct dev_pm_ops cs42l42_runtime_pm = { 1938 SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume, 1939 NULL) 1940 }; 1941 1942 static const struct of_device_id cs42l42_of_match[] = { 1943 { .compatible = "cirrus,cs42l42", }, 1944 {}, 1945 }; 1946 MODULE_DEVICE_TABLE(of, cs42l42_of_match); 1947 1948 1949 static const struct i2c_device_id cs42l42_id[] = { 1950 {"cs42l42", 0}, 1951 {} 1952 }; 1953 1954 MODULE_DEVICE_TABLE(i2c, cs42l42_id); 1955 1956 static struct i2c_driver cs42l42_i2c_driver = { 1957 .driver = { 1958 .name = "cs42l42", 1959 .pm = &cs42l42_runtime_pm, 1960 .of_match_table = cs42l42_of_match, 1961 }, 1962 .id_table = cs42l42_id, 1963 .probe = cs42l42_i2c_probe, 1964 .remove = cs42l42_i2c_remove, 1965 }; 1966 1967 module_i2c_driver(cs42l42_i2c_driver); 1968 1969 MODULE_DESCRIPTION("ASoC CS42L42 driver"); 1970 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 1971 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 1972 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>"); 1973 MODULE_LICENSE("GPL"); 1974