1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 */ 7 8 #define pr_fmt(fmt) "CPU features: " fmt 9 10 #include <linux/bsearch.h> 11 #include <linux/cpumask.h> 12 #include <linux/crash_dump.h> 13 #include <linux/sort.h> 14 #include <linux/stop_machine.h> 15 #include <linux/types.h> 16 #include <linux/mm.h> 17 #include <linux/cpu.h> 18 #include <asm/cpu.h> 19 #include <asm/cpufeature.h> 20 #include <asm/cpu_ops.h> 21 #include <asm/fpsimd.h> 22 #include <asm/mmu_context.h> 23 #include <asm/processor.h> 24 #include <asm/sysreg.h> 25 #include <asm/traps.h> 26 #include <asm/virt.h> 27 28 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 29 static unsigned long elf_hwcap __read_mostly; 30 31 #ifdef CONFIG_COMPAT 32 #define COMPAT_ELF_HWCAP_DEFAULT \ 33 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 34 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 35 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 36 COMPAT_HWCAP_LPAE) 37 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 38 unsigned int compat_elf_hwcap2 __read_mostly; 39 #endif 40 41 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 42 EXPORT_SYMBOL(cpu_hwcaps); 43 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 44 45 /* Need also bit for ARM64_CB_PATCH */ 46 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 47 48 bool arm64_use_ng_mappings = false; 49 EXPORT_SYMBOL(arm64_use_ng_mappings); 50 51 /* 52 * Flag to indicate if we have computed the system wide 53 * capabilities based on the boot time active CPUs. This 54 * will be used to determine if a new booting CPU should 55 * go through the verification process to make sure that it 56 * supports the system capabilities, without using a hotplug 57 * notifier. This is also used to decide if we could use 58 * the fast path for checking constant CPU caps. 59 */ 60 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 61 EXPORT_SYMBOL(arm64_const_caps_ready); 62 static inline void finalize_system_capabilities(void) 63 { 64 static_branch_enable(&arm64_const_caps_ready); 65 } 66 67 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p) 68 { 69 /* file-wide pr_fmt adds "CPU features: " prefix */ 70 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 71 return 0; 72 } 73 74 static struct notifier_block cpu_hwcaps_notifier = { 75 .notifier_call = dump_cpu_hwcaps 76 }; 77 78 static int __init register_cpu_hwcaps_dumper(void) 79 { 80 atomic_notifier_chain_register(&panic_notifier_list, 81 &cpu_hwcaps_notifier); 82 return 0; 83 } 84 __initcall(register_cpu_hwcaps_dumper); 85 86 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 87 EXPORT_SYMBOL(cpu_hwcap_keys); 88 89 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 90 { \ 91 .sign = SIGNED, \ 92 .visible = VISIBLE, \ 93 .strict = STRICT, \ 94 .type = TYPE, \ 95 .shift = SHIFT, \ 96 .width = WIDTH, \ 97 .safe_val = SAFE_VAL, \ 98 } 99 100 /* Define a feature with unsigned values */ 101 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 102 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 103 104 /* Define a feature with a signed value */ 105 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 106 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 107 108 #define ARM64_FTR_END \ 109 { \ 110 .width = 0, \ 111 } 112 113 /* meta feature for alternatives */ 114 static bool __maybe_unused 115 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused); 116 117 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 118 119 static bool __system_matches_cap(unsigned int n); 120 121 /* 122 * NOTE: Any changes to the visibility of features should be kept in 123 * sync with the documentation of the CPU feature register ABI. 124 */ 125 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 126 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), 127 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 128 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 134 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 135 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 136 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 137 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 138 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 139 ARM64_FTR_END, 140 }; 141 142 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 143 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), 144 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), 145 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), 146 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), 147 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 148 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), 149 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 150 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 151 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 152 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 153 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 154 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 155 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 156 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 157 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0), 158 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 159 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0), 160 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 161 ARM64_FTR_END, 162 }; 163 164 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 165 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 166 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 167 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 169 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 170 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 171 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 172 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 173 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 174 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 175 /* Linux doesn't care about the EL3 */ 176 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 177 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 178 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 179 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 180 ARM64_FTR_END, 181 }; 182 183 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 184 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 185 ARM64_FTR_END, 186 }; 187 188 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 189 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 190 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 192 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 194 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 196 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 198 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 199 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 200 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), 201 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 202 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 204 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 206 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 207 ARM64_FTR_END, 208 }; 209 210 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 211 /* 212 * We already refuse to boot CPUs that don't support our configured 213 * page size, so we can only detect mismatches for a page size other 214 * than the one we're currently using. Unfortunately, SoCs like this 215 * exist in the wild so, even though we don't like it, we'll have to go 216 * along with it and treat them as non-strict. 217 */ 218 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 219 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 221 222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 223 /* Linux shouldn't care about secure memory */ 224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 227 /* 228 * Differing PARange is fine as long as all peripherals and memory are mapped 229 * within the minimum PARange of all CPUs 230 */ 231 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 232 ARM64_FTR_END, 233 }; 234 235 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 242 ARM64_FTR_END, 243 }; 244 245 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 254 ARM64_FTR_END, 255 }; 256 257 static const struct arm64_ftr_bits ftr_ctr[] = { 258 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 260 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 261 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 263 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 264 /* 265 * Linux can handle differing I-cache policies. Userspace JITs will 266 * make use of *minLine. 267 * If we have differing I-cache policies, report it as the weakest - VIPT. 268 */ 269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 270 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 271 ARM64_FTR_END, 272 }; 273 274 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 275 .name = "SYS_CTR_EL0", 276 .ftr_bits = ftr_ctr 277 }; 278 279 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 280 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */ 281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */ 282 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */ 283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */ 284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */ 285 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */ 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */ 287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */ 288 ARM64_FTR_END, 289 }; 290 291 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0), 293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 297 /* 298 * We can instantiate multiple PMU instances with different levels 299 * of support. 300 */ 301 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 304 ARM64_FTR_END, 305 }; 306 307 static const struct arm64_ftr_bits ftr_mvfr2[] = { 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */ 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */ 310 ARM64_FTR_END, 311 }; 312 313 static const struct arm64_ftr_bits ftr_dczid[] = { 314 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */ 315 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */ 316 ARM64_FTR_END, 317 }; 318 319 320 static const struct arm64_ftr_bits ftr_id_isar5[] = { 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 327 ARM64_FTR_END, 328 }; 329 330 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */ 332 ARM64_FTR_END, 333 }; 334 335 static const struct arm64_ftr_bits ftr_id_isar6[] = { 336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 339 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 340 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 343 ARM64_FTR_END, 344 }; 345 346 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */ 348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */ 349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */ 350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */ 351 ARM64_FTR_END, 352 }; 353 354 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 356 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */ 357 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 359 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 360 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 361 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 363 ARM64_FTR_END, 364 }; 365 366 static const struct arm64_ftr_bits ftr_zcr[] = { 367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 368 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 369 ARM64_FTR_END, 370 }; 371 372 /* 373 * Common ftr bits for a 32bit register with all hidden, strict 374 * attributes, with 4bit feature fields and a default safe value of 375 * 0. Covers the following 32bit registers: 376 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 377 */ 378 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 382 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 383 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 384 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 385 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 387 ARM64_FTR_END, 388 }; 389 390 /* Table for a single 32bit feature value */ 391 static const struct arm64_ftr_bits ftr_single32[] = { 392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 393 ARM64_FTR_END, 394 }; 395 396 static const struct arm64_ftr_bits ftr_raz[] = { 397 ARM64_FTR_END, 398 }; 399 400 #define ARM64_FTR_REG(id, table) { \ 401 .sys_id = id, \ 402 .reg = &(struct arm64_ftr_reg){ \ 403 .name = #id, \ 404 .ftr_bits = &((table)[0]), \ 405 }} 406 407 static const struct __ftr_reg_entry { 408 u32 sys_id; 409 struct arm64_ftr_reg *reg; 410 } arm64_ftr_regs[] = { 411 412 /* Op1 = 0, CRn = 0, CRm = 1 */ 413 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 414 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits), 415 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 416 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 417 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 418 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 419 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 420 421 /* Op1 = 0, CRn = 0, CRm = 2 */ 422 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits), 423 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 424 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 425 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 426 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits), 427 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 428 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 429 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 430 431 /* Op1 = 0, CRn = 0, CRm = 3 */ 432 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 433 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 434 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 435 436 /* Op1 = 0, CRn = 0, CRm = 4 */ 437 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 438 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1), 439 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 440 441 /* Op1 = 0, CRn = 0, CRm = 5 */ 442 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 443 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 444 445 /* Op1 = 0, CRn = 0, CRm = 6 */ 446 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 447 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), 448 449 /* Op1 = 0, CRn = 0, CRm = 7 */ 450 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 451 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), 452 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 453 454 /* Op1 = 0, CRn = 1, CRm = 2 */ 455 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 456 457 /* Op1 = 3, CRn = 0, CRm = 0 */ 458 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 459 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 460 461 /* Op1 = 3, CRn = 14, CRm = 0 */ 462 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 463 }; 464 465 static int search_cmp_ftr_reg(const void *id, const void *regp) 466 { 467 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 468 } 469 470 /* 471 * get_arm64_ftr_reg - Lookup a feature register entry using its 472 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the 473 * ascending order of sys_id , we use binary search to find a matching 474 * entry. 475 * 476 * returns - Upon success, matching ftr_reg entry for id. 477 * - NULL on failure. It is upto the caller to decide 478 * the impact of a failure. 479 */ 480 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 481 { 482 const struct __ftr_reg_entry *ret; 483 484 ret = bsearch((const void *)(unsigned long)sys_id, 485 arm64_ftr_regs, 486 ARRAY_SIZE(arm64_ftr_regs), 487 sizeof(arm64_ftr_regs[0]), 488 search_cmp_ftr_reg); 489 if (ret) 490 return ret->reg; 491 return NULL; 492 } 493 494 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 495 s64 ftr_val) 496 { 497 u64 mask = arm64_ftr_mask(ftrp); 498 499 reg &= ~mask; 500 reg |= (ftr_val << ftrp->shift) & mask; 501 return reg; 502 } 503 504 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 505 s64 cur) 506 { 507 s64 ret = 0; 508 509 switch (ftrp->type) { 510 case FTR_EXACT: 511 ret = ftrp->safe_val; 512 break; 513 case FTR_LOWER_SAFE: 514 ret = new < cur ? new : cur; 515 break; 516 case FTR_HIGHER_OR_ZERO_SAFE: 517 if (!cur || !new) 518 break; 519 /* Fallthrough */ 520 case FTR_HIGHER_SAFE: 521 ret = new > cur ? new : cur; 522 break; 523 default: 524 BUG(); 525 } 526 527 return ret; 528 } 529 530 static void __init sort_ftr_regs(void) 531 { 532 int i; 533 534 /* Check that the array is sorted so that we can do the binary search */ 535 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++) 536 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 537 } 538 539 /* 540 * Initialise the CPU feature register from Boot CPU values. 541 * Also initiliases the strict_mask for the register. 542 * Any bits that are not covered by an arm64_ftr_bits entry are considered 543 * RES0 for the system-wide value, and must strictly match. 544 */ 545 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 546 { 547 u64 val = 0; 548 u64 strict_mask = ~0x0ULL; 549 u64 user_mask = 0; 550 u64 valid_mask = 0; 551 552 const struct arm64_ftr_bits *ftrp; 553 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 554 555 BUG_ON(!reg); 556 557 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 558 u64 ftr_mask = arm64_ftr_mask(ftrp); 559 s64 ftr_new = arm64_ftr_value(ftrp, new); 560 561 val = arm64_ftr_set_value(ftrp, val, ftr_new); 562 563 valid_mask |= ftr_mask; 564 if (!ftrp->strict) 565 strict_mask &= ~ftr_mask; 566 if (ftrp->visible) 567 user_mask |= ftr_mask; 568 else 569 reg->user_val = arm64_ftr_set_value(ftrp, 570 reg->user_val, 571 ftrp->safe_val); 572 } 573 574 val &= valid_mask; 575 576 reg->sys_val = val; 577 reg->strict_mask = strict_mask; 578 reg->user_mask = user_mask; 579 } 580 581 extern const struct arm64_cpu_capabilities arm64_errata[]; 582 static const struct arm64_cpu_capabilities arm64_features[]; 583 584 static void __init 585 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 586 { 587 for (; caps->matches; caps++) { 588 if (WARN(caps->capability >= ARM64_NCAPS, 589 "Invalid capability %d\n", caps->capability)) 590 continue; 591 if (WARN(cpu_hwcaps_ptrs[caps->capability], 592 "Duplicate entry for capability %d\n", 593 caps->capability)) 594 continue; 595 cpu_hwcaps_ptrs[caps->capability] = caps; 596 } 597 } 598 599 static void __init init_cpu_hwcaps_indirect_list(void) 600 { 601 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 602 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 603 } 604 605 static void __init setup_boot_cpu_capabilities(void); 606 607 void __init init_cpu_features(struct cpuinfo_arm64 *info) 608 { 609 /* Before we start using the tables, make sure it is sorted */ 610 sort_ftr_regs(); 611 612 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 613 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 614 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 615 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 616 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 617 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 618 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 619 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 620 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 621 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 622 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 623 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 624 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 625 626 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 627 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 628 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 629 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 630 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 631 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 632 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 633 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 634 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 635 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 636 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 637 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 638 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 639 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 640 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 641 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 642 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 643 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 644 } 645 646 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 647 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 648 sve_init_vq_map(); 649 } 650 651 /* 652 * Initialize the indirect array of CPU hwcaps capabilities pointers 653 * before we handle the boot CPU below. 654 */ 655 init_cpu_hwcaps_indirect_list(); 656 657 /* 658 * Detect and enable early CPU capabilities based on the boot CPU, 659 * after we have initialised the CPU feature infrastructure. 660 */ 661 setup_boot_cpu_capabilities(); 662 } 663 664 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 665 { 666 const struct arm64_ftr_bits *ftrp; 667 668 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 669 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 670 s64 ftr_new = arm64_ftr_value(ftrp, new); 671 672 if (ftr_cur == ftr_new) 673 continue; 674 /* Find a safe value */ 675 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 676 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 677 } 678 679 } 680 681 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 682 { 683 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 684 685 BUG_ON(!regp); 686 update_cpu_ftr_reg(regp, val); 687 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 688 return 0; 689 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 690 regp->name, boot, cpu, val); 691 return 1; 692 } 693 694 /* 695 * Update system wide CPU feature registers with the values from a 696 * non-boot CPU. Also performs SANITY checks to make sure that there 697 * aren't any insane variations from that of the boot CPU. 698 */ 699 void update_cpu_features(int cpu, 700 struct cpuinfo_arm64 *info, 701 struct cpuinfo_arm64 *boot) 702 { 703 int taint = 0; 704 705 /* 706 * The kernel can handle differing I-cache policies, but otherwise 707 * caches should look identical. Userspace JITs will make use of 708 * *minLine. 709 */ 710 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 711 info->reg_ctr, boot->reg_ctr); 712 713 /* 714 * Userspace may perform DC ZVA instructions. Mismatched block sizes 715 * could result in too much or too little memory being zeroed if a 716 * process is preempted and migrated between CPUs. 717 */ 718 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 719 info->reg_dczid, boot->reg_dczid); 720 721 /* If different, timekeeping will be broken (especially with KVM) */ 722 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 723 info->reg_cntfrq, boot->reg_cntfrq); 724 725 /* 726 * The kernel uses self-hosted debug features and expects CPUs to 727 * support identical debug features. We presently need CTX_CMPs, WRPs, 728 * and BRPs to be identical. 729 * ID_AA64DFR1 is currently RES0. 730 */ 731 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 732 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 733 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 734 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 735 /* 736 * Even in big.LITTLE, processors should be identical instruction-set 737 * wise. 738 */ 739 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 740 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 741 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 742 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 743 744 /* 745 * Differing PARange support is fine as long as all peripherals and 746 * memory are mapped within the minimum PARange of all CPUs. 747 * Linux should not care about secure memory. 748 */ 749 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 750 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 751 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 752 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 753 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 754 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 755 756 /* 757 * EL3 is not our concern. 758 */ 759 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 760 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 761 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 762 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 763 764 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 765 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 766 767 /* 768 * If we have AArch32, we care about 32-bit features for compat. 769 * If the system doesn't support AArch32, don't update them. 770 */ 771 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 772 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 773 774 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 775 info->reg_id_dfr0, boot->reg_id_dfr0); 776 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 777 info->reg_id_isar0, boot->reg_id_isar0); 778 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 779 info->reg_id_isar1, boot->reg_id_isar1); 780 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 781 info->reg_id_isar2, boot->reg_id_isar2); 782 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 783 info->reg_id_isar3, boot->reg_id_isar3); 784 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 785 info->reg_id_isar4, boot->reg_id_isar4); 786 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 787 info->reg_id_isar5, boot->reg_id_isar5); 788 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 789 info->reg_id_isar6, boot->reg_id_isar6); 790 791 /* 792 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 793 * ACTLR formats could differ across CPUs and therefore would have to 794 * be trapped for virtualization anyway. 795 */ 796 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 797 info->reg_id_mmfr0, boot->reg_id_mmfr0); 798 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 799 info->reg_id_mmfr1, boot->reg_id_mmfr1); 800 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 801 info->reg_id_mmfr2, boot->reg_id_mmfr2); 802 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 803 info->reg_id_mmfr3, boot->reg_id_mmfr3); 804 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 805 info->reg_id_pfr0, boot->reg_id_pfr0); 806 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 807 info->reg_id_pfr1, boot->reg_id_pfr1); 808 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 809 info->reg_mvfr0, boot->reg_mvfr0); 810 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 811 info->reg_mvfr1, boot->reg_mvfr1); 812 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 813 info->reg_mvfr2, boot->reg_mvfr2); 814 } 815 816 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 817 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 818 info->reg_zcr, boot->reg_zcr); 819 820 /* Probe vector lengths, unless we already gave up on SVE */ 821 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 822 !system_capabilities_finalized()) 823 sve_update_vq_map(); 824 } 825 826 /* 827 * Mismatched CPU features are a recipe for disaster. Don't even 828 * pretend to support them. 829 */ 830 if (taint) { 831 pr_warn_once("Unsupported CPU feature variation detected.\n"); 832 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 833 } 834 } 835 836 u64 read_sanitised_ftr_reg(u32 id) 837 { 838 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 839 840 /* We shouldn't get a request for an unsupported register */ 841 BUG_ON(!regp); 842 return regp->sys_val; 843 } 844 845 #define read_sysreg_case(r) \ 846 case r: return read_sysreg_s(r) 847 848 /* 849 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 850 * Read the system register on the current CPU 851 */ 852 static u64 __read_sysreg_by_encoding(u32 sys_id) 853 { 854 switch (sys_id) { 855 read_sysreg_case(SYS_ID_PFR0_EL1); 856 read_sysreg_case(SYS_ID_PFR1_EL1); 857 read_sysreg_case(SYS_ID_DFR0_EL1); 858 read_sysreg_case(SYS_ID_MMFR0_EL1); 859 read_sysreg_case(SYS_ID_MMFR1_EL1); 860 read_sysreg_case(SYS_ID_MMFR2_EL1); 861 read_sysreg_case(SYS_ID_MMFR3_EL1); 862 read_sysreg_case(SYS_ID_ISAR0_EL1); 863 read_sysreg_case(SYS_ID_ISAR1_EL1); 864 read_sysreg_case(SYS_ID_ISAR2_EL1); 865 read_sysreg_case(SYS_ID_ISAR3_EL1); 866 read_sysreg_case(SYS_ID_ISAR4_EL1); 867 read_sysreg_case(SYS_ID_ISAR5_EL1); 868 read_sysreg_case(SYS_ID_ISAR6_EL1); 869 read_sysreg_case(SYS_MVFR0_EL1); 870 read_sysreg_case(SYS_MVFR1_EL1); 871 read_sysreg_case(SYS_MVFR2_EL1); 872 873 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 874 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 875 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 876 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 877 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 878 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 879 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 880 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 881 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 882 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 883 884 read_sysreg_case(SYS_CNTFRQ_EL0); 885 read_sysreg_case(SYS_CTR_EL0); 886 read_sysreg_case(SYS_DCZID_EL0); 887 888 default: 889 BUG(); 890 return 0; 891 } 892 } 893 894 #include <linux/irqchip/arm-gic-v3.h> 895 896 static bool 897 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 898 { 899 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 900 901 return val >= entry->min_field_value; 902 } 903 904 static bool 905 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 906 { 907 u64 val; 908 909 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 910 if (scope == SCOPE_SYSTEM) 911 val = read_sanitised_ftr_reg(entry->sys_reg); 912 else 913 val = __read_sysreg_by_encoding(entry->sys_reg); 914 915 return feature_matches(val, entry); 916 } 917 918 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 919 { 920 bool has_sre; 921 922 if (!has_cpuid_feature(entry, scope)) 923 return false; 924 925 has_sre = gic_enable_sre(); 926 if (!has_sre) 927 pr_warn_once("%s present but disabled by higher exception level\n", 928 entry->desc); 929 930 return has_sre; 931 } 932 933 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 934 { 935 u32 midr = read_cpuid_id(); 936 937 /* Cavium ThunderX pass 1.x and 2.x */ 938 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 939 MIDR_CPU_VAR_REV(0, 0), 940 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 941 } 942 943 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 944 { 945 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 946 947 return cpuid_feature_extract_signed_field(pfr0, 948 ID_AA64PFR0_FP_SHIFT) < 0; 949 } 950 951 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 952 int scope) 953 { 954 u64 ctr; 955 956 if (scope == SCOPE_SYSTEM) 957 ctr = arm64_ftr_reg_ctrel0.sys_val; 958 else 959 ctr = read_cpuid_effective_cachetype(); 960 961 return ctr & BIT(CTR_IDC_SHIFT); 962 } 963 964 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 965 { 966 /* 967 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 968 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 969 * to the CTR_EL0 on this CPU and emulate it with the real/safe 970 * value. 971 */ 972 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 973 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 974 } 975 976 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 977 int scope) 978 { 979 u64 ctr; 980 981 if (scope == SCOPE_SYSTEM) 982 ctr = arm64_ftr_reg_ctrel0.sys_val; 983 else 984 ctr = read_cpuid_cachetype(); 985 986 return ctr & BIT(CTR_DIC_SHIFT); 987 } 988 989 static bool __maybe_unused 990 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 991 { 992 /* 993 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 994 * may share TLB entries with a CPU stuck in the crashed 995 * kernel. 996 */ 997 if (is_kdump_kernel()) 998 return false; 999 1000 return has_cpuid_feature(entry, scope); 1001 } 1002 1003 /* 1004 * This check is triggered during the early boot before the cpufeature 1005 * is initialised. Checking the status on the local CPU allows the boot 1006 * CPU to detect the need for non-global mappings and thus avoiding a 1007 * pagetable re-write after all the CPUs are booted. This check will be 1008 * anyway run on individual CPUs, allowing us to get the consistent 1009 * state once the SMP CPUs are up and thus make the switch to non-global 1010 * mappings if required. 1011 */ 1012 bool kaslr_requires_kpti(void) 1013 { 1014 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1015 return false; 1016 1017 /* 1018 * E0PD does a similar job to KPTI so can be used instead 1019 * where available. 1020 */ 1021 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1022 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1023 if (cpuid_feature_extract_unsigned_field(mmfr2, 1024 ID_AA64MMFR2_E0PD_SHIFT)) 1025 return false; 1026 } 1027 1028 /* 1029 * Systems affected by Cavium erratum 24756 are incompatible 1030 * with KPTI. 1031 */ 1032 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1033 extern const struct midr_range cavium_erratum_27456_cpus[]; 1034 1035 if (is_midr_in_range_list(read_cpuid_id(), 1036 cavium_erratum_27456_cpus)) 1037 return false; 1038 } 1039 1040 return kaslr_offset() > 0; 1041 } 1042 1043 static bool __meltdown_safe = true; 1044 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1045 1046 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1047 int scope) 1048 { 1049 /* List of CPUs that are not vulnerable and don't need KPTI */ 1050 static const struct midr_range kpti_safe_list[] = { 1051 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1052 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1053 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1054 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1055 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1056 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1057 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1058 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1059 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1060 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1061 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1062 { /* sentinel */ } 1063 }; 1064 char const *str = "kpti command line option"; 1065 bool meltdown_safe; 1066 1067 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1068 1069 /* Defer to CPU feature registers */ 1070 if (has_cpuid_feature(entry, scope)) 1071 meltdown_safe = true; 1072 1073 if (!meltdown_safe) 1074 __meltdown_safe = false; 1075 1076 /* 1077 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1078 * ThunderX leads to apparent I-cache corruption of kernel text, which 1079 * ends as well as you might imagine. Don't even try. 1080 */ 1081 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1082 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1083 __kpti_forced = -1; 1084 } 1085 1086 /* Useful for KASLR robustness */ 1087 if (kaslr_requires_kpti()) { 1088 if (!__kpti_forced) { 1089 str = "KASLR"; 1090 __kpti_forced = 1; 1091 } 1092 } 1093 1094 if (cpu_mitigations_off() && !__kpti_forced) { 1095 str = "mitigations=off"; 1096 __kpti_forced = -1; 1097 } 1098 1099 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1100 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1101 return false; 1102 } 1103 1104 /* Forced? */ 1105 if (__kpti_forced) { 1106 pr_info_once("kernel page table isolation forced %s by %s\n", 1107 __kpti_forced > 0 ? "ON" : "OFF", str); 1108 return __kpti_forced > 0; 1109 } 1110 1111 return !meltdown_safe; 1112 } 1113 1114 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1115 static void 1116 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1117 { 1118 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1119 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1120 kpti_remap_fn *remap_fn; 1121 1122 int cpu = smp_processor_id(); 1123 1124 /* 1125 * We don't need to rewrite the page-tables if either we've done 1126 * it already or we have KASLR enabled and therefore have not 1127 * created any global mappings at all. 1128 */ 1129 if (arm64_use_ng_mappings) 1130 return; 1131 1132 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1133 1134 cpu_install_idmap(); 1135 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1136 cpu_uninstall_idmap(); 1137 1138 if (!cpu) 1139 arm64_use_ng_mappings = true; 1140 1141 return; 1142 } 1143 #else 1144 static void 1145 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1146 { 1147 } 1148 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1149 1150 static int __init parse_kpti(char *str) 1151 { 1152 bool enabled; 1153 int ret = strtobool(str, &enabled); 1154 1155 if (ret) 1156 return ret; 1157 1158 __kpti_forced = enabled ? 1 : -1; 1159 return 0; 1160 } 1161 early_param("kpti", parse_kpti); 1162 1163 #ifdef CONFIG_ARM64_HW_AFDBM 1164 static inline void __cpu_enable_hw_dbm(void) 1165 { 1166 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1167 1168 write_sysreg(tcr, tcr_el1); 1169 isb(); 1170 } 1171 1172 static bool cpu_has_broken_dbm(void) 1173 { 1174 /* List of CPUs which have broken DBM support. */ 1175 static const struct midr_range cpus[] = { 1176 #ifdef CONFIG_ARM64_ERRATUM_1024718 1177 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 1178 #endif 1179 {}, 1180 }; 1181 1182 return is_midr_in_range_list(read_cpuid_id(), cpus); 1183 } 1184 1185 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1186 { 1187 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1188 !cpu_has_broken_dbm(); 1189 } 1190 1191 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1192 { 1193 if (cpu_can_use_dbm(cap)) 1194 __cpu_enable_hw_dbm(); 1195 } 1196 1197 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1198 int __unused) 1199 { 1200 static bool detected = false; 1201 /* 1202 * DBM is a non-conflicting feature. i.e, the kernel can safely 1203 * run a mix of CPUs with and without the feature. So, we 1204 * unconditionally enable the capability to allow any late CPU 1205 * to use the feature. We only enable the control bits on the 1206 * CPU, if it actually supports. 1207 * 1208 * We have to make sure we print the "feature" detection only 1209 * when at least one CPU actually uses it. So check if this CPU 1210 * can actually use it and print the message exactly once. 1211 * 1212 * This is safe as all CPUs (including secondary CPUs - due to the 1213 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1214 * goes through the "matches" check exactly once. Also if a CPU 1215 * matches the criteria, it is guaranteed that the CPU will turn 1216 * the DBM on, as the capability is unconditionally enabled. 1217 */ 1218 if (!detected && cpu_can_use_dbm(cap)) { 1219 detected = true; 1220 pr_info("detected: Hardware dirty bit management\n"); 1221 } 1222 1223 return true; 1224 } 1225 1226 #endif 1227 1228 #ifdef CONFIG_ARM64_AMU_EXTN 1229 1230 /* 1231 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1232 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1233 * information regarding all the events that it supports. When a CPU bit is 1234 * set in the cpumask, the user of this feature can only rely on the presence 1235 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1236 * counters are enabled or access to these counters is enabled by code 1237 * executed at higher exception levels (firmware). 1238 */ 1239 static struct cpumask amu_cpus __read_mostly; 1240 1241 bool cpu_has_amu_feat(int cpu) 1242 { 1243 return cpumask_test_cpu(cpu, &amu_cpus); 1244 } 1245 1246 /* Initialize the use of AMU counters for frequency invariance */ 1247 extern void init_cpu_freq_invariance_counters(void); 1248 1249 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1250 { 1251 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1252 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1253 smp_processor_id()); 1254 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1255 init_cpu_freq_invariance_counters(); 1256 } 1257 } 1258 1259 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1260 int __unused) 1261 { 1262 /* 1263 * The AMU extension is a non-conflicting feature: the kernel can 1264 * safely run a mix of CPUs with and without support for the 1265 * activity monitors extension. Therefore, unconditionally enable 1266 * the capability to allow any late CPU to use the feature. 1267 * 1268 * With this feature unconditionally enabled, the cpu_enable 1269 * function will be called for all CPUs that match the criteria, 1270 * including secondary and hotplugged, marking this feature as 1271 * present on that respective CPU. The enable function will also 1272 * print a detection message. 1273 */ 1274 1275 return true; 1276 } 1277 #endif 1278 1279 #ifdef CONFIG_ARM64_VHE 1280 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1281 { 1282 return is_kernel_in_hyp_mode(); 1283 } 1284 1285 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1286 { 1287 /* 1288 * Copy register values that aren't redirected by hardware. 1289 * 1290 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1291 * this value to tpidr_el2 before we patch the code. Once we've done 1292 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1293 * do anything here. 1294 */ 1295 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1296 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1297 } 1298 #endif 1299 1300 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1301 { 1302 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1303 1304 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1305 WARN_ON(val & (7 << 27 | 7 << 21)); 1306 } 1307 1308 #ifdef CONFIG_ARM64_SSBD 1309 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr) 1310 { 1311 if (user_mode(regs)) 1312 return 1; 1313 1314 if (instr & BIT(PSTATE_Imm_shift)) 1315 regs->pstate |= PSR_SSBS_BIT; 1316 else 1317 regs->pstate &= ~PSR_SSBS_BIT; 1318 1319 arm64_skip_faulting_instruction(regs, 4); 1320 return 0; 1321 } 1322 1323 static struct undef_hook ssbs_emulation_hook = { 1324 .instr_mask = ~(1U << PSTATE_Imm_shift), 1325 .instr_val = 0xd500401f | PSTATE_SSBS, 1326 .fn = ssbs_emulation_handler, 1327 }; 1328 1329 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused) 1330 { 1331 static bool undef_hook_registered = false; 1332 static DEFINE_RAW_SPINLOCK(hook_lock); 1333 1334 raw_spin_lock(&hook_lock); 1335 if (!undef_hook_registered) { 1336 register_undef_hook(&ssbs_emulation_hook); 1337 undef_hook_registered = true; 1338 } 1339 raw_spin_unlock(&hook_lock); 1340 1341 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) { 1342 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS); 1343 arm64_set_ssbd_mitigation(false); 1344 } else { 1345 arm64_set_ssbd_mitigation(true); 1346 } 1347 } 1348 #endif /* CONFIG_ARM64_SSBD */ 1349 1350 #ifdef CONFIG_ARM64_PAN 1351 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1352 { 1353 /* 1354 * We modify PSTATE. This won't work from irq context as the PSTATE 1355 * is discarded once we return from the exception. 1356 */ 1357 WARN_ON_ONCE(in_interrupt()); 1358 1359 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1360 asm(SET_PSTATE_PAN(1)); 1361 } 1362 #endif /* CONFIG_ARM64_PAN */ 1363 1364 #ifdef CONFIG_ARM64_RAS_EXTN 1365 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1366 { 1367 /* Firmware may have left a deferred SError in this register. */ 1368 write_sysreg_s(0, SYS_DISR_EL1); 1369 } 1370 #endif /* CONFIG_ARM64_RAS_EXTN */ 1371 1372 #ifdef CONFIG_ARM64_PTR_AUTH 1373 static bool has_address_auth(const struct arm64_cpu_capabilities *entry, 1374 int __unused) 1375 { 1376 return __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_ARCH) || 1377 __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_IMP_DEF); 1378 } 1379 1380 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1381 int __unused) 1382 { 1383 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) || 1384 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1385 } 1386 #endif /* CONFIG_ARM64_PTR_AUTH */ 1387 1388 #ifdef CONFIG_ARM64_E0PD 1389 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1390 { 1391 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1392 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1393 } 1394 #endif /* CONFIG_ARM64_E0PD */ 1395 1396 #ifdef CONFIG_ARM64_PSEUDO_NMI 1397 static bool enable_pseudo_nmi; 1398 1399 static int __init early_enable_pseudo_nmi(char *p) 1400 { 1401 return strtobool(p, &enable_pseudo_nmi); 1402 } 1403 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1404 1405 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1406 int scope) 1407 { 1408 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1409 } 1410 #endif 1411 1412 /* Internal helper functions to match cpu capability type */ 1413 static bool 1414 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 1415 { 1416 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 1417 } 1418 1419 static bool 1420 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 1421 { 1422 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 1423 } 1424 1425 static bool 1426 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 1427 { 1428 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 1429 } 1430 1431 static const struct arm64_cpu_capabilities arm64_features[] = { 1432 { 1433 .desc = "GIC system register CPU interface", 1434 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1435 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1436 .matches = has_useable_gicv3_cpuif, 1437 .sys_reg = SYS_ID_AA64PFR0_EL1, 1438 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1439 .sign = FTR_UNSIGNED, 1440 .min_field_value = 1, 1441 }, 1442 #ifdef CONFIG_ARM64_PAN 1443 { 1444 .desc = "Privileged Access Never", 1445 .capability = ARM64_HAS_PAN, 1446 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1447 .matches = has_cpuid_feature, 1448 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1449 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1450 .sign = FTR_UNSIGNED, 1451 .min_field_value = 1, 1452 .cpu_enable = cpu_enable_pan, 1453 }, 1454 #endif /* CONFIG_ARM64_PAN */ 1455 #ifdef CONFIG_ARM64_LSE_ATOMICS 1456 { 1457 .desc = "LSE atomic instructions", 1458 .capability = ARM64_HAS_LSE_ATOMICS, 1459 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1460 .matches = has_cpuid_feature, 1461 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1462 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 1463 .sign = FTR_UNSIGNED, 1464 .min_field_value = 2, 1465 }, 1466 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 1467 { 1468 .desc = "Software prefetching using PRFM", 1469 .capability = ARM64_HAS_NO_HW_PREFETCH, 1470 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1471 .matches = has_no_hw_prefetch, 1472 }, 1473 #ifdef CONFIG_ARM64_UAO 1474 { 1475 .desc = "User Access Override", 1476 .capability = ARM64_HAS_UAO, 1477 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1478 .matches = has_cpuid_feature, 1479 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1480 .field_pos = ID_AA64MMFR2_UAO_SHIFT, 1481 .min_field_value = 1, 1482 /* 1483 * We rely on stop_machine() calling uao_thread_switch() to set 1484 * UAO immediately after patching. 1485 */ 1486 }, 1487 #endif /* CONFIG_ARM64_UAO */ 1488 #ifdef CONFIG_ARM64_PAN 1489 { 1490 .capability = ARM64_ALT_PAN_NOT_UAO, 1491 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1492 .matches = cpufeature_pan_not_uao, 1493 }, 1494 #endif /* CONFIG_ARM64_PAN */ 1495 #ifdef CONFIG_ARM64_VHE 1496 { 1497 .desc = "Virtualization Host Extensions", 1498 .capability = ARM64_HAS_VIRT_HOST_EXTN, 1499 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1500 .matches = runs_at_el2, 1501 .cpu_enable = cpu_copy_el2regs, 1502 }, 1503 #endif /* CONFIG_ARM64_VHE */ 1504 { 1505 .desc = "32-bit EL0 Support", 1506 .capability = ARM64_HAS_32BIT_EL0, 1507 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1508 .matches = has_cpuid_feature, 1509 .sys_reg = SYS_ID_AA64PFR0_EL1, 1510 .sign = FTR_UNSIGNED, 1511 .field_pos = ID_AA64PFR0_EL0_SHIFT, 1512 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 1513 }, 1514 { 1515 .desc = "Kernel page table isolation (KPTI)", 1516 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 1517 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1518 /* 1519 * The ID feature fields below are used to indicate that 1520 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 1521 * more details. 1522 */ 1523 .sys_reg = SYS_ID_AA64PFR0_EL1, 1524 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 1525 .min_field_value = 1, 1526 .matches = unmap_kernel_at_el0, 1527 .cpu_enable = kpti_install_ng_mappings, 1528 }, 1529 { 1530 /* FP/SIMD is not implemented */ 1531 .capability = ARM64_HAS_NO_FPSIMD, 1532 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1533 .min_field_value = 0, 1534 .matches = has_no_fpsimd, 1535 }, 1536 #ifdef CONFIG_ARM64_PMEM 1537 { 1538 .desc = "Data cache clean to Point of Persistence", 1539 .capability = ARM64_HAS_DCPOP, 1540 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1541 .matches = has_cpuid_feature, 1542 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1543 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1544 .min_field_value = 1, 1545 }, 1546 { 1547 .desc = "Data cache clean to Point of Deep Persistence", 1548 .capability = ARM64_HAS_DCPODP, 1549 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1550 .matches = has_cpuid_feature, 1551 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1552 .sign = FTR_UNSIGNED, 1553 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1554 .min_field_value = 2, 1555 }, 1556 #endif 1557 #ifdef CONFIG_ARM64_SVE 1558 { 1559 .desc = "Scalable Vector Extension", 1560 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1561 .capability = ARM64_SVE, 1562 .sys_reg = SYS_ID_AA64PFR0_EL1, 1563 .sign = FTR_UNSIGNED, 1564 .field_pos = ID_AA64PFR0_SVE_SHIFT, 1565 .min_field_value = ID_AA64PFR0_SVE, 1566 .matches = has_cpuid_feature, 1567 .cpu_enable = sve_kernel_enable, 1568 }, 1569 #endif /* CONFIG_ARM64_SVE */ 1570 #ifdef CONFIG_ARM64_RAS_EXTN 1571 { 1572 .desc = "RAS Extension Support", 1573 .capability = ARM64_HAS_RAS_EXTN, 1574 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1575 .matches = has_cpuid_feature, 1576 .sys_reg = SYS_ID_AA64PFR0_EL1, 1577 .sign = FTR_UNSIGNED, 1578 .field_pos = ID_AA64PFR0_RAS_SHIFT, 1579 .min_field_value = ID_AA64PFR0_RAS_V1, 1580 .cpu_enable = cpu_clear_disr, 1581 }, 1582 #endif /* CONFIG_ARM64_RAS_EXTN */ 1583 #ifdef CONFIG_ARM64_AMU_EXTN 1584 { 1585 /* 1586 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 1587 * Therefore, don't provide .desc as we don't want the detection 1588 * message to be shown until at least one CPU is detected to 1589 * support the feature. 1590 */ 1591 .capability = ARM64_HAS_AMU_EXTN, 1592 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1593 .matches = has_amu, 1594 .sys_reg = SYS_ID_AA64PFR0_EL1, 1595 .sign = FTR_UNSIGNED, 1596 .field_pos = ID_AA64PFR0_AMU_SHIFT, 1597 .min_field_value = ID_AA64PFR0_AMU, 1598 .cpu_enable = cpu_amu_enable, 1599 }, 1600 #endif /* CONFIG_ARM64_AMU_EXTN */ 1601 { 1602 .desc = "Data cache clean to the PoU not required for I/D coherence", 1603 .capability = ARM64_HAS_CACHE_IDC, 1604 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1605 .matches = has_cache_idc, 1606 .cpu_enable = cpu_emulate_effective_ctr, 1607 }, 1608 { 1609 .desc = "Instruction cache invalidation not required for I/D coherence", 1610 .capability = ARM64_HAS_CACHE_DIC, 1611 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1612 .matches = has_cache_dic, 1613 }, 1614 { 1615 .desc = "Stage-2 Force Write-Back", 1616 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1617 .capability = ARM64_HAS_STAGE2_FWB, 1618 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1619 .sign = FTR_UNSIGNED, 1620 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 1621 .min_field_value = 1, 1622 .matches = has_cpuid_feature, 1623 .cpu_enable = cpu_has_fwb, 1624 }, 1625 #ifdef CONFIG_ARM64_HW_AFDBM 1626 { 1627 /* 1628 * Since we turn this on always, we don't want the user to 1629 * think that the feature is available when it may not be. 1630 * So hide the description. 1631 * 1632 * .desc = "Hardware pagetable Dirty Bit Management", 1633 * 1634 */ 1635 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1636 .capability = ARM64_HW_DBM, 1637 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1638 .sign = FTR_UNSIGNED, 1639 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 1640 .min_field_value = 2, 1641 .matches = has_hw_dbm, 1642 .cpu_enable = cpu_enable_hw_dbm, 1643 }, 1644 #endif 1645 { 1646 .desc = "CRC32 instructions", 1647 .capability = ARM64_HAS_CRC32, 1648 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1649 .matches = has_cpuid_feature, 1650 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1651 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 1652 .min_field_value = 1, 1653 }, 1654 #ifdef CONFIG_ARM64_SSBD 1655 { 1656 .desc = "Speculative Store Bypassing Safe (SSBS)", 1657 .capability = ARM64_SSBS, 1658 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1659 .matches = has_cpuid_feature, 1660 .sys_reg = SYS_ID_AA64PFR1_EL1, 1661 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 1662 .sign = FTR_UNSIGNED, 1663 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 1664 .cpu_enable = cpu_enable_ssbs, 1665 }, 1666 #endif 1667 #ifdef CONFIG_ARM64_CNP 1668 { 1669 .desc = "Common not Private translations", 1670 .capability = ARM64_HAS_CNP, 1671 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1672 .matches = has_useable_cnp, 1673 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1674 .sign = FTR_UNSIGNED, 1675 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 1676 .min_field_value = 1, 1677 .cpu_enable = cpu_enable_cnp, 1678 }, 1679 #endif 1680 { 1681 .desc = "Speculation barrier (SB)", 1682 .capability = ARM64_HAS_SB, 1683 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1684 .matches = has_cpuid_feature, 1685 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1686 .field_pos = ID_AA64ISAR1_SB_SHIFT, 1687 .sign = FTR_UNSIGNED, 1688 .min_field_value = 1, 1689 }, 1690 #ifdef CONFIG_ARM64_PTR_AUTH 1691 { 1692 .desc = "Address authentication (architected algorithm)", 1693 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 1694 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 1695 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1696 .sign = FTR_UNSIGNED, 1697 .field_pos = ID_AA64ISAR1_APA_SHIFT, 1698 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 1699 .matches = has_cpuid_feature, 1700 }, 1701 { 1702 .desc = "Address authentication (IMP DEF algorithm)", 1703 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 1704 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 1705 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1706 .sign = FTR_UNSIGNED, 1707 .field_pos = ID_AA64ISAR1_API_SHIFT, 1708 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 1709 .matches = has_cpuid_feature, 1710 }, 1711 { 1712 .capability = ARM64_HAS_ADDRESS_AUTH, 1713 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 1714 .matches = has_address_auth, 1715 }, 1716 { 1717 .desc = "Generic authentication (architected algorithm)", 1718 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 1719 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1720 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1721 .sign = FTR_UNSIGNED, 1722 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 1723 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 1724 .matches = has_cpuid_feature, 1725 }, 1726 { 1727 .desc = "Generic authentication (IMP DEF algorithm)", 1728 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 1729 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1730 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1731 .sign = FTR_UNSIGNED, 1732 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 1733 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 1734 .matches = has_cpuid_feature, 1735 }, 1736 { 1737 .capability = ARM64_HAS_GENERIC_AUTH, 1738 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1739 .matches = has_generic_auth, 1740 }, 1741 #endif /* CONFIG_ARM64_PTR_AUTH */ 1742 #ifdef CONFIG_ARM64_PSEUDO_NMI 1743 { 1744 /* 1745 * Depends on having GICv3 1746 */ 1747 .desc = "IRQ priority masking", 1748 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 1749 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1750 .matches = can_use_gic_priorities, 1751 .sys_reg = SYS_ID_AA64PFR0_EL1, 1752 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1753 .sign = FTR_UNSIGNED, 1754 .min_field_value = 1, 1755 }, 1756 #endif 1757 #ifdef CONFIG_ARM64_E0PD 1758 { 1759 .desc = "E0PD", 1760 .capability = ARM64_HAS_E0PD, 1761 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1762 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1763 .sign = FTR_UNSIGNED, 1764 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 1765 .matches = has_cpuid_feature, 1766 .min_field_value = 1, 1767 .cpu_enable = cpu_enable_e0pd, 1768 }, 1769 #endif 1770 #ifdef CONFIG_ARCH_RANDOM 1771 { 1772 .desc = "Random Number Generator", 1773 .capability = ARM64_HAS_RNG, 1774 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1775 .matches = has_cpuid_feature, 1776 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1777 .field_pos = ID_AA64ISAR0_RNDR_SHIFT, 1778 .sign = FTR_UNSIGNED, 1779 .min_field_value = 1, 1780 }, 1781 #endif 1782 {}, 1783 }; 1784 1785 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 1786 .matches = has_cpuid_feature, \ 1787 .sys_reg = reg, \ 1788 .field_pos = field, \ 1789 .sign = s, \ 1790 .min_field_value = min_value, 1791 1792 #define __HWCAP_CAP(name, cap_type, cap) \ 1793 .desc = name, \ 1794 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 1795 .hwcap_type = cap_type, \ 1796 .hwcap = cap, \ 1797 1798 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 1799 { \ 1800 __HWCAP_CAP(#cap, cap_type, cap) \ 1801 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 1802 } 1803 1804 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 1805 { \ 1806 __HWCAP_CAP(#cap, cap_type, cap) \ 1807 .matches = cpucap_multi_entry_cap_matches, \ 1808 .match_list = list, \ 1809 } 1810 1811 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 1812 { \ 1813 __HWCAP_CAP(#cap, cap_type, cap) \ 1814 .matches = match, \ 1815 } 1816 1817 #ifdef CONFIG_ARM64_PTR_AUTH 1818 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 1819 { 1820 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 1821 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 1822 }, 1823 { 1824 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 1825 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 1826 }, 1827 {}, 1828 }; 1829 1830 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 1831 { 1832 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 1833 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 1834 }, 1835 { 1836 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 1837 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 1838 }, 1839 {}, 1840 }; 1841 #endif 1842 1843 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 1844 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 1845 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 1846 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 1847 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 1848 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 1849 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 1850 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 1851 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 1852 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 1853 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 1854 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 1855 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 1856 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 1857 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 1858 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 1859 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 1860 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 1861 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 1862 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 1863 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 1864 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 1865 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 1866 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 1867 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 1868 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 1869 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 1870 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 1871 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 1872 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 1873 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 1874 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 1875 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 1876 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 1877 #ifdef CONFIG_ARM64_SVE 1878 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 1879 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 1880 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 1881 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 1882 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 1883 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 1884 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 1885 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 1886 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 1887 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 1888 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 1889 #endif 1890 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 1891 #ifdef CONFIG_ARM64_PTR_AUTH 1892 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 1893 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 1894 #endif 1895 {}, 1896 }; 1897 1898 #ifdef CONFIG_COMPAT 1899 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 1900 { 1901 /* 1902 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 1903 * in line with that of arm32 as in vfp_init(). We make sure that the 1904 * check is future proof, by making sure value is non-zero. 1905 */ 1906 u32 mvfr1; 1907 1908 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1909 if (scope == SCOPE_SYSTEM) 1910 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 1911 else 1912 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 1913 1914 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 1915 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 1916 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 1917 } 1918 #endif 1919 1920 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 1921 #ifdef CONFIG_COMPAT 1922 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 1923 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 1924 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 1925 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 1926 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 1927 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 1928 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 1929 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 1930 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 1931 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 1932 #endif 1933 {}, 1934 }; 1935 1936 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 1937 { 1938 switch (cap->hwcap_type) { 1939 case CAP_HWCAP: 1940 cpu_set_feature(cap->hwcap); 1941 break; 1942 #ifdef CONFIG_COMPAT 1943 case CAP_COMPAT_HWCAP: 1944 compat_elf_hwcap |= (u32)cap->hwcap; 1945 break; 1946 case CAP_COMPAT_HWCAP2: 1947 compat_elf_hwcap2 |= (u32)cap->hwcap; 1948 break; 1949 #endif 1950 default: 1951 WARN_ON(1); 1952 break; 1953 } 1954 } 1955 1956 /* Check if we have a particular HWCAP enabled */ 1957 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 1958 { 1959 bool rc; 1960 1961 switch (cap->hwcap_type) { 1962 case CAP_HWCAP: 1963 rc = cpu_have_feature(cap->hwcap); 1964 break; 1965 #ifdef CONFIG_COMPAT 1966 case CAP_COMPAT_HWCAP: 1967 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 1968 break; 1969 case CAP_COMPAT_HWCAP2: 1970 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 1971 break; 1972 #endif 1973 default: 1974 WARN_ON(1); 1975 rc = false; 1976 } 1977 1978 return rc; 1979 } 1980 1981 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 1982 { 1983 /* We support emulation of accesses to CPU ID feature registers */ 1984 cpu_set_named_feature(CPUID); 1985 for (; hwcaps->matches; hwcaps++) 1986 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 1987 cap_set_elf_hwcap(hwcaps); 1988 } 1989 1990 static void update_cpu_capabilities(u16 scope_mask) 1991 { 1992 int i; 1993 const struct arm64_cpu_capabilities *caps; 1994 1995 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 1996 for (i = 0; i < ARM64_NCAPS; i++) { 1997 caps = cpu_hwcaps_ptrs[i]; 1998 if (!caps || !(caps->type & scope_mask) || 1999 cpus_have_cap(caps->capability) || 2000 !caps->matches(caps, cpucap_default_scope(caps))) 2001 continue; 2002 2003 if (caps->desc) 2004 pr_info("detected: %s\n", caps->desc); 2005 cpus_set_cap(caps->capability); 2006 2007 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2008 set_bit(caps->capability, boot_capabilities); 2009 } 2010 } 2011 2012 /* 2013 * Enable all the available capabilities on this CPU. The capabilities 2014 * with BOOT_CPU scope are handled separately and hence skipped here. 2015 */ 2016 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2017 { 2018 int i; 2019 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2020 2021 for_each_available_cap(i) { 2022 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2023 2024 if (WARN_ON(!cap)) 2025 continue; 2026 2027 if (!(cap->type & non_boot_scope)) 2028 continue; 2029 2030 if (cap->cpu_enable) 2031 cap->cpu_enable(cap); 2032 } 2033 return 0; 2034 } 2035 2036 /* 2037 * Run through the enabled capabilities and enable() it on all active 2038 * CPUs 2039 */ 2040 static void __init enable_cpu_capabilities(u16 scope_mask) 2041 { 2042 int i; 2043 const struct arm64_cpu_capabilities *caps; 2044 bool boot_scope; 2045 2046 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2047 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2048 2049 for (i = 0; i < ARM64_NCAPS; i++) { 2050 unsigned int num; 2051 2052 caps = cpu_hwcaps_ptrs[i]; 2053 if (!caps || !(caps->type & scope_mask)) 2054 continue; 2055 num = caps->capability; 2056 if (!cpus_have_cap(num)) 2057 continue; 2058 2059 /* Ensure cpus_have_const_cap(num) works */ 2060 static_branch_enable(&cpu_hwcap_keys[num]); 2061 2062 if (boot_scope && caps->cpu_enable) 2063 /* 2064 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2065 * before any secondary CPU boots. Thus, each secondary 2066 * will enable the capability as appropriate via 2067 * check_local_cpu_capabilities(). The only exception is 2068 * the boot CPU, for which the capability must be 2069 * enabled here. This approach avoids costly 2070 * stop_machine() calls for this case. 2071 */ 2072 caps->cpu_enable(caps); 2073 } 2074 2075 /* 2076 * For all non-boot scope capabilities, use stop_machine() 2077 * as it schedules the work allowing us to modify PSTATE, 2078 * instead of on_each_cpu() which uses an IPI, giving us a 2079 * PSTATE that disappears when we return. 2080 */ 2081 if (!boot_scope) 2082 stop_machine(cpu_enable_non_boot_scope_capabilities, 2083 NULL, cpu_online_mask); 2084 } 2085 2086 /* 2087 * Run through the list of capabilities to check for conflicts. 2088 * If the system has already detected a capability, take necessary 2089 * action on this CPU. 2090 */ 2091 static void verify_local_cpu_caps(u16 scope_mask) 2092 { 2093 int i; 2094 bool cpu_has_cap, system_has_cap; 2095 const struct arm64_cpu_capabilities *caps; 2096 2097 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2098 2099 for (i = 0; i < ARM64_NCAPS; i++) { 2100 caps = cpu_hwcaps_ptrs[i]; 2101 if (!caps || !(caps->type & scope_mask)) 2102 continue; 2103 2104 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2105 system_has_cap = cpus_have_cap(caps->capability); 2106 2107 if (system_has_cap) { 2108 /* 2109 * Check if the new CPU misses an advertised feature, 2110 * which is not safe to miss. 2111 */ 2112 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2113 break; 2114 /* 2115 * We have to issue cpu_enable() irrespective of 2116 * whether the CPU has it or not, as it is enabeld 2117 * system wide. It is upto the call back to take 2118 * appropriate action on this CPU. 2119 */ 2120 if (caps->cpu_enable) 2121 caps->cpu_enable(caps); 2122 } else { 2123 /* 2124 * Check if the CPU has this capability if it isn't 2125 * safe to have when the system doesn't. 2126 */ 2127 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2128 break; 2129 } 2130 } 2131 2132 if (i < ARM64_NCAPS) { 2133 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 2134 smp_processor_id(), caps->capability, 2135 caps->desc, system_has_cap, cpu_has_cap); 2136 2137 if (cpucap_panic_on_conflict(caps)) 2138 cpu_panic_kernel(); 2139 else 2140 cpu_die_early(); 2141 } 2142 } 2143 2144 /* 2145 * Check for CPU features that are used in early boot 2146 * based on the Boot CPU value. 2147 */ 2148 static void check_early_cpu_features(void) 2149 { 2150 verify_cpu_asid_bits(); 2151 2152 verify_local_cpu_caps(SCOPE_BOOT_CPU); 2153 } 2154 2155 static void 2156 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 2157 { 2158 2159 for (; caps->matches; caps++) 2160 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 2161 pr_crit("CPU%d: missing HWCAP: %s\n", 2162 smp_processor_id(), caps->desc); 2163 cpu_die_early(); 2164 } 2165 } 2166 2167 static void verify_sve_features(void) 2168 { 2169 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 2170 u64 zcr = read_zcr_features(); 2171 2172 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 2173 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 2174 2175 if (len < safe_len || sve_verify_vq_map()) { 2176 pr_crit("CPU%d: SVE: vector length support mismatch\n", 2177 smp_processor_id()); 2178 cpu_die_early(); 2179 } 2180 2181 /* Add checks on other ZCR bits here if necessary */ 2182 } 2183 2184 2185 /* 2186 * Run through the enabled system capabilities and enable() it on this CPU. 2187 * The capabilities were decided based on the available CPUs at the boot time. 2188 * Any new CPU should match the system wide status of the capability. If the 2189 * new CPU doesn't have a capability which the system now has enabled, we 2190 * cannot do anything to fix it up and could cause unexpected failures. So 2191 * we park the CPU. 2192 */ 2193 static void verify_local_cpu_capabilities(void) 2194 { 2195 /* 2196 * The capabilities with SCOPE_BOOT_CPU are checked from 2197 * check_early_cpu_features(), as they need to be verified 2198 * on all secondary CPUs. 2199 */ 2200 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2201 2202 verify_local_elf_hwcaps(arm64_elf_hwcaps); 2203 2204 if (system_supports_32bit_el0()) 2205 verify_local_elf_hwcaps(compat_elf_hwcaps); 2206 2207 if (system_supports_sve()) 2208 verify_sve_features(); 2209 } 2210 2211 void check_local_cpu_capabilities(void) 2212 { 2213 /* 2214 * All secondary CPUs should conform to the early CPU features 2215 * in use by the kernel based on boot CPU. 2216 */ 2217 check_early_cpu_features(); 2218 2219 /* 2220 * If we haven't finalised the system capabilities, this CPU gets 2221 * a chance to update the errata work arounds and local features. 2222 * Otherwise, this CPU should verify that it has all the system 2223 * advertised capabilities. 2224 */ 2225 if (!system_capabilities_finalized()) 2226 update_cpu_capabilities(SCOPE_LOCAL_CPU); 2227 else 2228 verify_local_cpu_capabilities(); 2229 } 2230 2231 static void __init setup_boot_cpu_capabilities(void) 2232 { 2233 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 2234 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 2235 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 2236 enable_cpu_capabilities(SCOPE_BOOT_CPU); 2237 } 2238 2239 bool this_cpu_has_cap(unsigned int n) 2240 { 2241 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 2242 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2243 2244 if (cap) 2245 return cap->matches(cap, SCOPE_LOCAL_CPU); 2246 } 2247 2248 return false; 2249 } 2250 2251 /* 2252 * This helper function is used in a narrow window when, 2253 * - The system wide safe registers are set with all the SMP CPUs and, 2254 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 2255 * In all other cases cpus_have_{const_}cap() should be used. 2256 */ 2257 static bool __system_matches_cap(unsigned int n) 2258 { 2259 if (n < ARM64_NCAPS) { 2260 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2261 2262 if (cap) 2263 return cap->matches(cap, SCOPE_SYSTEM); 2264 } 2265 return false; 2266 } 2267 2268 void cpu_set_feature(unsigned int num) 2269 { 2270 WARN_ON(num >= MAX_CPU_FEATURES); 2271 elf_hwcap |= BIT(num); 2272 } 2273 EXPORT_SYMBOL_GPL(cpu_set_feature); 2274 2275 bool cpu_have_feature(unsigned int num) 2276 { 2277 WARN_ON(num >= MAX_CPU_FEATURES); 2278 return elf_hwcap & BIT(num); 2279 } 2280 EXPORT_SYMBOL_GPL(cpu_have_feature); 2281 2282 unsigned long cpu_get_elf_hwcap(void) 2283 { 2284 /* 2285 * We currently only populate the first 32 bits of AT_HWCAP. Please 2286 * note that for userspace compatibility we guarantee that bits 62 2287 * and 63 will always be returned as 0. 2288 */ 2289 return lower_32_bits(elf_hwcap); 2290 } 2291 2292 unsigned long cpu_get_elf_hwcap2(void) 2293 { 2294 return upper_32_bits(elf_hwcap); 2295 } 2296 2297 static void __init setup_system_capabilities(void) 2298 { 2299 /* 2300 * We have finalised the system-wide safe feature 2301 * registers, finalise the capabilities that depend 2302 * on it. Also enable all the available capabilities, 2303 * that are not enabled already. 2304 */ 2305 update_cpu_capabilities(SCOPE_SYSTEM); 2306 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2307 } 2308 2309 void __init setup_cpu_features(void) 2310 { 2311 u32 cwg; 2312 2313 setup_system_capabilities(); 2314 setup_elf_hwcaps(arm64_elf_hwcaps); 2315 2316 if (system_supports_32bit_el0()) 2317 setup_elf_hwcaps(compat_elf_hwcaps); 2318 2319 if (system_uses_ttbr0_pan()) 2320 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 2321 2322 sve_setup(); 2323 minsigstksz_setup(); 2324 2325 /* Advertise that we have computed the system capabilities */ 2326 finalize_system_capabilities(); 2327 2328 /* 2329 * Check for sane CTR_EL0.CWG value. 2330 */ 2331 cwg = cache_type_cwg(); 2332 if (!cwg) 2333 pr_warn("No Cache Writeback Granule information, assuming %d\n", 2334 ARCH_DMA_MINALIGN); 2335 } 2336 2337 static bool __maybe_unused 2338 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) 2339 { 2340 return (__system_matches_cap(ARM64_HAS_PAN) && !__system_matches_cap(ARM64_HAS_UAO)); 2341 } 2342 2343 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 2344 { 2345 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 2346 } 2347 2348 /* 2349 * We emulate only the following system register space. 2350 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 2351 * See Table C5-6 System instruction encodings for System register accesses, 2352 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 2353 */ 2354 static inline bool __attribute_const__ is_emulated(u32 id) 2355 { 2356 return (sys_reg_Op0(id) == 0x3 && 2357 sys_reg_CRn(id) == 0x0 && 2358 sys_reg_Op1(id) == 0x0 && 2359 (sys_reg_CRm(id) == 0 || 2360 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 2361 } 2362 2363 /* 2364 * With CRm == 0, reg should be one of : 2365 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 2366 */ 2367 static inline int emulate_id_reg(u32 id, u64 *valp) 2368 { 2369 switch (id) { 2370 case SYS_MIDR_EL1: 2371 *valp = read_cpuid_id(); 2372 break; 2373 case SYS_MPIDR_EL1: 2374 *valp = SYS_MPIDR_SAFE_VAL; 2375 break; 2376 case SYS_REVIDR_EL1: 2377 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 2378 *valp = 0; 2379 break; 2380 default: 2381 return -EINVAL; 2382 } 2383 2384 return 0; 2385 } 2386 2387 static int emulate_sys_reg(u32 id, u64 *valp) 2388 { 2389 struct arm64_ftr_reg *regp; 2390 2391 if (!is_emulated(id)) 2392 return -EINVAL; 2393 2394 if (sys_reg_CRm(id) == 0) 2395 return emulate_id_reg(id, valp); 2396 2397 regp = get_arm64_ftr_reg(id); 2398 if (regp) 2399 *valp = arm64_ftr_reg_user_value(regp); 2400 else 2401 /* 2402 * The untracked registers are either IMPLEMENTATION DEFINED 2403 * (e.g, ID_AFR0_EL1) or reserved RAZ. 2404 */ 2405 *valp = 0; 2406 return 0; 2407 } 2408 2409 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 2410 { 2411 int rc; 2412 u64 val; 2413 2414 rc = emulate_sys_reg(sys_reg, &val); 2415 if (!rc) { 2416 pt_regs_write_reg(regs, rt, val); 2417 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 2418 } 2419 return rc; 2420 } 2421 2422 static int emulate_mrs(struct pt_regs *regs, u32 insn) 2423 { 2424 u32 sys_reg, rt; 2425 2426 /* 2427 * sys_reg values are defined as used in mrs/msr instruction. 2428 * shift the imm value to get the encoding. 2429 */ 2430 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 2431 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 2432 return do_emulate_mrs(regs, sys_reg, rt); 2433 } 2434 2435 static struct undef_hook mrs_hook = { 2436 .instr_mask = 0xfff00000, 2437 .instr_val = 0xd5300000, 2438 .pstate_mask = PSR_AA32_MODE_MASK, 2439 .pstate_val = PSR_MODE_EL0t, 2440 .fn = emulate_mrs, 2441 }; 2442 2443 static int __init enable_mrs_emulation(void) 2444 { 2445 register_undef_hook(&mrs_hook); 2446 return 0; 2447 } 2448 2449 core_initcall(enable_mrs_emulation); 2450 2451 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 2452 char *buf) 2453 { 2454 if (__meltdown_safe) 2455 return sprintf(buf, "Not affected\n"); 2456 2457 if (arm64_kernel_unmapped_at_el0()) 2458 return sprintf(buf, "Mitigation: PTI\n"); 2459 2460 return sprintf(buf, "Vulnerable\n"); 2461 } 2462