1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #ifndef _ROCKCHIP_DRM_VOP_H 8 #define _ROCKCHIP_DRM_VOP_H 9 10 /* 11 * major: IP major version, used for IP structure 12 * minor: big feature change under same structure 13 */ 14 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 15 #define VOP_MAJOR(version) ((version) >> 8) 16 #define VOP_MINOR(version) ((version) & 0xff) 17 18 #define NUM_YUV2YUV_COEFFICIENTS 12 19 20 #define ROCKCHIP_AFBC_MOD \ 21 DRM_FORMAT_MOD_ARM_AFBC( \ 22 AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | AFBC_FORMAT_MOD_SPARSE \ 23 ) 24 25 enum vop_data_format { 26 VOP_FMT_ARGB8888 = 0, 27 VOP_FMT_RGB888, 28 VOP_FMT_RGB565, 29 VOP_FMT_YUV420SP = 4, 30 VOP_FMT_YUV422SP, 31 VOP_FMT_YUV444SP, 32 }; 33 34 struct vop_reg { 35 uint32_t mask; 36 uint16_t offset; 37 uint8_t shift; 38 bool write_mask; 39 bool relaxed; 40 }; 41 42 struct vop_afbc { 43 struct vop_reg enable; 44 struct vop_reg win_sel; 45 struct vop_reg format; 46 struct vop_reg hreg_block_split; 47 struct vop_reg pic_size; 48 struct vop_reg hdr_ptr; 49 struct vop_reg rstn; 50 }; 51 52 struct vop_modeset { 53 struct vop_reg htotal_pw; 54 struct vop_reg hact_st_end; 55 struct vop_reg hpost_st_end; 56 struct vop_reg vtotal_pw; 57 struct vop_reg vact_st_end; 58 struct vop_reg vpost_st_end; 59 }; 60 61 struct vop_output { 62 struct vop_reg pin_pol; 63 struct vop_reg dp_pin_pol; 64 struct vop_reg dp_dclk_pol; 65 struct vop_reg edp_pin_pol; 66 struct vop_reg edp_dclk_pol; 67 struct vop_reg hdmi_pin_pol; 68 struct vop_reg hdmi_dclk_pol; 69 struct vop_reg mipi_pin_pol; 70 struct vop_reg mipi_dclk_pol; 71 struct vop_reg rgb_pin_pol; 72 struct vop_reg rgb_dclk_pol; 73 struct vop_reg dp_en; 74 struct vop_reg edp_en; 75 struct vop_reg hdmi_en; 76 struct vop_reg mipi_en; 77 struct vop_reg mipi_dual_channel_en; 78 struct vop_reg rgb_en; 79 }; 80 81 struct vop_common { 82 struct vop_reg cfg_done; 83 struct vop_reg dsp_blank; 84 struct vop_reg data_blank; 85 struct vop_reg pre_dither_down; 86 struct vop_reg dither_down_sel; 87 struct vop_reg dither_down_mode; 88 struct vop_reg dither_down_en; 89 struct vop_reg dither_up; 90 struct vop_reg dsp_lut_en; 91 struct vop_reg gate_en; 92 struct vop_reg mmu_en; 93 struct vop_reg out_mode; 94 struct vop_reg standby; 95 }; 96 97 struct vop_misc { 98 struct vop_reg global_regdone_en; 99 }; 100 101 struct vop_intr { 102 const int *intrs; 103 uint32_t nintrs; 104 105 struct vop_reg line_flag_num[2]; 106 struct vop_reg enable; 107 struct vop_reg clear; 108 struct vop_reg status; 109 }; 110 111 struct vop_scl_extension { 112 struct vop_reg cbcr_vsd_mode; 113 struct vop_reg cbcr_vsu_mode; 114 struct vop_reg cbcr_hsd_mode; 115 struct vop_reg cbcr_ver_scl_mode; 116 struct vop_reg cbcr_hor_scl_mode; 117 struct vop_reg yrgb_vsd_mode; 118 struct vop_reg yrgb_vsu_mode; 119 struct vop_reg yrgb_hsd_mode; 120 struct vop_reg yrgb_ver_scl_mode; 121 struct vop_reg yrgb_hor_scl_mode; 122 struct vop_reg line_load_mode; 123 struct vop_reg cbcr_axi_gather_num; 124 struct vop_reg yrgb_axi_gather_num; 125 struct vop_reg vsd_cbcr_gt2; 126 struct vop_reg vsd_cbcr_gt4; 127 struct vop_reg vsd_yrgb_gt2; 128 struct vop_reg vsd_yrgb_gt4; 129 struct vop_reg bic_coe_sel; 130 struct vop_reg cbcr_axi_gather_en; 131 struct vop_reg yrgb_axi_gather_en; 132 struct vop_reg lb_mode; 133 }; 134 135 struct vop_scl_regs { 136 const struct vop_scl_extension *ext; 137 138 struct vop_reg scale_yrgb_x; 139 struct vop_reg scale_yrgb_y; 140 struct vop_reg scale_cbcr_x; 141 struct vop_reg scale_cbcr_y; 142 }; 143 144 struct vop_yuv2yuv_phy { 145 struct vop_reg y2r_coefficients[NUM_YUV2YUV_COEFFICIENTS]; 146 }; 147 148 struct vop_win_phy { 149 const struct vop_scl_regs *scl; 150 const uint32_t *data_formats; 151 uint32_t nformats; 152 const uint64_t *format_modifiers; 153 154 struct vop_reg enable; 155 struct vop_reg gate; 156 struct vop_reg format; 157 struct vop_reg rb_swap; 158 struct vop_reg act_info; 159 struct vop_reg dsp_info; 160 struct vop_reg dsp_st; 161 struct vop_reg yrgb_mst; 162 struct vop_reg uv_mst; 163 struct vop_reg yrgb_vir; 164 struct vop_reg uv_vir; 165 struct vop_reg y_mir_en; 166 struct vop_reg x_mir_en; 167 168 struct vop_reg dst_alpha_ctl; 169 struct vop_reg src_alpha_ctl; 170 struct vop_reg channel; 171 }; 172 173 struct vop_win_yuv2yuv_data { 174 uint32_t base; 175 const struct vop_yuv2yuv_phy *phy; 176 struct vop_reg y2r_en; 177 }; 178 179 struct vop_win_data { 180 uint32_t base; 181 const struct vop_win_phy *phy; 182 enum drm_plane_type type; 183 }; 184 185 struct vop_data { 186 uint32_t version; 187 const struct vop_intr *intr; 188 const struct vop_common *common; 189 const struct vop_misc *misc; 190 const struct vop_modeset *modeset; 191 const struct vop_output *output; 192 const struct vop_afbc *afbc; 193 const struct vop_win_yuv2yuv_data *win_yuv2yuv; 194 const struct vop_win_data *win; 195 unsigned int win_size; 196 unsigned int lut_size; 197 198 #define VOP_FEATURE_OUTPUT_RGB10 BIT(0) 199 #define VOP_FEATURE_INTERNAL_RGB BIT(1) 200 u64 feature; 201 }; 202 203 /* interrupt define */ 204 #define DSP_HOLD_VALID_INTR (1 << 0) 205 #define FS_INTR (1 << 1) 206 #define LINE_FLAG_INTR (1 << 2) 207 #define BUS_ERROR_INTR (1 << 3) 208 209 #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \ 210 LINE_FLAG_INTR | BUS_ERROR_INTR) 211 212 #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4) 213 #define FS_INTR_EN(x) ((x) << 5) 214 #define LINE_FLAG_INTR_EN(x) ((x) << 6) 215 #define BUS_ERROR_INTR_EN(x) ((x) << 7) 216 #define DSP_HOLD_VALID_INTR_MASK (1 << 4) 217 #define FS_INTR_MASK (1 << 5) 218 #define LINE_FLAG_INTR_MASK (1 << 6) 219 #define BUS_ERROR_INTR_MASK (1 << 7) 220 221 #define INTR_CLR_SHIFT 8 222 #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0)) 223 #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1)) 224 #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2)) 225 #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3)) 226 227 #define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12) 228 #define DSP_LINE_NUM_MASK (0x1fff << 12) 229 230 /* src alpha ctrl define */ 231 #define SRC_FADING_VALUE(x) (((x) & 0xff) << 24) 232 #define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16) 233 #define SRC_FACTOR_M0(x) (((x) & 0x7) << 6) 234 #define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5) 235 #define SRC_BLEND_M0(x) (((x) & 0x3) << 3) 236 #define SRC_ALPHA_M0(x) (((x) & 0x1) << 2) 237 #define SRC_COLOR_M0(x) (((x) & 0x1) << 1) 238 #define SRC_ALPHA_EN(x) (((x) & 0x1) << 0) 239 /* dst alpha ctrl define */ 240 #define DST_FACTOR_M0(x) (((x) & 0x7) << 6) 241 242 /* 243 * display output interface supported by rockchip lcdc 244 */ 245 #define ROCKCHIP_OUT_MODE_P888 0 246 #define ROCKCHIP_OUT_MODE_P666 1 247 #define ROCKCHIP_OUT_MODE_P565 2 248 /* for use special outface */ 249 #define ROCKCHIP_OUT_MODE_AAAA 15 250 251 /* output flags */ 252 #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) 253 254 enum alpha_mode { 255 ALPHA_STRAIGHT, 256 ALPHA_INVERSE, 257 }; 258 259 enum global_blend_mode { 260 ALPHA_GLOBAL, 261 ALPHA_PER_PIX, 262 ALPHA_PER_PIX_GLOBAL, 263 }; 264 265 enum alpha_cal_mode { 266 ALPHA_SATURATION, 267 ALPHA_NO_SATURATION, 268 }; 269 270 enum color_mode { 271 ALPHA_SRC_PRE_MUL, 272 ALPHA_SRC_NO_PRE_MUL, 273 }; 274 275 enum factor_mode { 276 ALPHA_ZERO, 277 ALPHA_ONE, 278 ALPHA_SRC, 279 ALPHA_SRC_INVERSE, 280 ALPHA_SRC_GLOBAL, 281 }; 282 283 enum scale_mode { 284 SCALE_NONE = 0x0, 285 SCALE_UP = 0x1, 286 SCALE_DOWN = 0x2 287 }; 288 289 enum lb_mode { 290 LB_YUV_3840X5 = 0x0, 291 LB_YUV_2560X8 = 0x1, 292 LB_RGB_3840X2 = 0x2, 293 LB_RGB_2560X4 = 0x3, 294 LB_RGB_1920X5 = 0x4, 295 LB_RGB_1280X8 = 0x5 296 }; 297 298 enum sacle_up_mode { 299 SCALE_UP_BIL = 0x0, 300 SCALE_UP_BIC = 0x1 301 }; 302 303 enum scale_down_mode { 304 SCALE_DOWN_BIL = 0x0, 305 SCALE_DOWN_AVG = 0x1 306 }; 307 308 enum dither_down_mode { 309 RGB888_TO_RGB565 = 0x0, 310 RGB888_TO_RGB666 = 0x1 311 }; 312 313 enum dither_down_mode_sel { 314 DITHER_DOWN_ALLEGRO = 0x0, 315 DITHER_DOWN_FRC = 0x1 316 }; 317 318 enum vop_pol { 319 HSYNC_POSITIVE = 0, 320 VSYNC_POSITIVE = 1, 321 DEN_NEGATIVE = 2 322 }; 323 324 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 325 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12 326 #define SCL_MAX_VSKIPLINES 4 327 #define MIN_SCL_FT_AFTER_VSKIP 1 328 329 static inline uint16_t scl_cal_scale(int src, int dst, int shift) 330 { 331 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 332 } 333 334 static inline uint16_t scl_cal_scale2(int src, int dst) 335 { 336 return ((src - 1) << 12) / (dst - 1); 337 } 338 339 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12) 340 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16) 341 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16) 342 343 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, 344 int vskiplines) 345 { 346 int act_height; 347 348 act_height = DIV_ROUND_UP(src_h, vskiplines); 349 350 if (act_height == dst_h) 351 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines; 352 353 return GET_SCL_FT_BILI_DN(act_height, dst_h); 354 } 355 356 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 357 { 358 if (src < dst) 359 return SCALE_UP; 360 else if (src > dst) 361 return SCALE_DOWN; 362 363 return SCALE_NONE; 364 } 365 366 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth) 367 { 368 uint32_t vskiplines; 369 370 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2) 371 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP) 372 break; 373 374 return vskiplines; 375 } 376 377 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) 378 { 379 int lb_mode; 380 381 if (is_yuv) { 382 if (width > 1280) 383 lb_mode = LB_YUV_3840X5; 384 else 385 lb_mode = LB_YUV_2560X8; 386 } else { 387 if (width > 2560) 388 lb_mode = LB_RGB_3840X2; 389 else if (width > 1920) 390 lb_mode = LB_RGB_2560X4; 391 else 392 lb_mode = LB_RGB_1920X5; 393 } 394 395 return lb_mode; 396 } 397 398 extern const struct component_ops vop_component_ops; 399 #endif /* _ROCKCHIP_DRM_VOP_H */ 400