1 /* 2 * drivers/w1/masters/omap_hdq.c 3 * 4 * Copyright (C) 2007,2012 Texas Instruments, Inc. 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 * 10 */ 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/interrupt.h> 15 #include <linux/slab.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/sched.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/of.h> 21 22 #include <linux/w1.h> 23 24 #define MOD_NAME "OMAP_HDQ:" 25 26 #define OMAP_HDQ_REVISION 0x00 27 #define OMAP_HDQ_TX_DATA 0x04 28 #define OMAP_HDQ_RX_DATA 0x08 29 #define OMAP_HDQ_CTRL_STATUS 0x0c 30 #define OMAP_HDQ_CTRL_STATUS_SINGLE BIT(7) 31 #define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK BIT(6) 32 #define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE BIT(5) 33 #define OMAP_HDQ_CTRL_STATUS_GO BIT(4) 34 #define OMAP_HDQ_CTRL_STATUS_PRESENCE BIT(3) 35 #define OMAP_HDQ_CTRL_STATUS_INITIALIZATION BIT(2) 36 #define OMAP_HDQ_CTRL_STATUS_DIR BIT(1) 37 #define OMAP_HDQ_INT_STATUS 0x10 38 #define OMAP_HDQ_INT_STATUS_TXCOMPLETE BIT(2) 39 #define OMAP_HDQ_INT_STATUS_RXCOMPLETE BIT(1) 40 #define OMAP_HDQ_INT_STATUS_TIMEOUT BIT(0) 41 42 #define OMAP_HDQ_FLAG_CLEAR 0 43 #define OMAP_HDQ_FLAG_SET 1 44 #define OMAP_HDQ_TIMEOUT (HZ/5) 45 46 #define OMAP_HDQ_MAX_USER 4 47 48 static DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue); 49 50 static int w1_id; 51 module_param(w1_id, int, S_IRUSR); 52 MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection in HDQ mode"); 53 54 struct hdq_data { 55 struct device *dev; 56 void __iomem *hdq_base; 57 /* lock status update */ 58 struct mutex hdq_mutex; 59 u8 hdq_irqstatus; 60 /* device lock */ 61 spinlock_t hdq_spinlock; 62 /* mode: 0-HDQ 1-W1 */ 63 int mode; 64 65 }; 66 67 /* HDQ register I/O routines */ 68 static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset) 69 { 70 return __raw_readl(hdq_data->hdq_base + offset); 71 } 72 73 static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val) 74 { 75 __raw_writel(val, hdq_data->hdq_base + offset); 76 } 77 78 static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset, 79 u8 val, u8 mask) 80 { 81 u8 new_val = (__raw_readl(hdq_data->hdq_base + offset) & ~mask) 82 | (val & mask); 83 __raw_writel(new_val, hdq_data->hdq_base + offset); 84 85 return new_val; 86 } 87 88 /* 89 * Wait for one or more bits in flag change. 90 * HDQ_FLAG_SET: wait until any bit in the flag is set. 91 * HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared. 92 * return 0 on success and -ETIMEDOUT in the case of timeout. 93 */ 94 static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset, 95 u8 flag, u8 flag_set, u8 *status) 96 { 97 int ret = 0; 98 unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT; 99 100 if (flag_set == OMAP_HDQ_FLAG_CLEAR) { 101 /* wait for the flag clear */ 102 while (((*status = hdq_reg_in(hdq_data, offset)) & flag) 103 && time_before(jiffies, timeout)) { 104 schedule_timeout_uninterruptible(1); 105 } 106 if (*status & flag) 107 ret = -ETIMEDOUT; 108 } else if (flag_set == OMAP_HDQ_FLAG_SET) { 109 /* wait for the flag set */ 110 while (!((*status = hdq_reg_in(hdq_data, offset)) & flag) 111 && time_before(jiffies, timeout)) { 112 schedule_timeout_uninterruptible(1); 113 } 114 if (!(*status & flag)) 115 ret = -ETIMEDOUT; 116 } else 117 return -EINVAL; 118 119 return ret; 120 } 121 122 /* Clear saved irqstatus after using an interrupt */ 123 static void hdq_reset_irqstatus(struct hdq_data *hdq_data) 124 { 125 unsigned long irqflags; 126 127 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags); 128 hdq_data->hdq_irqstatus = 0; 129 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags); 130 } 131 132 /* write out a byte and fill *status with HDQ_INT_STATUS */ 133 static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status) 134 { 135 int ret; 136 u8 tmp_status; 137 138 *status = 0; 139 140 hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val); 141 142 /* set the GO bit */ 143 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO, 144 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO); 145 /* wait for the TXCOMPLETE bit */ 146 ret = wait_event_timeout(hdq_wait_queue, 147 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT); 148 if (ret == 0) { 149 dev_dbg(hdq_data->dev, "TX wait elapsed\n"); 150 ret = -ETIMEDOUT; 151 goto out; 152 } 153 154 *status = hdq_data->hdq_irqstatus; 155 /* check irqstatus */ 156 if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) { 157 dev_dbg(hdq_data->dev, "timeout waiting for" 158 " TXCOMPLETE/RXCOMPLETE, %x", *status); 159 ret = -ETIMEDOUT; 160 goto out; 161 } 162 163 /* wait for the GO bit return to zero */ 164 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS, 165 OMAP_HDQ_CTRL_STATUS_GO, 166 OMAP_HDQ_FLAG_CLEAR, &tmp_status); 167 if (ret) { 168 dev_dbg(hdq_data->dev, "timeout waiting GO bit" 169 " return to zero, %x", tmp_status); 170 } 171 172 out: 173 hdq_reset_irqstatus(hdq_data); 174 return ret; 175 } 176 177 /* HDQ Interrupt service routine */ 178 static irqreturn_t hdq_isr(int irq, void *_hdq) 179 { 180 struct hdq_data *hdq_data = _hdq; 181 unsigned long irqflags; 182 183 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags); 184 hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS); 185 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags); 186 dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus); 187 188 if (hdq_data->hdq_irqstatus & 189 (OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE 190 | OMAP_HDQ_INT_STATUS_TIMEOUT)) { 191 /* wake up sleeping process */ 192 wake_up(&hdq_wait_queue); 193 } 194 195 return IRQ_HANDLED; 196 } 197 198 /* W1 search callback function in HDQ mode */ 199 static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev, 200 u8 search_type, w1_slave_found_callback slave_found) 201 { 202 u64 module_id, rn_le, cs, id; 203 204 if (w1_id) 205 module_id = w1_id; 206 else 207 module_id = 0x1; 208 209 rn_le = cpu_to_le64(module_id); 210 /* 211 * HDQ might not obey truly the 1-wire spec. 212 * So calculate CRC based on module parameter. 213 */ 214 cs = w1_calc_crc8((u8 *)&rn_le, 7); 215 id = (cs << 56) | module_id; 216 217 slave_found(master_dev, id); 218 } 219 220 /* Issue break pulse to the device */ 221 static int omap_hdq_break(struct hdq_data *hdq_data) 222 { 223 int ret = 0; 224 u8 tmp_status; 225 226 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex); 227 if (ret < 0) { 228 dev_dbg(hdq_data->dev, "Could not acquire mutex\n"); 229 ret = -EINTR; 230 goto rtn; 231 } 232 233 /* set the INIT and GO bit */ 234 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 235 OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO, 236 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION | 237 OMAP_HDQ_CTRL_STATUS_GO); 238 239 /* wait for the TIMEOUT bit */ 240 ret = wait_event_timeout(hdq_wait_queue, 241 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT); 242 if (ret == 0) { 243 dev_dbg(hdq_data->dev, "break wait elapsed\n"); 244 ret = -EINTR; 245 goto out; 246 } 247 248 tmp_status = hdq_data->hdq_irqstatus; 249 /* check irqstatus */ 250 if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) { 251 dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x", 252 tmp_status); 253 ret = -ETIMEDOUT; 254 goto out; 255 } 256 257 /* 258 * check for the presence detect bit to get 259 * set to show that the slave is responding 260 */ 261 if (!(hdq_reg_in(hdq_data, OMAP_HDQ_CTRL_STATUS) & 262 OMAP_HDQ_CTRL_STATUS_PRESENCE)) { 263 dev_dbg(hdq_data->dev, "Presence bit not set\n"); 264 ret = -ETIMEDOUT; 265 goto out; 266 } 267 268 /* 269 * wait for both INIT and GO bits rerurn to zero. 270 * zero wait time expected for interrupt mode. 271 */ 272 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS, 273 OMAP_HDQ_CTRL_STATUS_INITIALIZATION | 274 OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR, 275 &tmp_status); 276 if (ret) 277 dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits" 278 " return to zero, %x", tmp_status); 279 280 out: 281 hdq_reset_irqstatus(hdq_data); 282 mutex_unlock(&hdq_data->hdq_mutex); 283 rtn: 284 return ret; 285 } 286 287 static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val) 288 { 289 int ret = 0; 290 u8 status; 291 292 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex); 293 if (ret < 0) { 294 ret = -EINTR; 295 goto rtn; 296 } 297 298 if (pm_runtime_suspended(hdq_data->dev)) { 299 ret = -EINVAL; 300 goto out; 301 } 302 303 if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) { 304 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 305 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO, 306 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO); 307 /* 308 * The RX comes immediately after TX. 309 */ 310 wait_event_timeout(hdq_wait_queue, 311 (hdq_data->hdq_irqstatus 312 & OMAP_HDQ_INT_STATUS_RXCOMPLETE), 313 OMAP_HDQ_TIMEOUT); 314 315 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0, 316 OMAP_HDQ_CTRL_STATUS_DIR); 317 status = hdq_data->hdq_irqstatus; 318 /* check irqstatus */ 319 if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) { 320 dev_dbg(hdq_data->dev, "timeout waiting for" 321 " RXCOMPLETE, %x", status); 322 ret = -ETIMEDOUT; 323 goto out; 324 } 325 } 326 /* the data is ready. Read it in! */ 327 *val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA); 328 out: 329 hdq_reset_irqstatus(hdq_data); 330 mutex_unlock(&hdq_data->hdq_mutex); 331 rtn: 332 return ret; 333 334 } 335 336 /* 337 * W1 triplet callback function - used for searching ROM addresses. 338 * Registered only when controller is in 1-wire mode. 339 */ 340 static u8 omap_w1_triplet(void *_hdq, u8 bdir) 341 { 342 u8 id_bit, comp_bit; 343 int err; 344 u8 ret = 0x3; /* no slaves responded */ 345 struct hdq_data *hdq_data = _hdq; 346 u8 ctrl = OMAP_HDQ_CTRL_STATUS_SINGLE | OMAP_HDQ_CTRL_STATUS_GO | 347 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK; 348 u8 mask = ctrl | OMAP_HDQ_CTRL_STATUS_DIR; 349 350 err = pm_runtime_get_sync(hdq_data->dev); 351 if (err < 0) { 352 pm_runtime_put_noidle(hdq_data->dev); 353 354 return err; 355 } 356 357 err = mutex_lock_interruptible(&hdq_data->hdq_mutex); 358 if (err < 0) { 359 dev_dbg(hdq_data->dev, "Could not acquire mutex\n"); 360 goto rtn; 361 } 362 363 /* read id_bit */ 364 hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, 365 ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask); 366 err = wait_event_timeout(hdq_wait_queue, 367 (hdq_data->hdq_irqstatus 368 & OMAP_HDQ_INT_STATUS_RXCOMPLETE), 369 OMAP_HDQ_TIMEOUT); 370 if (err == 0) { 371 dev_dbg(hdq_data->dev, "RX wait elapsed\n"); 372 goto out; 373 } 374 id_bit = (hdq_reg_in(_hdq, OMAP_HDQ_RX_DATA) & 0x01); 375 376 /* Must clear irqstatus for another RXCOMPLETE interrupt */ 377 hdq_reset_irqstatus(hdq_data); 378 379 /* read comp_bit */ 380 hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, 381 ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask); 382 err = wait_event_timeout(hdq_wait_queue, 383 (hdq_data->hdq_irqstatus 384 & OMAP_HDQ_INT_STATUS_RXCOMPLETE), 385 OMAP_HDQ_TIMEOUT); 386 if (err == 0) { 387 dev_dbg(hdq_data->dev, "RX wait elapsed\n"); 388 goto out; 389 } 390 comp_bit = (hdq_reg_in(_hdq, OMAP_HDQ_RX_DATA) & 0x01); 391 392 if (id_bit && comp_bit) { 393 ret = 0x03; /* no slaves responded */ 394 goto out; 395 } 396 if (!id_bit && !comp_bit) { 397 /* Both bits are valid, take the direction given */ 398 ret = bdir ? 0x04 : 0; 399 } else { 400 /* Only one bit is valid, take that direction */ 401 bdir = id_bit; 402 ret = id_bit ? 0x05 : 0x02; 403 } 404 405 /* write bdir bit */ 406 hdq_reg_out(_hdq, OMAP_HDQ_TX_DATA, bdir); 407 hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, ctrl, mask); 408 err = wait_event_timeout(hdq_wait_queue, 409 (hdq_data->hdq_irqstatus 410 & OMAP_HDQ_INT_STATUS_TXCOMPLETE), 411 OMAP_HDQ_TIMEOUT); 412 if (err == 0) { 413 dev_dbg(hdq_data->dev, "TX wait elapsed\n"); 414 goto out; 415 } 416 417 hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, 0, 418 OMAP_HDQ_CTRL_STATUS_SINGLE); 419 420 out: 421 hdq_reset_irqstatus(hdq_data); 422 mutex_unlock(&hdq_data->hdq_mutex); 423 rtn: 424 pm_runtime_mark_last_busy(hdq_data->dev); 425 pm_runtime_put_autosuspend(hdq_data->dev); 426 427 return ret; 428 } 429 430 /* reset callback */ 431 static u8 omap_w1_reset_bus(void *_hdq) 432 { 433 struct hdq_data *hdq_data = _hdq; 434 int err; 435 436 err = pm_runtime_get_sync(hdq_data->dev); 437 if (err < 0) { 438 pm_runtime_put_noidle(hdq_data->dev); 439 440 return err; 441 } 442 443 omap_hdq_break(hdq_data); 444 445 pm_runtime_mark_last_busy(hdq_data->dev); 446 pm_runtime_put_autosuspend(hdq_data->dev); 447 448 return 0; 449 } 450 451 /* Read a byte of data from the device */ 452 static u8 omap_w1_read_byte(void *_hdq) 453 { 454 struct hdq_data *hdq_data = _hdq; 455 u8 val = 0; 456 int ret; 457 458 ret = pm_runtime_get_sync(hdq_data->dev); 459 if (ret < 0) { 460 pm_runtime_put_noidle(hdq_data->dev); 461 462 return -1; 463 } 464 465 ret = hdq_read_byte(hdq_data, &val); 466 if (ret) 467 ret = -1; 468 469 pm_runtime_mark_last_busy(hdq_data->dev); 470 pm_runtime_put_autosuspend(hdq_data->dev); 471 472 return val; 473 } 474 475 /* Write a byte of data to the device */ 476 static void omap_w1_write_byte(void *_hdq, u8 byte) 477 { 478 struct hdq_data *hdq_data = _hdq; 479 int ret; 480 u8 status; 481 482 ret = pm_runtime_get_sync(hdq_data->dev); 483 if (ret < 0) { 484 pm_runtime_put_noidle(hdq_data->dev); 485 486 return; 487 } 488 489 /* 490 * We need to reset the slave before 491 * issuing the SKIP ROM command, else 492 * the slave will not work. 493 */ 494 if (byte == W1_SKIP_ROM) 495 omap_hdq_break(hdq_data); 496 497 ret = hdq_write_byte(hdq_data, byte, &status); 498 if (ret < 0) { 499 dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status); 500 goto out_err; 501 } 502 503 out_err: 504 pm_runtime_mark_last_busy(hdq_data->dev); 505 pm_runtime_put_autosuspend(hdq_data->dev); 506 } 507 508 static struct w1_bus_master omap_w1_master = { 509 .read_byte = omap_w1_read_byte, 510 .write_byte = omap_w1_write_byte, 511 .reset_bus = omap_w1_reset_bus, 512 }; 513 514 static int __maybe_unused omap_hdq_runtime_suspend(struct device *dev) 515 { 516 struct hdq_data *hdq_data = dev_get_drvdata(dev); 517 518 hdq_reg_out(hdq_data, 0, hdq_data->mode); 519 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS); 520 521 return 0; 522 } 523 524 static int __maybe_unused omap_hdq_runtime_resume(struct device *dev) 525 { 526 struct hdq_data *hdq_data = dev_get_drvdata(dev); 527 528 /* select HDQ/1W mode & enable clocks */ 529 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS, 530 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE | 531 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK | 532 hdq_data->mode); 533 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS); 534 535 return 0; 536 } 537 538 static const struct dev_pm_ops omap_hdq_pm_ops = { 539 SET_RUNTIME_PM_OPS(omap_hdq_runtime_suspend, 540 omap_hdq_runtime_resume, NULL) 541 }; 542 543 static int omap_hdq_probe(struct platform_device *pdev) 544 { 545 struct device *dev = &pdev->dev; 546 struct hdq_data *hdq_data; 547 int ret, irq; 548 u8 rev; 549 const char *mode; 550 551 hdq_data = devm_kzalloc(dev, sizeof(*hdq_data), GFP_KERNEL); 552 if (!hdq_data) { 553 dev_dbg(&pdev->dev, "unable to allocate memory\n"); 554 return -ENOMEM; 555 } 556 557 hdq_data->dev = dev; 558 platform_set_drvdata(pdev, hdq_data); 559 560 hdq_data->hdq_base = devm_platform_ioremap_resource(pdev, 0); 561 if (IS_ERR(hdq_data->hdq_base)) 562 return PTR_ERR(hdq_data->hdq_base); 563 564 mutex_init(&hdq_data->hdq_mutex); 565 566 ret = of_property_read_string(pdev->dev.of_node, "ti,mode", &mode); 567 if (ret < 0 || !strcmp(mode, "hdq")) { 568 hdq_data->mode = 0; 569 omap_w1_master.search = omap_w1_search_bus; 570 } else { 571 hdq_data->mode = 1; 572 omap_w1_master.triplet = omap_w1_triplet; 573 } 574 575 pm_runtime_enable(&pdev->dev); 576 pm_runtime_use_autosuspend(&pdev->dev); 577 pm_runtime_set_autosuspend_delay(&pdev->dev, 300); 578 ret = pm_runtime_get_sync(&pdev->dev); 579 if (ret < 0) { 580 pm_runtime_put_noidle(&pdev->dev); 581 dev_dbg(&pdev->dev, "pm_runtime_get_sync failed\n"); 582 goto err_w1; 583 } 584 585 rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION); 586 dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n", 587 (rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt"); 588 589 spin_lock_init(&hdq_data->hdq_spinlock); 590 591 irq = platform_get_irq(pdev, 0); 592 if (irq < 0) { 593 dev_dbg(&pdev->dev, "Failed to get IRQ: %d\n", irq); 594 ret = irq; 595 goto err_irq; 596 } 597 598 ret = devm_request_irq(dev, irq, hdq_isr, 0, "omap_hdq", hdq_data); 599 if (ret < 0) { 600 dev_dbg(&pdev->dev, "could not request irq\n"); 601 goto err_irq; 602 } 603 604 omap_hdq_break(hdq_data); 605 606 pm_runtime_mark_last_busy(&pdev->dev); 607 pm_runtime_put_autosuspend(&pdev->dev); 608 609 omap_w1_master.data = hdq_data; 610 611 ret = w1_add_master_device(&omap_w1_master); 612 if (ret) { 613 dev_dbg(&pdev->dev, "Failure in registering w1 master\n"); 614 goto err_w1; 615 } 616 617 return 0; 618 619 err_irq: 620 pm_runtime_put_sync(&pdev->dev); 621 err_w1: 622 pm_runtime_dont_use_autosuspend(&pdev->dev); 623 pm_runtime_disable(&pdev->dev); 624 625 return ret; 626 } 627 628 static int omap_hdq_remove(struct platform_device *pdev) 629 { 630 int active; 631 632 active = pm_runtime_get_sync(&pdev->dev); 633 if (active < 0) 634 pm_runtime_put_noidle(&pdev->dev); 635 636 w1_remove_master_device(&omap_w1_master); 637 638 pm_runtime_dont_use_autosuspend(&pdev->dev); 639 if (active >= 0) 640 pm_runtime_put_sync(&pdev->dev); 641 pm_runtime_disable(&pdev->dev); 642 643 return 0; 644 } 645 646 static const struct of_device_id omap_hdq_dt_ids[] = { 647 { .compatible = "ti,omap3-1w" }, 648 { .compatible = "ti,am4372-hdq" }, 649 {} 650 }; 651 MODULE_DEVICE_TABLE(of, omap_hdq_dt_ids); 652 653 static struct platform_driver omap_hdq_driver = { 654 .probe = omap_hdq_probe, 655 .remove = omap_hdq_remove, 656 .driver = { 657 .name = "omap_hdq", 658 .of_match_table = omap_hdq_dt_ids, 659 .pm = &omap_hdq_pm_ops, 660 }, 661 }; 662 module_platform_driver(omap_hdq_driver); 663 664 MODULE_AUTHOR("Texas Instruments"); 665 MODULE_DESCRIPTION("HDQ-1W driver Library"); 666 MODULE_LICENSE("GPL"); 667