1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics STM32F7 I2C controller 4 * 5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc 6 * reference manual. 7 * Please see below a link to the documentation: 8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf 9 * 10 * Copyright (C) M'boumba Cedric Madianga 2017 11 * Copyright (C) STMicroelectronics 2017 12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 13 * 14 * This driver is based on i2c-stm32f4.c 15 * 16 */ 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/i2c.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/iopoll.h> 24 #include <linux/mfd/syscon.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/pm_wakeirq.h> 33 #include <linux/regmap.h> 34 #include <linux/reset.h> 35 #include <linux/slab.h> 36 37 #include "i2c-stm32.h" 38 39 /* STM32F7 I2C registers */ 40 #define STM32F7_I2C_CR1 0x00 41 #define STM32F7_I2C_CR2 0x04 42 #define STM32F7_I2C_OAR1 0x08 43 #define STM32F7_I2C_OAR2 0x0C 44 #define STM32F7_I2C_PECR 0x20 45 #define STM32F7_I2C_TIMINGR 0x10 46 #define STM32F7_I2C_ISR 0x18 47 #define STM32F7_I2C_ICR 0x1C 48 #define STM32F7_I2C_RXDR 0x24 49 #define STM32F7_I2C_TXDR 0x28 50 51 /* STM32F7 I2C control 1 */ 52 #define STM32F7_I2C_CR1_PECEN BIT(23) 53 #define STM32F7_I2C_CR1_WUPEN BIT(18) 54 #define STM32F7_I2C_CR1_SBC BIT(16) 55 #define STM32F7_I2C_CR1_RXDMAEN BIT(15) 56 #define STM32F7_I2C_CR1_TXDMAEN BIT(14) 57 #define STM32F7_I2C_CR1_ANFOFF BIT(12) 58 #define STM32F7_I2C_CR1_ERRIE BIT(7) 59 #define STM32F7_I2C_CR1_TCIE BIT(6) 60 #define STM32F7_I2C_CR1_STOPIE BIT(5) 61 #define STM32F7_I2C_CR1_NACKIE BIT(4) 62 #define STM32F7_I2C_CR1_ADDRIE BIT(3) 63 #define STM32F7_I2C_CR1_RXIE BIT(2) 64 #define STM32F7_I2C_CR1_TXIE BIT(1) 65 #define STM32F7_I2C_CR1_PE BIT(0) 66 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \ 67 | STM32F7_I2C_CR1_TCIE \ 68 | STM32F7_I2C_CR1_STOPIE \ 69 | STM32F7_I2C_CR1_NACKIE \ 70 | STM32F7_I2C_CR1_RXIE \ 71 | STM32F7_I2C_CR1_TXIE) 72 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \ 73 | STM32F7_I2C_CR1_STOPIE \ 74 | STM32F7_I2C_CR1_NACKIE \ 75 | STM32F7_I2C_CR1_RXIE \ 76 | STM32F7_I2C_CR1_TXIE) 77 78 /* STM32F7 I2C control 2 */ 79 #define STM32F7_I2C_CR2_PECBYTE BIT(26) 80 #define STM32F7_I2C_CR2_RELOAD BIT(24) 81 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 82 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16) 83 #define STM32F7_I2C_CR2_NACK BIT(15) 84 #define STM32F7_I2C_CR2_STOP BIT(14) 85 #define STM32F7_I2C_CR2_START BIT(13) 86 #define STM32F7_I2C_CR2_HEAD10R BIT(12) 87 #define STM32F7_I2C_CR2_ADD10 BIT(11) 88 #define STM32F7_I2C_CR2_RD_WRN BIT(10) 89 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0) 90 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \ 91 STM32F7_I2C_CR2_SADD10_MASK)) 92 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1) 93 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1) 94 95 /* STM32F7 I2C Own Address 1 */ 96 #define STM32F7_I2C_OAR1_OA1EN BIT(15) 97 #define STM32F7_I2C_OAR1_OA1MODE BIT(10) 98 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0) 99 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \ 100 STM32F7_I2C_OAR1_OA1_10_MASK)) 101 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1) 102 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1) 103 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \ 104 | STM32F7_I2C_OAR1_OA1_10_MASK \ 105 | STM32F7_I2C_OAR1_OA1EN \ 106 | STM32F7_I2C_OAR1_OA1MODE) 107 108 /* STM32F7 I2C Own Address 2 */ 109 #define STM32F7_I2C_OAR2_OA2EN BIT(15) 110 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8) 111 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8) 112 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1) 113 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1) 114 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \ 115 | STM32F7_I2C_OAR2_OA2_7_MASK \ 116 | STM32F7_I2C_OAR2_OA2EN) 117 118 /* STM32F7 I2C Interrupt Status */ 119 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17) 120 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \ 121 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17) 122 #define STM32F7_I2C_ISR_DIR BIT(16) 123 #define STM32F7_I2C_ISR_BUSY BIT(15) 124 #define STM32F7_I2C_ISR_PECERR BIT(11) 125 #define STM32F7_I2C_ISR_ARLO BIT(9) 126 #define STM32F7_I2C_ISR_BERR BIT(8) 127 #define STM32F7_I2C_ISR_TCR BIT(7) 128 #define STM32F7_I2C_ISR_TC BIT(6) 129 #define STM32F7_I2C_ISR_STOPF BIT(5) 130 #define STM32F7_I2C_ISR_NACKF BIT(4) 131 #define STM32F7_I2C_ISR_ADDR BIT(3) 132 #define STM32F7_I2C_ISR_RXNE BIT(2) 133 #define STM32F7_I2C_ISR_TXIS BIT(1) 134 #define STM32F7_I2C_ISR_TXE BIT(0) 135 136 /* STM32F7 I2C Interrupt Clear */ 137 #define STM32F7_I2C_ICR_PECCF BIT(11) 138 #define STM32F7_I2C_ICR_ARLOCF BIT(9) 139 #define STM32F7_I2C_ICR_BERRCF BIT(8) 140 #define STM32F7_I2C_ICR_STOPCF BIT(5) 141 #define STM32F7_I2C_ICR_NACKCF BIT(4) 142 #define STM32F7_I2C_ICR_ADDRCF BIT(3) 143 144 /* STM32F7 I2C Timing */ 145 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28) 146 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20) 147 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16) 148 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8) 149 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff) 150 151 #define STM32F7_I2C_MAX_LEN 0xff 152 #define STM32F7_I2C_DMA_LEN_MIN 0x16 153 #define STM32F7_I2C_MAX_SLAVE 0x2 154 155 #define STM32F7_I2C_DNF_DEFAULT 0 156 #define STM32F7_I2C_DNF_MAX 16 157 158 #define STM32F7_I2C_ANALOG_FILTER_ENABLE 1 159 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 160 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 161 162 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */ 163 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */ 164 165 #define STM32F7_PRESC_MAX BIT(4) 166 #define STM32F7_SCLDEL_MAX BIT(4) 167 #define STM32F7_SDADEL_MAX BIT(4) 168 #define STM32F7_SCLH_MAX BIT(8) 169 #define STM32F7_SCLL_MAX BIT(8) 170 171 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100) 172 173 /** 174 * struct stm32f7_i2c_regs - i2c f7 registers backup 175 * @cr1: Control register 1 176 * @cr2: Control register 2 177 * @oar1: Own address 1 register 178 * @oar2: Own address 2 register 179 * @tmgr: Timing register 180 */ 181 struct stm32f7_i2c_regs { 182 u32 cr1; 183 u32 cr2; 184 u32 oar1; 185 u32 oar2; 186 u32 tmgr; 187 }; 188 189 /** 190 * struct stm32f7_i2c_spec - private i2c specification timing 191 * @rate: I2C bus speed (Hz) 192 * @fall_max: Max fall time of both SDA and SCL signals (ns) 193 * @rise_max: Max rise time of both SDA and SCL signals (ns) 194 * @hddat_min: Min data hold time (ns) 195 * @vddat_max: Max data valid time (ns) 196 * @sudat_min: Min data setup time (ns) 197 * @l_min: Min low period of the SCL clock (ns) 198 * @h_min: Min high period of the SCL clock (ns) 199 */ 200 struct stm32f7_i2c_spec { 201 u32 rate; 202 u32 fall_max; 203 u32 rise_max; 204 u32 hddat_min; 205 u32 vddat_max; 206 u32 sudat_min; 207 u32 l_min; 208 u32 h_min; 209 }; 210 211 /** 212 * struct stm32f7_i2c_setup - private I2C timing setup parameters 213 * @speed_freq: I2C speed frequency (Hz) 214 * @clock_src: I2C clock source frequency (Hz) 215 * @rise_time: Rise time (ns) 216 * @fall_time: Fall time (ns) 217 * @dnf: Digital filter coefficient (0-16) 218 * @analog_filter: Analog filter delay (On/Off) 219 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register 220 */ 221 struct stm32f7_i2c_setup { 222 u32 speed_freq; 223 u32 clock_src; 224 u32 rise_time; 225 u32 fall_time; 226 u8 dnf; 227 bool analog_filter; 228 u32 fmp_clr_offset; 229 }; 230 231 /** 232 * struct stm32f7_i2c_timings - private I2C output parameters 233 * @node: List entry 234 * @presc: Prescaler value 235 * @scldel: Data setup time 236 * @sdadel: Data hold time 237 * @sclh: SCL high period (master mode) 238 * @scll: SCL low period (master mode) 239 */ 240 struct stm32f7_i2c_timings { 241 struct list_head node; 242 u8 presc; 243 u8 scldel; 244 u8 sdadel; 245 u8 sclh; 246 u8 scll; 247 }; 248 249 /** 250 * struct stm32f7_i2c_msg - client specific data 251 * @addr: 8-bit or 10-bit slave addr, including r/w bit 252 * @count: number of bytes to be transferred 253 * @buf: data buffer 254 * @result: result of the transfer 255 * @stop: last I2C msg to be sent, i.e. STOP to be generated 256 * @smbus: boolean to know if the I2C IP is used in SMBus mode 257 * @size: type of SMBus protocol 258 * @read_write: direction of SMBus protocol 259 * SMBus block read and SMBus block write - block read process call protocols 260 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will 261 * contain a maximum of 32 bytes of data + byte command + byte count + PEC 262 * This buffer has to be 32-bit aligned to be compliant with memory address 263 * register in DMA mode. 264 */ 265 struct stm32f7_i2c_msg { 266 u16 addr; 267 u32 count; 268 u8 *buf; 269 int result; 270 bool stop; 271 bool smbus; 272 int size; 273 char read_write; 274 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4); 275 }; 276 277 /** 278 * struct stm32f7_i2c_dev - private data of the controller 279 * @adap: I2C adapter for this controller 280 * @dev: device for this controller 281 * @base: virtual memory area 282 * @complete: completion of I2C message 283 * @clk: hw i2c clock 284 * @bus_rate: I2C clock frequency of the controller 285 * @msg: Pointer to data to be written 286 * @msg_num: number of I2C messages to be executed 287 * @msg_id: message identifiant 288 * @f7_msg: customized i2c msg for driver usage 289 * @setup: I2C timing input setup 290 * @timing: I2C computed timings 291 * @slave: list of slave devices registered on the I2C bus 292 * @slave_running: slave device currently used 293 * @backup_regs: backup of i2c controller registers (for suspend/resume) 294 * @slave_dir: transfer direction for the current slave device 295 * @master_mode: boolean to know in which mode the I2C is running (master or 296 * slave) 297 * @dma: dma data 298 * @use_dma: boolean to know if dma is used in the current transfer 299 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits 300 * @fmp_sreg: register address for setting Fast Mode Plus bits 301 * @fmp_creg: register address for clearing Fast Mode Plus bits 302 * @fmp_mask: mask for Fast Mode Plus bits in set register 303 * @wakeup_src: boolean to know if the device is a wakeup source 304 */ 305 struct stm32f7_i2c_dev { 306 struct i2c_adapter adap; 307 struct device *dev; 308 void __iomem *base; 309 struct completion complete; 310 struct clk *clk; 311 unsigned int bus_rate; 312 struct i2c_msg *msg; 313 unsigned int msg_num; 314 unsigned int msg_id; 315 struct stm32f7_i2c_msg f7_msg; 316 struct stm32f7_i2c_setup setup; 317 struct stm32f7_i2c_timings timing; 318 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE]; 319 struct i2c_client *slave_running; 320 struct stm32f7_i2c_regs backup_regs; 321 u32 slave_dir; 322 bool master_mode; 323 struct stm32_i2c_dma *dma; 324 bool use_dma; 325 struct regmap *regmap; 326 u32 fmp_sreg; 327 u32 fmp_creg; 328 u32 fmp_mask; 329 bool wakeup_src; 330 }; 331 332 /* 333 * All these values are coming from I2C Specification, Version 6.0, 4th of 334 * April 2014. 335 * 336 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast, 337 * and Fast-mode Plus I2C-bus devices 338 */ 339 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = { 340 { 341 .rate = I2C_MAX_STANDARD_MODE_FREQ, 342 .fall_max = 300, 343 .rise_max = 1000, 344 .hddat_min = 0, 345 .vddat_max = 3450, 346 .sudat_min = 250, 347 .l_min = 4700, 348 .h_min = 4000, 349 }, 350 { 351 .rate = I2C_MAX_FAST_MODE_FREQ, 352 .fall_max = 300, 353 .rise_max = 300, 354 .hddat_min = 0, 355 .vddat_max = 900, 356 .sudat_min = 100, 357 .l_min = 1300, 358 .h_min = 600, 359 }, 360 { 361 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ, 362 .fall_max = 100, 363 .rise_max = 120, 364 .hddat_min = 0, 365 .vddat_max = 450, 366 .sudat_min = 50, 367 .l_min = 500, 368 .h_min = 260, 369 }, 370 }; 371 372 static const struct stm32f7_i2c_setup stm32f7_setup = { 373 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 374 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 375 .dnf = STM32F7_I2C_DNF_DEFAULT, 376 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE, 377 }; 378 379 static const struct stm32f7_i2c_setup stm32mp15_setup = { 380 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 381 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 382 .dnf = STM32F7_I2C_DNF_DEFAULT, 383 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE, 384 .fmp_clr_offset = 0x40, 385 }; 386 387 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask) 388 { 389 writel_relaxed(readl_relaxed(reg) | mask, reg); 390 } 391 392 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask) 393 { 394 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 395 } 396 397 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask) 398 { 399 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); 400 } 401 402 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate) 403 { 404 int i; 405 406 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++) 407 if (rate <= stm32f7_i2c_specs[i].rate) 408 return &stm32f7_i2c_specs[i]; 409 410 return ERR_PTR(-EINVAL); 411 } 412 413 #define RATE_MIN(rate) ((rate) * 8 / 10) 414 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev, 415 struct stm32f7_i2c_setup *setup, 416 struct stm32f7_i2c_timings *output) 417 { 418 struct stm32f7_i2c_spec *specs; 419 u32 p_prev = STM32F7_PRESC_MAX; 420 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 421 setup->clock_src); 422 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 423 setup->speed_freq); 424 u32 clk_error_prev = i2cbus; 425 u32 tsync; 426 u32 af_delay_min, af_delay_max; 427 u32 dnf_delay; 428 u32 clk_min, clk_max; 429 int sdadel_min, sdadel_max; 430 int scldel_min; 431 struct stm32f7_i2c_timings *v, *_v, *s; 432 struct list_head solutions; 433 u16 p, l, a, h; 434 int ret = 0; 435 436 specs = stm32f7_get_specs(setup->speed_freq); 437 if (specs == ERR_PTR(-EINVAL)) { 438 dev_err(i2c_dev->dev, "speed out of bound {%d}\n", 439 setup->speed_freq); 440 return -EINVAL; 441 } 442 443 if ((setup->rise_time > specs->rise_max) || 444 (setup->fall_time > specs->fall_max)) { 445 dev_err(i2c_dev->dev, 446 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", 447 setup->rise_time, specs->rise_max, 448 setup->fall_time, specs->fall_max); 449 return -EINVAL; 450 } 451 452 if (setup->dnf > STM32F7_I2C_DNF_MAX) { 453 dev_err(i2c_dev->dev, 454 "DNF out of bound %d/%d\n", 455 setup->dnf, STM32F7_I2C_DNF_MAX); 456 return -EINVAL; 457 } 458 459 /* Analog and Digital Filters */ 460 af_delay_min = 461 (setup->analog_filter ? 462 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0); 463 af_delay_max = 464 (setup->analog_filter ? 465 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0); 466 dnf_delay = setup->dnf * i2cclk; 467 468 sdadel_min = specs->hddat_min + setup->fall_time - 469 af_delay_min - (setup->dnf + 3) * i2cclk; 470 471 sdadel_max = specs->vddat_max - setup->rise_time - 472 af_delay_max - (setup->dnf + 4) * i2cclk; 473 474 scldel_min = setup->rise_time + specs->sudat_min; 475 476 if (sdadel_min < 0) 477 sdadel_min = 0; 478 if (sdadel_max < 0) 479 sdadel_max = 0; 480 481 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", 482 sdadel_min, sdadel_max, scldel_min); 483 484 INIT_LIST_HEAD(&solutions); 485 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 486 for (p = 0; p < STM32F7_PRESC_MAX; p++) { 487 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) { 488 u32 scldel = (l + 1) * (p + 1) * i2cclk; 489 490 if (scldel < scldel_min) 491 continue; 492 493 for (a = 0; a < STM32F7_SDADEL_MAX; a++) { 494 u32 sdadel = (a * (p + 1) + 1) * i2cclk; 495 496 if (((sdadel >= sdadel_min) && 497 (sdadel <= sdadel_max)) && 498 (p != p_prev)) { 499 v = kmalloc(sizeof(*v), GFP_KERNEL); 500 if (!v) { 501 ret = -ENOMEM; 502 goto exit; 503 } 504 505 v->presc = p; 506 v->scldel = l; 507 v->sdadel = a; 508 p_prev = p; 509 510 list_add_tail(&v->node, 511 &solutions); 512 break; 513 } 514 } 515 516 if (p_prev == p) 517 break; 518 } 519 } 520 521 if (list_empty(&solutions)) { 522 dev_err(i2c_dev->dev, "no Prescaler solution\n"); 523 ret = -EPERM; 524 goto exit; 525 } 526 527 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 528 s = NULL; 529 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq); 530 clk_min = NSEC_PER_SEC / setup->speed_freq; 531 532 /* 533 * Among Prescaler possibilities discovered above figures out SCL Low 534 * and High Period. Provided: 535 * - SCL Low Period has to be higher than SCL Clock Low Period 536 * defined by I2C Specification. I2C Clock has to be lower than 537 * (SCL Low Period - Analog/Digital filters) / 4. 538 * - SCL High Period has to be lower than SCL Clock High Period 539 * defined by I2C Specification 540 * - I2C Clock has to be lower than SCL High Period 541 */ 542 list_for_each_entry(v, &solutions, node) { 543 u32 prescaler = (v->presc + 1) * i2cclk; 544 545 for (l = 0; l < STM32F7_SCLL_MAX; l++) { 546 u32 tscl_l = (l + 1) * prescaler + tsync; 547 548 if ((tscl_l < specs->l_min) || 549 (i2cclk >= 550 ((tscl_l - af_delay_min - dnf_delay) / 4))) { 551 continue; 552 } 553 554 for (h = 0; h < STM32F7_SCLH_MAX; h++) { 555 u32 tscl_h = (h + 1) * prescaler + tsync; 556 u32 tscl = tscl_l + tscl_h + 557 setup->rise_time + setup->fall_time; 558 559 if ((tscl >= clk_min) && (tscl <= clk_max) && 560 (tscl_h >= specs->h_min) && 561 (i2cclk < tscl_h)) { 562 int clk_error = tscl - i2cbus; 563 564 if (clk_error < 0) 565 clk_error = -clk_error; 566 567 if (clk_error < clk_error_prev) { 568 clk_error_prev = clk_error; 569 v->scll = l; 570 v->sclh = h; 571 s = v; 572 } 573 } 574 } 575 } 576 } 577 578 if (!s) { 579 dev_err(i2c_dev->dev, "no solution at all\n"); 580 ret = -EPERM; 581 goto exit; 582 } 583 584 output->presc = s->presc; 585 output->scldel = s->scldel; 586 output->sdadel = s->sdadel; 587 output->scll = s->scll; 588 output->sclh = s->sclh; 589 590 dev_dbg(i2c_dev->dev, 591 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", 592 output->presc, 593 output->scldel, output->sdadel, 594 output->scll, output->sclh); 595 596 exit: 597 /* Release list and memory */ 598 list_for_each_entry_safe(v, _v, &solutions, node) { 599 list_del(&v->node); 600 kfree(v); 601 } 602 603 return ret; 604 } 605 606 static u32 stm32f7_get_lower_rate(u32 rate) 607 { 608 int i = ARRAY_SIZE(stm32f7_i2c_specs); 609 610 while (--i) 611 if (stm32f7_i2c_specs[i].rate < rate) 612 break; 613 614 return stm32f7_i2c_specs[i].rate; 615 } 616 617 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev, 618 struct stm32f7_i2c_setup *setup) 619 { 620 struct i2c_timings timings, *t = &timings; 621 int ret = 0; 622 623 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 624 t->scl_rise_ns = i2c_dev->setup.rise_time; 625 t->scl_fall_ns = i2c_dev->setup.fall_time; 626 627 i2c_parse_fw_timings(i2c_dev->dev, t, false); 628 629 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { 630 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n", 631 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ); 632 return -EINVAL; 633 } 634 635 setup->speed_freq = t->bus_freq_hz; 636 i2c_dev->setup.rise_time = t->scl_rise_ns; 637 i2c_dev->setup.fall_time = t->scl_fall_ns; 638 setup->clock_src = clk_get_rate(i2c_dev->clk); 639 640 if (!setup->clock_src) { 641 dev_err(i2c_dev->dev, "clock rate is 0\n"); 642 return -EINVAL; 643 } 644 645 do { 646 ret = stm32f7_i2c_compute_timing(i2c_dev, setup, 647 &i2c_dev->timing); 648 if (ret) { 649 dev_err(i2c_dev->dev, 650 "failed to compute I2C timings.\n"); 651 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ) 652 break; 653 setup->speed_freq = 654 stm32f7_get_lower_rate(setup->speed_freq); 655 dev_warn(i2c_dev->dev, 656 "downgrade I2C Speed Freq to (%i)\n", 657 setup->speed_freq); 658 } 659 } while (ret); 660 661 if (ret) { 662 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n"); 663 return ret; 664 } 665 666 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n", 667 setup->speed_freq, setup->clock_src); 668 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", 669 setup->rise_time, setup->fall_time); 670 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", 671 (setup->analog_filter ? "On" : "Off"), setup->dnf); 672 673 i2c_dev->bus_rate = setup->speed_freq; 674 675 return 0; 676 } 677 678 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev) 679 { 680 void __iomem *base = i2c_dev->base; 681 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN; 682 683 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 684 } 685 686 static void stm32f7_i2c_dma_callback(void *arg) 687 { 688 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg; 689 struct stm32_i2c_dma *dma = i2c_dev->dma; 690 struct device *dev = dma->chan_using->device->dev; 691 692 stm32f7_i2c_disable_dma_req(i2c_dev); 693 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir); 694 complete(&dma->dma_complete); 695 } 696 697 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev) 698 { 699 struct stm32f7_i2c_timings *t = &i2c_dev->timing; 700 u32 timing = 0; 701 702 /* Timing settings */ 703 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); 704 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); 705 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); 706 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); 707 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); 708 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); 709 710 /* Enable I2C */ 711 if (i2c_dev->setup.analog_filter) 712 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 713 STM32F7_I2C_CR1_ANFOFF); 714 else 715 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 716 STM32F7_I2C_CR1_ANFOFF); 717 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 718 STM32F7_I2C_CR1_PE); 719 } 720 721 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev) 722 { 723 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 724 void __iomem *base = i2c_dev->base; 725 726 if (f7_msg->count) { 727 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); 728 f7_msg->count--; 729 } 730 } 731 732 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev) 733 { 734 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 735 void __iomem *base = i2c_dev->base; 736 737 if (f7_msg->count) { 738 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); 739 f7_msg->count--; 740 } else { 741 /* Flush RX buffer has no data is expected */ 742 readb_relaxed(base + STM32F7_I2C_RXDR); 743 } 744 } 745 746 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev) 747 { 748 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 749 u32 cr2; 750 751 if (i2c_dev->use_dma) 752 f7_msg->count -= STM32F7_I2C_MAX_LEN; 753 754 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 755 756 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK; 757 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 758 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 759 } else { 760 cr2 &= ~STM32F7_I2C_CR2_RELOAD; 761 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 762 } 763 764 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 765 } 766 767 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev) 768 { 769 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 770 u32 cr2; 771 u8 *val; 772 773 /* 774 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first 775 * data received inform us how many data will follow. 776 */ 777 stm32f7_i2c_read_rx_data(i2c_dev); 778 779 /* 780 * Update NBYTES with the value read to continue the transfer 781 */ 782 val = f7_msg->buf - sizeof(u8); 783 f7_msg->count = *val; 784 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 785 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 786 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 787 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 788 } 789 790 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap) 791 { 792 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 793 794 dev_info(i2c_dev->dev, "Trying to recover bus\n"); 795 796 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 797 STM32F7_I2C_CR1_PE); 798 799 stm32f7_i2c_hw_config(i2c_dev); 800 801 return 0; 802 } 803 804 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev) 805 { 806 u32 status; 807 int ret; 808 809 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, 810 status, 811 !(status & STM32F7_I2C_ISR_BUSY), 812 10, 1000); 813 if (!ret) 814 return 0; 815 816 dev_info(i2c_dev->dev, "bus busy\n"); 817 818 ret = stm32f7_i2c_release_bus(&i2c_dev->adap); 819 if (ret) { 820 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret); 821 return ret; 822 } 823 824 return -EBUSY; 825 } 826 827 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 828 struct i2c_msg *msg) 829 { 830 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 831 void __iomem *base = i2c_dev->base; 832 u32 cr1, cr2; 833 int ret; 834 835 f7_msg->addr = msg->addr; 836 f7_msg->buf = msg->buf; 837 f7_msg->count = msg->len; 838 f7_msg->result = 0; 839 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); 840 841 reinit_completion(&i2c_dev->complete); 842 843 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 844 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 845 846 /* Set transfer direction */ 847 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 848 if (msg->flags & I2C_M_RD) 849 cr2 |= STM32F7_I2C_CR2_RD_WRN; 850 851 /* Set slave address */ 852 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10); 853 if (msg->flags & I2C_M_TEN) { 854 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK; 855 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr); 856 cr2 |= STM32F7_I2C_CR2_ADD10; 857 } else { 858 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK; 859 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 860 } 861 862 /* Set nb bytes to transfer and reload if needed */ 863 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 864 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 865 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 866 cr2 |= STM32F7_I2C_CR2_RELOAD; 867 } else { 868 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 869 } 870 871 /* Enable NACK, STOP, error and transfer complete interrupts */ 872 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 873 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 874 875 /* Clear DMA req and TX/RX interrupt */ 876 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 877 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 878 879 /* Configure DMA or enable RX/TX interrupt */ 880 i2c_dev->use_dma = false; 881 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 882 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 883 msg->flags & I2C_M_RD, 884 f7_msg->count, f7_msg->buf, 885 stm32f7_i2c_dma_callback, 886 i2c_dev); 887 if (!ret) 888 i2c_dev->use_dma = true; 889 else 890 dev_warn(i2c_dev->dev, "can't use DMA\n"); 891 } 892 893 if (!i2c_dev->use_dma) { 894 if (msg->flags & I2C_M_RD) 895 cr1 |= STM32F7_I2C_CR1_RXIE; 896 else 897 cr1 |= STM32F7_I2C_CR1_TXIE; 898 } else { 899 if (msg->flags & I2C_M_RD) 900 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 901 else 902 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 903 } 904 905 /* Configure Start/Repeated Start */ 906 cr2 |= STM32F7_I2C_CR2_START; 907 908 i2c_dev->master_mode = true; 909 910 /* Write configurations registers */ 911 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 912 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 913 } 914 915 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 916 unsigned short flags, u8 command, 917 union i2c_smbus_data *data) 918 { 919 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 920 struct device *dev = i2c_dev->dev; 921 void __iomem *base = i2c_dev->base; 922 u32 cr1, cr2; 923 int i, ret; 924 925 f7_msg->result = 0; 926 reinit_completion(&i2c_dev->complete); 927 928 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 929 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 930 931 /* Set transfer direction */ 932 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 933 if (f7_msg->read_write) 934 cr2 |= STM32F7_I2C_CR2_RD_WRN; 935 936 /* Set slave address */ 937 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK); 938 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 939 940 f7_msg->smbus_buf[0] = command; 941 switch (f7_msg->size) { 942 case I2C_SMBUS_QUICK: 943 f7_msg->stop = true; 944 f7_msg->count = 0; 945 break; 946 case I2C_SMBUS_BYTE: 947 f7_msg->stop = true; 948 f7_msg->count = 1; 949 break; 950 case I2C_SMBUS_BYTE_DATA: 951 if (f7_msg->read_write) { 952 f7_msg->stop = false; 953 f7_msg->count = 1; 954 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 955 } else { 956 f7_msg->stop = true; 957 f7_msg->count = 2; 958 f7_msg->smbus_buf[1] = data->byte; 959 } 960 break; 961 case I2C_SMBUS_WORD_DATA: 962 if (f7_msg->read_write) { 963 f7_msg->stop = false; 964 f7_msg->count = 1; 965 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 966 } else { 967 f7_msg->stop = true; 968 f7_msg->count = 3; 969 f7_msg->smbus_buf[1] = data->word & 0xff; 970 f7_msg->smbus_buf[2] = data->word >> 8; 971 } 972 break; 973 case I2C_SMBUS_BLOCK_DATA: 974 if (f7_msg->read_write) { 975 f7_msg->stop = false; 976 f7_msg->count = 1; 977 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 978 } else { 979 f7_msg->stop = true; 980 if (data->block[0] > I2C_SMBUS_BLOCK_MAX || 981 !data->block[0]) { 982 dev_err(dev, "Invalid block write size %d\n", 983 data->block[0]); 984 return -EINVAL; 985 } 986 f7_msg->count = data->block[0] + 2; 987 for (i = 1; i < f7_msg->count; i++) 988 f7_msg->smbus_buf[i] = data->block[i - 1]; 989 } 990 break; 991 case I2C_SMBUS_PROC_CALL: 992 f7_msg->stop = false; 993 f7_msg->count = 3; 994 f7_msg->smbus_buf[1] = data->word & 0xff; 995 f7_msg->smbus_buf[2] = data->word >> 8; 996 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 997 f7_msg->read_write = I2C_SMBUS_READ; 998 break; 999 case I2C_SMBUS_BLOCK_PROC_CALL: 1000 f7_msg->stop = false; 1001 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) { 1002 dev_err(dev, "Invalid block write size %d\n", 1003 data->block[0]); 1004 return -EINVAL; 1005 } 1006 f7_msg->count = data->block[0] + 2; 1007 for (i = 1; i < f7_msg->count; i++) 1008 f7_msg->smbus_buf[i] = data->block[i - 1]; 1009 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1010 f7_msg->read_write = I2C_SMBUS_READ; 1011 break; 1012 case I2C_SMBUS_I2C_BLOCK_DATA: 1013 /* Rely on emulated i2c transfer (through master_xfer) */ 1014 return -EOPNOTSUPP; 1015 default: 1016 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size); 1017 return -EOPNOTSUPP; 1018 } 1019 1020 f7_msg->buf = f7_msg->smbus_buf; 1021 1022 /* Configure PEC */ 1023 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { 1024 cr1 |= STM32F7_I2C_CR1_PECEN; 1025 cr2 |= STM32F7_I2C_CR2_PECBYTE; 1026 if (!f7_msg->read_write) 1027 f7_msg->count++; 1028 } else { 1029 cr1 &= ~STM32F7_I2C_CR1_PECEN; 1030 cr2 &= ~STM32F7_I2C_CR2_PECBYTE; 1031 } 1032 1033 /* Set number of bytes to be transferred */ 1034 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 1035 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1036 1037 /* Enable NACK, STOP, error and transfer complete interrupts */ 1038 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 1039 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 1040 1041 /* Clear DMA req and TX/RX interrupt */ 1042 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1043 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1044 1045 /* Configure DMA or enable RX/TX interrupt */ 1046 i2c_dev->use_dma = false; 1047 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 1048 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1049 cr2 & STM32F7_I2C_CR2_RD_WRN, 1050 f7_msg->count, f7_msg->buf, 1051 stm32f7_i2c_dma_callback, 1052 i2c_dev); 1053 if (!ret) 1054 i2c_dev->use_dma = true; 1055 else 1056 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1057 } 1058 1059 if (!i2c_dev->use_dma) { 1060 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1061 cr1 |= STM32F7_I2C_CR1_RXIE; 1062 else 1063 cr1 |= STM32F7_I2C_CR1_TXIE; 1064 } else { 1065 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1066 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1067 else 1068 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 1069 } 1070 1071 /* Set Start bit */ 1072 cr2 |= STM32F7_I2C_CR2_START; 1073 1074 i2c_dev->master_mode = true; 1075 1076 /* Write configurations registers */ 1077 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1078 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1079 1080 return 0; 1081 } 1082 1083 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev) 1084 { 1085 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1086 void __iomem *base = i2c_dev->base; 1087 u32 cr1, cr2; 1088 int ret; 1089 1090 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 1091 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 1092 1093 /* Set transfer direction */ 1094 cr2 |= STM32F7_I2C_CR2_RD_WRN; 1095 1096 switch (f7_msg->size) { 1097 case I2C_SMBUS_BYTE_DATA: 1098 f7_msg->count = 1; 1099 break; 1100 case I2C_SMBUS_WORD_DATA: 1101 case I2C_SMBUS_PROC_CALL: 1102 f7_msg->count = 2; 1103 break; 1104 case I2C_SMBUS_BLOCK_DATA: 1105 case I2C_SMBUS_BLOCK_PROC_CALL: 1106 f7_msg->count = 1; 1107 cr2 |= STM32F7_I2C_CR2_RELOAD; 1108 break; 1109 } 1110 1111 f7_msg->buf = f7_msg->smbus_buf; 1112 f7_msg->stop = true; 1113 1114 /* Add one byte for PEC if needed */ 1115 if (cr1 & STM32F7_I2C_CR1_PECEN) 1116 f7_msg->count++; 1117 1118 /* Set number of bytes to be transferred */ 1119 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK); 1120 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1121 1122 /* 1123 * Configure RX/TX interrupt: 1124 */ 1125 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE); 1126 cr1 |= STM32F7_I2C_CR1_RXIE; 1127 1128 /* 1129 * Configure DMA or enable RX/TX interrupt: 1130 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use 1131 * dma as we don't know in advance how many data will be received 1132 */ 1133 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1134 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1135 1136 i2c_dev->use_dma = false; 1137 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN && 1138 f7_msg->size != I2C_SMBUS_BLOCK_DATA && 1139 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) { 1140 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1141 cr2 & STM32F7_I2C_CR2_RD_WRN, 1142 f7_msg->count, f7_msg->buf, 1143 stm32f7_i2c_dma_callback, 1144 i2c_dev); 1145 1146 if (!ret) 1147 i2c_dev->use_dma = true; 1148 else 1149 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1150 } 1151 1152 if (!i2c_dev->use_dma) 1153 cr1 |= STM32F7_I2C_CR1_RXIE; 1154 else 1155 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1156 1157 /* Configure Repeated Start */ 1158 cr2 |= STM32F7_I2C_CR2_START; 1159 1160 /* Write configurations registers */ 1161 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1162 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1163 } 1164 1165 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev) 1166 { 1167 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1168 u8 count, internal_pec, received_pec; 1169 1170 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); 1171 1172 switch (f7_msg->size) { 1173 case I2C_SMBUS_BYTE: 1174 case I2C_SMBUS_BYTE_DATA: 1175 received_pec = f7_msg->smbus_buf[1]; 1176 break; 1177 case I2C_SMBUS_WORD_DATA: 1178 case I2C_SMBUS_PROC_CALL: 1179 received_pec = f7_msg->smbus_buf[2]; 1180 break; 1181 case I2C_SMBUS_BLOCK_DATA: 1182 case I2C_SMBUS_BLOCK_PROC_CALL: 1183 count = f7_msg->smbus_buf[0]; 1184 received_pec = f7_msg->smbus_buf[count]; 1185 break; 1186 default: 1187 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n"); 1188 return -EINVAL; 1189 } 1190 1191 if (internal_pec != received_pec) { 1192 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n", 1193 internal_pec, received_pec); 1194 return -EBADMSG; 1195 } 1196 1197 return 0; 1198 } 1199 1200 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode) 1201 { 1202 u32 addr; 1203 1204 if (!slave) 1205 return false; 1206 1207 if (slave->flags & I2C_CLIENT_TEN) { 1208 /* 1209 * For 10-bit addr, addcode = 11110XY with 1210 * X = Bit 9 of slave address 1211 * Y = Bit 8 of slave address 1212 */ 1213 addr = slave->addr >> 8; 1214 addr |= 0x78; 1215 if (addr == addcode) 1216 return true; 1217 } else { 1218 addr = slave->addr & 0x7f; 1219 if (addr == addcode) 1220 return true; 1221 } 1222 1223 return false; 1224 } 1225 1226 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev) 1227 { 1228 struct i2c_client *slave = i2c_dev->slave_running; 1229 void __iomem *base = i2c_dev->base; 1230 u32 mask; 1231 u8 value = 0; 1232 1233 if (i2c_dev->slave_dir) { 1234 /* Notify i2c slave that new read transfer is starting */ 1235 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1236 1237 /* 1238 * Disable slave TX config in case of I2C combined message 1239 * (I2C Write followed by I2C Read) 1240 */ 1241 mask = STM32F7_I2C_CR2_RELOAD; 1242 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask); 1243 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1244 STM32F7_I2C_CR1_TCIE; 1245 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1246 1247 /* Enable TX empty, STOP, NACK interrupts */ 1248 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1249 STM32F7_I2C_CR1_TXIE; 1250 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1251 1252 /* Write 1st data byte */ 1253 writel_relaxed(value, base + STM32F7_I2C_TXDR); 1254 } else { 1255 /* Notify i2c slave that new write transfer is starting */ 1256 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1257 1258 /* Set reload mode to be able to ACK/NACK each received byte */ 1259 mask = STM32F7_I2C_CR2_RELOAD; 1260 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1261 1262 /* 1263 * Set STOP, NACK, RX empty and transfer complete interrupts.* 1264 * Set Slave Byte Control to be able to ACK/NACK each data 1265 * byte received 1266 */ 1267 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1268 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1269 STM32F7_I2C_CR1_TCIE; 1270 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1271 } 1272 } 1273 1274 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev) 1275 { 1276 void __iomem *base = i2c_dev->base; 1277 u32 isr, addcode, dir, mask; 1278 int i; 1279 1280 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1281 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr); 1282 dir = isr & STM32F7_I2C_ISR_DIR; 1283 1284 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1285 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) { 1286 i2c_dev->slave_running = i2c_dev->slave[i]; 1287 i2c_dev->slave_dir = dir; 1288 1289 /* Start I2C slave processing */ 1290 stm32f7_i2c_slave_start(i2c_dev); 1291 1292 /* Clear ADDR flag */ 1293 mask = STM32F7_I2C_ICR_ADDRCF; 1294 writel_relaxed(mask, base + STM32F7_I2C_ICR); 1295 break; 1296 } 1297 } 1298 } 1299 1300 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1301 struct i2c_client *slave, int *id) 1302 { 1303 int i; 1304 1305 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1306 if (i2c_dev->slave[i] == slave) { 1307 *id = i; 1308 return 0; 1309 } 1310 } 1311 1312 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr); 1313 1314 return -ENODEV; 1315 } 1316 1317 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1318 struct i2c_client *slave, int *id) 1319 { 1320 struct device *dev = i2c_dev->dev; 1321 int i; 1322 1323 /* 1324 * slave[0] supports 7-bit and 10-bit slave address 1325 * slave[1] supports 7-bit slave address only 1326 */ 1327 for (i = STM32F7_I2C_MAX_SLAVE - 1; i >= 0; i--) { 1328 if (i == 1 && (slave->flags & I2C_CLIENT_TEN)) 1329 continue; 1330 if (!i2c_dev->slave[i]) { 1331 *id = i; 1332 return 0; 1333 } 1334 } 1335 1336 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr); 1337 1338 return -EINVAL; 1339 } 1340 1341 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev) 1342 { 1343 int i; 1344 1345 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1346 if (i2c_dev->slave[i]) 1347 return true; 1348 } 1349 1350 return false; 1351 } 1352 1353 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev) 1354 { 1355 int i, busy; 1356 1357 busy = 0; 1358 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1359 if (i2c_dev->slave[i]) 1360 busy++; 1361 } 1362 1363 return i == busy; 1364 } 1365 1366 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev) 1367 { 1368 void __iomem *base = i2c_dev->base; 1369 u32 cr2, status, mask; 1370 u8 val; 1371 int ret; 1372 1373 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1374 1375 /* Slave transmitter mode */ 1376 if (status & STM32F7_I2C_ISR_TXIS) { 1377 i2c_slave_event(i2c_dev->slave_running, 1378 I2C_SLAVE_READ_PROCESSED, 1379 &val); 1380 1381 /* Write data byte */ 1382 writel_relaxed(val, base + STM32F7_I2C_TXDR); 1383 } 1384 1385 /* Transfer Complete Reload for Slave receiver mode */ 1386 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) { 1387 /* 1388 * Read data byte then set NBYTES to receive next byte or NACK 1389 * the current received byte 1390 */ 1391 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); 1392 ret = i2c_slave_event(i2c_dev->slave_running, 1393 I2C_SLAVE_WRITE_RECEIVED, 1394 &val); 1395 if (!ret) { 1396 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 1397 cr2 |= STM32F7_I2C_CR2_NBYTES(1); 1398 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 1399 } else { 1400 mask = STM32F7_I2C_CR2_NACK; 1401 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1402 } 1403 } 1404 1405 /* NACK received */ 1406 if (status & STM32F7_I2C_ISR_NACKF) { 1407 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); 1408 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1409 } 1410 1411 /* STOP received */ 1412 if (status & STM32F7_I2C_ISR_STOPF) { 1413 /* Disable interrupts */ 1414 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK); 1415 1416 if (i2c_dev->slave_dir) { 1417 /* 1418 * Flush TX buffer in order to not used the byte in 1419 * TXDR for the next transfer 1420 */ 1421 mask = STM32F7_I2C_ISR_TXE; 1422 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask); 1423 } 1424 1425 /* Clear STOP flag */ 1426 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1427 1428 /* Notify i2c slave that a STOP flag has been detected */ 1429 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); 1430 1431 i2c_dev->slave_running = NULL; 1432 } 1433 1434 /* Address match received */ 1435 if (status & STM32F7_I2C_ISR_ADDR) 1436 stm32f7_i2c_slave_addr(i2c_dev); 1437 1438 return IRQ_HANDLED; 1439 } 1440 1441 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data) 1442 { 1443 struct stm32f7_i2c_dev *i2c_dev = data; 1444 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1445 void __iomem *base = i2c_dev->base; 1446 u32 status, mask; 1447 int ret = IRQ_HANDLED; 1448 1449 /* Check if the interrupt if for a slave device */ 1450 if (!i2c_dev->master_mode) { 1451 ret = stm32f7_i2c_slave_isr_event(i2c_dev); 1452 return ret; 1453 } 1454 1455 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1456 1457 /* Tx empty */ 1458 if (status & STM32F7_I2C_ISR_TXIS) 1459 stm32f7_i2c_write_tx_data(i2c_dev); 1460 1461 /* RX not empty */ 1462 if (status & STM32F7_I2C_ISR_RXNE) 1463 stm32f7_i2c_read_rx_data(i2c_dev); 1464 1465 /* NACK received */ 1466 if (status & STM32F7_I2C_ISR_NACKF) { 1467 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n", 1468 __func__, f7_msg->addr); 1469 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1470 f7_msg->result = -ENXIO; 1471 } 1472 1473 /* STOP detection flag */ 1474 if (status & STM32F7_I2C_ISR_STOPF) { 1475 /* Disable interrupts */ 1476 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1477 mask = STM32F7_I2C_XFER_IRQ_MASK; 1478 else 1479 mask = STM32F7_I2C_ALL_IRQ_MASK; 1480 stm32f7_i2c_disable_irq(i2c_dev, mask); 1481 1482 /* Clear STOP flag */ 1483 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1484 1485 if (i2c_dev->use_dma) { 1486 ret = IRQ_WAKE_THREAD; 1487 } else { 1488 i2c_dev->master_mode = false; 1489 complete(&i2c_dev->complete); 1490 } 1491 } 1492 1493 /* Transfer complete */ 1494 if (status & STM32F7_I2C_ISR_TC) { 1495 if (f7_msg->stop) { 1496 mask = STM32F7_I2C_CR2_STOP; 1497 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1498 } else if (i2c_dev->use_dma) { 1499 ret = IRQ_WAKE_THREAD; 1500 } else if (f7_msg->smbus) { 1501 stm32f7_i2c_smbus_rep_start(i2c_dev); 1502 } else { 1503 i2c_dev->msg_id++; 1504 i2c_dev->msg++; 1505 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1506 } 1507 } 1508 1509 if (status & STM32F7_I2C_ISR_TCR) { 1510 if (f7_msg->smbus) 1511 stm32f7_i2c_smbus_reload(i2c_dev); 1512 else 1513 stm32f7_i2c_reload(i2c_dev); 1514 } 1515 1516 return ret; 1517 } 1518 1519 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data) 1520 { 1521 struct stm32f7_i2c_dev *i2c_dev = data; 1522 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1523 struct stm32_i2c_dma *dma = i2c_dev->dma; 1524 u32 status; 1525 int ret; 1526 1527 /* 1528 * Wait for dma transfer completion before sending next message or 1529 * notity the end of xfer to the client 1530 */ 1531 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ); 1532 if (!ret) { 1533 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__); 1534 stm32f7_i2c_disable_dma_req(i2c_dev); 1535 dmaengine_terminate_all(dma->chan_using); 1536 f7_msg->result = -ETIMEDOUT; 1537 } 1538 1539 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1540 1541 if (status & STM32F7_I2C_ISR_TC) { 1542 if (f7_msg->smbus) { 1543 stm32f7_i2c_smbus_rep_start(i2c_dev); 1544 } else { 1545 i2c_dev->msg_id++; 1546 i2c_dev->msg++; 1547 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1548 } 1549 } else { 1550 i2c_dev->master_mode = false; 1551 complete(&i2c_dev->complete); 1552 } 1553 1554 return IRQ_HANDLED; 1555 } 1556 1557 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data) 1558 { 1559 struct stm32f7_i2c_dev *i2c_dev = data; 1560 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1561 void __iomem *base = i2c_dev->base; 1562 struct device *dev = i2c_dev->dev; 1563 struct stm32_i2c_dma *dma = i2c_dev->dma; 1564 u32 status; 1565 1566 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1567 1568 /* Bus error */ 1569 if (status & STM32F7_I2C_ISR_BERR) { 1570 dev_err(dev, "<%s>: Bus error\n", __func__); 1571 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR); 1572 stm32f7_i2c_release_bus(&i2c_dev->adap); 1573 f7_msg->result = -EIO; 1574 } 1575 1576 /* Arbitration loss */ 1577 if (status & STM32F7_I2C_ISR_ARLO) { 1578 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__); 1579 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR); 1580 f7_msg->result = -EAGAIN; 1581 } 1582 1583 if (status & STM32F7_I2C_ISR_PECERR) { 1584 dev_err(dev, "<%s>: PEC error in reception\n", __func__); 1585 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR); 1586 f7_msg->result = -EINVAL; 1587 } 1588 1589 if (!i2c_dev->slave_running) { 1590 u32 mask; 1591 /* Disable interrupts */ 1592 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1593 mask = STM32F7_I2C_XFER_IRQ_MASK; 1594 else 1595 mask = STM32F7_I2C_ALL_IRQ_MASK; 1596 stm32f7_i2c_disable_irq(i2c_dev, mask); 1597 } 1598 1599 /* Disable dma */ 1600 if (i2c_dev->use_dma) { 1601 stm32f7_i2c_disable_dma_req(i2c_dev); 1602 dmaengine_terminate_all(dma->chan_using); 1603 } 1604 1605 i2c_dev->master_mode = false; 1606 complete(&i2c_dev->complete); 1607 1608 return IRQ_HANDLED; 1609 } 1610 1611 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap, 1612 struct i2c_msg msgs[], int num) 1613 { 1614 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1615 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1616 struct stm32_i2c_dma *dma = i2c_dev->dma; 1617 unsigned long time_left; 1618 int ret; 1619 1620 i2c_dev->msg = msgs; 1621 i2c_dev->msg_num = num; 1622 i2c_dev->msg_id = 0; 1623 f7_msg->smbus = false; 1624 1625 ret = pm_runtime_get_sync(i2c_dev->dev); 1626 if (ret < 0) 1627 return ret; 1628 1629 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1630 if (ret) 1631 goto pm_free; 1632 1633 stm32f7_i2c_xfer_msg(i2c_dev, msgs); 1634 1635 time_left = wait_for_completion_timeout(&i2c_dev->complete, 1636 i2c_dev->adap.timeout); 1637 ret = f7_msg->result; 1638 1639 if (!time_left) { 1640 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", 1641 i2c_dev->msg->addr); 1642 if (i2c_dev->use_dma) 1643 dmaengine_terminate_all(dma->chan_using); 1644 ret = -ETIMEDOUT; 1645 } 1646 1647 pm_free: 1648 pm_runtime_mark_last_busy(i2c_dev->dev); 1649 pm_runtime_put_autosuspend(i2c_dev->dev); 1650 1651 return (ret < 0) ? ret : num; 1652 } 1653 1654 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr, 1655 unsigned short flags, char read_write, 1656 u8 command, int size, 1657 union i2c_smbus_data *data) 1658 { 1659 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); 1660 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1661 struct stm32_i2c_dma *dma = i2c_dev->dma; 1662 struct device *dev = i2c_dev->dev; 1663 unsigned long timeout; 1664 int i, ret; 1665 1666 f7_msg->addr = addr; 1667 f7_msg->size = size; 1668 f7_msg->read_write = read_write; 1669 f7_msg->smbus = true; 1670 1671 ret = pm_runtime_get_sync(dev); 1672 if (ret < 0) 1673 return ret; 1674 1675 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1676 if (ret) 1677 goto pm_free; 1678 1679 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data); 1680 if (ret) 1681 goto pm_free; 1682 1683 timeout = wait_for_completion_timeout(&i2c_dev->complete, 1684 i2c_dev->adap.timeout); 1685 ret = f7_msg->result; 1686 if (ret) 1687 goto pm_free; 1688 1689 if (!timeout) { 1690 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr); 1691 if (i2c_dev->use_dma) 1692 dmaengine_terminate_all(dma->chan_using); 1693 ret = -ETIMEDOUT; 1694 goto pm_free; 1695 } 1696 1697 /* Check PEC */ 1698 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) { 1699 ret = stm32f7_i2c_smbus_check_pec(i2c_dev); 1700 if (ret) 1701 goto pm_free; 1702 } 1703 1704 if (read_write && size != I2C_SMBUS_QUICK) { 1705 switch (size) { 1706 case I2C_SMBUS_BYTE: 1707 case I2C_SMBUS_BYTE_DATA: 1708 data->byte = f7_msg->smbus_buf[0]; 1709 break; 1710 case I2C_SMBUS_WORD_DATA: 1711 case I2C_SMBUS_PROC_CALL: 1712 data->word = f7_msg->smbus_buf[0] | 1713 (f7_msg->smbus_buf[1] << 8); 1714 break; 1715 case I2C_SMBUS_BLOCK_DATA: 1716 case I2C_SMBUS_BLOCK_PROC_CALL: 1717 for (i = 0; i <= f7_msg->smbus_buf[0]; i++) 1718 data->block[i] = f7_msg->smbus_buf[i]; 1719 break; 1720 default: 1721 dev_err(dev, "Unsupported smbus transaction\n"); 1722 ret = -EINVAL; 1723 } 1724 } 1725 1726 pm_free: 1727 pm_runtime_mark_last_busy(dev); 1728 pm_runtime_put_autosuspend(dev); 1729 return ret; 1730 } 1731 1732 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev, 1733 bool enable) 1734 { 1735 void __iomem *base = i2c_dev->base; 1736 u32 mask = STM32F7_I2C_CR1_WUPEN; 1737 1738 if (!i2c_dev->wakeup_src) 1739 return; 1740 1741 if (enable) { 1742 device_set_wakeup_enable(i2c_dev->dev, true); 1743 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1744 } else { 1745 device_set_wakeup_enable(i2c_dev->dev, false); 1746 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1747 } 1748 } 1749 1750 static int stm32f7_i2c_reg_slave(struct i2c_client *slave) 1751 { 1752 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1753 void __iomem *base = i2c_dev->base; 1754 struct device *dev = i2c_dev->dev; 1755 u32 oar1, oar2, mask; 1756 int id, ret; 1757 1758 if (slave->flags & I2C_CLIENT_PEC) { 1759 dev_err(dev, "SMBus PEC not supported in slave mode\n"); 1760 return -EINVAL; 1761 } 1762 1763 if (stm32f7_i2c_is_slave_busy(i2c_dev)) { 1764 dev_err(dev, "Too much slave registered\n"); 1765 return -EBUSY; 1766 } 1767 1768 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id); 1769 if (ret) 1770 return ret; 1771 1772 ret = pm_runtime_get_sync(dev); 1773 if (ret < 0) 1774 return ret; 1775 1776 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1777 stm32f7_i2c_enable_wakeup(i2c_dev, true); 1778 1779 if (id == 0) { 1780 /* Configure Own Address 1 */ 1781 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 1782 oar1 &= ~STM32F7_I2C_OAR1_MASK; 1783 if (slave->flags & I2C_CLIENT_TEN) { 1784 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr); 1785 oar1 |= STM32F7_I2C_OAR1_OA1MODE; 1786 } else { 1787 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr); 1788 } 1789 oar1 |= STM32F7_I2C_OAR1_OA1EN; 1790 i2c_dev->slave[id] = slave; 1791 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); 1792 } else if (id == 1) { 1793 /* Configure Own Address 2 */ 1794 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 1795 oar2 &= ~STM32F7_I2C_OAR2_MASK; 1796 if (slave->flags & I2C_CLIENT_TEN) { 1797 ret = -EOPNOTSUPP; 1798 goto pm_free; 1799 } 1800 1801 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr); 1802 oar2 |= STM32F7_I2C_OAR2_OA2EN; 1803 i2c_dev->slave[id] = slave; 1804 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); 1805 } else { 1806 ret = -ENODEV; 1807 goto pm_free; 1808 } 1809 1810 /* Enable ACK */ 1811 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK); 1812 1813 /* Enable Address match interrupt, error interrupt and enable I2C */ 1814 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE | 1815 STM32F7_I2C_CR1_PE; 1816 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1817 1818 ret = 0; 1819 pm_free: 1820 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1821 stm32f7_i2c_enable_wakeup(i2c_dev, false); 1822 1823 pm_runtime_mark_last_busy(dev); 1824 pm_runtime_put_autosuspend(dev); 1825 1826 return ret; 1827 } 1828 1829 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave) 1830 { 1831 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1832 void __iomem *base = i2c_dev->base; 1833 u32 mask; 1834 int id, ret; 1835 1836 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id); 1837 if (ret) 1838 return ret; 1839 1840 WARN_ON(!i2c_dev->slave[id]); 1841 1842 ret = pm_runtime_get_sync(i2c_dev->dev); 1843 if (ret < 0) 1844 return ret; 1845 1846 if (id == 0) { 1847 mask = STM32F7_I2C_OAR1_OA1EN; 1848 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask); 1849 } else { 1850 mask = STM32F7_I2C_OAR2_OA2EN; 1851 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask); 1852 } 1853 1854 i2c_dev->slave[id] = NULL; 1855 1856 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 1857 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK); 1858 stm32f7_i2c_enable_wakeup(i2c_dev, false); 1859 } 1860 1861 pm_runtime_mark_last_busy(i2c_dev->dev); 1862 pm_runtime_put_autosuspend(i2c_dev->dev); 1863 1864 return 0; 1865 } 1866 1867 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev, 1868 bool enable) 1869 { 1870 int ret; 1871 1872 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ || 1873 IS_ERR_OR_NULL(i2c_dev->regmap)) 1874 /* Optional */ 1875 return 0; 1876 1877 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg) 1878 ret = regmap_update_bits(i2c_dev->regmap, 1879 i2c_dev->fmp_sreg, 1880 i2c_dev->fmp_mask, 1881 enable ? i2c_dev->fmp_mask : 0); 1882 else 1883 ret = regmap_write(i2c_dev->regmap, 1884 enable ? i2c_dev->fmp_sreg : 1885 i2c_dev->fmp_creg, 1886 i2c_dev->fmp_mask); 1887 1888 return ret; 1889 } 1890 1891 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev, 1892 struct stm32f7_i2c_dev *i2c_dev) 1893 { 1894 struct device_node *np = pdev->dev.of_node; 1895 int ret; 1896 1897 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp"); 1898 if (IS_ERR(i2c_dev->regmap)) 1899 /* Optional */ 1900 return 0; 1901 1902 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, 1903 &i2c_dev->fmp_sreg); 1904 if (ret) 1905 return ret; 1906 1907 i2c_dev->fmp_creg = i2c_dev->fmp_sreg + 1908 i2c_dev->setup.fmp_clr_offset; 1909 1910 return of_property_read_u32_index(np, "st,syscfg-fmp", 2, 1911 &i2c_dev->fmp_mask); 1912 } 1913 1914 static u32 stm32f7_i2c_func(struct i2c_adapter *adap) 1915 { 1916 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE | 1917 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 1918 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 1919 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 1920 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC | 1921 I2C_FUNC_SMBUS_I2C_BLOCK; 1922 } 1923 1924 static const struct i2c_algorithm stm32f7_i2c_algo = { 1925 .master_xfer = stm32f7_i2c_xfer, 1926 .smbus_xfer = stm32f7_i2c_smbus_xfer, 1927 .functionality = stm32f7_i2c_func, 1928 .reg_slave = stm32f7_i2c_reg_slave, 1929 .unreg_slave = stm32f7_i2c_unreg_slave, 1930 }; 1931 1932 static int stm32f7_i2c_probe(struct platform_device *pdev) 1933 { 1934 struct stm32f7_i2c_dev *i2c_dev; 1935 const struct stm32f7_i2c_setup *setup; 1936 struct resource *res; 1937 struct i2c_adapter *adap; 1938 struct reset_control *rst; 1939 dma_addr_t phy_addr; 1940 int irq_error, irq_event, ret; 1941 1942 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 1943 if (!i2c_dev) 1944 return -ENOMEM; 1945 1946 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1947 if (IS_ERR(i2c_dev->base)) 1948 return PTR_ERR(i2c_dev->base); 1949 phy_addr = (dma_addr_t)res->start; 1950 1951 irq_event = platform_get_irq(pdev, 0); 1952 if (irq_event <= 0) { 1953 if (irq_event != -EPROBE_DEFER) 1954 dev_err(&pdev->dev, "Failed to get IRQ event: %d\n", 1955 irq_event); 1956 return irq_event ? : -ENOENT; 1957 } 1958 1959 irq_error = platform_get_irq(pdev, 1); 1960 if (irq_error <= 0) { 1961 if (irq_error != -EPROBE_DEFER) 1962 dev_err(&pdev->dev, "Failed to get IRQ error: %d\n", 1963 irq_error); 1964 return irq_error ? : -ENOENT; 1965 } 1966 1967 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node, 1968 "wakeup-source"); 1969 1970 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); 1971 if (IS_ERR(i2c_dev->clk)) { 1972 if (PTR_ERR(i2c_dev->clk) != -EPROBE_DEFER) 1973 dev_err(&pdev->dev, "Failed to get controller clock\n"); 1974 return PTR_ERR(i2c_dev->clk); 1975 } 1976 1977 ret = clk_prepare_enable(i2c_dev->clk); 1978 if (ret) { 1979 dev_err(&pdev->dev, "Failed to prepare_enable clock\n"); 1980 return ret; 1981 } 1982 1983 rst = devm_reset_control_get(&pdev->dev, NULL); 1984 if (IS_ERR(rst)) { 1985 ret = PTR_ERR(rst); 1986 if (ret != -EPROBE_DEFER) 1987 dev_err(&pdev->dev, "Error: Missing reset ctrl\n"); 1988 1989 goto clk_free; 1990 } 1991 reset_control_assert(rst); 1992 udelay(2); 1993 reset_control_deassert(rst); 1994 1995 i2c_dev->dev = &pdev->dev; 1996 1997 ret = devm_request_threaded_irq(&pdev->dev, irq_event, 1998 stm32f7_i2c_isr_event, 1999 stm32f7_i2c_isr_event_thread, 2000 IRQF_ONESHOT, 2001 pdev->name, i2c_dev); 2002 if (ret) { 2003 dev_err(&pdev->dev, "Failed to request irq event %i\n", 2004 irq_event); 2005 goto clk_free; 2006 } 2007 2008 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0, 2009 pdev->name, i2c_dev); 2010 if (ret) { 2011 dev_err(&pdev->dev, "Failed to request irq error %i\n", 2012 irq_error); 2013 goto clk_free; 2014 } 2015 2016 setup = of_device_get_match_data(&pdev->dev); 2017 if (!setup) { 2018 dev_err(&pdev->dev, "Can't get device data\n"); 2019 ret = -ENODEV; 2020 goto clk_free; 2021 } 2022 i2c_dev->setup = *setup; 2023 2024 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup); 2025 if (ret) 2026 goto clk_free; 2027 2028 /* Setup Fast mode plus if necessary */ 2029 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) { 2030 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev); 2031 if (ret) 2032 goto clk_free; 2033 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2034 if (ret) 2035 goto clk_free; 2036 } 2037 2038 adap = &i2c_dev->adap; 2039 i2c_set_adapdata(adap, i2c_dev); 2040 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", 2041 &res->start); 2042 adap->owner = THIS_MODULE; 2043 adap->timeout = 2 * HZ; 2044 adap->retries = 3; 2045 adap->algo = &stm32f7_i2c_algo; 2046 adap->dev.parent = &pdev->dev; 2047 adap->dev.of_node = pdev->dev.of_node; 2048 2049 init_completion(&i2c_dev->complete); 2050 2051 /* Init DMA config if supported */ 2052 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr, 2053 STM32F7_I2C_TXDR, 2054 STM32F7_I2C_RXDR); 2055 if (PTR_ERR(i2c_dev->dma) == -ENODEV) 2056 i2c_dev->dma = NULL; 2057 else if (IS_ERR(i2c_dev->dma)) { 2058 ret = PTR_ERR(i2c_dev->dma); 2059 if (ret != -EPROBE_DEFER) 2060 dev_err(&pdev->dev, 2061 "Failed to request dma error %i\n", ret); 2062 goto fmp_clear; 2063 } 2064 2065 if (i2c_dev->wakeup_src) { 2066 device_set_wakeup_capable(i2c_dev->dev, true); 2067 2068 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event); 2069 if (ret) { 2070 dev_err(i2c_dev->dev, "Failed to set wake up irq\n"); 2071 goto clr_wakeup_capable; 2072 } 2073 } 2074 2075 platform_set_drvdata(pdev, i2c_dev); 2076 2077 pm_runtime_set_autosuspend_delay(i2c_dev->dev, 2078 STM32F7_AUTOSUSPEND_DELAY); 2079 pm_runtime_use_autosuspend(i2c_dev->dev); 2080 pm_runtime_set_active(i2c_dev->dev); 2081 pm_runtime_enable(i2c_dev->dev); 2082 2083 pm_runtime_get_noresume(&pdev->dev); 2084 2085 stm32f7_i2c_hw_config(i2c_dev); 2086 2087 ret = i2c_add_adapter(adap); 2088 if (ret) 2089 goto pm_disable; 2090 2091 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); 2092 2093 pm_runtime_mark_last_busy(i2c_dev->dev); 2094 pm_runtime_put_autosuspend(i2c_dev->dev); 2095 2096 return 0; 2097 2098 pm_disable: 2099 pm_runtime_put_noidle(i2c_dev->dev); 2100 pm_runtime_disable(i2c_dev->dev); 2101 pm_runtime_set_suspended(i2c_dev->dev); 2102 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2103 2104 if (i2c_dev->wakeup_src) 2105 dev_pm_clear_wake_irq(i2c_dev->dev); 2106 2107 clr_wakeup_capable: 2108 if (i2c_dev->wakeup_src) 2109 device_set_wakeup_capable(i2c_dev->dev, false); 2110 2111 if (i2c_dev->dma) { 2112 stm32_i2c_dma_free(i2c_dev->dma); 2113 i2c_dev->dma = NULL; 2114 } 2115 2116 fmp_clear: 2117 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2118 2119 clk_free: 2120 clk_disable_unprepare(i2c_dev->clk); 2121 2122 return ret; 2123 } 2124 2125 static int stm32f7_i2c_remove(struct platform_device *pdev) 2126 { 2127 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 2128 2129 i2c_del_adapter(&i2c_dev->adap); 2130 pm_runtime_get_sync(i2c_dev->dev); 2131 2132 if (i2c_dev->wakeup_src) { 2133 dev_pm_clear_wake_irq(i2c_dev->dev); 2134 /* 2135 * enforce that wakeup is disabled and that the device 2136 * is marked as non wakeup capable 2137 */ 2138 device_init_wakeup(i2c_dev->dev, false); 2139 } 2140 2141 pm_runtime_put_noidle(i2c_dev->dev); 2142 pm_runtime_disable(i2c_dev->dev); 2143 pm_runtime_set_suspended(i2c_dev->dev); 2144 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2145 2146 if (i2c_dev->dma) { 2147 stm32_i2c_dma_free(i2c_dev->dma); 2148 i2c_dev->dma = NULL; 2149 } 2150 2151 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2152 2153 clk_disable_unprepare(i2c_dev->clk); 2154 2155 return 0; 2156 } 2157 2158 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev) 2159 { 2160 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2161 2162 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 2163 clk_disable_unprepare(i2c_dev->clk); 2164 2165 return 0; 2166 } 2167 2168 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev) 2169 { 2170 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2171 int ret; 2172 2173 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 2174 ret = clk_prepare_enable(i2c_dev->clk); 2175 if (ret) { 2176 dev_err(dev, "failed to prepare_enable clock\n"); 2177 return ret; 2178 } 2179 } 2180 2181 return 0; 2182 } 2183 2184 #ifdef CONFIG_PM_SLEEP 2185 static int stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev) 2186 { 2187 int ret; 2188 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2189 2190 ret = pm_runtime_get_sync(i2c_dev->dev); 2191 if (ret < 0) 2192 return ret; 2193 2194 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2195 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 2196 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 2197 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 2198 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR); 2199 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2200 2201 pm_runtime_put_sync(i2c_dev->dev); 2202 2203 return ret; 2204 } 2205 2206 static int stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev) 2207 { 2208 u32 cr1; 2209 int ret; 2210 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2211 2212 ret = pm_runtime_get_sync(i2c_dev->dev); 2213 if (ret < 0) 2214 return ret; 2215 2216 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2217 if (cr1 & STM32F7_I2C_CR1_PE) 2218 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 2219 STM32F7_I2C_CR1_PE); 2220 2221 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR); 2222 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE, 2223 i2c_dev->base + STM32F7_I2C_CR1); 2224 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE) 2225 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 2226 STM32F7_I2C_CR1_PE); 2227 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2); 2228 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1); 2229 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2); 2230 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2231 2232 pm_runtime_put_sync(i2c_dev->dev); 2233 2234 return ret; 2235 } 2236 2237 static int stm32f7_i2c_suspend(struct device *dev) 2238 { 2239 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2240 int ret; 2241 2242 i2c_mark_adapter_suspended(&i2c_dev->adap); 2243 2244 if (!device_may_wakeup(dev) && !dev->power.wakeup_path) { 2245 ret = stm32f7_i2c_regs_backup(i2c_dev); 2246 if (ret < 0) { 2247 i2c_mark_adapter_resumed(&i2c_dev->adap); 2248 return ret; 2249 } 2250 2251 pinctrl_pm_select_sleep_state(dev); 2252 pm_runtime_force_suspend(dev); 2253 } 2254 2255 return 0; 2256 } 2257 2258 static int stm32f7_i2c_resume(struct device *dev) 2259 { 2260 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2261 int ret; 2262 2263 if (!device_may_wakeup(dev) && !dev->power.wakeup_path) { 2264 ret = pm_runtime_force_resume(dev); 2265 if (ret < 0) 2266 return ret; 2267 pinctrl_pm_select_default_state(dev); 2268 2269 ret = stm32f7_i2c_regs_restore(i2c_dev); 2270 if (ret < 0) 2271 return ret; 2272 } 2273 2274 i2c_mark_adapter_resumed(&i2c_dev->adap); 2275 2276 return 0; 2277 } 2278 #endif 2279 2280 static const struct dev_pm_ops stm32f7_i2c_pm_ops = { 2281 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend, 2282 stm32f7_i2c_runtime_resume, NULL) 2283 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume) 2284 }; 2285 2286 static const struct of_device_id stm32f7_i2c_match[] = { 2287 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup}, 2288 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup}, 2289 {}, 2290 }; 2291 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match); 2292 2293 static struct platform_driver stm32f7_i2c_driver = { 2294 .driver = { 2295 .name = "stm32f7-i2c", 2296 .of_match_table = stm32f7_i2c_match, 2297 .pm = &stm32f7_i2c_pm_ops, 2298 }, 2299 .probe = stm32f7_i2c_probe, 2300 .remove = stm32f7_i2c_remove, 2301 }; 2302 2303 module_platform_driver(stm32f7_i2c_driver); 2304 2305 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); 2306 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver"); 2307 MODULE_LICENSE("GPL v2"); 2308