1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2// Copyright (C) 2016 ARM Ltd.
3// based on the Allwinner H3 dtsi:
4//    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5
6#include <dt-bindings/clock/sun50i-a64-ccu.h>
7#include <dt-bindings/clock/sun8i-de2.h>
8#include <dt-bindings/clock/sun8i-r-ccu.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/reset/sun50i-a64-ccu.h>
11#include <dt-bindings/reset/sun8i-de2.h>
12#include <dt-bindings/reset/sun8i-r-ccu.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	interrupt-parent = <&gic>;
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	chosen {
21		#address-cells = <1>;
22		#size-cells = <1>;
23		ranges;
24
25		simplefb_lcd: framebuffer-lcd {
26			compatible = "allwinner,simple-framebuffer",
27				     "simple-framebuffer";
28			allwinner,pipeline = "mixer0-lcd0";
29			clocks = <&ccu CLK_TCON0>,
30				 <&display_clocks CLK_MIXER0>;
31			status = "disabled";
32		};
33
34		simplefb_hdmi: framebuffer-hdmi {
35			compatible = "allwinner,simple-framebuffer",
36				     "simple-framebuffer";
37			allwinner,pipeline = "mixer1-lcd1-hdmi";
38			clocks = <&display_clocks CLK_MIXER1>,
39				 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
40			status = "disabled";
41		};
42	};
43
44	cpus {
45		#address-cells = <1>;
46		#size-cells = <0>;
47
48		cpu0: cpu@0 {
49			compatible = "arm,cortex-a53";
50			device_type = "cpu";
51			reg = <0>;
52			enable-method = "psci";
53			next-level-cache = <&L2>;
54			clocks = <&ccu 21>;
55			clock-names = "cpu";
56			#cooling-cells = <2>;
57		};
58
59		cpu1: cpu@1 {
60			compatible = "arm,cortex-a53";
61			device_type = "cpu";
62			reg = <1>;
63			enable-method = "psci";
64			next-level-cache = <&L2>;
65			clocks = <&ccu 21>;
66			clock-names = "cpu";
67			#cooling-cells = <2>;
68		};
69
70		cpu2: cpu@2 {
71			compatible = "arm,cortex-a53";
72			device_type = "cpu";
73			reg = <2>;
74			enable-method = "psci";
75			next-level-cache = <&L2>;
76			clocks = <&ccu 21>;
77			clock-names = "cpu";
78			#cooling-cells = <2>;
79		};
80
81		cpu3: cpu@3 {
82			compatible = "arm,cortex-a53";
83			device_type = "cpu";
84			reg = <3>;
85			enable-method = "psci";
86			next-level-cache = <&L2>;
87			clocks = <&ccu 21>;
88			clock-names = "cpu";
89			#cooling-cells = <2>;
90		};
91
92		L2: l2-cache {
93			compatible = "cache";
94			cache-level = <2>;
95		};
96	};
97
98	de: display-engine {
99		compatible = "allwinner,sun50i-a64-display-engine";
100		allwinner,pipelines = <&mixer0>,
101				      <&mixer1>;
102		status = "disabled";
103	};
104
105	osc24M: osc24M_clk {
106		#clock-cells = <0>;
107		compatible = "fixed-clock";
108		clock-frequency = <24000000>;
109		clock-output-names = "osc24M";
110	};
111
112	osc32k: osc32k_clk {
113		#clock-cells = <0>;
114		compatible = "fixed-clock";
115		clock-frequency = <32768>;
116		clock-output-names = "ext-osc32k";
117	};
118
119	pmu {
120		compatible = "arm,cortex-a53-pmu";
121		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
122			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
123			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
124			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
125		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
126	};
127
128	psci {
129		compatible = "arm,psci-0.2";
130		method = "smc";
131	};
132
133	sound: sound {
134		compatible = "simple-audio-card";
135		simple-audio-card,name = "sun50i-a64-audio";
136		simple-audio-card,format = "i2s";
137		simple-audio-card,frame-master = <&cpudai>;
138		simple-audio-card,bitclock-master = <&cpudai>;
139		simple-audio-card,mclk-fs = <128>;
140		simple-audio-card,aux-devs = <&codec_analog>;
141		simple-audio-card,routing =
142				"Left DAC", "AIF1 Slot 0 Left",
143				"Right DAC", "AIF1 Slot 0 Right",
144				"AIF1 Slot 0 Left ADC", "Left ADC",
145				"AIF1 Slot 0 Right ADC", "Right ADC";
146		status = "disabled";
147
148		cpudai: simple-audio-card,cpu {
149			sound-dai = <&dai>;
150		};
151
152		link_codec: simple-audio-card,codec {
153			sound-dai = <&codec>;
154		};
155	};
156
157	timer {
158		compatible = "arm,armv8-timer";
159		allwinner,erratum-unknown1;
160		interrupts = <GIC_PPI 13
161			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
162			     <GIC_PPI 14
163			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
164			     <GIC_PPI 11
165			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
166			     <GIC_PPI 10
167			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
168	};
169
170	thermal-zones {
171		cpu_thermal: cpu0-thermal {
172			/* milliseconds */
173			polling-delay-passive = <0>;
174			polling-delay = <0>;
175			thermal-sensors = <&ths 0>;
176
177			cooling-maps {
178				map0 {
179					trip = <&cpu_alert0>;
180					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
181							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
182							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
183							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
184				};
185				map1 {
186					trip = <&cpu_alert1>;
187					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
188							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
189							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
190							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
191				};
192			};
193
194			trips {
195				cpu_alert0: cpu_alert0 {
196					/* milliCelsius */
197					temperature = <75000>;
198					hysteresis = <2000>;
199					type = "passive";
200				};
201
202				cpu_alert1: cpu_alert1 {
203					/* milliCelsius */
204					temperature = <90000>;
205					hysteresis = <2000>;
206					type = "hot";
207				};
208
209				cpu_crit: cpu_crit {
210					/* milliCelsius */
211					temperature = <110000>;
212					hysteresis = <2000>;
213					type = "critical";
214				};
215			};
216		};
217
218		gpu0_thermal: gpu0-thermal {
219			/* milliseconds */
220			polling-delay-passive = <0>;
221			polling-delay = <0>;
222			thermal-sensors = <&ths 1>;
223		};
224
225		gpu1_thermal: gpu1-thermal {
226			/* milliseconds */
227			polling-delay-passive = <0>;
228			polling-delay = <0>;
229			thermal-sensors = <&ths 2>;
230		};
231	};
232
233	soc {
234		compatible = "simple-bus";
235		#address-cells = <1>;
236		#size-cells = <1>;
237		ranges;
238
239		bus@1000000 {
240			compatible = "allwinner,sun50i-a64-de2";
241			reg = <0x1000000 0x400000>;
242			allwinner,sram = <&de2_sram 1>;
243			#address-cells = <1>;
244			#size-cells = <1>;
245			ranges = <0 0x1000000 0x400000>;
246
247			display_clocks: clock@0 {
248				compatible = "allwinner,sun50i-a64-de2-clk";
249				reg = <0x0 0x10000>;
250				clocks = <&ccu CLK_BUS_DE>,
251					 <&ccu CLK_DE>;
252				clock-names = "bus",
253					      "mod";
254				resets = <&ccu RST_BUS_DE>;
255				#clock-cells = <1>;
256				#reset-cells = <1>;
257			};
258
259			rotate: rotate@20000 {
260				compatible = "allwinner,sun50i-a64-de2-rotate",
261					     "allwinner,sun8i-a83t-de2-rotate";
262				reg = <0x20000 0x10000>;
263				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
264				clocks = <&display_clocks CLK_BUS_ROT>,
265					 <&display_clocks CLK_ROT>;
266				clock-names = "bus",
267					      "mod";
268				resets = <&display_clocks RST_ROT>;
269			};
270
271			mixer0: mixer@100000 {
272				compatible = "allwinner,sun50i-a64-de2-mixer-0";
273				reg = <0x100000 0x100000>;
274				clocks = <&display_clocks CLK_BUS_MIXER0>,
275					 <&display_clocks CLK_MIXER0>;
276				clock-names = "bus",
277					      "mod";
278				resets = <&display_clocks RST_MIXER0>;
279
280				ports {
281					#address-cells = <1>;
282					#size-cells = <0>;
283
284					mixer0_out: port@1 {
285						#address-cells = <1>;
286						#size-cells = <0>;
287						reg = <1>;
288
289						mixer0_out_tcon0: endpoint@0 {
290							reg = <0>;
291							remote-endpoint = <&tcon0_in_mixer0>;
292						};
293
294						mixer0_out_tcon1: endpoint@1 {
295							reg = <1>;
296							remote-endpoint = <&tcon1_in_mixer0>;
297						};
298					};
299				};
300			};
301
302			mixer1: mixer@200000 {
303				compatible = "allwinner,sun50i-a64-de2-mixer-1";
304				reg = <0x200000 0x100000>;
305				clocks = <&display_clocks CLK_BUS_MIXER1>,
306					 <&display_clocks CLK_MIXER1>;
307				clock-names = "bus",
308					      "mod";
309				resets = <&display_clocks RST_MIXER1>;
310
311				ports {
312					#address-cells = <1>;
313					#size-cells = <0>;
314
315					mixer1_out: port@1 {
316						#address-cells = <1>;
317						#size-cells = <0>;
318						reg = <1>;
319
320						mixer1_out_tcon0: endpoint@0 {
321							reg = <0>;
322							remote-endpoint = <&tcon0_in_mixer1>;
323						};
324
325						mixer1_out_tcon1: endpoint@1 {
326							reg = <1>;
327							remote-endpoint = <&tcon1_in_mixer1>;
328						};
329					};
330				};
331			};
332		};
333
334		syscon: syscon@1c00000 {
335			compatible = "allwinner,sun50i-a64-system-control";
336			reg = <0x01c00000 0x1000>;
337			#address-cells = <1>;
338			#size-cells = <1>;
339			ranges;
340
341			sram_c: sram@18000 {
342				compatible = "mmio-sram";
343				reg = <0x00018000 0x28000>;
344				#address-cells = <1>;
345				#size-cells = <1>;
346				ranges = <0 0x00018000 0x28000>;
347
348				de2_sram: sram-section@0 {
349					compatible = "allwinner,sun50i-a64-sram-c";
350					reg = <0x0000 0x28000>;
351				};
352			};
353
354			sram_c1: sram@1d00000 {
355				compatible = "mmio-sram";
356				reg = <0x01d00000 0x40000>;
357				#address-cells = <1>;
358				#size-cells = <1>;
359				ranges = <0 0x01d00000 0x40000>;
360
361				ve_sram: sram-section@0 {
362					compatible = "allwinner,sun50i-a64-sram-c1",
363						     "allwinner,sun4i-a10-sram-c1";
364					reg = <0x000000 0x40000>;
365				};
366			};
367		};
368
369		dma: dma-controller@1c02000 {
370			compatible = "allwinner,sun50i-a64-dma";
371			reg = <0x01c02000 0x1000>;
372			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
373			clocks = <&ccu CLK_BUS_DMA>;
374			dma-channels = <8>;
375			dma-requests = <27>;
376			resets = <&ccu RST_BUS_DMA>;
377			#dma-cells = <1>;
378		};
379
380		tcon0: lcd-controller@1c0c000 {
381			compatible = "allwinner,sun50i-a64-tcon-lcd",
382				     "allwinner,sun8i-a83t-tcon-lcd";
383			reg = <0x01c0c000 0x1000>;
384			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
385			clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
386			clock-names = "ahb", "tcon-ch0";
387			clock-output-names = "tcon-pixel-clock";
388			#clock-cells = <0>;
389			resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
390			reset-names = "lcd", "lvds";
391
392			ports {
393				#address-cells = <1>;
394				#size-cells = <0>;
395
396				tcon0_in: port@0 {
397					#address-cells = <1>;
398					#size-cells = <0>;
399					reg = <0>;
400
401					tcon0_in_mixer0: endpoint@0 {
402						reg = <0>;
403						remote-endpoint = <&mixer0_out_tcon0>;
404					};
405
406					tcon0_in_mixer1: endpoint@1 {
407						reg = <1>;
408						remote-endpoint = <&mixer1_out_tcon0>;
409					};
410				};
411
412				tcon0_out: port@1 {
413					#address-cells = <1>;
414					#size-cells = <0>;
415					reg = <1>;
416
417					tcon0_out_dsi: endpoint@1 {
418						reg = <1>;
419						remote-endpoint = <&dsi_in_tcon0>;
420						allwinner,tcon-channel = <1>;
421					};
422				};
423			};
424		};
425
426		tcon1: lcd-controller@1c0d000 {
427			compatible = "allwinner,sun50i-a64-tcon-tv",
428				     "allwinner,sun8i-a83t-tcon-tv";
429			reg = <0x01c0d000 0x1000>;
430			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
431			clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
432			clock-names = "ahb", "tcon-ch1";
433			resets = <&ccu RST_BUS_TCON1>;
434			reset-names = "lcd";
435
436			ports {
437				#address-cells = <1>;
438				#size-cells = <0>;
439
440				tcon1_in: port@0 {
441					#address-cells = <1>;
442					#size-cells = <0>;
443					reg = <0>;
444
445					tcon1_in_mixer0: endpoint@0 {
446						reg = <0>;
447						remote-endpoint = <&mixer0_out_tcon1>;
448					};
449
450					tcon1_in_mixer1: endpoint@1 {
451						reg = <1>;
452						remote-endpoint = <&mixer1_out_tcon1>;
453					};
454				};
455
456				tcon1_out: port@1 {
457					#address-cells = <1>;
458					#size-cells = <0>;
459					reg = <1>;
460
461					tcon1_out_hdmi: endpoint@1 {
462						reg = <1>;
463						remote-endpoint = <&hdmi_in_tcon1>;
464					};
465				};
466			};
467		};
468
469		video-codec@1c0e000 {
470			compatible = "allwinner,sun50i-a64-video-engine";
471			reg = <0x01c0e000 0x1000>;
472			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
473				 <&ccu CLK_DRAM_VE>;
474			clock-names = "ahb", "mod", "ram";
475			resets = <&ccu RST_BUS_VE>;
476			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
477			allwinner,sram = <&ve_sram 1>;
478		};
479
480		mmc0: mmc@1c0f000 {
481			compatible = "allwinner,sun50i-a64-mmc";
482			reg = <0x01c0f000 0x1000>;
483			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
484			clock-names = "ahb", "mmc";
485			resets = <&ccu RST_BUS_MMC0>;
486			reset-names = "ahb";
487			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
488			max-frequency = <150000000>;
489			status = "disabled";
490			#address-cells = <1>;
491			#size-cells = <0>;
492		};
493
494		mmc1: mmc@1c10000 {
495			compatible = "allwinner,sun50i-a64-mmc";
496			reg = <0x01c10000 0x1000>;
497			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
498			clock-names = "ahb", "mmc";
499			resets = <&ccu RST_BUS_MMC1>;
500			reset-names = "ahb";
501			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
502			max-frequency = <150000000>;
503			status = "disabled";
504			#address-cells = <1>;
505			#size-cells = <0>;
506		};
507
508		mmc2: mmc@1c11000 {
509			compatible = "allwinner,sun50i-a64-emmc";
510			reg = <0x01c11000 0x1000>;
511			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
512			clock-names = "ahb", "mmc";
513			resets = <&ccu RST_BUS_MMC2>;
514			reset-names = "ahb";
515			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
516			max-frequency = <200000000>;
517			status = "disabled";
518			#address-cells = <1>;
519			#size-cells = <0>;
520		};
521
522		sid: eeprom@1c14000 {
523			compatible = "allwinner,sun50i-a64-sid";
524			reg = <0x1c14000 0x400>;
525			#address-cells = <1>;
526			#size-cells = <1>;
527
528			ths_calibration: thermal-sensor-calibration@34 {
529				reg = <0x34 0x8>;
530			};
531		};
532
533		crypto: crypto@1c15000 {
534			compatible = "allwinner,sun50i-a64-crypto";
535			reg = <0x01c15000 0x1000>;
536			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
537			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
538			clock-names = "bus", "mod";
539			resets = <&ccu RST_BUS_CE>;
540		};
541
542		msgbox: mailbox@1c17000 {
543			compatible = "allwinner,sun50i-a64-msgbox",
544				     "allwinner,sun6i-a31-msgbox";
545			reg = <0x01c17000 0x1000>;
546			clocks = <&ccu CLK_BUS_MSGBOX>;
547			resets = <&ccu RST_BUS_MSGBOX>;
548			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
549			#mbox-cells = <1>;
550		};
551
552		usb_otg: usb@1c19000 {
553			compatible = "allwinner,sun8i-a33-musb";
554			reg = <0x01c19000 0x0400>;
555			clocks = <&ccu CLK_BUS_OTG>;
556			resets = <&ccu RST_BUS_OTG>;
557			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
558			interrupt-names = "mc";
559			phys = <&usbphy 0>;
560			phy-names = "usb";
561			extcon = <&usbphy 0>;
562			dr_mode = "otg";
563			status = "disabled";
564		};
565
566		usbphy: phy@1c19400 {
567			compatible = "allwinner,sun50i-a64-usb-phy";
568			reg = <0x01c19400 0x14>,
569			      <0x01c1a800 0x4>,
570			      <0x01c1b800 0x4>;
571			reg-names = "phy_ctrl",
572				    "pmu0",
573				    "pmu1";
574			clocks = <&ccu CLK_USB_PHY0>,
575				 <&ccu CLK_USB_PHY1>;
576			clock-names = "usb0_phy",
577				      "usb1_phy";
578			resets = <&ccu RST_USB_PHY0>,
579				 <&ccu RST_USB_PHY1>;
580			reset-names = "usb0_reset",
581				      "usb1_reset";
582			status = "disabled";
583			#phy-cells = <1>;
584		};
585
586		ehci0: usb@1c1a000 {
587			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
588			reg = <0x01c1a000 0x100>;
589			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
590			clocks = <&ccu CLK_BUS_OHCI0>,
591				 <&ccu CLK_BUS_EHCI0>,
592				 <&ccu CLK_USB_OHCI0>;
593			resets = <&ccu RST_BUS_OHCI0>,
594				 <&ccu RST_BUS_EHCI0>;
595			status = "disabled";
596		};
597
598		ohci0: usb@1c1a400 {
599			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
600			reg = <0x01c1a400 0x100>;
601			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
602			clocks = <&ccu CLK_BUS_OHCI0>,
603				 <&ccu CLK_USB_OHCI0>;
604			resets = <&ccu RST_BUS_OHCI0>;
605			status = "disabled";
606		};
607
608		ehci1: usb@1c1b000 {
609			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
610			reg = <0x01c1b000 0x100>;
611			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
612			clocks = <&ccu CLK_BUS_OHCI1>,
613				 <&ccu CLK_BUS_EHCI1>,
614				 <&ccu CLK_USB_OHCI1>;
615			resets = <&ccu RST_BUS_OHCI1>,
616				 <&ccu RST_BUS_EHCI1>;
617			phys = <&usbphy 1>;
618			phy-names = "usb";
619			status = "disabled";
620		};
621
622		ohci1: usb@1c1b400 {
623			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
624			reg = <0x01c1b400 0x100>;
625			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
626			clocks = <&ccu CLK_BUS_OHCI1>,
627				 <&ccu CLK_USB_OHCI1>;
628			resets = <&ccu RST_BUS_OHCI1>;
629			phys = <&usbphy 1>;
630			phy-names = "usb";
631			status = "disabled";
632		};
633
634		ccu: clock@1c20000 {
635			compatible = "allwinner,sun50i-a64-ccu";
636			reg = <0x01c20000 0x400>;
637			clocks = <&osc24M>, <&rtc 0>;
638			clock-names = "hosc", "losc";
639			#clock-cells = <1>;
640			#reset-cells = <1>;
641		};
642
643		pio: pinctrl@1c20800 {
644			compatible = "allwinner,sun50i-a64-pinctrl";
645			reg = <0x01c20800 0x400>;
646			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
647				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
648				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
649			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
650			clock-names = "apb", "hosc", "losc";
651			gpio-controller;
652			#gpio-cells = <3>;
653			interrupt-controller;
654			#interrupt-cells = <3>;
655
656			csi_pins: csi-pins {
657				pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
658				       "PE7", "PE8", "PE9", "PE10", "PE11";
659				function = "csi";
660			};
661
662			/omit-if-no-ref/
663			csi_mclk_pin: csi-mclk-pin {
664				pins = "PE1";
665				function = "csi";
666			};
667
668			i2c0_pins: i2c0-pins {
669				pins = "PH0", "PH1";
670				function = "i2c0";
671			};
672
673			i2c1_pins: i2c1-pins {
674				pins = "PH2", "PH3";
675				function = "i2c1";
676			};
677
678			i2c2_pins: i2c2-pins {
679				pins = "PE14", "PE15";
680				function = "i2c2";
681			};
682
683			/omit-if-no-ref/
684			lcd_rgb666_pins: lcd-rgb666-pins {
685				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
686				       "PD5", "PD6", "PD7", "PD8", "PD9",
687				       "PD10", "PD11", "PD12", "PD13",
688				       "PD14", "PD15", "PD16", "PD17",
689				       "PD18", "PD19", "PD20", "PD21";
690				function = "lcd0";
691			};
692
693			mmc0_pins: mmc0-pins {
694				pins = "PF0", "PF1", "PF2", "PF3",
695				       "PF4", "PF5";
696				function = "mmc0";
697				drive-strength = <30>;
698				bias-pull-up;
699			};
700
701			mmc1_pins: mmc1-pins {
702				pins = "PG0", "PG1", "PG2", "PG3",
703				       "PG4", "PG5";
704				function = "mmc1";
705				drive-strength = <30>;
706				bias-pull-up;
707			};
708
709			mmc2_pins: mmc2-pins {
710				pins = "PC5", "PC6", "PC8", "PC9",
711				       "PC10","PC11", "PC12", "PC13",
712				       "PC14", "PC15", "PC16";
713				function = "mmc2";
714				drive-strength = <30>;
715				bias-pull-up;
716			};
717
718			mmc2_ds_pin: mmc2-ds-pin {
719				pins = "PC1";
720				function = "mmc2";
721				drive-strength = <30>;
722				bias-pull-up;
723			};
724
725			pwm_pin: pwm-pin {
726				pins = "PD22";
727				function = "pwm";
728			};
729
730			rmii_pins: rmii-pins {
731				pins = "PD10", "PD11", "PD13", "PD14", "PD17",
732				       "PD18", "PD19", "PD20", "PD22", "PD23";
733				function = "emac";
734				drive-strength = <40>;
735			};
736
737			rgmii_pins: rgmii-pins {
738				pins = "PD8", "PD9", "PD10", "PD11", "PD12",
739				       "PD13", "PD15", "PD16", "PD17", "PD18",
740				       "PD19", "PD20", "PD21", "PD22", "PD23";
741				function = "emac";
742				drive-strength = <40>;
743			};
744
745			spdif_tx_pin: spdif-tx-pin {
746				pins = "PH8";
747				function = "spdif";
748			};
749
750			spi0_pins: spi0-pins {
751				pins = "PC0", "PC1", "PC2", "PC3";
752				function = "spi0";
753			};
754
755			spi1_pins: spi1-pins {
756				pins = "PD0", "PD1", "PD2", "PD3";
757				function = "spi1";
758			};
759
760			uart0_pb_pins: uart0-pb-pins {
761				pins = "PB8", "PB9";
762				function = "uart0";
763			};
764
765			uart1_pins: uart1-pins {
766				pins = "PG6", "PG7";
767				function = "uart1";
768			};
769
770			uart1_rts_cts_pins: uart1-rts-cts-pins {
771				pins = "PG8", "PG9";
772				function = "uart1";
773			};
774
775			uart2_pins: uart2-pins {
776				pins = "PB0", "PB1";
777				function = "uart2";
778			};
779
780			uart3_pins: uart3-pins {
781				pins = "PD0", "PD1";
782				function = "uart3";
783			};
784
785			uart4_pins: uart4-pins {
786				pins = "PD2", "PD3";
787				function = "uart4";
788			};
789
790			uart4_rts_cts_pins: uart4-rts-cts-pins {
791				pins = "PD4", "PD5";
792				function = "uart4";
793			};
794		};
795
796		spdif: spdif@1c21000 {
797			#sound-dai-cells = <0>;
798			compatible = "allwinner,sun50i-a64-spdif",
799				     "allwinner,sun8i-h3-spdif";
800			reg = <0x01c21000 0x400>;
801			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
802			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
803			resets = <&ccu RST_BUS_SPDIF>;
804			clock-names = "apb", "spdif";
805			dmas = <&dma 2>;
806			dma-names = "tx";
807			pinctrl-names = "default";
808			pinctrl-0 = <&spdif_tx_pin>;
809			status = "disabled";
810		};
811
812		lradc: lradc@1c21800 {
813			compatible = "allwinner,sun50i-a64-lradc",
814				     "allwinner,sun8i-a83t-r-lradc";
815			reg = <0x01c21800 0x400>;
816			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
817			status = "disabled";
818		};
819
820		i2s0: i2s@1c22000 {
821			#sound-dai-cells = <0>;
822			compatible = "allwinner,sun50i-a64-i2s",
823				     "allwinner,sun8i-h3-i2s";
824			reg = <0x01c22000 0x400>;
825			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
826			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
827			clock-names = "apb", "mod";
828			resets = <&ccu RST_BUS_I2S0>;
829			dma-names = "rx", "tx";
830			dmas = <&dma 3>, <&dma 3>;
831			status = "disabled";
832		};
833
834		i2s1: i2s@1c22400 {
835			#sound-dai-cells = <0>;
836			compatible = "allwinner,sun50i-a64-i2s",
837				     "allwinner,sun8i-h3-i2s";
838			reg = <0x01c22400 0x400>;
839			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
840			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
841			clock-names = "apb", "mod";
842			resets = <&ccu RST_BUS_I2S1>;
843			dma-names = "rx", "tx";
844			dmas = <&dma 4>, <&dma 4>;
845			status = "disabled";
846		};
847
848		dai: dai@1c22c00 {
849			#sound-dai-cells = <0>;
850			compatible = "allwinner,sun50i-a64-codec-i2s";
851			reg = <0x01c22c00 0x200>;
852			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
853			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
854			clock-names = "apb", "mod";
855			resets = <&ccu RST_BUS_CODEC>;
856			dmas = <&dma 15>, <&dma 15>;
857			dma-names = "rx", "tx";
858			status = "disabled";
859		};
860
861		codec: codec@1c22e00 {
862			#sound-dai-cells = <0>;
863			compatible = "allwinner,sun8i-a33-codec";
864			reg = <0x01c22e00 0x600>;
865			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
866			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
867			clock-names = "bus", "mod";
868			status = "disabled";
869		};
870
871		ths: thermal-sensor@1c25000 {
872			compatible = "allwinner,sun50i-a64-ths";
873			reg = <0x01c25000 0x100>;
874			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
875			clock-names = "bus", "mod";
876			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
877			resets = <&ccu RST_BUS_THS>;
878			nvmem-cells = <&ths_calibration>;
879			nvmem-cell-names = "calibration";
880			#thermal-sensor-cells = <1>;
881		};
882
883		uart0: serial@1c28000 {
884			compatible = "snps,dw-apb-uart";
885			reg = <0x01c28000 0x400>;
886			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
887			reg-shift = <2>;
888			reg-io-width = <4>;
889			clocks = <&ccu CLK_BUS_UART0>;
890			resets = <&ccu RST_BUS_UART0>;
891			status = "disabled";
892		};
893
894		uart1: serial@1c28400 {
895			compatible = "snps,dw-apb-uart";
896			reg = <0x01c28400 0x400>;
897			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
898			reg-shift = <2>;
899			reg-io-width = <4>;
900			clocks = <&ccu CLK_BUS_UART1>;
901			resets = <&ccu RST_BUS_UART1>;
902			status = "disabled";
903		};
904
905		uart2: serial@1c28800 {
906			compatible = "snps,dw-apb-uart";
907			reg = <0x01c28800 0x400>;
908			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
909			reg-shift = <2>;
910			reg-io-width = <4>;
911			clocks = <&ccu CLK_BUS_UART2>;
912			resets = <&ccu RST_BUS_UART2>;
913			status = "disabled";
914		};
915
916		uart3: serial@1c28c00 {
917			compatible = "snps,dw-apb-uart";
918			reg = <0x01c28c00 0x400>;
919			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
920			reg-shift = <2>;
921			reg-io-width = <4>;
922			clocks = <&ccu CLK_BUS_UART3>;
923			resets = <&ccu RST_BUS_UART3>;
924			status = "disabled";
925		};
926
927		uart4: serial@1c29000 {
928			compatible = "snps,dw-apb-uart";
929			reg = <0x01c29000 0x400>;
930			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
931			reg-shift = <2>;
932			reg-io-width = <4>;
933			clocks = <&ccu CLK_BUS_UART4>;
934			resets = <&ccu RST_BUS_UART4>;
935			status = "disabled";
936		};
937
938		i2c0: i2c@1c2ac00 {
939			compatible = "allwinner,sun6i-a31-i2c";
940			reg = <0x01c2ac00 0x400>;
941			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
942			clocks = <&ccu CLK_BUS_I2C0>;
943			resets = <&ccu RST_BUS_I2C0>;
944			pinctrl-names = "default";
945			pinctrl-0 = <&i2c0_pins>;
946			status = "disabled";
947			#address-cells = <1>;
948			#size-cells = <0>;
949		};
950
951		i2c1: i2c@1c2b000 {
952			compatible = "allwinner,sun6i-a31-i2c";
953			reg = <0x01c2b000 0x400>;
954			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
955			clocks = <&ccu CLK_BUS_I2C1>;
956			resets = <&ccu RST_BUS_I2C1>;
957			pinctrl-names = "default";
958			pinctrl-0 = <&i2c1_pins>;
959			status = "disabled";
960			#address-cells = <1>;
961			#size-cells = <0>;
962		};
963
964		i2c2: i2c@1c2b400 {
965			compatible = "allwinner,sun6i-a31-i2c";
966			reg = <0x01c2b400 0x400>;
967			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
968			clocks = <&ccu CLK_BUS_I2C2>;
969			resets = <&ccu RST_BUS_I2C2>;
970			pinctrl-names = "default";
971			pinctrl-0 = <&i2c2_pins>;
972			status = "disabled";
973			#address-cells = <1>;
974			#size-cells = <0>;
975		};
976
977		spi0: spi@1c68000 {
978			compatible = "allwinner,sun8i-h3-spi";
979			reg = <0x01c68000 0x1000>;
980			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
981			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
982			clock-names = "ahb", "mod";
983			dmas = <&dma 23>, <&dma 23>;
984			dma-names = "rx", "tx";
985			pinctrl-names = "default";
986			pinctrl-0 = <&spi0_pins>;
987			resets = <&ccu RST_BUS_SPI0>;
988			status = "disabled";
989			num-cs = <1>;
990			#address-cells = <1>;
991			#size-cells = <0>;
992		};
993
994		spi1: spi@1c69000 {
995			compatible = "allwinner,sun8i-h3-spi";
996			reg = <0x01c69000 0x1000>;
997			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
998			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
999			clock-names = "ahb", "mod";
1000			dmas = <&dma 24>, <&dma 24>;
1001			dma-names = "rx", "tx";
1002			pinctrl-names = "default";
1003			pinctrl-0 = <&spi1_pins>;
1004			resets = <&ccu RST_BUS_SPI1>;
1005			status = "disabled";
1006			num-cs = <1>;
1007			#address-cells = <1>;
1008			#size-cells = <0>;
1009		};
1010
1011		emac: ethernet@1c30000 {
1012			compatible = "allwinner,sun50i-a64-emac";
1013			syscon = <&syscon>;
1014			reg = <0x01c30000 0x10000>;
1015			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1016			interrupt-names = "macirq";
1017			resets = <&ccu RST_BUS_EMAC>;
1018			reset-names = "stmmaceth";
1019			clocks = <&ccu CLK_BUS_EMAC>;
1020			clock-names = "stmmaceth";
1021			status = "disabled";
1022
1023			mdio: mdio {
1024				compatible = "snps,dwmac-mdio";
1025				#address-cells = <1>;
1026				#size-cells = <0>;
1027			};
1028		};
1029
1030		mali: gpu@1c40000 {
1031			compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1032			reg = <0x01c40000 0x10000>;
1033			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1034				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1035				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1036				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1037				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1038				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1039				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1040			interrupt-names = "gp",
1041					  "gpmmu",
1042					  "pp0",
1043					  "ppmmu0",
1044					  "pp1",
1045					  "ppmmu1",
1046					  "pmu";
1047			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1048			clock-names = "bus", "core";
1049			resets = <&ccu RST_BUS_GPU>;
1050		};
1051
1052		gic: interrupt-controller@1c81000 {
1053			compatible = "arm,gic-400";
1054			reg = <0x01c81000 0x1000>,
1055			      <0x01c82000 0x2000>,
1056			      <0x01c84000 0x2000>,
1057			      <0x01c86000 0x2000>;
1058			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1059			interrupt-controller;
1060			#interrupt-cells = <3>;
1061		};
1062
1063		pwm: pwm@1c21400 {
1064			compatible = "allwinner,sun50i-a64-pwm",
1065				     "allwinner,sun5i-a13-pwm";
1066			reg = <0x01c21400 0x400>;
1067			clocks = <&osc24M>;
1068			pinctrl-names = "default";
1069			pinctrl-0 = <&pwm_pin>;
1070			#pwm-cells = <3>;
1071			status = "disabled";
1072		};
1073
1074		mbus: dram-controller@1c62000 {
1075			compatible = "allwinner,sun50i-a64-mbus";
1076			reg = <0x01c62000 0x1000>;
1077			clocks = <&ccu 112>;
1078			#address-cells = <1>;
1079			#size-cells = <1>;
1080			dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1081			#interconnect-cells = <1>;
1082		};
1083
1084		csi: csi@1cb0000 {
1085			compatible = "allwinner,sun50i-a64-csi";
1086			reg = <0x01cb0000 0x1000>;
1087			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1088			clocks = <&ccu CLK_BUS_CSI>,
1089				 <&ccu CLK_CSI_SCLK>,
1090				 <&ccu CLK_DRAM_CSI>;
1091			clock-names = "bus", "mod", "ram";
1092			resets = <&ccu RST_BUS_CSI>;
1093			pinctrl-names = "default";
1094			pinctrl-0 = <&csi_pins>;
1095			status = "disabled";
1096		};
1097
1098		dsi: dsi@1ca0000 {
1099			compatible = "allwinner,sun50i-a64-mipi-dsi";
1100			reg = <0x01ca0000 0x1000>;
1101			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1102			clocks = <&ccu CLK_BUS_MIPI_DSI>;
1103			resets = <&ccu RST_BUS_MIPI_DSI>;
1104			phys = <&dphy>;
1105			phy-names = "dphy";
1106			status = "disabled";
1107			#address-cells = <1>;
1108			#size-cells = <0>;
1109
1110			port {
1111				dsi_in_tcon0: endpoint {
1112					remote-endpoint = <&tcon0_out_dsi>;
1113				};
1114			};
1115		};
1116
1117		dphy: d-phy@1ca1000 {
1118			compatible = "allwinner,sun50i-a64-mipi-dphy",
1119				     "allwinner,sun6i-a31-mipi-dphy";
1120			reg = <0x01ca1000 0x1000>;
1121			clocks = <&ccu CLK_BUS_MIPI_DSI>,
1122				 <&ccu CLK_DSI_DPHY>;
1123			clock-names = "bus", "mod";
1124			resets = <&ccu RST_BUS_MIPI_DSI>;
1125			status = "disabled";
1126			#phy-cells = <0>;
1127		};
1128
1129		deinterlace: deinterlace@1e00000 {
1130			compatible = "allwinner,sun50i-a64-deinterlace",
1131				     "allwinner,sun8i-h3-deinterlace";
1132			reg = <0x01e00000 0x20000>;
1133			clocks = <&ccu CLK_BUS_DEINTERLACE>,
1134				 <&ccu CLK_DEINTERLACE>,
1135				 <&ccu CLK_DRAM_DEINTERLACE>;
1136			clock-names = "bus", "mod", "ram";
1137			resets = <&ccu RST_BUS_DEINTERLACE>;
1138			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1139			interconnects = <&mbus 9>;
1140			interconnect-names = "dma-mem";
1141		};
1142
1143		hdmi: hdmi@1ee0000 {
1144			compatible = "allwinner,sun50i-a64-dw-hdmi",
1145				     "allwinner,sun8i-a83t-dw-hdmi";
1146			reg = <0x01ee0000 0x10000>;
1147			reg-io-width = <1>;
1148			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1149			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1150				 <&ccu CLK_HDMI>;
1151			clock-names = "iahb", "isfr", "tmds";
1152			resets = <&ccu RST_BUS_HDMI1>;
1153			reset-names = "ctrl";
1154			phys = <&hdmi_phy>;
1155			phy-names = "phy";
1156			status = "disabled";
1157
1158			ports {
1159				#address-cells = <1>;
1160				#size-cells = <0>;
1161
1162				hdmi_in: port@0 {
1163					reg = <0>;
1164
1165					hdmi_in_tcon1: endpoint {
1166						remote-endpoint = <&tcon1_out_hdmi>;
1167					};
1168				};
1169
1170				hdmi_out: port@1 {
1171					reg = <1>;
1172				};
1173			};
1174		};
1175
1176		hdmi_phy: hdmi-phy@1ef0000 {
1177			compatible = "allwinner,sun50i-a64-hdmi-phy";
1178			reg = <0x01ef0000 0x10000>;
1179			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1180				 <&ccu CLK_PLL_VIDEO0>;
1181			clock-names = "bus", "mod", "pll-0";
1182			resets = <&ccu RST_BUS_HDMI0>;
1183			reset-names = "phy";
1184			#phy-cells = <0>;
1185		};
1186
1187		rtc: rtc@1f00000 {
1188			compatible = "allwinner,sun50i-a64-rtc",
1189				     "allwinner,sun8i-h3-rtc";
1190			reg = <0x01f00000 0x400>;
1191			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1192				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1193			clock-output-names = "osc32k", "osc32k-out", "iosc";
1194			clocks = <&osc32k>;
1195			#clock-cells = <1>;
1196		};
1197
1198		r_intc: interrupt-controller@1f00c00 {
1199			compatible = "allwinner,sun50i-a64-r-intc",
1200				     "allwinner,sun6i-a31-r-intc";
1201			interrupt-controller;
1202			#interrupt-cells = <2>;
1203			reg = <0x01f00c00 0x400>;
1204			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1205		};
1206
1207		r_ccu: clock@1f01400 {
1208			compatible = "allwinner,sun50i-a64-r-ccu";
1209			reg = <0x01f01400 0x100>;
1210			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1211				 <&ccu CLK_PLL_PERIPH0>;
1212			clock-names = "hosc", "losc", "iosc", "pll-periph";
1213			#clock-cells = <1>;
1214			#reset-cells = <1>;
1215		};
1216
1217		codec_analog: codec-analog@1f015c0 {
1218			compatible = "allwinner,sun50i-a64-codec-analog";
1219			reg = <0x01f015c0 0x4>;
1220			status = "disabled";
1221		};
1222
1223		r_i2c: i2c@1f02400 {
1224			compatible = "allwinner,sun50i-a64-i2c",
1225				     "allwinner,sun6i-a31-i2c";
1226			reg = <0x01f02400 0x400>;
1227			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1228			clocks = <&r_ccu CLK_APB0_I2C>;
1229			resets = <&r_ccu RST_APB0_I2C>;
1230			status = "disabled";
1231			#address-cells = <1>;
1232			#size-cells = <0>;
1233		};
1234
1235		r_ir: ir@1f02000 {
1236			compatible = "allwinner,sun50i-a64-ir",
1237				     "allwinner,sun6i-a31-ir";
1238			reg = <0x01f02000 0x400>;
1239			clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1240			clock-names = "apb", "ir";
1241			resets = <&r_ccu RST_APB0_IR>;
1242			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1243			pinctrl-names = "default";
1244			pinctrl-0 = <&r_ir_rx_pin>;
1245			status = "disabled";
1246		};
1247
1248		r_pwm: pwm@1f03800 {
1249			compatible = "allwinner,sun50i-a64-pwm",
1250				     "allwinner,sun5i-a13-pwm";
1251			reg = <0x01f03800 0x400>;
1252			clocks = <&osc24M>;
1253			pinctrl-names = "default";
1254			pinctrl-0 = <&r_pwm_pin>;
1255			#pwm-cells = <3>;
1256			status = "disabled";
1257		};
1258
1259		r_pio: pinctrl@1f02c00 {
1260			compatible = "allwinner,sun50i-a64-r-pinctrl";
1261			reg = <0x01f02c00 0x400>;
1262			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1263			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1264			clock-names = "apb", "hosc", "losc";
1265			gpio-controller;
1266			#gpio-cells = <3>;
1267			interrupt-controller;
1268			#interrupt-cells = <3>;
1269
1270			r_i2c_pl89_pins: r-i2c-pl89-pins {
1271				pins = "PL8", "PL9";
1272				function = "s_i2c";
1273			};
1274
1275			r_ir_rx_pin: r-ir-rx-pin {
1276				pins = "PL11";
1277				function = "s_cir_rx";
1278			};
1279
1280			r_pwm_pin: r-pwm-pin {
1281				pins = "PL10";
1282				function = "s_pwm";
1283			};
1284
1285			r_rsb_pins: r-rsb-pins {
1286				pins = "PL0", "PL1";
1287				function = "s_rsb";
1288			};
1289		};
1290
1291		r_rsb: rsb@1f03400 {
1292			compatible = "allwinner,sun8i-a23-rsb";
1293			reg = <0x01f03400 0x400>;
1294			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1295			clocks = <&r_ccu 6>;
1296			clock-frequency = <3000000>;
1297			resets = <&r_ccu 2>;
1298			pinctrl-names = "default";
1299			pinctrl-0 = <&r_rsb_pins>;
1300			status = "disabled";
1301			#address-cells = <1>;
1302			#size-cells = <0>;
1303		};
1304
1305		wdt0: watchdog@1c20ca0 {
1306			compatible = "allwinner,sun50i-a64-wdt",
1307				     "allwinner,sun6i-a31-wdt";
1308			reg = <0x01c20ca0 0x20>;
1309			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1310			clocks = <&osc24M>;
1311		};
1312	};
1313};
1314