1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Renesas Clock Pulse Generator / Module Standby and Software Reset
8
9maintainers:
10  - Geert Uytterhoeven <geert+renesas@glider.be>
11
12description: |
13  On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
14  and MSSR (Module Standby and Software Reset) blocks are intimately connected,
15  and share the same register block.
16
17  They provide the following functionalities:
18    - The CPG block generates various core clocks,
19    - The MSSR block provides two functions:
20        1. Module Standby, providing a Clock Domain to control the clock supply
21           to individual SoC devices,
22        2. Reset Control, to perform a software reset of individual SoC devices.
23
24properties:
25  compatible:
26    enum:
27      - renesas,r7s9210-cpg-mssr  # RZ/A2
28      - renesas,r8a7742-cpg-mssr  # RZ/G1H
29      - renesas,r8a7743-cpg-mssr  # RZ/G1M
30      - renesas,r8a7744-cpg-mssr  # RZ/G1N
31      - renesas,r8a7745-cpg-mssr  # RZ/G1E
32      - renesas,r8a77470-cpg-mssr # RZ/G1C
33      - renesas,r8a774a1-cpg-mssr # RZ/G2M
34      - renesas,r8a774b1-cpg-mssr # RZ/G2N
35      - renesas,r8a774c0-cpg-mssr # RZ/G2E
36      - renesas,r8a774e1-cpg-mssr # RZ/G2H
37      - renesas,r8a7790-cpg-mssr  # R-Car H2
38      - renesas,r8a7791-cpg-mssr  # R-Car M2-W
39      - renesas,r8a7792-cpg-mssr  # R-Car V2H
40      - renesas,r8a7793-cpg-mssr  # R-Car M2-N
41      - renesas,r8a7794-cpg-mssr  # R-Car E2
42      - renesas,r8a7795-cpg-mssr  # R-Car H3
43      - renesas,r8a7796-cpg-mssr  # R-Car M3-W
44      - renesas,r8a77961-cpg-mssr # R-Car M3-W+
45      - renesas,r8a77965-cpg-mssr # R-Car M3-N
46      - renesas,r8a77970-cpg-mssr # R-Car V3M
47      - renesas,r8a77980-cpg-mssr # R-Car V3H
48      - renesas,r8a77990-cpg-mssr # R-Car E3
49      - renesas,r8a77995-cpg-mssr # R-Car D3
50
51  reg:
52    maxItems: 1
53
54  clocks:
55    minItems: 1
56    maxItems: 2
57
58  clock-names:
59    minItems: 1
60    maxItems: 2
61    items:
62      enum:
63        - extal     # All
64        - extalr    # Most R-Car Gen3 and RZ/G2
65        - usb_extal # Most R-Car Gen2 and RZ/G1
66
67  '#clock-cells':
68    description: |
69      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
70        and a core clock reference, as defined in
71        <dt-bindings/clock/*-cpg-mssr.h>
72      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
73        a module number, as defined in the datasheet.
74    const: 2
75
76  '#power-domain-cells':
77    description:
78      SoC devices that are part of the CPG/MSSR Clock Domain and can be
79      power-managed through Module Standby should refer to the CPG device node
80      in their "power-domains" property, as documented by the generic PM Domain
81      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
82    const: 0
83
84  '#reset-cells':
85    description:
86      The single reset specifier cell must be the module number, as defined in
87      the datasheet.
88    const: 1
89
90if:
91  not:
92    properties:
93      compatible:
94        items:
95          enum:
96            - renesas,r7s9210-cpg-mssr
97then:
98  required:
99    - '#reset-cells'
100
101required:
102  - compatible
103  - reg
104  - clocks
105  - clock-names
106  - '#clock-cells'
107  - '#power-domain-cells'
108
109additionalProperties: false
110
111examples:
112  - |
113    cpg: clock-controller@e6150000 {
114            compatible = "renesas,r8a7795-cpg-mssr";
115            reg = <0xe6150000 0x1000>;
116            clocks = <&extal_clk>, <&extalr_clk>;
117            clock-names = "extal", "extalr";
118            #clock-cells = <2>;
119            #power-domain-cells = <0>;
120            #reset-cells = <1>;
121    };
122