1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * KVM/MIPS: MIPS specific KVM APIs 7 * 8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 9 * Authors: Sanjay Lal <sanjayl@kymasys.com> 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/errno.h> 14 #include <linux/err.h> 15 #include <linux/kdebug.h> 16 #include <linux/module.h> 17 #include <linux/uaccess.h> 18 #include <linux/vmalloc.h> 19 #include <linux/sched/signal.h> 20 #include <linux/fs.h> 21 #include <linux/memblock.h> 22 23 #include <asm/fpu.h> 24 #include <asm/page.h> 25 #include <asm/cacheflush.h> 26 #include <asm/mmu_context.h> 27 #include <asm/pgalloc.h> 28 #include <asm/pgtable.h> 29 30 #include <linux/kvm_host.h> 31 32 #include "interrupt.h" 33 #include "commpage.h" 34 35 #define CREATE_TRACE_POINTS 36 #include "trace.h" 37 38 #ifndef VECTORSPACING 39 #define VECTORSPACING 0x100 /* for EI/VI mode */ 40 #endif 41 42 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x) 43 struct kvm_stats_debugfs_item debugfs_entries[] = { 44 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU }, 45 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU }, 46 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU }, 47 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU }, 48 { "cop_unusable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU }, 49 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU }, 50 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU }, 51 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU }, 52 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU }, 53 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU }, 54 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU }, 55 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU }, 56 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU }, 57 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU }, 58 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU }, 59 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU }, 60 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU }, 61 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU }, 62 #ifdef CONFIG_KVM_MIPS_VZ 63 { "vz_gpsi", VCPU_STAT(vz_gpsi_exits), KVM_STAT_VCPU }, 64 { "vz_gsfc", VCPU_STAT(vz_gsfc_exits), KVM_STAT_VCPU }, 65 { "vz_hc", VCPU_STAT(vz_hc_exits), KVM_STAT_VCPU }, 66 { "vz_grr", VCPU_STAT(vz_grr_exits), KVM_STAT_VCPU }, 67 { "vz_gva", VCPU_STAT(vz_gva_exits), KVM_STAT_VCPU }, 68 { "vz_ghfc", VCPU_STAT(vz_ghfc_exits), KVM_STAT_VCPU }, 69 { "vz_gpa", VCPU_STAT(vz_gpa_exits), KVM_STAT_VCPU }, 70 { "vz_resvd", VCPU_STAT(vz_resvd_exits), KVM_STAT_VCPU }, 71 #endif 72 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU }, 73 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU }, 74 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU }, 75 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU }, 76 {NULL} 77 }; 78 79 bool kvm_trace_guest_mode_change; 80 81 int kvm_guest_mode_change_trace_reg(void) 82 { 83 kvm_trace_guest_mode_change = 1; 84 return 0; 85 } 86 87 void kvm_guest_mode_change_trace_unreg(void) 88 { 89 kvm_trace_guest_mode_change = 0; 90 } 91 92 /* 93 * XXXKYMA: We are simulatoring a processor that has the WII bit set in 94 * Config7, so we are "runnable" if interrupts are pending 95 */ 96 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 97 { 98 return !!(vcpu->arch.pending_exceptions); 99 } 100 101 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 102 { 103 return false; 104 } 105 106 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 107 { 108 return 1; 109 } 110 111 int kvm_arch_hardware_enable(void) 112 { 113 return kvm_mips_callbacks->hardware_enable(); 114 } 115 116 void kvm_arch_hardware_disable(void) 117 { 118 kvm_mips_callbacks->hardware_disable(); 119 } 120 121 int kvm_arch_hardware_setup(void) 122 { 123 return 0; 124 } 125 126 int kvm_arch_check_processor_compat(void) 127 { 128 return 0; 129 } 130 131 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 132 { 133 switch (type) { 134 #ifdef CONFIG_KVM_MIPS_VZ 135 case KVM_VM_MIPS_VZ: 136 #else 137 case KVM_VM_MIPS_TE: 138 #endif 139 break; 140 default: 141 /* Unsupported KVM type */ 142 return -EINVAL; 143 }; 144 145 /* Allocate page table to map GPA -> RPA */ 146 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc(); 147 if (!kvm->arch.gpa_mm.pgd) 148 return -ENOMEM; 149 150 return 0; 151 } 152 153 void kvm_mips_free_vcpus(struct kvm *kvm) 154 { 155 unsigned int i; 156 struct kvm_vcpu *vcpu; 157 158 kvm_for_each_vcpu(i, vcpu, kvm) { 159 kvm_vcpu_destroy(vcpu); 160 } 161 162 mutex_lock(&kvm->lock); 163 164 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 165 kvm->vcpus[i] = NULL; 166 167 atomic_set(&kvm->online_vcpus, 0); 168 169 mutex_unlock(&kvm->lock); 170 } 171 172 static void kvm_mips_free_gpa_pt(struct kvm *kvm) 173 { 174 /* It should always be safe to remove after flushing the whole range */ 175 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0)); 176 pgd_free(NULL, kvm->arch.gpa_mm.pgd); 177 } 178 179 void kvm_arch_destroy_vm(struct kvm *kvm) 180 { 181 kvm_mips_free_vcpus(kvm); 182 kvm_mips_free_gpa_pt(kvm); 183 } 184 185 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, 186 unsigned long arg) 187 { 188 return -ENOIOCTLCMD; 189 } 190 191 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 192 unsigned long npages) 193 { 194 return 0; 195 } 196 197 void kvm_arch_flush_shadow_all(struct kvm *kvm) 198 { 199 /* Flush whole GPA */ 200 kvm_mips_flush_gpa_pt(kvm, 0, ~0); 201 202 /* Let implementation do the rest */ 203 kvm_mips_callbacks->flush_shadow_all(kvm); 204 } 205 206 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 207 struct kvm_memory_slot *slot) 208 { 209 /* 210 * The slot has been made invalid (ready for moving or deletion), so we 211 * need to ensure that it can no longer be accessed by any guest VCPUs. 212 */ 213 214 spin_lock(&kvm->mmu_lock); 215 /* Flush slot from GPA */ 216 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn, 217 slot->base_gfn + slot->npages - 1); 218 /* Let implementation do the rest */ 219 kvm_mips_callbacks->flush_shadow_memslot(kvm, slot); 220 spin_unlock(&kvm->mmu_lock); 221 } 222 223 int kvm_arch_prepare_memory_region(struct kvm *kvm, 224 struct kvm_memory_slot *memslot, 225 const struct kvm_userspace_memory_region *mem, 226 enum kvm_mr_change change) 227 { 228 return 0; 229 } 230 231 void kvm_arch_commit_memory_region(struct kvm *kvm, 232 const struct kvm_userspace_memory_region *mem, 233 const struct kvm_memory_slot *old, 234 const struct kvm_memory_slot *new, 235 enum kvm_mr_change change) 236 { 237 int needs_flush; 238 239 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n", 240 __func__, kvm, mem->slot, mem->guest_phys_addr, 241 mem->memory_size, mem->userspace_addr); 242 243 /* 244 * If dirty page logging is enabled, write protect all pages in the slot 245 * ready for dirty logging. 246 * 247 * There is no need to do this in any of the following cases: 248 * CREATE: No dirty mappings will already exist. 249 * MOVE/DELETE: The old mappings will already have been cleaned up by 250 * kvm_arch_flush_shadow_memslot() 251 */ 252 if (change == KVM_MR_FLAGS_ONLY && 253 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 254 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) { 255 spin_lock(&kvm->mmu_lock); 256 /* Write protect GPA page table entries */ 257 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn, 258 new->base_gfn + new->npages - 1); 259 /* Let implementation do the rest */ 260 if (needs_flush) 261 kvm_mips_callbacks->flush_shadow_memslot(kvm, new); 262 spin_unlock(&kvm->mmu_lock); 263 } 264 } 265 266 static inline void dump_handler(const char *symbol, void *start, void *end) 267 { 268 u32 *p; 269 270 pr_debug("LEAF(%s)\n", symbol); 271 272 pr_debug("\t.set push\n"); 273 pr_debug("\t.set noreorder\n"); 274 275 for (p = start; p < (u32 *)end; ++p) 276 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p); 277 278 pr_debug("\t.set\tpop\n"); 279 280 pr_debug("\tEND(%s)\n", symbol); 281 } 282 283 /* low level hrtimer wake routine */ 284 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer) 285 { 286 struct kvm_vcpu *vcpu; 287 288 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer); 289 290 kvm_mips_callbacks->queue_timer_int(vcpu); 291 292 vcpu->arch.wait = 0; 293 if (swq_has_sleeper(&vcpu->wq)) 294 swake_up_one(&vcpu->wq); 295 296 return kvm_mips_count_timeout(vcpu); 297 } 298 299 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 300 { 301 return 0; 302 } 303 304 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 305 { 306 int err, size; 307 void *gebase, *p, *handler, *refill_start, *refill_end; 308 int i; 309 310 kvm_debug("kvm @ %p: create cpu %d at %p\n", 311 vcpu->kvm, vcpu->vcpu_id, vcpu); 312 313 err = kvm_mips_callbacks->vcpu_init(vcpu); 314 if (err) 315 return err; 316 317 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, 318 HRTIMER_MODE_REL); 319 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; 320 321 /* 322 * Allocate space for host mode exception handlers that handle 323 * guest mode exits 324 */ 325 if (cpu_has_veic || cpu_has_vint) 326 size = 0x200 + VECTORSPACING * 64; 327 else 328 size = 0x4000; 329 330 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL); 331 332 if (!gebase) { 333 err = -ENOMEM; 334 goto out_uninit_vcpu; 335 } 336 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n", 337 ALIGN(size, PAGE_SIZE), gebase); 338 339 /* 340 * Check new ebase actually fits in CP0_EBase. The lack of a write gate 341 * limits us to the low 512MB of physical address space. If the memory 342 * we allocate is out of range, just give up now. 343 */ 344 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) { 345 kvm_err("CP0_EBase.WG required for guest exception base %pK\n", 346 gebase); 347 err = -ENOMEM; 348 goto out_free_gebase; 349 } 350 351 /* Save new ebase */ 352 vcpu->arch.guest_ebase = gebase; 353 354 /* Build guest exception vectors dynamically in unmapped memory */ 355 handler = gebase + 0x2000; 356 357 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */ 358 refill_start = gebase; 359 if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT)) 360 refill_start += 0x080; 361 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler); 362 363 /* General Exception Entry point */ 364 kvm_mips_build_exception(gebase + 0x180, handler); 365 366 /* For vectored interrupts poke the exception code @ all offsets 0-7 */ 367 for (i = 0; i < 8; i++) { 368 kvm_debug("L1 Vectored handler @ %p\n", 369 gebase + 0x200 + (i * VECTORSPACING)); 370 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING, 371 handler); 372 } 373 374 /* General exit handler */ 375 p = handler; 376 p = kvm_mips_build_exit(p); 377 378 /* Guest entry routine */ 379 vcpu->arch.vcpu_run = p; 380 p = kvm_mips_build_vcpu_run(p); 381 382 /* Dump the generated code */ 383 pr_debug("#include <asm/asm.h>\n"); 384 pr_debug("#include <asm/regdef.h>\n"); 385 pr_debug("\n"); 386 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p); 387 dump_handler("kvm_tlb_refill", refill_start, refill_end); 388 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200); 389 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run); 390 391 /* Invalidate the icache for these ranges */ 392 flush_icache_range((unsigned long)gebase, 393 (unsigned long)gebase + ALIGN(size, PAGE_SIZE)); 394 395 /* 396 * Allocate comm page for guest kernel, a TLB will be reserved for 397 * mapping GVA @ 0xFFFF8000 to this page 398 */ 399 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL); 400 401 if (!vcpu->arch.kseg0_commpage) { 402 err = -ENOMEM; 403 goto out_free_gebase; 404 } 405 406 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage); 407 kvm_mips_commpage_init(vcpu); 408 409 /* Init */ 410 vcpu->arch.last_sched_cpu = -1; 411 vcpu->arch.last_exec_cpu = -1; 412 413 /* Initial guest state */ 414 err = kvm_mips_callbacks->vcpu_setup(vcpu); 415 if (err) 416 goto out_free_commpage; 417 418 return 0; 419 420 out_free_commpage: 421 kfree(vcpu->arch.kseg0_commpage); 422 out_free_gebase: 423 kfree(gebase); 424 out_uninit_vcpu: 425 kvm_mips_callbacks->vcpu_uninit(vcpu); 426 return err; 427 } 428 429 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 430 { 431 hrtimer_cancel(&vcpu->arch.comparecount_timer); 432 433 kvm_mips_dump_stats(vcpu); 434 435 kvm_mmu_free_memory_caches(vcpu); 436 kfree(vcpu->arch.guest_ebase); 437 kfree(vcpu->arch.kseg0_commpage); 438 439 kvm_mips_callbacks->vcpu_uninit(vcpu); 440 } 441 442 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 443 struct kvm_guest_debug *dbg) 444 { 445 return -ENOIOCTLCMD; 446 } 447 448 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) 449 { 450 int r = -EINTR; 451 452 vcpu_load(vcpu); 453 454 kvm_sigset_activate(vcpu); 455 456 if (vcpu->mmio_needed) { 457 if (!vcpu->mmio_is_write) 458 kvm_mips_complete_mmio_load(vcpu, run); 459 vcpu->mmio_needed = 0; 460 } 461 462 if (run->immediate_exit) 463 goto out; 464 465 lose_fpu(1); 466 467 local_irq_disable(); 468 guest_enter_irqoff(); 469 trace_kvm_enter(vcpu); 470 471 /* 472 * Make sure the read of VCPU requests in vcpu_run() callback is not 473 * reordered ahead of the write to vcpu->mode, or we could miss a TLB 474 * flush request while the requester sees the VCPU as outside of guest 475 * mode and not needing an IPI. 476 */ 477 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 478 479 r = kvm_mips_callbacks->vcpu_run(run, vcpu); 480 481 trace_kvm_out(vcpu); 482 guest_exit_irqoff(); 483 local_irq_enable(); 484 485 out: 486 kvm_sigset_deactivate(vcpu); 487 488 vcpu_put(vcpu); 489 return r; 490 } 491 492 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 493 struct kvm_mips_interrupt *irq) 494 { 495 int intr = (int)irq->irq; 496 struct kvm_vcpu *dvcpu = NULL; 497 498 if (intr == 3 || intr == -3 || intr == 4 || intr == -4) 499 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu, 500 (int)intr); 501 502 if (irq->cpu == -1) 503 dvcpu = vcpu; 504 else 505 dvcpu = vcpu->kvm->vcpus[irq->cpu]; 506 507 if (intr == 2 || intr == 3 || intr == 4) { 508 kvm_mips_callbacks->queue_io_int(dvcpu, irq); 509 510 } else if (intr == -2 || intr == -3 || intr == -4) { 511 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq); 512 } else { 513 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__, 514 irq->cpu, irq->irq); 515 return -EINVAL; 516 } 517 518 dvcpu->arch.wait = 0; 519 520 if (swq_has_sleeper(&dvcpu->wq)) 521 swake_up_one(&dvcpu->wq); 522 523 return 0; 524 } 525 526 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 527 struct kvm_mp_state *mp_state) 528 { 529 return -ENOIOCTLCMD; 530 } 531 532 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 533 struct kvm_mp_state *mp_state) 534 { 535 return -ENOIOCTLCMD; 536 } 537 538 static u64 kvm_mips_get_one_regs[] = { 539 KVM_REG_MIPS_R0, 540 KVM_REG_MIPS_R1, 541 KVM_REG_MIPS_R2, 542 KVM_REG_MIPS_R3, 543 KVM_REG_MIPS_R4, 544 KVM_REG_MIPS_R5, 545 KVM_REG_MIPS_R6, 546 KVM_REG_MIPS_R7, 547 KVM_REG_MIPS_R8, 548 KVM_REG_MIPS_R9, 549 KVM_REG_MIPS_R10, 550 KVM_REG_MIPS_R11, 551 KVM_REG_MIPS_R12, 552 KVM_REG_MIPS_R13, 553 KVM_REG_MIPS_R14, 554 KVM_REG_MIPS_R15, 555 KVM_REG_MIPS_R16, 556 KVM_REG_MIPS_R17, 557 KVM_REG_MIPS_R18, 558 KVM_REG_MIPS_R19, 559 KVM_REG_MIPS_R20, 560 KVM_REG_MIPS_R21, 561 KVM_REG_MIPS_R22, 562 KVM_REG_MIPS_R23, 563 KVM_REG_MIPS_R24, 564 KVM_REG_MIPS_R25, 565 KVM_REG_MIPS_R26, 566 KVM_REG_MIPS_R27, 567 KVM_REG_MIPS_R28, 568 KVM_REG_MIPS_R29, 569 KVM_REG_MIPS_R30, 570 KVM_REG_MIPS_R31, 571 572 #ifndef CONFIG_CPU_MIPSR6 573 KVM_REG_MIPS_HI, 574 KVM_REG_MIPS_LO, 575 #endif 576 KVM_REG_MIPS_PC, 577 }; 578 579 static u64 kvm_mips_get_one_regs_fpu[] = { 580 KVM_REG_MIPS_FCR_IR, 581 KVM_REG_MIPS_FCR_CSR, 582 }; 583 584 static u64 kvm_mips_get_one_regs_msa[] = { 585 KVM_REG_MIPS_MSA_IR, 586 KVM_REG_MIPS_MSA_CSR, 587 }; 588 589 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu) 590 { 591 unsigned long ret; 592 593 ret = ARRAY_SIZE(kvm_mips_get_one_regs); 594 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 595 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48; 596 /* odd doubles */ 597 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64) 598 ret += 16; 599 } 600 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) 601 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32; 602 ret += kvm_mips_callbacks->num_regs(vcpu); 603 604 return ret; 605 } 606 607 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) 608 { 609 u64 index; 610 unsigned int i; 611 612 if (copy_to_user(indices, kvm_mips_get_one_regs, 613 sizeof(kvm_mips_get_one_regs))) 614 return -EFAULT; 615 indices += ARRAY_SIZE(kvm_mips_get_one_regs); 616 617 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 618 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu, 619 sizeof(kvm_mips_get_one_regs_fpu))) 620 return -EFAULT; 621 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu); 622 623 for (i = 0; i < 32; ++i) { 624 index = KVM_REG_MIPS_FPR_32(i); 625 if (copy_to_user(indices, &index, sizeof(index))) 626 return -EFAULT; 627 ++indices; 628 629 /* skip odd doubles if no F64 */ 630 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64)) 631 continue; 632 633 index = KVM_REG_MIPS_FPR_64(i); 634 if (copy_to_user(indices, &index, sizeof(index))) 635 return -EFAULT; 636 ++indices; 637 } 638 } 639 640 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) { 641 if (copy_to_user(indices, kvm_mips_get_one_regs_msa, 642 sizeof(kvm_mips_get_one_regs_msa))) 643 return -EFAULT; 644 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa); 645 646 for (i = 0; i < 32; ++i) { 647 index = KVM_REG_MIPS_VEC_128(i); 648 if (copy_to_user(indices, &index, sizeof(index))) 649 return -EFAULT; 650 ++indices; 651 } 652 } 653 654 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices); 655 } 656 657 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, 658 const struct kvm_one_reg *reg) 659 { 660 struct mips_coproc *cop0 = vcpu->arch.cop0; 661 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 662 int ret; 663 s64 v; 664 s64 vs[2]; 665 unsigned int idx; 666 667 switch (reg->id) { 668 /* General purpose registers */ 669 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31: 670 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0]; 671 break; 672 #ifndef CONFIG_CPU_MIPSR6 673 case KVM_REG_MIPS_HI: 674 v = (long)vcpu->arch.hi; 675 break; 676 case KVM_REG_MIPS_LO: 677 v = (long)vcpu->arch.lo; 678 break; 679 #endif 680 case KVM_REG_MIPS_PC: 681 v = (long)vcpu->arch.pc; 682 break; 683 684 /* Floating point registers */ 685 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 686 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 687 return -EINVAL; 688 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 689 /* Odd singles in top of even double when FR=0 */ 690 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 691 v = get_fpr32(&fpu->fpr[idx], 0); 692 else 693 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1); 694 break; 695 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 696 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 697 return -EINVAL; 698 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 699 /* Can't access odd doubles in FR=0 mode */ 700 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 701 return -EINVAL; 702 v = get_fpr64(&fpu->fpr[idx], 0); 703 break; 704 case KVM_REG_MIPS_FCR_IR: 705 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 706 return -EINVAL; 707 v = boot_cpu_data.fpu_id; 708 break; 709 case KVM_REG_MIPS_FCR_CSR: 710 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 711 return -EINVAL; 712 v = fpu->fcr31; 713 break; 714 715 /* MIPS SIMD Architecture (MSA) registers */ 716 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 717 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 718 return -EINVAL; 719 /* Can't access MSA registers in FR=0 mode */ 720 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR)) 721 return -EINVAL; 722 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 723 #ifdef CONFIG_CPU_LITTLE_ENDIAN 724 /* least significant byte first */ 725 vs[0] = get_fpr64(&fpu->fpr[idx], 0); 726 vs[1] = get_fpr64(&fpu->fpr[idx], 1); 727 #else 728 /* most significant byte first */ 729 vs[0] = get_fpr64(&fpu->fpr[idx], 1); 730 vs[1] = get_fpr64(&fpu->fpr[idx], 0); 731 #endif 732 break; 733 case KVM_REG_MIPS_MSA_IR: 734 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 735 return -EINVAL; 736 v = boot_cpu_data.msa_id; 737 break; 738 case KVM_REG_MIPS_MSA_CSR: 739 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 740 return -EINVAL; 741 v = fpu->msacsr; 742 break; 743 744 /* registers to be handled specially */ 745 default: 746 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v); 747 if (ret) 748 return ret; 749 break; 750 } 751 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 752 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 753 754 return put_user(v, uaddr64); 755 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 756 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 757 u32 v32 = (u32)v; 758 759 return put_user(v32, uaddr32); 760 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 761 void __user *uaddr = (void __user *)(long)reg->addr; 762 763 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0; 764 } else { 765 return -EINVAL; 766 } 767 } 768 769 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, 770 const struct kvm_one_reg *reg) 771 { 772 struct mips_coproc *cop0 = vcpu->arch.cop0; 773 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 774 s64 v; 775 s64 vs[2]; 776 unsigned int idx; 777 778 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 779 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 780 781 if (get_user(v, uaddr64) != 0) 782 return -EFAULT; 783 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 784 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 785 s32 v32; 786 787 if (get_user(v32, uaddr32) != 0) 788 return -EFAULT; 789 v = (s64)v32; 790 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 791 void __user *uaddr = (void __user *)(long)reg->addr; 792 793 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0; 794 } else { 795 return -EINVAL; 796 } 797 798 switch (reg->id) { 799 /* General purpose registers */ 800 case KVM_REG_MIPS_R0: 801 /* Silently ignore requests to set $0 */ 802 break; 803 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31: 804 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v; 805 break; 806 #ifndef CONFIG_CPU_MIPSR6 807 case KVM_REG_MIPS_HI: 808 vcpu->arch.hi = v; 809 break; 810 case KVM_REG_MIPS_LO: 811 vcpu->arch.lo = v; 812 break; 813 #endif 814 case KVM_REG_MIPS_PC: 815 vcpu->arch.pc = v; 816 break; 817 818 /* Floating point registers */ 819 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 820 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 821 return -EINVAL; 822 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 823 /* Odd singles in top of even double when FR=0 */ 824 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 825 set_fpr32(&fpu->fpr[idx], 0, v); 826 else 827 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v); 828 break; 829 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 830 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 831 return -EINVAL; 832 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 833 /* Can't access odd doubles in FR=0 mode */ 834 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 835 return -EINVAL; 836 set_fpr64(&fpu->fpr[idx], 0, v); 837 break; 838 case KVM_REG_MIPS_FCR_IR: 839 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 840 return -EINVAL; 841 /* Read-only */ 842 break; 843 case KVM_REG_MIPS_FCR_CSR: 844 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 845 return -EINVAL; 846 fpu->fcr31 = v; 847 break; 848 849 /* MIPS SIMD Architecture (MSA) registers */ 850 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 851 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 852 return -EINVAL; 853 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 854 #ifdef CONFIG_CPU_LITTLE_ENDIAN 855 /* least significant byte first */ 856 set_fpr64(&fpu->fpr[idx], 0, vs[0]); 857 set_fpr64(&fpu->fpr[idx], 1, vs[1]); 858 #else 859 /* most significant byte first */ 860 set_fpr64(&fpu->fpr[idx], 1, vs[0]); 861 set_fpr64(&fpu->fpr[idx], 0, vs[1]); 862 #endif 863 break; 864 case KVM_REG_MIPS_MSA_IR: 865 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 866 return -EINVAL; 867 /* Read-only */ 868 break; 869 case KVM_REG_MIPS_MSA_CSR: 870 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 871 return -EINVAL; 872 fpu->msacsr = v; 873 break; 874 875 /* registers to be handled specially */ 876 default: 877 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v); 878 } 879 return 0; 880 } 881 882 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 883 struct kvm_enable_cap *cap) 884 { 885 int r = 0; 886 887 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap)) 888 return -EINVAL; 889 if (cap->flags) 890 return -EINVAL; 891 if (cap->args[0]) 892 return -EINVAL; 893 894 switch (cap->cap) { 895 case KVM_CAP_MIPS_FPU: 896 vcpu->arch.fpu_enabled = true; 897 break; 898 case KVM_CAP_MIPS_MSA: 899 vcpu->arch.msa_enabled = true; 900 break; 901 default: 902 r = -EINVAL; 903 break; 904 } 905 906 return r; 907 } 908 909 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl, 910 unsigned long arg) 911 { 912 struct kvm_vcpu *vcpu = filp->private_data; 913 void __user *argp = (void __user *)arg; 914 915 if (ioctl == KVM_INTERRUPT) { 916 struct kvm_mips_interrupt irq; 917 918 if (copy_from_user(&irq, argp, sizeof(irq))) 919 return -EFAULT; 920 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, 921 irq.irq); 922 923 return kvm_vcpu_ioctl_interrupt(vcpu, &irq); 924 } 925 926 return -ENOIOCTLCMD; 927 } 928 929 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, 930 unsigned long arg) 931 { 932 struct kvm_vcpu *vcpu = filp->private_data; 933 void __user *argp = (void __user *)arg; 934 long r; 935 936 vcpu_load(vcpu); 937 938 switch (ioctl) { 939 case KVM_SET_ONE_REG: 940 case KVM_GET_ONE_REG: { 941 struct kvm_one_reg reg; 942 943 r = -EFAULT; 944 if (copy_from_user(®, argp, sizeof(reg))) 945 break; 946 if (ioctl == KVM_SET_ONE_REG) 947 r = kvm_mips_set_reg(vcpu, ®); 948 else 949 r = kvm_mips_get_reg(vcpu, ®); 950 break; 951 } 952 case KVM_GET_REG_LIST: { 953 struct kvm_reg_list __user *user_list = argp; 954 struct kvm_reg_list reg_list; 955 unsigned n; 956 957 r = -EFAULT; 958 if (copy_from_user(®_list, user_list, sizeof(reg_list))) 959 break; 960 n = reg_list.n; 961 reg_list.n = kvm_mips_num_regs(vcpu); 962 if (copy_to_user(user_list, ®_list, sizeof(reg_list))) 963 break; 964 r = -E2BIG; 965 if (n < reg_list.n) 966 break; 967 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg); 968 break; 969 } 970 case KVM_ENABLE_CAP: { 971 struct kvm_enable_cap cap; 972 973 r = -EFAULT; 974 if (copy_from_user(&cap, argp, sizeof(cap))) 975 break; 976 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 977 break; 978 } 979 default: 980 r = -ENOIOCTLCMD; 981 } 982 983 vcpu_put(vcpu); 984 return r; 985 } 986 987 /** 988 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 989 * @kvm: kvm instance 990 * @log: slot id and address to which we copy the log 991 * 992 * Steps 1-4 below provide general overview of dirty page logging. See 993 * kvm_get_dirty_log_protect() function description for additional details. 994 * 995 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 996 * always flush the TLB (step 4) even if previous step failed and the dirty 997 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 998 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 999 * writes will be marked dirty for next log read. 1000 * 1001 * 1. Take a snapshot of the bit and clear it if needed. 1002 * 2. Write protect the corresponding page. 1003 * 3. Copy the snapshot to the userspace. 1004 * 4. Flush TLB's if needed. 1005 */ 1006 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 1007 { 1008 struct kvm_memslots *slots; 1009 struct kvm_memory_slot *memslot; 1010 bool flush = false; 1011 int r; 1012 1013 mutex_lock(&kvm->slots_lock); 1014 1015 r = kvm_get_dirty_log_protect(kvm, log, &flush); 1016 1017 if (flush) { 1018 slots = kvm_memslots(kvm); 1019 memslot = id_to_memslot(slots, log->slot); 1020 1021 /* Let implementation handle TLB/GVA invalidation */ 1022 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot); 1023 } 1024 1025 mutex_unlock(&kvm->slots_lock); 1026 return r; 1027 } 1028 1029 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log) 1030 { 1031 struct kvm_memslots *slots; 1032 struct kvm_memory_slot *memslot; 1033 bool flush = false; 1034 int r; 1035 1036 mutex_lock(&kvm->slots_lock); 1037 1038 r = kvm_clear_dirty_log_protect(kvm, log, &flush); 1039 1040 if (flush) { 1041 slots = kvm_memslots(kvm); 1042 memslot = id_to_memslot(slots, log->slot); 1043 1044 /* Let implementation handle TLB/GVA invalidation */ 1045 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot); 1046 } 1047 1048 mutex_unlock(&kvm->slots_lock); 1049 return r; 1050 } 1051 1052 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) 1053 { 1054 long r; 1055 1056 switch (ioctl) { 1057 default: 1058 r = -ENOIOCTLCMD; 1059 } 1060 1061 return r; 1062 } 1063 1064 int kvm_arch_init(void *opaque) 1065 { 1066 if (kvm_mips_callbacks) { 1067 kvm_err("kvm: module already exists\n"); 1068 return -EEXIST; 1069 } 1070 1071 return kvm_mips_emulation_init(&kvm_mips_callbacks); 1072 } 1073 1074 void kvm_arch_exit(void) 1075 { 1076 kvm_mips_callbacks = NULL; 1077 } 1078 1079 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 1080 struct kvm_sregs *sregs) 1081 { 1082 return -ENOIOCTLCMD; 1083 } 1084 1085 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 1086 struct kvm_sregs *sregs) 1087 { 1088 return -ENOIOCTLCMD; 1089 } 1090 1091 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 1092 { 1093 } 1094 1095 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1096 { 1097 return -ENOIOCTLCMD; 1098 } 1099 1100 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1101 { 1102 return -ENOIOCTLCMD; 1103 } 1104 1105 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 1106 { 1107 return VM_FAULT_SIGBUS; 1108 } 1109 1110 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 1111 { 1112 int r; 1113 1114 switch (ext) { 1115 case KVM_CAP_ONE_REG: 1116 case KVM_CAP_ENABLE_CAP: 1117 case KVM_CAP_READONLY_MEM: 1118 case KVM_CAP_SYNC_MMU: 1119 case KVM_CAP_IMMEDIATE_EXIT: 1120 r = 1; 1121 break; 1122 case KVM_CAP_NR_VCPUS: 1123 r = num_online_cpus(); 1124 break; 1125 case KVM_CAP_MAX_VCPUS: 1126 r = KVM_MAX_VCPUS; 1127 break; 1128 case KVM_CAP_MAX_VCPU_ID: 1129 r = KVM_MAX_VCPU_ID; 1130 break; 1131 case KVM_CAP_MIPS_FPU: 1132 /* We don't handle systems with inconsistent cpu_has_fpu */ 1133 r = !!raw_cpu_has_fpu; 1134 break; 1135 case KVM_CAP_MIPS_MSA: 1136 /* 1137 * We don't support MSA vector partitioning yet: 1138 * 1) It would require explicit support which can't be tested 1139 * yet due to lack of support in current hardware. 1140 * 2) It extends the state that would need to be saved/restored 1141 * by e.g. QEMU for migration. 1142 * 1143 * When vector partitioning hardware becomes available, support 1144 * could be added by requiring a flag when enabling 1145 * KVM_CAP_MIPS_MSA capability to indicate that userland knows 1146 * to save/restore the appropriate extra state. 1147 */ 1148 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF); 1149 break; 1150 default: 1151 r = kvm_mips_callbacks->check_extension(kvm, ext); 1152 break; 1153 } 1154 return r; 1155 } 1156 1157 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 1158 { 1159 return kvm_mips_pending_timer(vcpu) || 1160 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI; 1161 } 1162 1163 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu) 1164 { 1165 int i; 1166 struct mips_coproc *cop0; 1167 1168 if (!vcpu) 1169 return -1; 1170 1171 kvm_debug("VCPU Register Dump:\n"); 1172 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc); 1173 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions); 1174 1175 for (i = 0; i < 32; i += 4) { 1176 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i, 1177 vcpu->arch.gprs[i], 1178 vcpu->arch.gprs[i + 1], 1179 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]); 1180 } 1181 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi); 1182 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo); 1183 1184 cop0 = vcpu->arch.cop0; 1185 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n", 1186 kvm_read_c0_guest_status(cop0), 1187 kvm_read_c0_guest_cause(cop0)); 1188 1189 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0)); 1190 1191 return 0; 1192 } 1193 1194 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1195 { 1196 int i; 1197 1198 vcpu_load(vcpu); 1199 1200 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1201 vcpu->arch.gprs[i] = regs->gpr[i]; 1202 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ 1203 vcpu->arch.hi = regs->hi; 1204 vcpu->arch.lo = regs->lo; 1205 vcpu->arch.pc = regs->pc; 1206 1207 vcpu_put(vcpu); 1208 return 0; 1209 } 1210 1211 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1212 { 1213 int i; 1214 1215 vcpu_load(vcpu); 1216 1217 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1218 regs->gpr[i] = vcpu->arch.gprs[i]; 1219 1220 regs->hi = vcpu->arch.hi; 1221 regs->lo = vcpu->arch.lo; 1222 regs->pc = vcpu->arch.pc; 1223 1224 vcpu_put(vcpu); 1225 return 0; 1226 } 1227 1228 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 1229 struct kvm_translation *tr) 1230 { 1231 return 0; 1232 } 1233 1234 static void kvm_mips_set_c0_status(void) 1235 { 1236 u32 status = read_c0_status(); 1237 1238 if (cpu_has_dsp) 1239 status |= (ST0_MX); 1240 1241 write_c0_status(status); 1242 ehb(); 1243 } 1244 1245 /* 1246 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) 1247 */ 1248 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu) 1249 { 1250 u32 cause = vcpu->arch.host_cp0_cause; 1251 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; 1252 u32 __user *opc = (u32 __user *) vcpu->arch.pc; 1253 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; 1254 enum emulation_result er = EMULATE_DONE; 1255 u32 inst; 1256 int ret = RESUME_GUEST; 1257 1258 vcpu->mode = OUTSIDE_GUEST_MODE; 1259 1260 /* re-enable HTW before enabling interrupts */ 1261 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) 1262 htw_start(); 1263 1264 /* Set a default exit reason */ 1265 run->exit_reason = KVM_EXIT_UNKNOWN; 1266 run->ready_for_interrupt_injection = 1; 1267 1268 /* 1269 * Set the appropriate status bits based on host CPU features, 1270 * before we hit the scheduler 1271 */ 1272 kvm_mips_set_c0_status(); 1273 1274 local_irq_enable(); 1275 1276 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n", 1277 cause, opc, run, vcpu); 1278 trace_kvm_exit(vcpu, exccode); 1279 1280 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) { 1281 /* 1282 * Do a privilege check, if in UM most of these exit conditions 1283 * end up causing an exception to be delivered to the Guest 1284 * Kernel 1285 */ 1286 er = kvm_mips_check_privilege(cause, opc, run, vcpu); 1287 if (er == EMULATE_PRIV_FAIL) { 1288 goto skip_emul; 1289 } else if (er == EMULATE_FAIL) { 1290 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1291 ret = RESUME_HOST; 1292 goto skip_emul; 1293 } 1294 } 1295 1296 switch (exccode) { 1297 case EXCCODE_INT: 1298 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc); 1299 1300 ++vcpu->stat.int_exits; 1301 1302 if (need_resched()) 1303 cond_resched(); 1304 1305 ret = RESUME_GUEST; 1306 break; 1307 1308 case EXCCODE_CPU: 1309 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc); 1310 1311 ++vcpu->stat.cop_unusable_exits; 1312 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu); 1313 /* XXXKYMA: Might need to return to user space */ 1314 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN) 1315 ret = RESUME_HOST; 1316 break; 1317 1318 case EXCCODE_MOD: 1319 ++vcpu->stat.tlbmod_exits; 1320 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu); 1321 break; 1322 1323 case EXCCODE_TLBS: 1324 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n", 1325 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc, 1326 badvaddr); 1327 1328 ++vcpu->stat.tlbmiss_st_exits; 1329 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu); 1330 break; 1331 1332 case EXCCODE_TLBL: 1333 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n", 1334 cause, opc, badvaddr); 1335 1336 ++vcpu->stat.tlbmiss_ld_exits; 1337 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu); 1338 break; 1339 1340 case EXCCODE_ADES: 1341 ++vcpu->stat.addrerr_st_exits; 1342 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu); 1343 break; 1344 1345 case EXCCODE_ADEL: 1346 ++vcpu->stat.addrerr_ld_exits; 1347 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu); 1348 break; 1349 1350 case EXCCODE_SYS: 1351 ++vcpu->stat.syscall_exits; 1352 ret = kvm_mips_callbacks->handle_syscall(vcpu); 1353 break; 1354 1355 case EXCCODE_RI: 1356 ++vcpu->stat.resvd_inst_exits; 1357 ret = kvm_mips_callbacks->handle_res_inst(vcpu); 1358 break; 1359 1360 case EXCCODE_BP: 1361 ++vcpu->stat.break_inst_exits; 1362 ret = kvm_mips_callbacks->handle_break(vcpu); 1363 break; 1364 1365 case EXCCODE_TR: 1366 ++vcpu->stat.trap_inst_exits; 1367 ret = kvm_mips_callbacks->handle_trap(vcpu); 1368 break; 1369 1370 case EXCCODE_MSAFPE: 1371 ++vcpu->stat.msa_fpe_exits; 1372 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu); 1373 break; 1374 1375 case EXCCODE_FPE: 1376 ++vcpu->stat.fpe_exits; 1377 ret = kvm_mips_callbacks->handle_fpe(vcpu); 1378 break; 1379 1380 case EXCCODE_MSADIS: 1381 ++vcpu->stat.msa_disabled_exits; 1382 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu); 1383 break; 1384 1385 case EXCCODE_GE: 1386 /* defer exit accounting to handler */ 1387 ret = kvm_mips_callbacks->handle_guest_exit(vcpu); 1388 break; 1389 1390 default: 1391 if (cause & CAUSEF_BD) 1392 opc += 1; 1393 inst = 0; 1394 kvm_get_badinstr(opc, vcpu, &inst); 1395 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n", 1396 exccode, opc, inst, badvaddr, 1397 kvm_read_c0_guest_status(vcpu->arch.cop0)); 1398 kvm_arch_vcpu_dump_regs(vcpu); 1399 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1400 ret = RESUME_HOST; 1401 break; 1402 1403 } 1404 1405 skip_emul: 1406 local_irq_disable(); 1407 1408 if (ret == RESUME_GUEST) 1409 kvm_vz_acquire_htimer(vcpu); 1410 1411 if (er == EMULATE_DONE && !(ret & RESUME_HOST)) 1412 kvm_mips_deliver_interrupts(vcpu, cause); 1413 1414 if (!(ret & RESUME_HOST)) { 1415 /* Only check for signals if not already exiting to userspace */ 1416 if (signal_pending(current)) { 1417 run->exit_reason = KVM_EXIT_INTR; 1418 ret = (-EINTR << 2) | RESUME_HOST; 1419 ++vcpu->stat.signal_exits; 1420 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL); 1421 } 1422 } 1423 1424 if (ret == RESUME_GUEST) { 1425 trace_kvm_reenter(vcpu); 1426 1427 /* 1428 * Make sure the read of VCPU requests in vcpu_reenter() 1429 * callback is not reordered ahead of the write to vcpu->mode, 1430 * or we could miss a TLB flush request while the requester sees 1431 * the VCPU as outside of guest mode and not needing an IPI. 1432 */ 1433 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 1434 1435 kvm_mips_callbacks->vcpu_reenter(run, vcpu); 1436 1437 /* 1438 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context 1439 * is live), restore FCR31 / MSACSR. 1440 * 1441 * This should be before returning to the guest exception 1442 * vector, as it may well cause an [MSA] FP exception if there 1443 * are pending exception bits unmasked. (see 1444 * kvm_mips_csr_die_notifier() for how that is handled). 1445 */ 1446 if (kvm_mips_guest_has_fpu(&vcpu->arch) && 1447 read_c0_status() & ST0_CU1) 1448 __kvm_restore_fcsr(&vcpu->arch); 1449 1450 if (kvm_mips_guest_has_msa(&vcpu->arch) && 1451 read_c0_config5() & MIPS_CONF5_MSAEN) 1452 __kvm_restore_msacsr(&vcpu->arch); 1453 } 1454 1455 /* Disable HTW before returning to guest or host */ 1456 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) 1457 htw_stop(); 1458 1459 return ret; 1460 } 1461 1462 /* Enable FPU for guest and restore context */ 1463 void kvm_own_fpu(struct kvm_vcpu *vcpu) 1464 { 1465 struct mips_coproc *cop0 = vcpu->arch.cop0; 1466 unsigned int sr, cfg5; 1467 1468 preempt_disable(); 1469 1470 sr = kvm_read_c0_guest_status(cop0); 1471 1472 /* 1473 * If MSA state is already live, it is undefined how it interacts with 1474 * FR=0 FPU state, and we don't want to hit reserved instruction 1475 * exceptions trying to save the MSA state later when CU=1 && FR=1, so 1476 * play it safe and save it first. 1477 * 1478 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should 1479 * get called when guest CU1 is set, however we can't trust the guest 1480 * not to clobber the status register directly via the commpage. 1481 */ 1482 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) && 1483 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) 1484 kvm_lose_fpu(vcpu); 1485 1486 /* 1487 * Enable FPU for guest 1488 * We set FR and FRE according to guest context 1489 */ 1490 change_c0_status(ST0_CU1 | ST0_FR, sr); 1491 if (cpu_has_fre) { 1492 cfg5 = kvm_read_c0_guest_config5(cop0); 1493 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1494 } 1495 enable_fpu_hazard(); 1496 1497 /* If guest FPU state not active, restore it now */ 1498 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) { 1499 __kvm_restore_fpu(&vcpu->arch); 1500 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1501 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU); 1502 } else { 1503 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU); 1504 } 1505 1506 preempt_enable(); 1507 } 1508 1509 #ifdef CONFIG_CPU_HAS_MSA 1510 /* Enable MSA for guest and restore context */ 1511 void kvm_own_msa(struct kvm_vcpu *vcpu) 1512 { 1513 struct mips_coproc *cop0 = vcpu->arch.cop0; 1514 unsigned int sr, cfg5; 1515 1516 preempt_disable(); 1517 1518 /* 1519 * Enable FPU if enabled in guest, since we're restoring FPU context 1520 * anyway. We set FR and FRE according to guest context. 1521 */ 1522 if (kvm_mips_guest_has_fpu(&vcpu->arch)) { 1523 sr = kvm_read_c0_guest_status(cop0); 1524 1525 /* 1526 * If FR=0 FPU state is already live, it is undefined how it 1527 * interacts with MSA state, so play it safe and save it first. 1528 */ 1529 if (!(sr & ST0_FR) && 1530 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | 1531 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU) 1532 kvm_lose_fpu(vcpu); 1533 1534 change_c0_status(ST0_CU1 | ST0_FR, sr); 1535 if (sr & ST0_CU1 && cpu_has_fre) { 1536 cfg5 = kvm_read_c0_guest_config5(cop0); 1537 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1538 } 1539 } 1540 1541 /* Enable MSA for guest */ 1542 set_c0_config5(MIPS_CONF5_MSAEN); 1543 enable_fpu_hazard(); 1544 1545 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) { 1546 case KVM_MIPS_AUX_FPU: 1547 /* 1548 * Guest FPU state already loaded, only restore upper MSA state 1549 */ 1550 __kvm_restore_msa_upper(&vcpu->arch); 1551 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1552 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA); 1553 break; 1554 case 0: 1555 /* Neither FPU or MSA already active, restore full MSA state */ 1556 __kvm_restore_msa(&vcpu->arch); 1557 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1558 if (kvm_mips_guest_has_fpu(&vcpu->arch)) 1559 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1560 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, 1561 KVM_TRACE_AUX_FPU_MSA); 1562 break; 1563 default: 1564 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA); 1565 break; 1566 } 1567 1568 preempt_enable(); 1569 } 1570 #endif 1571 1572 /* Drop FPU & MSA without saving it */ 1573 void kvm_drop_fpu(struct kvm_vcpu *vcpu) 1574 { 1575 preempt_disable(); 1576 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1577 disable_msa(); 1578 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA); 1579 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA; 1580 } 1581 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1582 clear_c0_status(ST0_CU1 | ST0_FR); 1583 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU); 1584 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1585 } 1586 preempt_enable(); 1587 } 1588 1589 /* Save and disable FPU & MSA */ 1590 void kvm_lose_fpu(struct kvm_vcpu *vcpu) 1591 { 1592 /* 1593 * With T&E, FPU & MSA get disabled in root context (hardware) when it 1594 * is disabled in guest context (software), but the register state in 1595 * the hardware may still be in use. 1596 * This is why we explicitly re-enable the hardware before saving. 1597 */ 1598 1599 preempt_disable(); 1600 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1601 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) { 1602 set_c0_config5(MIPS_CONF5_MSAEN); 1603 enable_fpu_hazard(); 1604 } 1605 1606 __kvm_save_msa(&vcpu->arch); 1607 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA); 1608 1609 /* Disable MSA & FPU */ 1610 disable_msa(); 1611 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1612 clear_c0_status(ST0_CU1 | ST0_FR); 1613 disable_fpu_hazard(); 1614 } 1615 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA); 1616 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1617 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) { 1618 set_c0_status(ST0_CU1); 1619 enable_fpu_hazard(); 1620 } 1621 1622 __kvm_save_fpu(&vcpu->arch); 1623 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1624 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU); 1625 1626 /* Disable FPU */ 1627 clear_c0_status(ST0_CU1 | ST0_FR); 1628 disable_fpu_hazard(); 1629 } 1630 preempt_enable(); 1631 } 1632 1633 /* 1634 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are 1635 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP 1636 * exception if cause bits are set in the value being written. 1637 */ 1638 static int kvm_mips_csr_die_notify(struct notifier_block *self, 1639 unsigned long cmd, void *ptr) 1640 { 1641 struct die_args *args = (struct die_args *)ptr; 1642 struct pt_regs *regs = args->regs; 1643 unsigned long pc; 1644 1645 /* Only interested in FPE and MSAFPE */ 1646 if (cmd != DIE_FP && cmd != DIE_MSAFP) 1647 return NOTIFY_DONE; 1648 1649 /* Return immediately if guest context isn't active */ 1650 if (!(current->flags & PF_VCPU)) 1651 return NOTIFY_DONE; 1652 1653 /* Should never get here from user mode */ 1654 BUG_ON(user_mode(regs)); 1655 1656 pc = instruction_pointer(regs); 1657 switch (cmd) { 1658 case DIE_FP: 1659 /* match 2nd instruction in __kvm_restore_fcsr */ 1660 if (pc != (unsigned long)&__kvm_restore_fcsr + 4) 1661 return NOTIFY_DONE; 1662 break; 1663 case DIE_MSAFP: 1664 /* match 2nd/3rd instruction in __kvm_restore_msacsr */ 1665 if (!cpu_has_msa || 1666 pc < (unsigned long)&__kvm_restore_msacsr + 4 || 1667 pc > (unsigned long)&__kvm_restore_msacsr + 8) 1668 return NOTIFY_DONE; 1669 break; 1670 } 1671 1672 /* Move PC forward a little and continue executing */ 1673 instruction_pointer(regs) += 4; 1674 1675 return NOTIFY_STOP; 1676 } 1677 1678 static struct notifier_block kvm_mips_csr_die_notifier = { 1679 .notifier_call = kvm_mips_csr_die_notify, 1680 }; 1681 1682 static int __init kvm_mips_init(void) 1683 { 1684 int ret; 1685 1686 if (cpu_has_mmid) { 1687 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n"); 1688 return -EOPNOTSUPP; 1689 } 1690 1691 ret = kvm_mips_entry_setup(); 1692 if (ret) 1693 return ret; 1694 1695 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); 1696 1697 if (ret) 1698 return ret; 1699 1700 register_die_notifier(&kvm_mips_csr_die_notifier); 1701 1702 return 0; 1703 } 1704 1705 static void __exit kvm_mips_exit(void) 1706 { 1707 kvm_exit(); 1708 1709 unregister_die_notifier(&kvm_mips_csr_die_notifier); 1710 } 1711 1712 module_init(kvm_mips_init); 1713 module_exit(kvm_mips_exit); 1714 1715 EXPORT_TRACEPOINT_SYMBOL(kvm_exit); 1716