1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ZynqMP Display Controller Driver 4 * 5 * Copyright (C) 2017 - 2020 Xilinx, Inc. 6 * 7 * Authors: 8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 */ 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_crtc.h> 16 #include <drm/drm_device.h> 17 #include <drm/drm_fb_cma_helper.h> 18 #include <drm/drm_fourcc.h> 19 #include <drm/drm_framebuffer.h> 20 #include <drm/drm_managed.h> 21 #include <drm/drm_plane.h> 22 #include <drm/drm_plane_helper.h> 23 #include <drm/drm_vblank.h> 24 25 #include <linux/clk.h> 26 #include <linux/delay.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmaengine.h> 29 #include <linux/module.h> 30 #include <linux/of.h> 31 #include <linux/of_dma.h> 32 #include <linux/platform_device.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/spinlock.h> 35 36 #include "zynqmp_disp.h" 37 #include "zynqmp_disp_regs.h" 38 #include "zynqmp_dp.h" 39 #include "zynqmp_dpsub.h" 40 41 /* 42 * Overview 43 * -------- 44 * 45 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video 46 * Buffer Manager, the Video Rendering Pipeline (blender) and the Audio Mixer. 47 * 48 * +------------------------------------------------------------+ 49 * +--------+ | +----------------+ +-----------+ | 50 * | DPDMA | --->| | --> | Video | Video +-------------+ | 51 * | 4x vid | | | | | Rendering | -+--> | | | +------+ 52 * | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 | 53 * +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+ 54 * | | and STC | +-----------+ | | Controller | | +------+ 55 * Live Video --->| | --> | Audio | Audio | |---> | PHY1 | 56 * | | | | Mixer | --+-> | | | +------+ 57 * Live Audio --->| | --> | | || +-------------+ | 58 * | +----------------+ +-----------+ || | 59 * +---------------------------------------||-------------------+ 60 * vv 61 * Blended Video and 62 * Mixed Audio to PL 63 * 64 * Only non-live input from the DPDMA and output to the DisplayPort Source 65 * Controller are currently supported. Interface with the programmable logic 66 * for live streams is not implemented. 67 * 68 * The display controller code creates planes for the DPDMA video and graphics 69 * layers, and a CRTC for the Video Rendering Pipeline. 70 */ 71 72 #define ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS 4 73 #define ZYNQMP_DISP_AV_BUF_NUM_BUFFERS 6 74 75 #define ZYNQMP_DISP_NUM_LAYERS 2 76 #define ZYNQMP_DISP_MAX_NUM_SUB_PLANES 3 77 78 /** 79 * struct zynqmp_disp_format - Display subsystem format information 80 * @drm_fmt: DRM format (4CC) 81 * @buf_fmt: AV buffer format 82 * @bus_fmt: Media bus formats (live formats) 83 * @swap: Flag to swap R & B for RGB formats, and U & V for YUV formats 84 * @sf: Scaling factors for color components 85 */ 86 struct zynqmp_disp_format { 87 u32 drm_fmt; 88 u32 buf_fmt; 89 u32 bus_fmt; 90 bool swap; 91 const u32 *sf; 92 }; 93 94 /** 95 * enum zynqmp_disp_id - Layer identifier 96 * @ZYNQMP_DISP_LAYER_VID: Video layer 97 * @ZYNQMP_DISP_LAYER_GFX: Graphics layer 98 */ 99 enum zynqmp_disp_layer_id { 100 ZYNQMP_DISP_LAYER_VID, 101 ZYNQMP_DISP_LAYER_GFX 102 }; 103 104 /** 105 * enum zynqmp_disp_layer_mode - Layer mode 106 * @ZYNQMP_DISP_LAYER_NONLIVE: non-live (memory) mode 107 * @ZYNQMP_DISP_LAYER_LIVE: live (stream) mode 108 */ 109 enum zynqmp_disp_layer_mode { 110 ZYNQMP_DISP_LAYER_NONLIVE, 111 ZYNQMP_DISP_LAYER_LIVE 112 }; 113 114 /** 115 * struct zynqmp_disp_layer_dma - DMA channel for one data plane of a layer 116 * @chan: DMA channel 117 * @xt: Interleaved DMA descriptor template 118 * @sgl: Data chunk for dma_interleaved_template 119 */ 120 struct zynqmp_disp_layer_dma { 121 struct dma_chan *chan; 122 struct dma_interleaved_template xt; 123 struct data_chunk sgl; 124 }; 125 126 /** 127 * struct zynqmp_disp_layer_info - Static layer information 128 * @formats: Array of supported formats 129 * @num_formats: Number of formats in @formats array 130 * @num_channels: Number of DMA channels 131 */ 132 struct zynqmp_disp_layer_info { 133 const struct zynqmp_disp_format *formats; 134 unsigned int num_formats; 135 unsigned int num_channels; 136 }; 137 138 /** 139 * struct zynqmp_disp_layer - Display layer (DRM plane) 140 * @plane: DRM plane 141 * @id: Layer ID 142 * @disp: Back pointer to struct zynqmp_disp 143 * @info: Static layer information 144 * @dmas: DMA channels 145 * @disp_fmt: Current format information 146 * @drm_fmt: Current DRM format information 147 * @mode: Current operation mode 148 */ 149 struct zynqmp_disp_layer { 150 struct drm_plane plane; 151 enum zynqmp_disp_layer_id id; 152 struct zynqmp_disp *disp; 153 const struct zynqmp_disp_layer_info *info; 154 155 struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES]; 156 157 const struct zynqmp_disp_format *disp_fmt; 158 const struct drm_format_info *drm_fmt; 159 enum zynqmp_disp_layer_mode mode; 160 }; 161 162 /** 163 * struct zynqmp_disp_blend - Blender 164 * @base: Registers I/O base address 165 */ 166 struct zynqmp_disp_blend { 167 void __iomem *base; 168 }; 169 170 /** 171 * struct zynqmp_disp_avbuf - Audio/video buffer manager 172 * @base: Registers I/O base address 173 */ 174 struct zynqmp_disp_avbuf { 175 void __iomem *base; 176 }; 177 178 /** 179 * struct zynqmp_disp_audio - Audio mixer 180 * @base: Registers I/O base address 181 * @clk: Audio clock 182 * @clk_from_ps: True of the audio clock comes from PS, false from PL 183 */ 184 struct zynqmp_disp_audio { 185 void __iomem *base; 186 struct clk *clk; 187 bool clk_from_ps; 188 }; 189 190 /** 191 * struct zynqmp_disp - Display controller 192 * @dev: Device structure 193 * @drm: DRM core 194 * @dpsub: Display subsystem 195 * @crtc: DRM CRTC 196 * @blend: Blender (video rendering pipeline) 197 * @avbuf: Audio/video buffer manager 198 * @audio: Audio mixer 199 * @layers: Layers (planes) 200 * @event: Pending vblank event request 201 * @pclk: Pixel clock 202 * @pclk_from_ps: True of the video clock comes from PS, false from PL 203 */ 204 struct zynqmp_disp { 205 struct device *dev; 206 struct drm_device *drm; 207 struct zynqmp_dpsub *dpsub; 208 209 struct drm_crtc crtc; 210 211 struct zynqmp_disp_blend blend; 212 struct zynqmp_disp_avbuf avbuf; 213 struct zynqmp_disp_audio audio; 214 215 struct zynqmp_disp_layer layers[ZYNQMP_DISP_NUM_LAYERS]; 216 217 struct drm_pending_vblank_event *event; 218 219 struct clk *pclk; 220 bool pclk_from_ps; 221 }; 222 223 /* ----------------------------------------------------------------------------- 224 * Audio/Video Buffer Manager 225 */ 226 227 static const u32 scaling_factors_444[] = { 228 ZYNQMP_DISP_AV_BUF_4BIT_SF, 229 ZYNQMP_DISP_AV_BUF_4BIT_SF, 230 ZYNQMP_DISP_AV_BUF_4BIT_SF, 231 }; 232 233 static const u32 scaling_factors_555[] = { 234 ZYNQMP_DISP_AV_BUF_5BIT_SF, 235 ZYNQMP_DISP_AV_BUF_5BIT_SF, 236 ZYNQMP_DISP_AV_BUF_5BIT_SF, 237 }; 238 239 static const u32 scaling_factors_565[] = { 240 ZYNQMP_DISP_AV_BUF_5BIT_SF, 241 ZYNQMP_DISP_AV_BUF_6BIT_SF, 242 ZYNQMP_DISP_AV_BUF_5BIT_SF, 243 }; 244 245 static const u32 scaling_factors_666[] = { 246 ZYNQMP_DISP_AV_BUF_6BIT_SF, 247 ZYNQMP_DISP_AV_BUF_6BIT_SF, 248 ZYNQMP_DISP_AV_BUF_6BIT_SF, 249 }; 250 251 static const u32 scaling_factors_888[] = { 252 ZYNQMP_DISP_AV_BUF_8BIT_SF, 253 ZYNQMP_DISP_AV_BUF_8BIT_SF, 254 ZYNQMP_DISP_AV_BUF_8BIT_SF, 255 }; 256 257 static const u32 scaling_factors_101010[] = { 258 ZYNQMP_DISP_AV_BUF_10BIT_SF, 259 ZYNQMP_DISP_AV_BUF_10BIT_SF, 260 ZYNQMP_DISP_AV_BUF_10BIT_SF, 261 }; 262 263 /* List of video layer formats */ 264 static const struct zynqmp_disp_format avbuf_vid_fmts[] = { 265 { 266 .drm_fmt = DRM_FORMAT_VYUY, 267 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY, 268 .swap = true, 269 .sf = scaling_factors_888, 270 }, { 271 .drm_fmt = DRM_FORMAT_UYVY, 272 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY, 273 .swap = false, 274 .sf = scaling_factors_888, 275 }, { 276 .drm_fmt = DRM_FORMAT_YUYV, 277 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV, 278 .swap = false, 279 .sf = scaling_factors_888, 280 }, { 281 .drm_fmt = DRM_FORMAT_YVYU, 282 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV, 283 .swap = true, 284 .sf = scaling_factors_888, 285 }, { 286 .drm_fmt = DRM_FORMAT_YUV422, 287 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16, 288 .swap = false, 289 .sf = scaling_factors_888, 290 }, { 291 .drm_fmt = DRM_FORMAT_YVU422, 292 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16, 293 .swap = true, 294 .sf = scaling_factors_888, 295 }, { 296 .drm_fmt = DRM_FORMAT_YUV444, 297 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24, 298 .swap = false, 299 .sf = scaling_factors_888, 300 }, { 301 .drm_fmt = DRM_FORMAT_YVU444, 302 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24, 303 .swap = true, 304 .sf = scaling_factors_888, 305 }, { 306 .drm_fmt = DRM_FORMAT_NV16, 307 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI, 308 .swap = false, 309 .sf = scaling_factors_888, 310 }, { 311 .drm_fmt = DRM_FORMAT_NV61, 312 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI, 313 .swap = true, 314 .sf = scaling_factors_888, 315 }, { 316 .drm_fmt = DRM_FORMAT_BGR888, 317 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888, 318 .swap = false, 319 .sf = scaling_factors_888, 320 }, { 321 .drm_fmt = DRM_FORMAT_RGB888, 322 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888, 323 .swap = true, 324 .sf = scaling_factors_888, 325 }, { 326 .drm_fmt = DRM_FORMAT_XBGR8888, 327 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880, 328 .swap = false, 329 .sf = scaling_factors_888, 330 }, { 331 .drm_fmt = DRM_FORMAT_XRGB8888, 332 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880, 333 .swap = true, 334 .sf = scaling_factors_888, 335 }, { 336 .drm_fmt = DRM_FORMAT_XBGR2101010, 337 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10, 338 .swap = false, 339 .sf = scaling_factors_101010, 340 }, { 341 .drm_fmt = DRM_FORMAT_XRGB2101010, 342 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10, 343 .swap = true, 344 .sf = scaling_factors_101010, 345 }, { 346 .drm_fmt = DRM_FORMAT_YUV420, 347 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420, 348 .swap = false, 349 .sf = scaling_factors_888, 350 }, { 351 .drm_fmt = DRM_FORMAT_YVU420, 352 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420, 353 .swap = true, 354 .sf = scaling_factors_888, 355 }, { 356 .drm_fmt = DRM_FORMAT_NV12, 357 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420, 358 .swap = false, 359 .sf = scaling_factors_888, 360 }, { 361 .drm_fmt = DRM_FORMAT_NV21, 362 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420, 363 .swap = true, 364 .sf = scaling_factors_888, 365 }, 366 }; 367 368 /* List of graphics layer formats */ 369 static const struct zynqmp_disp_format avbuf_gfx_fmts[] = { 370 { 371 .drm_fmt = DRM_FORMAT_ABGR8888, 372 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888, 373 .swap = false, 374 .sf = scaling_factors_888, 375 }, { 376 .drm_fmt = DRM_FORMAT_ARGB8888, 377 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888, 378 .swap = true, 379 .sf = scaling_factors_888, 380 }, { 381 .drm_fmt = DRM_FORMAT_RGBA8888, 382 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888, 383 .swap = false, 384 .sf = scaling_factors_888, 385 }, { 386 .drm_fmt = DRM_FORMAT_BGRA8888, 387 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888, 388 .swap = true, 389 .sf = scaling_factors_888, 390 }, { 391 .drm_fmt = DRM_FORMAT_BGR888, 392 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888, 393 .swap = false, 394 .sf = scaling_factors_888, 395 }, { 396 .drm_fmt = DRM_FORMAT_RGB888, 397 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888, 398 .swap = false, 399 .sf = scaling_factors_888, 400 }, { 401 .drm_fmt = DRM_FORMAT_RGBA5551, 402 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551, 403 .swap = false, 404 .sf = scaling_factors_555, 405 }, { 406 .drm_fmt = DRM_FORMAT_BGRA5551, 407 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551, 408 .swap = true, 409 .sf = scaling_factors_555, 410 }, { 411 .drm_fmt = DRM_FORMAT_RGBA4444, 412 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444, 413 .swap = false, 414 .sf = scaling_factors_444, 415 }, { 416 .drm_fmt = DRM_FORMAT_BGRA4444, 417 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444, 418 .swap = true, 419 .sf = scaling_factors_444, 420 }, { 421 .drm_fmt = DRM_FORMAT_RGB565, 422 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565, 423 .swap = false, 424 .sf = scaling_factors_565, 425 }, { 426 .drm_fmt = DRM_FORMAT_BGR565, 427 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565, 428 .swap = true, 429 .sf = scaling_factors_565, 430 }, 431 }; 432 433 static u32 zynqmp_disp_avbuf_read(struct zynqmp_disp_avbuf *avbuf, int reg) 434 { 435 return readl(avbuf->base + reg); 436 } 437 438 static void zynqmp_disp_avbuf_write(struct zynqmp_disp_avbuf *avbuf, 439 int reg, u32 val) 440 { 441 writel(val, avbuf->base + reg); 442 } 443 444 /** 445 * zynqmp_disp_avbuf_set_format - Set the input format for a layer 446 * @avbuf: Audio/video buffer manager 447 * @layer: The layer ID 448 * @fmt: The format information 449 * 450 * Set the video buffer manager format for @layer to @fmt. 451 */ 452 static void zynqmp_disp_avbuf_set_format(struct zynqmp_disp_avbuf *avbuf, 453 enum zynqmp_disp_layer_id layer, 454 const struct zynqmp_disp_format *fmt) 455 { 456 unsigned int i; 457 u32 val; 458 459 val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_FMT); 460 val &= layer == ZYNQMP_DISP_LAYER_VID 461 ? ~ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK 462 : ~ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK; 463 val |= fmt->buf_fmt; 464 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_FMT, val); 465 466 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_SF; i++) { 467 unsigned int reg = layer == ZYNQMP_DISP_LAYER_VID 468 ? ZYNQMP_DISP_AV_BUF_VID_COMP_SF(i) 469 : ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(i); 470 471 zynqmp_disp_avbuf_write(avbuf, reg, fmt->sf[i]); 472 } 473 } 474 475 /** 476 * zynqmp_disp_avbuf_set_clocks_sources - Set the clocks sources 477 * @avbuf: Audio/video buffer manager 478 * @video_from_ps: True if the video clock originates from the PS 479 * @audio_from_ps: True if the audio clock originates from the PS 480 * @timings_internal: True if video timings are generated internally 481 * 482 * Set the source for the video and audio clocks, as well as for the video 483 * timings. Clocks can originate from the PS or PL, and timings can be 484 * generated internally or externally. 485 */ 486 static void 487 zynqmp_disp_avbuf_set_clocks_sources(struct zynqmp_disp_avbuf *avbuf, 488 bool video_from_ps, bool audio_from_ps, 489 bool timings_internal) 490 { 491 u32 val = 0; 492 493 if (video_from_ps) 494 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS; 495 if (audio_from_ps) 496 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS; 497 if (timings_internal) 498 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING; 499 500 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_CLK_SRC, val); 501 } 502 503 /** 504 * zynqmp_disp_avbuf_enable_channels - Enable buffer channels 505 * @avbuf: Audio/video buffer manager 506 * 507 * Enable all (video and audio) buffer channels. 508 */ 509 static void zynqmp_disp_avbuf_enable_channels(struct zynqmp_disp_avbuf *avbuf) 510 { 511 unsigned int i; 512 u32 val; 513 514 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN | 515 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX << 516 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT); 517 518 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS; i++) 519 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_CHBUF(i), 520 val); 521 522 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN | 523 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX << 524 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT); 525 526 for (; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++) 527 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_CHBUF(i), 528 val); 529 } 530 531 /** 532 * zynqmp_disp_avbuf_disable_channels - Disable buffer channels 533 * @avbuf: Audio/video buffer manager 534 * 535 * Disable all (video and audio) buffer channels. 536 */ 537 static void zynqmp_disp_avbuf_disable_channels(struct zynqmp_disp_avbuf *avbuf) 538 { 539 unsigned int i; 540 541 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++) 542 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_CHBUF(i), 543 ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH); 544 } 545 546 /** 547 * zynqmp_disp_avbuf_enable_audio - Enable audio 548 * @avbuf: Audio/video buffer manager 549 * 550 * Enable all audio buffers with a non-live (memory) source. 551 */ 552 static void zynqmp_disp_avbuf_enable_audio(struct zynqmp_disp_avbuf *avbuf) 553 { 554 u32 val; 555 556 val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); 557 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK; 558 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM; 559 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN; 560 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 561 } 562 563 /** 564 * zynqmp_disp_avbuf_disable_audio - Disable audio 565 * @avbuf: Audio/video buffer manager 566 * 567 * Disable all audio buffers. 568 */ 569 static void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp_avbuf *avbuf) 570 { 571 u32 val; 572 573 val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); 574 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK; 575 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE; 576 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN; 577 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 578 } 579 580 /** 581 * zynqmp_disp_avbuf_enable_video - Enable a video layer 582 * @avbuf: Audio/video buffer manager 583 * @layer: The layer ID 584 * @mode: Operating mode of layer 585 * 586 * Enable the video/graphics buffer for @layer. 587 */ 588 static void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp_avbuf *avbuf, 589 enum zynqmp_disp_layer_id layer, 590 enum zynqmp_disp_layer_mode mode) 591 { 592 u32 val; 593 594 val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); 595 if (layer == ZYNQMP_DISP_LAYER_VID) { 596 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; 597 if (mode == ZYNQMP_DISP_LAYER_NONLIVE) 598 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM; 599 else 600 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE; 601 } else { 602 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK; 603 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM; 604 if (mode == ZYNQMP_DISP_LAYER_NONLIVE) 605 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM; 606 else 607 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE; 608 } 609 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 610 } 611 612 /** 613 * zynqmp_disp_avbuf_disable_video - Disable a video layer 614 * @avbuf: Audio/video buffer manager 615 * @layer: The layer ID 616 * 617 * Disable the video/graphics buffer for @layer. 618 */ 619 static void zynqmp_disp_avbuf_disable_video(struct zynqmp_disp_avbuf *avbuf, 620 enum zynqmp_disp_layer_id layer) 621 { 622 u32 val; 623 624 val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); 625 if (layer == ZYNQMP_DISP_LAYER_VID) { 626 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; 627 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE; 628 } else { 629 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK; 630 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE; 631 } 632 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 633 } 634 635 /** 636 * zynqmp_disp_avbuf_enable - Enable the video pipe 637 * @avbuf: Audio/video buffer manager 638 * 639 * De-assert the video pipe reset. 640 */ 641 static void zynqmp_disp_avbuf_enable(struct zynqmp_disp_avbuf *avbuf) 642 { 643 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_SRST_REG, 0); 644 } 645 646 /** 647 * zynqmp_disp_avbuf_disable - Disable the video pipe 648 * @avbuf: Audio/video buffer manager 649 * 650 * Assert the video pipe reset. 651 */ 652 static void zynqmp_disp_avbuf_disable(struct zynqmp_disp_avbuf *avbuf) 653 { 654 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_SRST_REG, 655 ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST); 656 } 657 658 /* ----------------------------------------------------------------------------- 659 * Blender (Video Pipeline) 660 */ 661 662 static void zynqmp_disp_blend_write(struct zynqmp_disp_blend *blend, 663 int reg, u32 val) 664 { 665 writel(val, blend->base + reg); 666 } 667 668 /* 669 * Colorspace conversion matrices. 670 * 671 * Hardcode RGB <-> YUV conversion to full-range SDTV for now. 672 */ 673 static const u16 csc_zero_matrix[] = { 674 0x0, 0x0, 0x0, 675 0x0, 0x0, 0x0, 676 0x0, 0x0, 0x0 677 }; 678 679 static const u16 csc_identity_matrix[] = { 680 0x1000, 0x0, 0x0, 681 0x0, 0x1000, 0x0, 682 0x0, 0x0, 0x1000 683 }; 684 685 static const u32 csc_zero_offsets[] = { 686 0, 0, 0 687 }; 688 689 static const u16 csc_rgb_to_sdtv_matrix[] = { 690 0x4c9, 0x864, 0x1d3, 691 0x7d4d, 0x7ab3, 0x800, 692 0x800, 0x794d, 0x7eb3 693 }; 694 695 static const u32 csc_rgb_to_sdtv_offsets[] = { 696 0x0, 0x8000000, 0x8000000 697 }; 698 699 static const u16 csc_sdtv_to_rgb_matrix[] = { 700 0x1000, 0x166f, 0x0, 701 0x1000, 0x7483, 0x7a7f, 702 0x1000, 0x0, 0x1c5a 703 }; 704 705 static const u32 csc_sdtv_to_rgb_offsets[] = { 706 0x0, 0x1800, 0x1800 707 }; 708 709 /** 710 * zynqmp_disp_blend_set_output_format - Set the output format of the blender 711 * @blend: Blender object 712 * @format: Output format 713 * 714 * Set the output format of the blender to @format. 715 */ 716 static void zynqmp_disp_blend_set_output_format(struct zynqmp_disp_blend *blend, 717 enum zynqmp_dpsub_format format) 718 { 719 static const unsigned int blend_output_fmts[] = { 720 [ZYNQMP_DPSUB_FORMAT_RGB] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB, 721 [ZYNQMP_DPSUB_FORMAT_YCRCB444] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444, 722 [ZYNQMP_DPSUB_FORMAT_YCRCB422] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422 723 | ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE, 724 [ZYNQMP_DPSUB_FORMAT_YONLY] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY, 725 }; 726 727 u32 fmt = blend_output_fmts[format]; 728 const u16 *coeffs; 729 const u32 *offsets; 730 unsigned int i; 731 732 zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT, fmt); 733 if (fmt == ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB) { 734 coeffs = csc_identity_matrix; 735 offsets = csc_zero_offsets; 736 } else { 737 coeffs = csc_rgb_to_sdtv_matrix; 738 offsets = csc_rgb_to_sdtv_offsets; 739 } 740 741 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i++) 742 zynqmp_disp_blend_write(blend, 743 ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(i), 744 coeffs[i]); 745 746 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++) 747 zynqmp_disp_blend_write(blend, 748 ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(i), 749 offsets[i]); 750 } 751 752 /** 753 * zynqmp_disp_blend_set_bg_color - Set the background color 754 * @blend: Blender object 755 * @rcr: Red/Cr color component 756 * @gy: Green/Y color component 757 * @bcb: Blue/Cb color component 758 * 759 * Set the background color to (@rcr, @gy, @bcb), corresponding to the R, G and 760 * B or Cr, Y and Cb components respectively depending on the selected output 761 * format. 762 */ 763 static void zynqmp_disp_blend_set_bg_color(struct zynqmp_disp_blend *blend, 764 u32 rcr, u32 gy, u32 bcb) 765 { 766 zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_BG_CLR_0, rcr); 767 zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_BG_CLR_1, gy); 768 zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_BG_CLR_2, bcb); 769 } 770 771 /** 772 * zynqmp_disp_blend_set_global_alpha - Configure global alpha blending 773 * @blend: Blender object 774 * @enable: True to enable global alpha blending 775 * @alpha: Global alpha value (ignored if @enabled is false) 776 */ 777 static void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp_blend *blend, 778 bool enable, u32 alpha) 779 { 780 zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA, 781 ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(alpha) | 782 (enable ? ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN : 0)); 783 } 784 785 /** 786 * zynqmp_disp_blend_layer_set_csc - Configure colorspace conversion for layer 787 * @blend: Blender object 788 * @layer: The layer 789 * @coeffs: Colorspace conversion matrix 790 * @offsets: Colorspace conversion offsets 791 * 792 * Configure the input colorspace conversion matrix and offsets for the @layer. 793 * Columns of the matrix are automatically swapped based on the input format to 794 * handle RGB and YCrCb components permutations. 795 */ 796 static void zynqmp_disp_blend_layer_set_csc(struct zynqmp_disp_blend *blend, 797 struct zynqmp_disp_layer *layer, 798 const u16 *coeffs, 799 const u32 *offsets) 800 { 801 unsigned int swap[3] = { 0, 1, 2 }; 802 unsigned int reg; 803 unsigned int i; 804 805 if (layer->disp_fmt->swap) { 806 if (layer->drm_fmt->is_yuv) { 807 /* Swap U and V. */ 808 swap[1] = 2; 809 swap[2] = 1; 810 } else { 811 /* Swap R and B. */ 812 swap[0] = 2; 813 swap[2] = 0; 814 } 815 } 816 817 if (layer->id == ZYNQMP_DISP_LAYER_VID) 818 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(0); 819 else 820 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(0); 821 822 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i += 3, reg += 12) { 823 zynqmp_disp_blend_write(blend, reg + 0, coeffs[i + swap[0]]); 824 zynqmp_disp_blend_write(blend, reg + 4, coeffs[i + swap[1]]); 825 zynqmp_disp_blend_write(blend, reg + 8, coeffs[i + swap[2]]); 826 } 827 828 if (layer->id == ZYNQMP_DISP_LAYER_VID) 829 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(0); 830 else 831 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(0); 832 833 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++) 834 zynqmp_disp_blend_write(blend, reg + i * 4, offsets[i]); 835 } 836 837 /** 838 * zynqmp_disp_blend_layer_enable - Enable a layer 839 * @blend: Blender object 840 * @layer: The layer 841 */ 842 static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp_blend *blend, 843 struct zynqmp_disp_layer *layer) 844 { 845 const u16 *coeffs; 846 const u32 *offsets; 847 u32 val; 848 849 val = (layer->drm_fmt->is_yuv ? 850 0 : ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB) | 851 (layer->drm_fmt->hsub > 1 ? 852 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US : 0); 853 854 zynqmp_disp_blend_write(blend, 855 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id), 856 val); 857 858 if (layer->drm_fmt->is_yuv) { 859 coeffs = csc_sdtv_to_rgb_matrix; 860 offsets = csc_sdtv_to_rgb_offsets; 861 } else { 862 coeffs = csc_identity_matrix; 863 offsets = csc_zero_offsets; 864 } 865 866 zynqmp_disp_blend_layer_set_csc(blend, layer, coeffs, offsets); 867 } 868 869 /** 870 * zynqmp_disp_blend_layer_disable - Disable a layer 871 * @blend: Blender object 872 * @layer: The layer 873 */ 874 static void zynqmp_disp_blend_layer_disable(struct zynqmp_disp_blend *blend, 875 struct zynqmp_disp_layer *layer) 876 { 877 zynqmp_disp_blend_write(blend, 878 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id), 879 0); 880 881 zynqmp_disp_blend_layer_set_csc(blend, layer, csc_zero_matrix, 882 csc_zero_offsets); 883 } 884 885 /* ----------------------------------------------------------------------------- 886 * Audio Mixer 887 */ 888 889 static void zynqmp_disp_audio_write(struct zynqmp_disp_audio *audio, 890 int reg, u32 val) 891 { 892 writel(val, audio->base + reg); 893 } 894 895 /** 896 * zynqmp_disp_audio_enable - Enable the audio mixer 897 * @audio: Audio mixer 898 * 899 * Enable the audio mixer by de-asserting the soft reset. The audio state is set to 900 * default values by the reset, set the default mixer volume explicitly. 901 */ 902 static void zynqmp_disp_audio_enable(struct zynqmp_disp_audio *audio) 903 { 904 /* Clear the audio soft reset register as it's an non-reset flop. */ 905 zynqmp_disp_audio_write(audio, ZYNQMP_DISP_AUD_SOFT_RESET, 0); 906 zynqmp_disp_audio_write(audio, ZYNQMP_DISP_AUD_MIXER_VOLUME, 907 ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE); 908 } 909 910 /** 911 * zynqmp_disp_audio_disable - Disable the audio mixer 912 * @audio: Audio mixer 913 * 914 * Disable the audio mixer by asserting its soft reset. 915 */ 916 static void zynqmp_disp_audio_disable(struct zynqmp_disp_audio *audio) 917 { 918 zynqmp_disp_audio_write(audio, ZYNQMP_DISP_AUD_SOFT_RESET, 919 ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST); 920 } 921 922 static void zynqmp_disp_audio_init(struct device *dev, 923 struct zynqmp_disp_audio *audio) 924 { 925 /* Try the live PL audio clock. */ 926 audio->clk = devm_clk_get(dev, "dp_live_audio_aclk"); 927 if (!IS_ERR(audio->clk)) { 928 audio->clk_from_ps = false; 929 return; 930 } 931 932 /* If the live PL audio clock is not valid, fall back to PS clock. */ 933 audio->clk = devm_clk_get(dev, "dp_aud_clk"); 934 if (!IS_ERR(audio->clk)) { 935 audio->clk_from_ps = true; 936 return; 937 } 938 939 dev_err(dev, "audio disabled due to missing clock\n"); 940 } 941 942 /* ----------------------------------------------------------------------------- 943 * ZynqMP Display external functions for zynqmp_dp 944 */ 945 946 /** 947 * zynqmp_disp_handle_vblank - Handle the vblank event 948 * @disp: Display controller 949 * 950 * This function handles the vblank interrupt, and sends an event to 951 * CRTC object. This will be called by the DP vblank interrupt handler. 952 */ 953 void zynqmp_disp_handle_vblank(struct zynqmp_disp *disp) 954 { 955 struct drm_crtc *crtc = &disp->crtc; 956 957 drm_crtc_handle_vblank(crtc); 958 } 959 960 /** 961 * zynqmp_disp_audio_enabled - If the audio is enabled 962 * @disp: Display controller 963 * 964 * Return if the audio is enabled depending on the audio clock. 965 * 966 * Return: true if audio is enabled, or false. 967 */ 968 bool zynqmp_disp_audio_enabled(struct zynqmp_disp *disp) 969 { 970 return !!disp->audio.clk; 971 } 972 973 /** 974 * zynqmp_disp_get_audio_clk_rate - Get the current audio clock rate 975 * @disp: Display controller 976 * 977 * Return: the current audio clock rate. 978 */ 979 unsigned int zynqmp_disp_get_audio_clk_rate(struct zynqmp_disp *disp) 980 { 981 if (zynqmp_disp_audio_enabled(disp)) 982 return 0; 983 return clk_get_rate(disp->audio.clk); 984 } 985 986 /** 987 * zynqmp_disp_get_crtc_mask - Return the CRTC bit mask 988 * @disp: Display controller 989 * 990 * Return: the crtc mask of the zyqnmp_disp CRTC. 991 */ 992 uint32_t zynqmp_disp_get_crtc_mask(struct zynqmp_disp *disp) 993 { 994 return drm_crtc_mask(&disp->crtc); 995 } 996 997 /* ----------------------------------------------------------------------------- 998 * ZynqMP Display Layer & DRM Plane 999 */ 1000 1001 /** 1002 * zynqmp_disp_layer_find_format - Find format information for a DRM format 1003 * @layer: The layer 1004 * @drm_fmt: DRM format to search 1005 * 1006 * Search display subsystem format information corresponding to the given DRM 1007 * format @drm_fmt for the @layer, and return a pointer to the format 1008 * descriptor. 1009 * 1010 * Return: A pointer to the format descriptor if found, NULL otherwise 1011 */ 1012 static const struct zynqmp_disp_format * 1013 zynqmp_disp_layer_find_format(struct zynqmp_disp_layer *layer, 1014 u32 drm_fmt) 1015 { 1016 unsigned int i; 1017 1018 for (i = 0; i < layer->info->num_formats; i++) { 1019 if (layer->info->formats[i].drm_fmt == drm_fmt) 1020 return &layer->info->formats[i]; 1021 } 1022 1023 return NULL; 1024 } 1025 1026 /** 1027 * zynqmp_disp_layer_enable - Enable a layer 1028 * @layer: The layer 1029 * 1030 * Enable the @layer in the audio/video buffer manager and the blender. DMA 1031 * channels are started separately by zynqmp_disp_layer_update(). 1032 */ 1033 static void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer) 1034 { 1035 zynqmp_disp_avbuf_enable_video(&layer->disp->avbuf, layer->id, 1036 ZYNQMP_DISP_LAYER_NONLIVE); 1037 zynqmp_disp_blend_layer_enable(&layer->disp->blend, layer); 1038 1039 layer->mode = ZYNQMP_DISP_LAYER_NONLIVE; 1040 } 1041 1042 /** 1043 * zynqmp_disp_layer_disable - Disable the layer 1044 * @layer: The layer 1045 * 1046 * Disable the layer by stopping its DMA channels and disabling it in the 1047 * audio/video buffer manager and the blender. 1048 */ 1049 static void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer) 1050 { 1051 unsigned int i; 1052 1053 for (i = 0; i < layer->drm_fmt->num_planes; i++) 1054 dmaengine_terminate_sync(layer->dmas[i].chan); 1055 1056 zynqmp_disp_avbuf_disable_video(&layer->disp->avbuf, layer->id); 1057 zynqmp_disp_blend_layer_disable(&layer->disp->blend, layer); 1058 } 1059 1060 /** 1061 * zynqmp_disp_layer_set_format - Set the layer format 1062 * @layer: The layer 1063 * @state: The plane state 1064 * 1065 * Set the format for @layer based on @state->fb->format. The layer must be 1066 * disabled. 1067 */ 1068 static void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, 1069 struct drm_plane_state *state) 1070 { 1071 const struct drm_format_info *info = state->fb->format; 1072 unsigned int i; 1073 1074 layer->disp_fmt = zynqmp_disp_layer_find_format(layer, info->format); 1075 layer->drm_fmt = info; 1076 1077 zynqmp_disp_avbuf_set_format(&layer->disp->avbuf, layer->id, 1078 layer->disp_fmt); 1079 1080 /* 1081 * Set slave_id for each DMA channel to indicate they're part of a 1082 * video group. 1083 */ 1084 for (i = 0; i < info->num_planes; i++) { 1085 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1086 struct dma_slave_config config = { 1087 .direction = DMA_MEM_TO_DEV, 1088 .slave_id = 1, 1089 }; 1090 1091 dmaengine_slave_config(dma->chan, &config); 1092 } 1093 } 1094 1095 /** 1096 * zynqmp_disp_layer_update - Update the layer framebuffer 1097 * @layer: The layer 1098 * @state: The plane state 1099 * 1100 * Update the framebuffer for the layer by issuing a new DMA engine transaction 1101 * for the new framebuffer. 1102 * 1103 * Return: 0 on success, or the DMA descriptor failure error otherwise 1104 */ 1105 static int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer, 1106 struct drm_plane_state *state) 1107 { 1108 const struct drm_format_info *info = layer->drm_fmt; 1109 unsigned int i; 1110 1111 for (i = 0; i < layer->drm_fmt->num_planes; i++) { 1112 unsigned int width = state->crtc_w / (i ? info->hsub : 1); 1113 unsigned int height = state->crtc_h / (i ? info->vsub : 1); 1114 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1115 struct dma_async_tx_descriptor *desc; 1116 dma_addr_t paddr; 1117 1118 paddr = drm_fb_cma_get_gem_addr(state->fb, state, i); 1119 1120 dma->xt.numf = height; 1121 dma->sgl.size = width * info->cpp[i]; 1122 dma->sgl.icg = state->fb->pitches[i] - dma->sgl.size; 1123 dma->xt.src_start = paddr; 1124 dma->xt.frame_size = 1; 1125 dma->xt.dir = DMA_MEM_TO_DEV; 1126 dma->xt.src_sgl = true; 1127 dma->xt.dst_sgl = false; 1128 1129 desc = dmaengine_prep_interleaved_dma(dma->chan, &dma->xt, 1130 DMA_CTRL_ACK | 1131 DMA_PREP_REPEAT | 1132 DMA_PREP_LOAD_EOT); 1133 if (!desc) { 1134 dev_err(layer->disp->dev, 1135 "failed to prepare DMA descriptor\n"); 1136 return -ENOMEM; 1137 } 1138 1139 dmaengine_submit(desc); 1140 dma_async_issue_pending(dma->chan); 1141 } 1142 1143 return 0; 1144 } 1145 1146 static inline struct zynqmp_disp_layer *plane_to_layer(struct drm_plane *plane) 1147 { 1148 return container_of(plane, struct zynqmp_disp_layer, plane); 1149 } 1150 1151 static int 1152 zynqmp_disp_plane_atomic_check(struct drm_plane *plane, 1153 struct drm_plane_state *state) 1154 { 1155 struct drm_crtc_state *crtc_state; 1156 1157 if (!state->crtc) 1158 return 0; 1159 1160 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); 1161 if (IS_ERR(crtc_state)) 1162 return PTR_ERR(crtc_state); 1163 1164 return drm_atomic_helper_check_plane_state(state, crtc_state, 1165 DRM_PLANE_HELPER_NO_SCALING, 1166 DRM_PLANE_HELPER_NO_SCALING, 1167 false, false); 1168 } 1169 1170 static void 1171 zynqmp_disp_plane_atomic_disable(struct drm_plane *plane, 1172 struct drm_plane_state *old_state) 1173 { 1174 struct zynqmp_disp_layer *layer = plane_to_layer(plane); 1175 1176 if (!old_state->fb) 1177 return; 1178 1179 zynqmp_disp_layer_disable(layer); 1180 } 1181 1182 static void 1183 zynqmp_disp_plane_atomic_update(struct drm_plane *plane, 1184 struct drm_plane_state *old_state) 1185 { 1186 struct zynqmp_disp_layer *layer = plane_to_layer(plane); 1187 bool format_changed = false; 1188 1189 if (!old_state->fb || 1190 old_state->fb->format->format != plane->state->fb->format->format) 1191 format_changed = true; 1192 1193 /* 1194 * If the format has changed (including going from a previously 1195 * disabled state to any format), reconfigure the format. Disable the 1196 * plane first if needed. 1197 */ 1198 if (format_changed) { 1199 if (old_state->fb) 1200 zynqmp_disp_layer_disable(layer); 1201 1202 zynqmp_disp_layer_set_format(layer, plane->state); 1203 } 1204 1205 zynqmp_disp_layer_update(layer, plane->state); 1206 1207 /* Enable or re-enable the plane is the format has changed. */ 1208 if (format_changed) 1209 zynqmp_disp_layer_enable(layer); 1210 } 1211 1212 static const struct drm_plane_helper_funcs zynqmp_disp_plane_helper_funcs = { 1213 .atomic_check = zynqmp_disp_plane_atomic_check, 1214 .atomic_update = zynqmp_disp_plane_atomic_update, 1215 .atomic_disable = zynqmp_disp_plane_atomic_disable, 1216 }; 1217 1218 static const struct drm_plane_funcs zynqmp_disp_plane_funcs = { 1219 .update_plane = drm_atomic_helper_update_plane, 1220 .disable_plane = drm_atomic_helper_disable_plane, 1221 .destroy = drm_plane_cleanup, 1222 .reset = drm_atomic_helper_plane_reset, 1223 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1224 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1225 }; 1226 1227 static int zynqmp_disp_create_planes(struct zynqmp_disp *disp) 1228 { 1229 unsigned int i, j; 1230 int ret; 1231 1232 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) { 1233 struct zynqmp_disp_layer *layer = &disp->layers[i]; 1234 enum drm_plane_type type; 1235 u32 *drm_formats; 1236 1237 drm_formats = drmm_kcalloc(disp->drm, sizeof(*drm_formats), 1238 layer->info->num_formats, 1239 GFP_KERNEL); 1240 if (!drm_formats) 1241 return -ENOMEM; 1242 1243 for (j = 0; j < layer->info->num_formats; ++j) 1244 drm_formats[j] = layer->info->formats[j].drm_fmt; 1245 1246 /* Graphics layer is primary, and video layer is overlay. */ 1247 type = i == ZYNQMP_DISP_LAYER_GFX 1248 ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY; 1249 ret = drm_universal_plane_init(disp->drm, &layer->plane, 0, 1250 &zynqmp_disp_plane_funcs, 1251 drm_formats, 1252 layer->info->num_formats, 1253 NULL, type, NULL); 1254 if (ret) 1255 return ret; 1256 1257 drm_plane_helper_add(&layer->plane, 1258 &zynqmp_disp_plane_helper_funcs); 1259 } 1260 1261 return 0; 1262 } 1263 1264 /** 1265 * zynqmp_disp_layer_release_dma - Release DMA channels for a layer 1266 * @disp: Display controller 1267 * @layer: The layer 1268 * 1269 * Release the DMA channels associated with @layer. 1270 */ 1271 static void zynqmp_disp_layer_release_dma(struct zynqmp_disp *disp, 1272 struct zynqmp_disp_layer *layer) 1273 { 1274 unsigned int i; 1275 1276 if (!layer->info) 1277 return; 1278 1279 for (i = 0; i < layer->info->num_channels; i++) { 1280 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1281 1282 if (!dma->chan) 1283 continue; 1284 1285 /* Make sure the channel is terminated before release. */ 1286 dmaengine_terminate_sync(dma->chan); 1287 dma_release_channel(dma->chan); 1288 } 1289 } 1290 1291 /** 1292 * zynqmp_disp_destroy_layers - Destroy all layers 1293 * @disp: Display controller 1294 */ 1295 static void zynqmp_disp_destroy_layers(struct zynqmp_disp *disp) 1296 { 1297 unsigned int i; 1298 1299 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) 1300 zynqmp_disp_layer_release_dma(disp, &disp->layers[i]); 1301 } 1302 1303 /** 1304 * zynqmp_disp_layer_request_dma - Request DMA channels for a layer 1305 * @disp: Display controller 1306 * @layer: The layer 1307 * 1308 * Request all DMA engine channels needed by @layer. 1309 * 1310 * Return: 0 on success, or the DMA channel request error otherwise 1311 */ 1312 static int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp, 1313 struct zynqmp_disp_layer *layer) 1314 { 1315 static const char * const dma_names[] = { "vid", "gfx" }; 1316 unsigned int i; 1317 int ret; 1318 1319 for (i = 0; i < layer->info->num_channels; i++) { 1320 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1321 char dma_channel_name[16]; 1322 1323 snprintf(dma_channel_name, sizeof(dma_channel_name), 1324 "%s%u", dma_names[layer->id], i); 1325 dma->chan = of_dma_request_slave_channel(disp->dev->of_node, 1326 dma_channel_name); 1327 if (IS_ERR(dma->chan)) { 1328 dev_err(disp->dev, "failed to request dma channel\n"); 1329 ret = PTR_ERR(dma->chan); 1330 dma->chan = NULL; 1331 return ret; 1332 } 1333 } 1334 1335 return 0; 1336 } 1337 1338 /** 1339 * zynqmp_disp_create_layers - Create and initialize all layers 1340 * @disp: Display controller 1341 * 1342 * Return: 0 on success, or the DMA channel request error otherwise 1343 */ 1344 static int zynqmp_disp_create_layers(struct zynqmp_disp *disp) 1345 { 1346 static const struct zynqmp_disp_layer_info layer_info[] = { 1347 [ZYNQMP_DISP_LAYER_VID] = { 1348 .formats = avbuf_vid_fmts, 1349 .num_formats = ARRAY_SIZE(avbuf_vid_fmts), 1350 .num_channels = 3, 1351 }, 1352 [ZYNQMP_DISP_LAYER_GFX] = { 1353 .formats = avbuf_gfx_fmts, 1354 .num_formats = ARRAY_SIZE(avbuf_gfx_fmts), 1355 .num_channels = 1, 1356 }, 1357 }; 1358 1359 unsigned int i; 1360 int ret; 1361 1362 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) { 1363 struct zynqmp_disp_layer *layer = &disp->layers[i]; 1364 1365 layer->id = i; 1366 layer->disp = disp; 1367 layer->info = &layer_info[i]; 1368 1369 ret = zynqmp_disp_layer_request_dma(disp, layer); 1370 if (ret) 1371 goto err; 1372 } 1373 1374 return 0; 1375 1376 err: 1377 zynqmp_disp_destroy_layers(disp); 1378 return ret; 1379 } 1380 1381 /* ----------------------------------------------------------------------------- 1382 * ZynqMP Display & DRM CRTC 1383 */ 1384 1385 /** 1386 * zynqmp_disp_enable - Enable the display controller 1387 * @disp: Display controller 1388 */ 1389 static void zynqmp_disp_enable(struct zynqmp_disp *disp) 1390 { 1391 zynqmp_disp_avbuf_enable(&disp->avbuf); 1392 /* Choose clock source based on the DT clock handle. */ 1393 zynqmp_disp_avbuf_set_clocks_sources(&disp->avbuf, disp->pclk_from_ps, 1394 disp->audio.clk_from_ps, true); 1395 zynqmp_disp_avbuf_enable_channels(&disp->avbuf); 1396 zynqmp_disp_avbuf_enable_audio(&disp->avbuf); 1397 1398 zynqmp_disp_audio_enable(&disp->audio); 1399 } 1400 1401 /** 1402 * zynqmp_disp_disable - Disable the display controller 1403 * @disp: Display controller 1404 */ 1405 static void zynqmp_disp_disable(struct zynqmp_disp *disp) 1406 { 1407 struct drm_crtc *crtc = &disp->crtc; 1408 1409 zynqmp_disp_audio_disable(&disp->audio); 1410 1411 zynqmp_disp_avbuf_disable_audio(&disp->avbuf); 1412 zynqmp_disp_avbuf_disable_channels(&disp->avbuf); 1413 zynqmp_disp_avbuf_disable(&disp->avbuf); 1414 1415 /* Mark the flip is done as crtc is disabled anyway */ 1416 if (crtc->state->event) { 1417 complete_all(crtc->state->event->base.completion); 1418 crtc->state->event = NULL; 1419 } 1420 } 1421 1422 static inline struct zynqmp_disp *crtc_to_disp(struct drm_crtc *crtc) 1423 { 1424 return container_of(crtc, struct zynqmp_disp, crtc); 1425 } 1426 1427 static int zynqmp_disp_crtc_setup_clock(struct drm_crtc *crtc, 1428 struct drm_display_mode *adjusted_mode) 1429 { 1430 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1431 unsigned long mode_clock = adjusted_mode->clock * 1000; 1432 unsigned long rate; 1433 long diff; 1434 int ret; 1435 1436 ret = clk_set_rate(disp->pclk, mode_clock); 1437 if (ret) { 1438 dev_err(disp->dev, "failed to set a pixel clock\n"); 1439 return ret; 1440 } 1441 1442 rate = clk_get_rate(disp->pclk); 1443 diff = rate - mode_clock; 1444 if (abs(diff) > mode_clock / 20) 1445 dev_info(disp->dev, 1446 "requested pixel rate: %lu actual rate: %lu\n", 1447 mode_clock, rate); 1448 else 1449 dev_dbg(disp->dev, 1450 "requested pixel rate: %lu actual rate: %lu\n", 1451 mode_clock, rate); 1452 1453 return 0; 1454 } 1455 1456 static void 1457 zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc, 1458 struct drm_crtc_state *old_crtc_state) 1459 { 1460 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1461 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1462 int ret, vrefresh; 1463 1464 zynqmp_disp_crtc_setup_clock(crtc, adjusted_mode); 1465 1466 pm_runtime_get_sync(disp->dev); 1467 ret = clk_prepare_enable(disp->pclk); 1468 if (ret) { 1469 dev_err(disp->dev, "failed to enable a pixel clock\n"); 1470 pm_runtime_put_sync(disp->dev); 1471 return; 1472 } 1473 1474 zynqmp_disp_blend_set_output_format(&disp->blend, 1475 ZYNQMP_DPSUB_FORMAT_RGB); 1476 zynqmp_disp_blend_set_bg_color(&disp->blend, 0, 0, 0); 1477 zynqmp_disp_blend_set_global_alpha(&disp->blend, false, 0); 1478 1479 zynqmp_disp_enable(disp); 1480 1481 /* Delay of 3 vblank intervals for timing gen to be stable */ 1482 vrefresh = (adjusted_mode->clock * 1000) / 1483 (adjusted_mode->vtotal * adjusted_mode->htotal); 1484 msleep(3 * 1000 / vrefresh); 1485 } 1486 1487 static void 1488 zynqmp_disp_crtc_atomic_disable(struct drm_crtc *crtc, 1489 struct drm_crtc_state *old_crtc_state) 1490 { 1491 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1492 struct drm_plane_state *old_plane_state; 1493 1494 /* 1495 * Disable the plane if active. The old plane state can be NULL in the 1496 * .shutdown() path if the plane is already disabled, skip 1497 * zynqmp_disp_plane_atomic_disable() in that case. 1498 */ 1499 old_plane_state = drm_atomic_get_old_plane_state(old_crtc_state->state, 1500 crtc->primary); 1501 if (old_plane_state) 1502 zynqmp_disp_plane_atomic_disable(crtc->primary, old_plane_state); 1503 1504 zynqmp_disp_disable(disp); 1505 1506 drm_crtc_vblank_off(&disp->crtc); 1507 1508 clk_disable_unprepare(disp->pclk); 1509 pm_runtime_put_sync(disp->dev); 1510 } 1511 1512 static int zynqmp_disp_crtc_atomic_check(struct drm_crtc *crtc, 1513 struct drm_crtc_state *state) 1514 { 1515 return drm_atomic_add_affected_planes(state->state, crtc); 1516 } 1517 1518 static void 1519 zynqmp_disp_crtc_atomic_begin(struct drm_crtc *crtc, 1520 struct drm_crtc_state *old_crtc_state) 1521 { 1522 drm_crtc_vblank_on(crtc); 1523 } 1524 1525 static void 1526 zynqmp_disp_crtc_atomic_flush(struct drm_crtc *crtc, 1527 struct drm_crtc_state *old_crtc_state) 1528 { 1529 if (crtc->state->event) { 1530 struct drm_pending_vblank_event *event; 1531 1532 /* Consume the flip_done event from atomic helper. */ 1533 event = crtc->state->event; 1534 crtc->state->event = NULL; 1535 1536 event->pipe = drm_crtc_index(crtc); 1537 1538 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1539 1540 spin_lock_irq(&crtc->dev->event_lock); 1541 drm_crtc_arm_vblank_event(crtc, event); 1542 spin_unlock_irq(&crtc->dev->event_lock); 1543 } 1544 } 1545 1546 static const struct drm_crtc_helper_funcs zynqmp_disp_crtc_helper_funcs = { 1547 .atomic_enable = zynqmp_disp_crtc_atomic_enable, 1548 .atomic_disable = zynqmp_disp_crtc_atomic_disable, 1549 .atomic_check = zynqmp_disp_crtc_atomic_check, 1550 .atomic_begin = zynqmp_disp_crtc_atomic_begin, 1551 .atomic_flush = zynqmp_disp_crtc_atomic_flush, 1552 }; 1553 1554 static int zynqmp_disp_crtc_enable_vblank(struct drm_crtc *crtc) 1555 { 1556 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1557 1558 zynqmp_dp_enable_vblank(disp->dpsub->dp); 1559 1560 return 0; 1561 } 1562 1563 static void zynqmp_disp_crtc_disable_vblank(struct drm_crtc *crtc) 1564 { 1565 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1566 1567 zynqmp_dp_disable_vblank(disp->dpsub->dp); 1568 } 1569 1570 static const struct drm_crtc_funcs zynqmp_disp_crtc_funcs = { 1571 .destroy = drm_crtc_cleanup, 1572 .set_config = drm_atomic_helper_set_config, 1573 .page_flip = drm_atomic_helper_page_flip, 1574 .reset = drm_atomic_helper_crtc_reset, 1575 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 1576 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 1577 .enable_vblank = zynqmp_disp_crtc_enable_vblank, 1578 .disable_vblank = zynqmp_disp_crtc_disable_vblank, 1579 }; 1580 1581 static int zynqmp_disp_create_crtc(struct zynqmp_disp *disp) 1582 { 1583 struct drm_plane *plane = &disp->layers[ZYNQMP_DISP_LAYER_GFX].plane; 1584 int ret; 1585 1586 ret = drm_crtc_init_with_planes(disp->drm, &disp->crtc, plane, 1587 NULL, &zynqmp_disp_crtc_funcs, NULL); 1588 if (ret < 0) 1589 return ret; 1590 1591 drm_crtc_helper_add(&disp->crtc, &zynqmp_disp_crtc_helper_funcs); 1592 1593 /* Start with vertical blanking interrupt reporting disabled. */ 1594 drm_crtc_vblank_off(&disp->crtc); 1595 1596 return 0; 1597 } 1598 1599 static void zynqmp_disp_map_crtc_to_plane(struct zynqmp_disp *disp) 1600 { 1601 u32 possible_crtcs = drm_crtc_mask(&disp->crtc); 1602 unsigned int i; 1603 1604 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) 1605 disp->layers[i].plane.possible_crtcs = possible_crtcs; 1606 } 1607 1608 /* ----------------------------------------------------------------------------- 1609 * Initialization & Cleanup 1610 */ 1611 1612 int zynqmp_disp_drm_init(struct zynqmp_dpsub *dpsub) 1613 { 1614 struct zynqmp_disp *disp = dpsub->disp; 1615 int ret; 1616 1617 ret = zynqmp_disp_create_planes(disp); 1618 if (ret) 1619 return ret; 1620 1621 ret = zynqmp_disp_create_crtc(disp); 1622 if (ret < 0) 1623 return ret; 1624 1625 zynqmp_disp_map_crtc_to_plane(disp); 1626 1627 return 0; 1628 } 1629 1630 int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub, struct drm_device *drm) 1631 { 1632 struct platform_device *pdev = to_platform_device(dpsub->dev); 1633 struct zynqmp_disp *disp; 1634 struct zynqmp_disp_layer *layer; 1635 struct resource *res; 1636 int ret; 1637 1638 disp = drmm_kzalloc(drm, sizeof(*disp), GFP_KERNEL); 1639 if (!disp) 1640 return -ENOMEM; 1641 1642 disp->dev = &pdev->dev; 1643 disp->dpsub = dpsub; 1644 disp->drm = drm; 1645 1646 dpsub->disp = disp; 1647 1648 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "blend"); 1649 disp->blend.base = devm_ioremap_resource(disp->dev, res); 1650 if (IS_ERR(disp->blend.base)) 1651 return PTR_ERR(disp->blend.base); 1652 1653 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "av_buf"); 1654 disp->avbuf.base = devm_ioremap_resource(disp->dev, res); 1655 if (IS_ERR(disp->avbuf.base)) 1656 return PTR_ERR(disp->avbuf.base); 1657 1658 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aud"); 1659 disp->audio.base = devm_ioremap_resource(disp->dev, res); 1660 if (IS_ERR(disp->audio.base)) 1661 return PTR_ERR(disp->audio.base); 1662 1663 /* Try the live PL video clock */ 1664 disp->pclk = devm_clk_get(disp->dev, "dp_live_video_in_clk"); 1665 if (!IS_ERR(disp->pclk)) 1666 disp->pclk_from_ps = false; 1667 else if (PTR_ERR(disp->pclk) == -EPROBE_DEFER) 1668 return PTR_ERR(disp->pclk); 1669 1670 /* If the live PL video clock is not valid, fall back to PS clock */ 1671 if (IS_ERR_OR_NULL(disp->pclk)) { 1672 disp->pclk = devm_clk_get(disp->dev, "dp_vtc_pixel_clk_in"); 1673 if (IS_ERR(disp->pclk)) { 1674 dev_err(disp->dev, "failed to init any video clock\n"); 1675 return PTR_ERR(disp->pclk); 1676 } 1677 disp->pclk_from_ps = true; 1678 } 1679 1680 zynqmp_disp_audio_init(disp->dev, &disp->audio); 1681 1682 ret = zynqmp_disp_create_layers(disp); 1683 if (ret) 1684 return ret; 1685 1686 layer = &disp->layers[ZYNQMP_DISP_LAYER_VID]; 1687 dpsub->dma_align = 1 << layer->dmas[0].chan->device->copy_align; 1688 1689 return 0; 1690 } 1691 1692 void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub) 1693 { 1694 struct zynqmp_disp *disp = dpsub->disp; 1695 1696 zynqmp_disp_destroy_layers(disp); 1697 } 1698