1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Mika Kuoppala <mika.kuoppala@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_renderstate.h" 30 #include "intel_ring.h" 31 32 static const struct intel_renderstate_rodata * 33 render_state_get_rodata(const struct intel_engine_cs *engine) 34 { 35 if (engine->class != RENDER_CLASS) 36 return NULL; 37 38 switch (INTEL_GEN(engine->i915)) { 39 case 6: 40 return &gen6_null_state; 41 case 7: 42 return &gen7_null_state; 43 case 8: 44 return &gen8_null_state; 45 case 9: 46 return &gen9_null_state; 47 } 48 49 return NULL; 50 } 51 52 /* 53 * Macro to add commands to auxiliary batch. 54 * This macro only checks for page overflow before inserting the commands, 55 * this is sufficient as the null state generator makes the final batch 56 * with two passes to build command and state separately. At this point 57 * the size of both are known and it compacts them by relocating the state 58 * right after the commands taking care of alignment so we should sufficient 59 * space below them for adding new commands. 60 */ 61 #define OUT_BATCH(batch, i, val) \ 62 do { \ 63 if ((i) >= PAGE_SIZE / sizeof(u32)) \ 64 goto out; \ 65 (batch)[(i)++] = (val); \ 66 } while(0) 67 68 static int render_state_setup(struct intel_renderstate *so, 69 struct drm_i915_private *i915) 70 { 71 const struct intel_renderstate_rodata *rodata = so->rodata; 72 unsigned int i = 0, reloc_index = 0; 73 int ret = -EINVAL; 74 u32 *d; 75 76 d = i915_gem_object_pin_map(so->vma->obj, I915_MAP_WB); 77 if (IS_ERR(d)) 78 return PTR_ERR(d); 79 80 while (i < rodata->batch_items) { 81 u32 s = rodata->batch[i]; 82 83 if (i * 4 == rodata->reloc[reloc_index]) { 84 u64 r = s + so->vma->node.start; 85 s = lower_32_bits(r); 86 if (HAS_64BIT_RELOC(i915)) { 87 if (i + 1 >= rodata->batch_items || 88 rodata->batch[i + 1] != 0) 89 goto out; 90 91 d[i++] = s; 92 s = upper_32_bits(r); 93 } 94 95 reloc_index++; 96 } 97 98 d[i++] = s; 99 } 100 101 if (rodata->reloc[reloc_index] != -1) { 102 drm_err(&i915->drm, "only %d relocs resolved\n", reloc_index); 103 goto out; 104 } 105 106 so->batch_offset = i915_ggtt_offset(so->vma); 107 so->batch_size = rodata->batch_items * sizeof(u32); 108 109 while (i % CACHELINE_DWORDS) 110 OUT_BATCH(d, i, MI_NOOP); 111 112 so->aux_offset = i * sizeof(u32); 113 114 if (HAS_POOLED_EU(i915)) { 115 /* 116 * We always program 3x6 pool config but depending upon which 117 * subslice is disabled HW drops down to appropriate config 118 * shown below. 119 * 120 * In the below table 2x6 config always refers to 121 * fused-down version, native 2x6 is not available and can 122 * be ignored 123 * 124 * SNo subslices config eu pool configuration 125 * ----------------------------------------------------------- 126 * 1 3 subslices enabled (3x6) - 0x00777000 (9+9) 127 * 2 ss0 disabled (2x6) - 0x00777000 (3+9) 128 * 3 ss1 disabled (2x6) - 0x00770000 (6+6) 129 * 4 ss2 disabled (2x6) - 0x00007000 (9+3) 130 */ 131 u32 eu_pool_config = 0x00777000; 132 133 OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE); 134 OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE); 135 OUT_BATCH(d, i, eu_pool_config); 136 OUT_BATCH(d, i, 0); 137 OUT_BATCH(d, i, 0); 138 OUT_BATCH(d, i, 0); 139 } 140 141 OUT_BATCH(d, i, MI_BATCH_BUFFER_END); 142 so->aux_size = i * sizeof(u32) - so->aux_offset; 143 so->aux_offset += so->batch_offset; 144 /* 145 * Since we are sending length, we need to strictly conform to 146 * all requirements. For Gen2 this must be a multiple of 8. 147 */ 148 so->aux_size = ALIGN(so->aux_size, 8); 149 150 ret = 0; 151 out: 152 __i915_gem_object_flush_map(so->vma->obj, 0, i * sizeof(u32)); 153 __i915_gem_object_release_map(so->vma->obj); 154 return ret; 155 } 156 157 #undef OUT_BATCH 158 159 int intel_renderstate_init(struct intel_renderstate *so, 160 struct intel_engine_cs *engine) 161 { 162 struct drm_i915_gem_object *obj; 163 int err; 164 165 memset(so, 0, sizeof(*so)); 166 167 so->rodata = render_state_get_rodata(engine); 168 if (!so->rodata) 169 return 0; 170 171 if (so->rodata->batch_items * 4 > PAGE_SIZE) 172 return -EINVAL; 173 174 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); 175 if (IS_ERR(obj)) 176 return PTR_ERR(obj); 177 178 so->vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); 179 if (IS_ERR(so->vma)) { 180 err = PTR_ERR(so->vma); 181 goto err_obj; 182 } 183 184 err = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH); 185 if (err) 186 goto err_obj; 187 188 err = render_state_setup(so, engine->i915); 189 if (err) 190 goto err_unpin; 191 192 return 0; 193 194 err_unpin: 195 i915_vma_unpin(so->vma); 196 err_obj: 197 i915_gem_object_put(obj); 198 so->vma = NULL; 199 return err; 200 } 201 202 int intel_renderstate_emit(struct intel_renderstate *so, 203 struct i915_request *rq) 204 { 205 struct intel_engine_cs *engine = rq->engine; 206 int err; 207 208 if (!so->vma) 209 return 0; 210 211 i915_vma_lock(so->vma); 212 err = i915_request_await_object(rq, so->vma->obj, false); 213 if (err == 0) 214 err = i915_vma_move_to_active(so->vma, rq, 0); 215 i915_vma_unlock(so->vma); 216 if (err) 217 return err; 218 219 err = engine->emit_bb_start(rq, 220 so->batch_offset, so->batch_size, 221 I915_DISPATCH_SECURE); 222 if (err) 223 return err; 224 225 if (so->aux_size > 8) { 226 err = engine->emit_bb_start(rq, 227 so->aux_offset, so->aux_size, 228 I915_DISPATCH_SECURE); 229 if (err) 230 return err; 231 } 232 233 return 0; 234 } 235 236 void intel_renderstate_fini(struct intel_renderstate *so) 237 { 238 i915_vma_unpin_and_release(&so->vma, 0); 239 } 240