1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Ingenic JZ4780 I2C bus driver 4 * 5 * Copyright (C) 2006 - 2009 Ingenic Semiconductor Inc. 6 * Copyright (C) 2015 Imagination Technologies 7 * Copyright (C) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/clk.h> 12 #include <linux/completion.h> 13 #include <linux/delay.h> 14 #include <linux/errno.h> 15 #include <linux/i2c.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/of_device.h> 22 #include <linux/platform_device.h> 23 #include <linux/sched.h> 24 #include <linux/slab.h> 25 #include <linux/time.h> 26 27 #define JZ4780_I2C_CTRL 0x00 28 #define JZ4780_I2C_TAR 0x04 29 #define JZ4780_I2C_SAR 0x08 30 #define JZ4780_I2C_DC 0x10 31 #define JZ4780_I2C_SHCNT 0x14 32 #define JZ4780_I2C_SLCNT 0x18 33 #define JZ4780_I2C_FHCNT 0x1C 34 #define JZ4780_I2C_FLCNT 0x20 35 #define JZ4780_I2C_INTST 0x2C 36 #define JZ4780_I2C_INTM 0x30 37 #define JZ4780_I2C_RXTL 0x38 38 #define JZ4780_I2C_TXTL 0x3C 39 #define JZ4780_I2C_CINTR 0x40 40 #define JZ4780_I2C_CRXUF 0x44 41 #define JZ4780_I2C_CRXOF 0x48 42 #define JZ4780_I2C_CTXOF 0x4C 43 #define JZ4780_I2C_CRXREQ 0x50 44 #define JZ4780_I2C_CTXABRT 0x54 45 #define JZ4780_I2C_CRXDONE 0x58 46 #define JZ4780_I2C_CACT 0x5C 47 #define JZ4780_I2C_CSTP 0x60 48 #define JZ4780_I2C_CSTT 0x64 49 #define JZ4780_I2C_CGC 0x68 50 #define JZ4780_I2C_ENB 0x6C 51 #define JZ4780_I2C_STA 0x70 52 #define JZ4780_I2C_TXABRT 0x80 53 #define JZ4780_I2C_DMACR 0x88 54 #define JZ4780_I2C_DMATDLR 0x8C 55 #define JZ4780_I2C_DMARDLR 0x90 56 #define JZ4780_I2C_SDASU 0x94 57 #define JZ4780_I2C_ACKGC 0x98 58 #define JZ4780_I2C_ENSTA 0x9C 59 #define JZ4780_I2C_SDAHD 0xD0 60 #define X1000_I2C_SDAHD 0x7C 61 62 #define JZ4780_I2C_CTRL_STPHLD BIT(7) 63 #define JZ4780_I2C_CTRL_SLVDIS BIT(6) 64 #define JZ4780_I2C_CTRL_REST BIT(5) 65 #define JZ4780_I2C_CTRL_MATP BIT(4) 66 #define JZ4780_I2C_CTRL_SATP BIT(3) 67 #define JZ4780_I2C_CTRL_SPDF BIT(2) 68 #define JZ4780_I2C_CTRL_SPDS BIT(1) 69 #define JZ4780_I2C_CTRL_MD BIT(0) 70 71 #define JZ4780_I2C_STA_SLVACT BIT(6) 72 #define JZ4780_I2C_STA_MSTACT BIT(5) 73 #define JZ4780_I2C_STA_RFF BIT(4) 74 #define JZ4780_I2C_STA_RFNE BIT(3) 75 #define JZ4780_I2C_STA_TFE BIT(2) 76 #define JZ4780_I2C_STA_TFNF BIT(1) 77 #define JZ4780_I2C_STA_ACT BIT(0) 78 79 #define X1000_I2C_DC_STOP BIT(9) 80 81 static const char * const jz4780_i2c_abrt_src[] = { 82 "ABRT_7B_ADDR_NOACK", 83 "ABRT_10ADDR1_NOACK", 84 "ABRT_10ADDR2_NOACK", 85 "ABRT_XDATA_NOACK", 86 "ABRT_GCALL_NOACK", 87 "ABRT_GCALL_READ", 88 "ABRT_HS_ACKD", 89 "SBYTE_ACKDET", 90 "ABRT_HS_NORSTRT", 91 "SBYTE_NORSTRT", 92 "ABRT_10B_RD_NORSTRT", 93 "ABRT_MASTER_DIS", 94 "ARB_LOST", 95 "SLVFLUSH_TXFIFO", 96 "SLV_ARBLOST", 97 "SLVRD_INTX", 98 }; 99 100 #define JZ4780_I2C_INTST_IGC BIT(11) 101 #define JZ4780_I2C_INTST_ISTT BIT(10) 102 #define JZ4780_I2C_INTST_ISTP BIT(9) 103 #define JZ4780_I2C_INTST_IACT BIT(8) 104 #define JZ4780_I2C_INTST_RXDN BIT(7) 105 #define JZ4780_I2C_INTST_TXABT BIT(6) 106 #define JZ4780_I2C_INTST_RDREQ BIT(5) 107 #define JZ4780_I2C_INTST_TXEMP BIT(4) 108 #define JZ4780_I2C_INTST_TXOF BIT(3) 109 #define JZ4780_I2C_INTST_RXFL BIT(2) 110 #define JZ4780_I2C_INTST_RXOF BIT(1) 111 #define JZ4780_I2C_INTST_RXUF BIT(0) 112 113 #define JZ4780_I2C_INTM_MIGC BIT(11) 114 #define JZ4780_I2C_INTM_MISTT BIT(10) 115 #define JZ4780_I2C_INTM_MISTP BIT(9) 116 #define JZ4780_I2C_INTM_MIACT BIT(8) 117 #define JZ4780_I2C_INTM_MRXDN BIT(7) 118 #define JZ4780_I2C_INTM_MTXABT BIT(6) 119 #define JZ4780_I2C_INTM_MRDREQ BIT(5) 120 #define JZ4780_I2C_INTM_MTXEMP BIT(4) 121 #define JZ4780_I2C_INTM_MTXOF BIT(3) 122 #define JZ4780_I2C_INTM_MRXFL BIT(2) 123 #define JZ4780_I2C_INTM_MRXOF BIT(1) 124 #define JZ4780_I2C_INTM_MRXUF BIT(0) 125 126 #define JZ4780_I2C_DC_READ BIT(8) 127 128 #define JZ4780_I2C_SDAHD_HDENB BIT(8) 129 130 #define JZ4780_I2C_ENB_I2C BIT(0) 131 132 #define JZ4780_I2CSHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8)) 133 #define JZ4780_I2CSLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1)) 134 #define JZ4780_I2CFHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8)) 135 #define JZ4780_I2CFLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1)) 136 137 #define JZ4780_I2C_FIFO_LEN 16 138 139 #define X1000_I2C_FIFO_LEN 64 140 141 #define JZ4780_I2C_TIMEOUT 300 142 143 #define BUFSIZE 200 144 145 enum ingenic_i2c_version { 146 ID_JZ4780, 147 ID_X1000, 148 }; 149 150 /* ingenic_i2c_config: SoC specific config data. */ 151 struct ingenic_i2c_config { 152 enum ingenic_i2c_version version; 153 154 int fifosize; 155 int tx_level; 156 int rx_level; 157 }; 158 159 struct jz4780_i2c { 160 void __iomem *iomem; 161 int irq; 162 struct clk *clk; 163 struct i2c_adapter adap; 164 const struct ingenic_i2c_config *cdata; 165 166 /* lock to protect rbuf and wbuf between xfer_rd/wr and irq handler */ 167 spinlock_t lock; 168 169 /* beginning of lock scope */ 170 unsigned char *rbuf; 171 int rd_total_len; 172 int rd_data_xfered; 173 int rd_cmd_xfered; 174 175 unsigned char *wbuf; 176 int wt_len; 177 178 int is_write; 179 int stop_hold; 180 int speed; 181 182 int data_buf[BUFSIZE]; 183 int cmd_buf[BUFSIZE]; 184 int cmd; 185 186 /* end of lock scope */ 187 struct completion trans_waitq; 188 }; 189 190 static inline unsigned short jz4780_i2c_readw(struct jz4780_i2c *i2c, 191 unsigned long offset) 192 { 193 return readw(i2c->iomem + offset); 194 } 195 196 static inline void jz4780_i2c_writew(struct jz4780_i2c *i2c, 197 unsigned long offset, unsigned short val) 198 { 199 writew(val, i2c->iomem + offset); 200 } 201 202 static int jz4780_i2c_disable(struct jz4780_i2c *i2c) 203 { 204 unsigned short regval; 205 unsigned long loops = 5; 206 207 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 0); 208 209 do { 210 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA); 211 if (!(regval & JZ4780_I2C_ENB_I2C)) 212 return 0; 213 214 usleep_range(5000, 15000); 215 } while (--loops); 216 217 dev_err(&i2c->adap.dev, "disable failed: ENSTA=0x%04x\n", regval); 218 return -ETIMEDOUT; 219 } 220 221 static int jz4780_i2c_enable(struct jz4780_i2c *i2c) 222 { 223 unsigned short regval; 224 unsigned long loops = 5; 225 226 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 1); 227 228 do { 229 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA); 230 if (regval & JZ4780_I2C_ENB_I2C) 231 return 0; 232 233 usleep_range(5000, 15000); 234 } while (--loops); 235 236 dev_err(&i2c->adap.dev, "enable failed: ENSTA=0x%04x\n", regval); 237 return -ETIMEDOUT; 238 } 239 240 static int jz4780_i2c_set_target(struct jz4780_i2c *i2c, unsigned char address) 241 { 242 unsigned short regval; 243 unsigned long loops = 5; 244 245 do { 246 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_STA); 247 if ((regval & JZ4780_I2C_STA_TFE) && 248 !(regval & JZ4780_I2C_STA_MSTACT)) 249 break; 250 251 usleep_range(5000, 15000); 252 } while (--loops); 253 254 if (loops) { 255 jz4780_i2c_writew(i2c, JZ4780_I2C_TAR, address); 256 return 0; 257 } 258 259 dev_err(&i2c->adap.dev, 260 "set device to address 0x%02x failed, STA=0x%04x\n", 261 address, regval); 262 263 return -ENXIO; 264 } 265 266 static int jz4780_i2c_set_speed(struct jz4780_i2c *i2c) 267 { 268 int dev_clk_khz = clk_get_rate(i2c->clk) / 1000; 269 int cnt_high = 0; /* HIGH period count of the SCL clock */ 270 int cnt_low = 0; /* LOW period count of the SCL clock */ 271 int cnt_period = 0; /* period count of the SCL clock */ 272 int setup_time = 0; 273 int hold_time = 0; 274 unsigned short tmp = 0; 275 int i2c_clk = i2c->speed; 276 277 if (jz4780_i2c_disable(i2c)) 278 dev_dbg(&i2c->adap.dev, "i2c not disabled\n"); 279 280 /* 281 * 1 JZ4780_I2C cycle equals to cnt_period PCLK(i2c_clk) 282 * standard mode, min LOW and HIGH period are 4700 ns and 4000 ns 283 * fast mode, min LOW and HIGH period are 1300 ns and 600 ns 284 */ 285 cnt_period = dev_clk_khz / i2c_clk; 286 287 if (i2c_clk <= 100) 288 cnt_high = (cnt_period * 4000) / (4700 + 4000); 289 else 290 cnt_high = (cnt_period * 600) / (1300 + 600); 291 292 cnt_low = cnt_period - cnt_high; 293 294 /* 295 * NOTE: JZ4780_I2C_CTRL_REST can't set when i2c enabled, because 296 * normal read are 2 messages, we cannot disable i2c controller 297 * between these two messages, this means that we must always set 298 * JZ4780_I2C_CTRL_REST when init JZ4780_I2C_CTRL 299 * 300 */ 301 if (i2c_clk <= 100) { 302 tmp = JZ4780_I2C_CTRL_SPDS | JZ4780_I2C_CTRL_REST 303 | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD; 304 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 305 306 jz4780_i2c_writew(i2c, JZ4780_I2C_SHCNT, 307 JZ4780_I2CSHCNT_ADJUST(cnt_high)); 308 jz4780_i2c_writew(i2c, JZ4780_I2C_SLCNT, 309 JZ4780_I2CSLCNT_ADJUST(cnt_low)); 310 } else { 311 tmp = JZ4780_I2C_CTRL_SPDF | JZ4780_I2C_CTRL_REST 312 | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD; 313 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 314 315 jz4780_i2c_writew(i2c, JZ4780_I2C_FHCNT, 316 JZ4780_I2CFHCNT_ADJUST(cnt_high)); 317 jz4780_i2c_writew(i2c, JZ4780_I2C_FLCNT, 318 JZ4780_I2CFLCNT_ADJUST(cnt_low)); 319 } 320 321 /* 322 * a i2c device must internally provide a hold time at least 300ns 323 * tHD:DAT 324 * Standard Mode: min=300ns, max=3450ns 325 * Fast Mode: min=0ns, max=900ns 326 * tSU:DAT 327 * Standard Mode: min=250ns, max=infinite 328 * Fast Mode: min=100(250ns is recommended), max=infinite 329 * 330 * 1i2c_clk = 10^6 / dev_clk_khz 331 * on FPGA, dev_clk_khz = 12000, so 1i2c_clk = 1000/12 = 83ns 332 * on Pisces(1008M), dev_clk_khz=126000, so 1i2c_clk = 1000 / 126 = 8ns 333 * 334 * The actual hold time is (SDAHD + 1) * (i2c_clk period). 335 * 336 * Length of setup time calculated using (SDASU - 1) * (ic_clk_period) 337 * 338 */ 339 if (i2c_clk <= 100) { /* standard mode */ 340 setup_time = 300; 341 hold_time = 400; 342 } else { 343 setup_time = 450; 344 hold_time = 450; 345 } 346 347 hold_time = ((hold_time * dev_clk_khz) / 1000000) - 1; 348 setup_time = ((setup_time * dev_clk_khz) / 1000000) + 1; 349 350 if (setup_time > 255) 351 setup_time = 255; 352 353 if (setup_time <= 0) 354 setup_time = 1; 355 356 jz4780_i2c_writew(i2c, JZ4780_I2C_SDASU, setup_time); 357 358 if (hold_time > 255) 359 hold_time = 255; 360 361 if (hold_time >= 0) { 362 /*i2c hold time enable */ 363 if (i2c->cdata->version >= ID_X1000) { 364 jz4780_i2c_writew(i2c, X1000_I2C_SDAHD, hold_time); 365 } else { 366 hold_time |= JZ4780_I2C_SDAHD_HDENB; 367 jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, hold_time); 368 } 369 } else { 370 /* disable hold time */ 371 if (i2c->cdata->version >= ID_X1000) 372 jz4780_i2c_writew(i2c, X1000_I2C_SDAHD, 0); 373 else 374 jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, 0); 375 } 376 377 return 0; 378 } 379 380 static int jz4780_i2c_cleanup(struct jz4780_i2c *i2c) 381 { 382 int ret; 383 unsigned long flags; 384 unsigned short tmp; 385 386 spin_lock_irqsave(&i2c->lock, flags); 387 388 /* can send stop now if need */ 389 if (i2c->cdata->version < ID_X1000) { 390 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL); 391 tmp &= ~JZ4780_I2C_CTRL_STPHLD; 392 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 393 } 394 395 /* disable all interrupts first */ 396 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0); 397 398 /* then clear all interrupts */ 399 jz4780_i2c_readw(i2c, JZ4780_I2C_CTXABRT); 400 jz4780_i2c_readw(i2c, JZ4780_I2C_CINTR); 401 402 /* then disable the controller */ 403 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL); 404 tmp &= ~JZ4780_I2C_ENB_I2C; 405 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 406 udelay(10); 407 tmp |= JZ4780_I2C_ENB_I2C; 408 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 409 410 spin_unlock_irqrestore(&i2c->lock, flags); 411 412 ret = jz4780_i2c_disable(i2c); 413 if (ret) 414 dev_err(&i2c->adap.dev, 415 "unable to disable device during cleanup!\n"); 416 417 if (unlikely(jz4780_i2c_readw(i2c, JZ4780_I2C_INTM) 418 & jz4780_i2c_readw(i2c, JZ4780_I2C_INTST))) 419 dev_err(&i2c->adap.dev, 420 "device has interrupts after a complete cleanup!\n"); 421 422 return ret; 423 } 424 425 static int jz4780_i2c_prepare(struct jz4780_i2c *i2c) 426 { 427 jz4780_i2c_set_speed(i2c); 428 return jz4780_i2c_enable(i2c); 429 } 430 431 static void jz4780_i2c_send_rcmd(struct jz4780_i2c *i2c, 432 int cmd_count, 433 int cmd_left) 434 { 435 int i; 436 437 for (i = 0; i < cmd_count - 1; i++) 438 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, JZ4780_I2C_DC_READ); 439 440 if ((cmd_left == 0) && (i2c->cdata->version >= ID_X1000)) 441 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, 442 JZ4780_I2C_DC_READ | X1000_I2C_DC_STOP); 443 else 444 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, JZ4780_I2C_DC_READ); 445 } 446 447 static void jz4780_i2c_trans_done(struct jz4780_i2c *i2c) 448 { 449 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0); 450 complete(&i2c->trans_waitq); 451 } 452 453 static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id) 454 { 455 unsigned short tmp; 456 unsigned short intst; 457 unsigned short intmsk; 458 struct jz4780_i2c *i2c = dev_id; 459 unsigned long flags; 460 461 spin_lock_irqsave(&i2c->lock, flags); 462 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM); 463 intst = jz4780_i2c_readw(i2c, JZ4780_I2C_INTST); 464 465 intst &= intmsk; 466 467 if (intst & JZ4780_I2C_INTST_TXABT) { 468 jz4780_i2c_trans_done(i2c); 469 goto done; 470 } 471 472 if (intst & JZ4780_I2C_INTST_RXOF) { 473 dev_dbg(&i2c->adap.dev, "received fifo overflow!\n"); 474 jz4780_i2c_trans_done(i2c); 475 goto done; 476 } 477 478 /* 479 * When reading, always drain RX FIFO before we send more Read 480 * Commands to avoid fifo overrun 481 */ 482 if (i2c->is_write == 0) { 483 int rd_left; 484 485 while ((jz4780_i2c_readw(i2c, JZ4780_I2C_STA) 486 & JZ4780_I2C_STA_RFNE)) { 487 *(i2c->rbuf++) = jz4780_i2c_readw(i2c, JZ4780_I2C_DC) 488 & 0xff; 489 i2c->rd_data_xfered++; 490 if (i2c->rd_data_xfered == i2c->rd_total_len) { 491 jz4780_i2c_trans_done(i2c); 492 goto done; 493 } 494 } 495 496 rd_left = i2c->rd_total_len - i2c->rd_data_xfered; 497 498 if (rd_left <= i2c->cdata->fifosize) 499 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, rd_left - 1); 500 } 501 502 if (intst & JZ4780_I2C_INTST_TXEMP) { 503 if (i2c->is_write == 0) { 504 int cmd_left = i2c->rd_total_len - i2c->rd_cmd_xfered; 505 int max_send = (i2c->cdata->fifosize - 1) 506 - (i2c->rd_cmd_xfered 507 - i2c->rd_data_xfered); 508 int cmd_to_send = min(cmd_left, max_send); 509 510 if (i2c->rd_cmd_xfered != 0) 511 cmd_to_send = min(cmd_to_send, 512 i2c->cdata->fifosize 513 - i2c->cdata->tx_level - 1); 514 515 if (cmd_to_send) { 516 i2c->rd_cmd_xfered += cmd_to_send; 517 cmd_left = i2c->rd_total_len - 518 i2c->rd_cmd_xfered; 519 jz4780_i2c_send_rcmd(i2c, 520 cmd_to_send, cmd_left); 521 522 } 523 524 if (cmd_left == 0) { 525 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM); 526 intmsk &= ~JZ4780_I2C_INTM_MTXEMP; 527 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, intmsk); 528 529 if (i2c->cdata->version < ID_X1000) { 530 tmp = jz4780_i2c_readw(i2c, 531 JZ4780_I2C_CTRL); 532 tmp &= ~JZ4780_I2C_CTRL_STPHLD; 533 jz4780_i2c_writew(i2c, 534 JZ4780_I2C_CTRL, tmp); 535 } 536 } 537 } else { 538 unsigned short data; 539 unsigned short i2c_sta; 540 541 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA); 542 543 while ((i2c_sta & JZ4780_I2C_STA_TFNF) && 544 (i2c->wt_len > 0)) { 545 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA); 546 data = *i2c->wbuf; 547 data &= ~JZ4780_I2C_DC_READ; 548 if ((!i2c->stop_hold) && (i2c->cdata->version >= 549 ID_X1000)) 550 data |= X1000_I2C_DC_STOP; 551 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, data); 552 i2c->wbuf++; 553 i2c->wt_len--; 554 } 555 556 if (i2c->wt_len == 0) { 557 if ((!i2c->stop_hold) && (i2c->cdata->version < 558 ID_X1000)) { 559 tmp = jz4780_i2c_readw(i2c, 560 JZ4780_I2C_CTRL); 561 tmp &= ~JZ4780_I2C_CTRL_STPHLD; 562 jz4780_i2c_writew(i2c, 563 JZ4780_I2C_CTRL, tmp); 564 } 565 566 jz4780_i2c_trans_done(i2c); 567 goto done; 568 } 569 } 570 } 571 572 done: 573 spin_unlock_irqrestore(&i2c->lock, flags); 574 return IRQ_HANDLED; 575 } 576 577 static void jz4780_i2c_txabrt(struct jz4780_i2c *i2c, int src) 578 { 579 int i; 580 581 dev_err(&i2c->adap.dev, "txabrt: 0x%08x\n", src); 582 dev_err(&i2c->adap.dev, "device addr=%x\n", 583 jz4780_i2c_readw(i2c, JZ4780_I2C_TAR)); 584 dev_err(&i2c->adap.dev, "send cmd count:%d %d\n", 585 i2c->cmd, i2c->cmd_buf[i2c->cmd]); 586 dev_err(&i2c->adap.dev, "receive data count:%d %d\n", 587 i2c->cmd, i2c->data_buf[i2c->cmd]); 588 589 for (i = 0; i < 16; i++) { 590 if (src & BIT(i)) 591 dev_dbg(&i2c->adap.dev, "I2C TXABRT[%d]=%s\n", 592 i, jz4780_i2c_abrt_src[i]); 593 } 594 } 595 596 static inline int jz4780_i2c_xfer_read(struct jz4780_i2c *i2c, 597 unsigned char *buf, int len, int cnt, 598 int idx) 599 { 600 int ret = 0; 601 long timeout; 602 int wait_time = JZ4780_I2C_TIMEOUT * (len + 5); 603 unsigned short tmp; 604 unsigned long flags; 605 606 memset(buf, 0, len); 607 608 spin_lock_irqsave(&i2c->lock, flags); 609 610 i2c->stop_hold = 0; 611 i2c->is_write = 0; 612 i2c->rbuf = buf; 613 i2c->rd_total_len = len; 614 i2c->rd_data_xfered = 0; 615 i2c->rd_cmd_xfered = 0; 616 617 if (len <= i2c->cdata->fifosize) 618 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, len - 1); 619 else 620 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, i2c->cdata->rx_level); 621 622 jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, i2c->cdata->tx_level); 623 624 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 625 JZ4780_I2C_INTM_MRXFL | JZ4780_I2C_INTM_MTXEMP 626 | JZ4780_I2C_INTM_MTXABT | JZ4780_I2C_INTM_MRXOF); 627 628 if (i2c->cdata->version < ID_X1000) { 629 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL); 630 tmp |= JZ4780_I2C_CTRL_STPHLD; 631 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 632 } 633 634 spin_unlock_irqrestore(&i2c->lock, flags); 635 636 timeout = wait_for_completion_timeout(&i2c->trans_waitq, 637 msecs_to_jiffies(wait_time)); 638 639 if (!timeout) { 640 dev_err(&i2c->adap.dev, "irq read timeout\n"); 641 dev_dbg(&i2c->adap.dev, "send cmd count:%d %d\n", 642 i2c->cmd, i2c->cmd_buf[i2c->cmd]); 643 dev_dbg(&i2c->adap.dev, "receive data count:%d %d\n", 644 i2c->cmd, i2c->data_buf[i2c->cmd]); 645 ret = -EIO; 646 } 647 648 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT); 649 if (tmp) { 650 jz4780_i2c_txabrt(i2c, tmp); 651 ret = -EIO; 652 } 653 654 return ret; 655 } 656 657 static inline int jz4780_i2c_xfer_write(struct jz4780_i2c *i2c, 658 unsigned char *buf, int len, 659 int cnt, int idx) 660 { 661 int ret = 0; 662 int wait_time = JZ4780_I2C_TIMEOUT * (len + 5); 663 long timeout; 664 unsigned short tmp; 665 unsigned long flags; 666 667 spin_lock_irqsave(&i2c->lock, flags); 668 669 if (idx < (cnt - 1)) 670 i2c->stop_hold = 1; 671 else 672 i2c->stop_hold = 0; 673 674 i2c->is_write = 1; 675 i2c->wbuf = buf; 676 i2c->wt_len = len; 677 678 jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, i2c->cdata->tx_level); 679 680 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, JZ4780_I2C_INTM_MTXEMP 681 | JZ4780_I2C_INTM_MTXABT); 682 683 if (i2c->cdata->version < ID_X1000) { 684 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL); 685 tmp |= JZ4780_I2C_CTRL_STPHLD; 686 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 687 } 688 689 spin_unlock_irqrestore(&i2c->lock, flags); 690 691 timeout = wait_for_completion_timeout(&i2c->trans_waitq, 692 msecs_to_jiffies(wait_time)); 693 if (timeout && !i2c->stop_hold) { 694 unsigned short i2c_sta; 695 int write_in_process; 696 697 timeout = JZ4780_I2C_TIMEOUT * 100; 698 for (; timeout > 0; timeout--) { 699 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA); 700 701 write_in_process = (i2c_sta & JZ4780_I2C_STA_MSTACT) || 702 !(i2c_sta & JZ4780_I2C_STA_TFE); 703 if (!write_in_process) 704 break; 705 udelay(10); 706 } 707 } 708 709 if (!timeout) { 710 dev_err(&i2c->adap.dev, "write wait timeout\n"); 711 ret = -EIO; 712 } 713 714 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT); 715 if (tmp) { 716 jz4780_i2c_txabrt(i2c, tmp); 717 ret = -EIO; 718 } 719 720 return ret; 721 } 722 723 static int jz4780_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, 724 int count) 725 { 726 int i = -EIO; 727 int ret = 0; 728 struct jz4780_i2c *i2c = adap->algo_data; 729 730 ret = jz4780_i2c_prepare(i2c); 731 if (ret) { 732 dev_err(&i2c->adap.dev, "I2C prepare failed\n"); 733 goto out; 734 } 735 736 if (msg->addr != jz4780_i2c_readw(i2c, JZ4780_I2C_TAR)) { 737 ret = jz4780_i2c_set_target(i2c, msg->addr); 738 if (ret) 739 goto out; 740 } 741 for (i = 0; i < count; i++, msg++) { 742 if (msg->flags & I2C_M_RD) 743 ret = jz4780_i2c_xfer_read(i2c, msg->buf, msg->len, 744 count, i); 745 else 746 ret = jz4780_i2c_xfer_write(i2c, msg->buf, msg->len, 747 count, i); 748 749 if (ret) 750 goto out; 751 } 752 753 ret = i; 754 755 out: 756 jz4780_i2c_cleanup(i2c); 757 return ret; 758 } 759 760 static u32 jz4780_i2c_functionality(struct i2c_adapter *adap) 761 { 762 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 763 } 764 765 static const struct i2c_algorithm jz4780_i2c_algorithm = { 766 .master_xfer = jz4780_i2c_xfer, 767 .functionality = jz4780_i2c_functionality, 768 }; 769 770 static const struct ingenic_i2c_config jz4780_i2c_config = { 771 .version = ID_JZ4780, 772 773 .fifosize = JZ4780_I2C_FIFO_LEN, 774 .tx_level = JZ4780_I2C_FIFO_LEN / 2, 775 .rx_level = JZ4780_I2C_FIFO_LEN / 2 - 1, 776 }; 777 778 static const struct ingenic_i2c_config x1000_i2c_config = { 779 .version = ID_X1000, 780 781 .fifosize = X1000_I2C_FIFO_LEN, 782 .tx_level = X1000_I2C_FIFO_LEN / 2, 783 .rx_level = X1000_I2C_FIFO_LEN / 2 - 1, 784 }; 785 786 static const struct of_device_id jz4780_i2c_of_matches[] = { 787 { .compatible = "ingenic,jz4780-i2c", .data = &jz4780_i2c_config }, 788 { .compatible = "ingenic,x1000-i2c", .data = &x1000_i2c_config }, 789 { /* sentinel */ } 790 }; 791 MODULE_DEVICE_TABLE(of, jz4780_i2c_of_matches); 792 793 static int jz4780_i2c_probe(struct platform_device *pdev) 794 { 795 int ret = 0; 796 unsigned int clk_freq = 0; 797 unsigned short tmp; 798 struct resource *r; 799 struct jz4780_i2c *i2c; 800 801 i2c = devm_kzalloc(&pdev->dev, sizeof(struct jz4780_i2c), GFP_KERNEL); 802 if (!i2c) 803 return -ENOMEM; 804 805 i2c->cdata = device_get_match_data(&pdev->dev); 806 if (!i2c->cdata) { 807 dev_err(&pdev->dev, "Error: No device match found\n"); 808 return -ENODEV; 809 } 810 811 i2c->adap.owner = THIS_MODULE; 812 i2c->adap.algo = &jz4780_i2c_algorithm; 813 i2c->adap.algo_data = i2c; 814 i2c->adap.retries = 5; 815 i2c->adap.dev.parent = &pdev->dev; 816 i2c->adap.dev.of_node = pdev->dev.of_node; 817 sprintf(i2c->adap.name, "%s", pdev->name); 818 819 init_completion(&i2c->trans_waitq); 820 spin_lock_init(&i2c->lock); 821 822 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 823 i2c->iomem = devm_ioremap_resource(&pdev->dev, r); 824 if (IS_ERR(i2c->iomem)) 825 return PTR_ERR(i2c->iomem); 826 827 platform_set_drvdata(pdev, i2c); 828 829 i2c->clk = devm_clk_get(&pdev->dev, NULL); 830 if (IS_ERR(i2c->clk)) 831 return PTR_ERR(i2c->clk); 832 833 ret = clk_prepare_enable(i2c->clk); 834 if (ret) 835 return ret; 836 837 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", 838 &clk_freq); 839 if (ret) { 840 dev_err(&pdev->dev, "clock-frequency not specified in DT\n"); 841 goto err; 842 } 843 844 i2c->speed = clk_freq / 1000; 845 if (i2c->speed == 0) { 846 ret = -EINVAL; 847 dev_err(&pdev->dev, "clock-frequency minimum is 1000\n"); 848 goto err; 849 } 850 jz4780_i2c_set_speed(i2c); 851 852 dev_info(&pdev->dev, "Bus frequency is %d KHz\n", i2c->speed); 853 854 if (i2c->cdata->version < ID_X1000) { 855 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL); 856 tmp &= ~JZ4780_I2C_CTRL_STPHLD; 857 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 858 } 859 860 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0x0); 861 862 i2c->irq = platform_get_irq(pdev, 0); 863 ret = devm_request_irq(&pdev->dev, i2c->irq, jz4780_i2c_irq, 0, 864 dev_name(&pdev->dev), i2c); 865 if (ret) 866 goto err; 867 868 ret = i2c_add_adapter(&i2c->adap); 869 if (ret < 0) 870 goto err; 871 872 return 0; 873 874 err: 875 clk_disable_unprepare(i2c->clk); 876 return ret; 877 } 878 879 static int jz4780_i2c_remove(struct platform_device *pdev) 880 { 881 struct jz4780_i2c *i2c = platform_get_drvdata(pdev); 882 883 clk_disable_unprepare(i2c->clk); 884 i2c_del_adapter(&i2c->adap); 885 return 0; 886 } 887 888 static struct platform_driver jz4780_i2c_driver = { 889 .probe = jz4780_i2c_probe, 890 .remove = jz4780_i2c_remove, 891 .driver = { 892 .name = "jz4780-i2c", 893 .of_match_table = of_match_ptr(jz4780_i2c_of_matches), 894 }, 895 }; 896 897 module_platform_driver(jz4780_i2c_driver); 898 899 MODULE_LICENSE("GPL"); 900 MODULE_AUTHOR("ztyan<ztyan@ingenic.cn>"); 901 MODULE_DESCRIPTION("i2c driver for JZ4780 SoCs"); 902