1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 8&cbass_main { 9 msmc_ram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x0 0x70000000 0x0 0x800000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x0 0x70000000 0x800000>; 15 16 atf-sram@0 { 17 reg = <0x0 0x20000>; 18 }; 19 }; 20 21 gic500: interrupt-controller@1800000 { 22 compatible = "arm,gic-v3"; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 #interrupt-cells = <3>; 27 interrupt-controller; 28 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 29 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 30 31 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 32 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 33 34 gic_its: gic-its@1820000 { 35 compatible = "arm,gic-v3-its"; 36 reg = <0x00 0x01820000 0x00 0x10000>; 37 socionext,synquacer-pre-its = <0x1000000 0x400000>; 38 msi-controller; 39 #msi-cells = <1>; 40 }; 41 }; 42 43 main_gpio_intr: interrupt-controller0 { 44 compatible = "ti,sci-intr"; 45 ti,intr-trigger-type = <1>; 46 interrupt-controller; 47 interrupt-parent = <&gic500>; 48 #interrupt-cells = <2>; 49 ti,sci = <&dmsc>; 50 ti,sci-dst-id = <14>; 51 ti,sci-rm-range-girq = <0x1>; 52 }; 53 54 main_navss { 55 compatible = "simple-mfd"; 56 #address-cells = <2>; 57 #size-cells = <2>; 58 ranges; 59 dma-coherent; 60 dma-ranges; 61 62 ti,sci-dev-id = <199>; 63 64 main_navss_intr: interrupt-controller1 { 65 compatible = "ti,sci-intr"; 66 ti,intr-trigger-type = <4>; 67 interrupt-controller; 68 interrupt-parent = <&gic500>; 69 #interrupt-cells = <2>; 70 ti,sci = <&dmsc>; 71 ti,sci-dst-id = <14>; 72 ti,sci-rm-range-girq = <0>, <2>; 73 }; 74 75 main_udmass_inta: interrupt-controller@33d00000 { 76 compatible = "ti,sci-inta"; 77 reg = <0x0 0x33d00000 0x0 0x100000>; 78 interrupt-controller; 79 interrupt-parent = <&main_navss_intr>; 80 msi-controller; 81 ti,sci = <&dmsc>; 82 ti,sci-dev-id = <209>; 83 ti,sci-rm-range-vint = <0xa>; 84 ti,sci-rm-range-global-event = <0xd>; 85 }; 86 87 secure_proxy_main: mailbox@32c00000 { 88 compatible = "ti,am654-secure-proxy"; 89 #mbox-cells = <1>; 90 reg-names = "target_data", "rt", "scfg"; 91 reg = <0x00 0x32c00000 0x00 0x100000>, 92 <0x00 0x32400000 0x00 0x100000>, 93 <0x00 0x32800000 0x00 0x100000>; 94 interrupt-names = "rx_011"; 95 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 96 }; 97 98 smmu0: smmu@36600000 { 99 compatible = "arm,smmu-v3"; 100 reg = <0x0 0x36600000 0x0 0x100000>; 101 interrupt-parent = <&gic500>; 102 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 103 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 104 interrupt-names = "eventq", "gerror"; 105 #iommu-cells = <1>; 106 }; 107 108 hwspinlock: spinlock@30e00000 { 109 compatible = "ti,am654-hwspinlock"; 110 reg = <0x00 0x30e00000 0x00 0x1000>; 111 #hwlock-cells = <1>; 112 }; 113 114 mailbox0_cluster0: mailbox@31f80000 { 115 compatible = "ti,am654-mailbox"; 116 reg = <0x00 0x31f80000 0x00 0x200>; 117 #mbox-cells = <1>; 118 ti,mbox-num-users = <4>; 119 ti,mbox-num-fifos = <16>; 120 interrupt-parent = <&main_navss_intr>; 121 }; 122 123 mailbox0_cluster1: mailbox@31f81000 { 124 compatible = "ti,am654-mailbox"; 125 reg = <0x00 0x31f81000 0x00 0x200>; 126 #mbox-cells = <1>; 127 ti,mbox-num-users = <4>; 128 ti,mbox-num-fifos = <16>; 129 interrupt-parent = <&main_navss_intr>; 130 }; 131 132 mailbox0_cluster2: mailbox@31f82000 { 133 compatible = "ti,am654-mailbox"; 134 reg = <0x00 0x31f82000 0x00 0x200>; 135 #mbox-cells = <1>; 136 ti,mbox-num-users = <4>; 137 ti,mbox-num-fifos = <16>; 138 interrupt-parent = <&main_navss_intr>; 139 }; 140 141 mailbox0_cluster3: mailbox@31f83000 { 142 compatible = "ti,am654-mailbox"; 143 reg = <0x00 0x31f83000 0x00 0x200>; 144 #mbox-cells = <1>; 145 ti,mbox-num-users = <4>; 146 ti,mbox-num-fifos = <16>; 147 interrupt-parent = <&main_navss_intr>; 148 }; 149 150 mailbox0_cluster4: mailbox@31f84000 { 151 compatible = "ti,am654-mailbox"; 152 reg = <0x00 0x31f84000 0x00 0x200>; 153 #mbox-cells = <1>; 154 ti,mbox-num-users = <4>; 155 ti,mbox-num-fifos = <16>; 156 interrupt-parent = <&main_navss_intr>; 157 }; 158 159 mailbox0_cluster5: mailbox@31f85000 { 160 compatible = "ti,am654-mailbox"; 161 reg = <0x00 0x31f85000 0x00 0x200>; 162 #mbox-cells = <1>; 163 ti,mbox-num-users = <4>; 164 ti,mbox-num-fifos = <16>; 165 interrupt-parent = <&main_navss_intr>; 166 }; 167 168 mailbox0_cluster6: mailbox@31f86000 { 169 compatible = "ti,am654-mailbox"; 170 reg = <0x00 0x31f86000 0x00 0x200>; 171 #mbox-cells = <1>; 172 ti,mbox-num-users = <4>; 173 ti,mbox-num-fifos = <16>; 174 interrupt-parent = <&main_navss_intr>; 175 }; 176 177 mailbox0_cluster7: mailbox@31f87000 { 178 compatible = "ti,am654-mailbox"; 179 reg = <0x00 0x31f87000 0x00 0x200>; 180 #mbox-cells = <1>; 181 ti,mbox-num-users = <4>; 182 ti,mbox-num-fifos = <16>; 183 interrupt-parent = <&main_navss_intr>; 184 }; 185 186 mailbox0_cluster8: mailbox@31f88000 { 187 compatible = "ti,am654-mailbox"; 188 reg = <0x00 0x31f88000 0x00 0x200>; 189 #mbox-cells = <1>; 190 ti,mbox-num-users = <4>; 191 ti,mbox-num-fifos = <16>; 192 interrupt-parent = <&main_navss_intr>; 193 }; 194 195 mailbox0_cluster9: mailbox@31f89000 { 196 compatible = "ti,am654-mailbox"; 197 reg = <0x00 0x31f89000 0x00 0x200>; 198 #mbox-cells = <1>; 199 ti,mbox-num-users = <4>; 200 ti,mbox-num-fifos = <16>; 201 interrupt-parent = <&main_navss_intr>; 202 }; 203 204 mailbox0_cluster10: mailbox@31f8a000 { 205 compatible = "ti,am654-mailbox"; 206 reg = <0x00 0x31f8a000 0x00 0x200>; 207 #mbox-cells = <1>; 208 ti,mbox-num-users = <4>; 209 ti,mbox-num-fifos = <16>; 210 interrupt-parent = <&main_navss_intr>; 211 }; 212 213 mailbox0_cluster11: mailbox@31f8b000 { 214 compatible = "ti,am654-mailbox"; 215 reg = <0x00 0x31f8b000 0x00 0x200>; 216 #mbox-cells = <1>; 217 ti,mbox-num-users = <4>; 218 ti,mbox-num-fifos = <16>; 219 interrupt-parent = <&main_navss_intr>; 220 }; 221 222 main_ringacc: ringacc@3c000000 { 223 compatible = "ti,am654-navss-ringacc"; 224 reg = <0x0 0x3c000000 0x0 0x400000>, 225 <0x0 0x38000000 0x0 0x400000>, 226 <0x0 0x31120000 0x0 0x100>, 227 <0x0 0x33000000 0x0 0x40000>; 228 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 229 ti,num-rings = <1024>; 230 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 231 ti,sci = <&dmsc>; 232 ti,sci-dev-id = <211>; 233 msi-parent = <&main_udmass_inta>; 234 }; 235 236 main_udmap: dma-controller@31150000 { 237 compatible = "ti,j721e-navss-main-udmap"; 238 reg = <0x0 0x31150000 0x0 0x100>, 239 <0x0 0x34000000 0x0 0x100000>, 240 <0x0 0x35000000 0x0 0x100000>; 241 reg-names = "gcfg", "rchanrt", "tchanrt"; 242 msi-parent = <&main_udmass_inta>; 243 #dma-cells = <1>; 244 245 ti,sci = <&dmsc>; 246 ti,sci-dev-id = <212>; 247 ti,ringacc = <&main_ringacc>; 248 249 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 250 <0x0f>, /* TX_HCHAN */ 251 <0x10>; /* TX_UHCHAN */ 252 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 253 <0x0b>, /* RX_HCHAN */ 254 <0x0c>; /* RX_UHCHAN */ 255 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 256 }; 257 258 cpts@310d0000 { 259 compatible = "ti,j721e-cpts"; 260 reg = <0x0 0x310d0000 0x0 0x400>; 261 reg-names = "cpts"; 262 clocks = <&k3_clks 201 1>; 263 clock-names = "cpts"; 264 interrupts-extended = <&main_navss_intr 201 0>; 265 interrupt-names = "cpts"; 266 ti,cpts-periodic-outputs = <6>; 267 ti,cpts-ext-ts-inputs = <8>; 268 }; 269 }; 270 271 main_pmx0: pinmux@11c000 { 272 compatible = "pinctrl-single"; 273 /* Proxy 0 addressing */ 274 reg = <0x0 0x11c000 0x0 0x2b4>; 275 #pinctrl-cells = <1>; 276 pinctrl-single,register-width = <32>; 277 pinctrl-single,function-mask = <0xffffffff>; 278 }; 279 280 main_uart0: serial@2800000 { 281 compatible = "ti,j721e-uart", "ti,am654-uart"; 282 reg = <0x00 0x02800000 0x00 0x100>; 283 reg-shift = <2>; 284 reg-io-width = <4>; 285 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 286 clock-frequency = <48000000>; 287 current-speed = <115200>; 288 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 289 clocks = <&k3_clks 146 0>; 290 clock-names = "fclk"; 291 }; 292 293 main_uart1: serial@2810000 { 294 compatible = "ti,j721e-uart", "ti,am654-uart"; 295 reg = <0x00 0x02810000 0x00 0x100>; 296 reg-shift = <2>; 297 reg-io-width = <4>; 298 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 299 clock-frequency = <48000000>; 300 current-speed = <115200>; 301 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 302 clocks = <&k3_clks 278 0>; 303 clock-names = "fclk"; 304 }; 305 306 main_uart2: serial@2820000 { 307 compatible = "ti,j721e-uart", "ti,am654-uart"; 308 reg = <0x00 0x02820000 0x00 0x100>; 309 reg-shift = <2>; 310 reg-io-width = <4>; 311 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 312 clock-frequency = <48000000>; 313 current-speed = <115200>; 314 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 315 clocks = <&k3_clks 279 0>; 316 clock-names = "fclk"; 317 }; 318 319 main_uart3: serial@2830000 { 320 compatible = "ti,j721e-uart", "ti,am654-uart"; 321 reg = <0x00 0x02830000 0x00 0x100>; 322 reg-shift = <2>; 323 reg-io-width = <4>; 324 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 325 clock-frequency = <48000000>; 326 current-speed = <115200>; 327 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 328 clocks = <&k3_clks 280 0>; 329 clock-names = "fclk"; 330 }; 331 332 main_uart4: serial@2840000 { 333 compatible = "ti,j721e-uart", "ti,am654-uart"; 334 reg = <0x00 0x02840000 0x00 0x100>; 335 reg-shift = <2>; 336 reg-io-width = <4>; 337 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 338 clock-frequency = <48000000>; 339 current-speed = <115200>; 340 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 341 clocks = <&k3_clks 281 0>; 342 clock-names = "fclk"; 343 }; 344 345 main_uart5: serial@2850000 { 346 compatible = "ti,j721e-uart", "ti,am654-uart"; 347 reg = <0x00 0x02850000 0x00 0x100>; 348 reg-shift = <2>; 349 reg-io-width = <4>; 350 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 351 clock-frequency = <48000000>; 352 current-speed = <115200>; 353 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 354 clocks = <&k3_clks 282 0>; 355 clock-names = "fclk"; 356 }; 357 358 main_uart6: serial@2860000 { 359 compatible = "ti,j721e-uart", "ti,am654-uart"; 360 reg = <0x00 0x02860000 0x00 0x100>; 361 reg-shift = <2>; 362 reg-io-width = <4>; 363 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 364 clock-frequency = <48000000>; 365 current-speed = <115200>; 366 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 367 clocks = <&k3_clks 283 0>; 368 clock-names = "fclk"; 369 }; 370 371 main_uart7: serial@2870000 { 372 compatible = "ti,j721e-uart", "ti,am654-uart"; 373 reg = <0x00 0x02870000 0x00 0x100>; 374 reg-shift = <2>; 375 reg-io-width = <4>; 376 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 377 clock-frequency = <48000000>; 378 current-speed = <115200>; 379 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 380 clocks = <&k3_clks 284 0>; 381 clock-names = "fclk"; 382 }; 383 384 main_uart8: serial@2880000 { 385 compatible = "ti,j721e-uart", "ti,am654-uart"; 386 reg = <0x00 0x02880000 0x00 0x100>; 387 reg-shift = <2>; 388 reg-io-width = <4>; 389 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 390 clock-frequency = <48000000>; 391 current-speed = <115200>; 392 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 393 clocks = <&k3_clks 285 0>; 394 clock-names = "fclk"; 395 }; 396 397 main_uart9: serial@2890000 { 398 compatible = "ti,j721e-uart", "ti,am654-uart"; 399 reg = <0x00 0x02890000 0x00 0x100>; 400 reg-shift = <2>; 401 reg-io-width = <4>; 402 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 403 clock-frequency = <48000000>; 404 current-speed = <115200>; 405 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 406 clocks = <&k3_clks 286 0>; 407 clock-names = "fclk"; 408 }; 409 410 main_gpio0: gpio@600000 { 411 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 412 reg = <0x0 0x00600000 0x0 0x100>; 413 gpio-controller; 414 #gpio-cells = <2>; 415 interrupt-parent = <&main_gpio_intr>; 416 interrupts = <105 0>, <105 1>, <105 2>, <105 3>, 417 <105 4>, <105 5>, <105 6>, <105 7>; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 ti,ngpio = <128>; 421 ti,davinci-gpio-unbanked = <0>; 422 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 423 clocks = <&k3_clks 105 0>; 424 clock-names = "gpio"; 425 }; 426 427 main_gpio1: gpio@601000 { 428 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 429 reg = <0x0 0x00601000 0x0 0x100>; 430 gpio-controller; 431 #gpio-cells = <2>; 432 interrupt-parent = <&main_gpio_intr>; 433 interrupts = <106 0>, <106 1>, <106 2>; 434 interrupt-controller; 435 #interrupt-cells = <2>; 436 ti,ngpio = <36>; 437 ti,davinci-gpio-unbanked = <0>; 438 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 439 clocks = <&k3_clks 106 0>; 440 clock-names = "gpio"; 441 }; 442 443 main_gpio2: gpio@610000 { 444 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 445 reg = <0x0 0x00610000 0x0 0x100>; 446 gpio-controller; 447 #gpio-cells = <2>; 448 interrupt-parent = <&main_gpio_intr>; 449 interrupts = <107 0>, <107 1>, <107 2>, <107 3>, 450 <107 4>, <107 5>, <107 6>, <107 7>; 451 interrupt-controller; 452 #interrupt-cells = <2>; 453 ti,ngpio = <128>; 454 ti,davinci-gpio-unbanked = <0>; 455 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 456 clocks = <&k3_clks 107 0>; 457 clock-names = "gpio"; 458 }; 459 460 main_gpio3: gpio@611000 { 461 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 462 reg = <0x0 0x00611000 0x0 0x100>; 463 gpio-controller; 464 #gpio-cells = <2>; 465 interrupt-parent = <&main_gpio_intr>; 466 interrupts = <108 0>, <108 1>, <108 2>; 467 interrupt-controller; 468 #interrupt-cells = <2>; 469 ti,ngpio = <36>; 470 ti,davinci-gpio-unbanked = <0>; 471 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 472 clocks = <&k3_clks 108 0>; 473 clock-names = "gpio"; 474 }; 475 476 main_gpio4: gpio@620000 { 477 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 478 reg = <0x0 0x00620000 0x0 0x100>; 479 gpio-controller; 480 #gpio-cells = <2>; 481 interrupt-parent = <&main_gpio_intr>; 482 interrupts = <109 0>, <109 1>, <109 2>, <109 3>, 483 <109 4>, <109 5>, <109 6>, <109 7>; 484 interrupt-controller; 485 #interrupt-cells = <2>; 486 ti,ngpio = <128>; 487 ti,davinci-gpio-unbanked = <0>; 488 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 489 clocks = <&k3_clks 109 0>; 490 clock-names = "gpio"; 491 }; 492 493 main_gpio5: gpio@621000 { 494 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 495 reg = <0x0 0x00621000 0x0 0x100>; 496 gpio-controller; 497 #gpio-cells = <2>; 498 interrupt-parent = <&main_gpio_intr>; 499 interrupts = <110 0>, <110 1>, <110 2>; 500 interrupt-controller; 501 #interrupt-cells = <2>; 502 ti,ngpio = <36>; 503 ti,davinci-gpio-unbanked = <0>; 504 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 505 clocks = <&k3_clks 110 0>; 506 clock-names = "gpio"; 507 }; 508 509 main_gpio6: gpio@630000 { 510 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 511 reg = <0x0 0x00630000 0x0 0x100>; 512 gpio-controller; 513 #gpio-cells = <2>; 514 interrupt-parent = <&main_gpio_intr>; 515 interrupts = <111 0>, <111 1>, <111 2>, <111 3>, 516 <111 4>, <111 5>, <111 6>, <111 7>; 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 ti,ngpio = <128>; 520 ti,davinci-gpio-unbanked = <0>; 521 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 522 clocks = <&k3_clks 111 0>; 523 clock-names = "gpio"; 524 }; 525 526 main_gpio7: gpio@631000 { 527 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 528 reg = <0x0 0x00631000 0x0 0x100>; 529 gpio-controller; 530 #gpio-cells = <2>; 531 interrupt-parent = <&main_gpio_intr>; 532 interrupts = <112 0>, <112 1>, <112 2>; 533 interrupt-controller; 534 #interrupt-cells = <2>; 535 ti,ngpio = <36>; 536 ti,davinci-gpio-unbanked = <0>; 537 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 538 clocks = <&k3_clks 112 0>; 539 clock-names = "gpio"; 540 }; 541 542 main_sdhci0: sdhci@4f80000 { 543 compatible = "ti,j721e-sdhci-8bit"; 544 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 545 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 546 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 547 clock-names = "clk_xin", "clk_ahb"; 548 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; 549 assigned-clocks = <&k3_clks 91 1>; 550 assigned-clock-parents = <&k3_clks 91 2>; 551 bus-width = <8>; 552 mmc-hs400-1_8v; 553 mmc-ddr-1_8v; 554 ti,otap-del-sel = <0x2>; 555 ti,trm-icp = <0x8>; 556 ti,strobe-sel = <0x77>; 557 dma-coherent; 558 }; 559 560 main_sdhci1: sdhci@4fb0000 { 561 compatible = "ti,j721e-sdhci-4bit"; 562 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 563 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 564 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 565 clock-names = "clk_xin", "clk_ahb"; 566 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; 567 assigned-clocks = <&k3_clks 92 0>; 568 assigned-clock-parents = <&k3_clks 92 1>; 569 ti,otap-del-sel = <0x2>; 570 ti,trm-icp = <0x8>; 571 ti,clkbuf-sel = <0x7>; 572 dma-coherent; 573 no-1-8-v; 574 }; 575 576 main_sdhci2: sdhci@4f98000 { 577 compatible = "ti,j721e-sdhci-4bit"; 578 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 579 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 580 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 581 clock-names = "clk_xin", "clk_ahb"; 582 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; 583 assigned-clocks = <&k3_clks 93 0>; 584 assigned-clock-parents = <&k3_clks 93 1>; 585 ti,otap-del-sel = <0x2>; 586 ti,trm-icp = <0x8>; 587 ti,clkbuf-sel = <0x7>; 588 dma-coherent; 589 no-1-8-v; 590 }; 591 592 usbss0: cdns_usb@4104000 { 593 compatible = "ti,j721e-usb"; 594 reg = <0x00 0x4104000 0x00 0x100>; 595 dma-coherent; 596 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 597 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 598 clock-names = "ref", "lpm"; 599 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 600 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 601 #address-cells = <2>; 602 #size-cells = <2>; 603 ranges; 604 605 usb0: usb@6000000 { 606 compatible = "cdns,usb3"; 607 reg = <0x00 0x6000000 0x00 0x10000>, 608 <0x00 0x6010000 0x00 0x10000>, 609 <0x00 0x6020000 0x00 0x10000>; 610 reg-names = "otg", "xhci", "dev"; 611 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 612 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 613 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 614 interrupt-names = "host", 615 "peripheral", 616 "otg"; 617 maximum-speed = "super-speed"; 618 dr_mode = "otg"; 619 }; 620 }; 621 622 usbss1: cdns_usb@4114000 { 623 compatible = "ti,j721e-usb"; 624 reg = <0x00 0x4114000 0x00 0x100>; 625 dma-coherent; 626 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 627 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 628 clock-names = "ref", "lpm"; 629 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 630 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 631 #address-cells = <2>; 632 #size-cells = <2>; 633 ranges; 634 635 usb1: usb@6400000 { 636 compatible = "cdns,usb3"; 637 reg = <0x00 0x6400000 0x00 0x10000>, 638 <0x00 0x6410000 0x00 0x10000>, 639 <0x00 0x6420000 0x00 0x10000>; 640 reg-names = "otg", "xhci", "dev"; 641 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 642 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 643 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 644 interrupt-names = "host", 645 "peripheral", 646 "otg"; 647 maximum-speed = "super-speed"; 648 dr_mode = "otg"; 649 }; 650 }; 651 652 main_i2c0: i2c@2000000 { 653 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 654 reg = <0x0 0x2000000 0x0 0x100>; 655 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 clock-names = "fck"; 659 clocks = <&k3_clks 187 0>; 660 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 661 }; 662 663 main_i2c1: i2c@2010000 { 664 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 665 reg = <0x0 0x2010000 0x0 0x100>; 666 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 clock-names = "fck"; 670 clocks = <&k3_clks 188 0>; 671 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 672 }; 673 674 main_i2c2: i2c@2020000 { 675 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 676 reg = <0x0 0x2020000 0x0 0x100>; 677 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 clock-names = "fck"; 681 clocks = <&k3_clks 189 0>; 682 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 683 }; 684 685 main_i2c3: i2c@2030000 { 686 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 687 reg = <0x0 0x2030000 0x0 0x100>; 688 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 clock-names = "fck"; 692 clocks = <&k3_clks 190 0>; 693 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 694 }; 695 696 main_i2c4: i2c@2040000 { 697 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 698 reg = <0x0 0x2040000 0x0 0x100>; 699 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 clock-names = "fck"; 703 clocks = <&k3_clks 191 0>; 704 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 705 }; 706 707 main_i2c5: i2c@2050000 { 708 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 709 reg = <0x0 0x2050000 0x0 0x100>; 710 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 711 #address-cells = <1>; 712 #size-cells = <0>; 713 clock-names = "fck"; 714 clocks = <&k3_clks 192 0>; 715 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 716 }; 717 718 main_i2c6: i2c@2060000 { 719 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 720 reg = <0x0 0x2060000 0x0 0x100>; 721 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 clock-names = "fck"; 725 clocks = <&k3_clks 193 0>; 726 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 727 }; 728 729 ufs_wrapper: ufs-wrapper@4e80000 { 730 compatible = "ti,j721e-ufs"; 731 reg = <0x0 0x4e80000 0x0 0x100>; 732 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 733 clocks = <&k3_clks 277 1>; 734 assigned-clocks = <&k3_clks 277 1>; 735 assigned-clock-parents = <&k3_clks 277 4>; 736 ranges; 737 #address-cells = <2>; 738 #size-cells = <2>; 739 740 ufs@4e84000 { 741 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 742 reg = <0x0 0x4e84000 0x0 0x10000>; 743 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 744 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 745 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 746 clock-names = "core_clk", "phy_clk", "ref_clk"; 747 dma-coherent; 748 }; 749 }; 750 751 dss: dss@04a00000 { 752 compatible = "ti,j721e-dss"; 753 reg = 754 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 755 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 756 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 757 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 758 759 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 760 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 761 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 762 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 763 764 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 765 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 766 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 767 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 768 769 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 770 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 771 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 772 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 773 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 774 775 reg-names = "common_m", "common_s0", 776 "common_s1", "common_s2", 777 "vidl1", "vidl2","vid1","vid2", 778 "ovr1", "ovr2", "ovr3", "ovr4", 779 "vp1", "vp2", "vp3", "vp4", 780 "wb"; 781 782 clocks = <&k3_clks 152 0>, 783 <&k3_clks 152 1>, 784 <&k3_clks 152 4>, 785 <&k3_clks 152 9>, 786 <&k3_clks 152 13>; 787 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 788 789 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 790 791 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 795 interrupt-names = "common_m", 796 "common_s0", 797 "common_s1", 798 "common_s2"; 799 800 status = "disabled"; 801 802 dss_ports: ports { 803 #address-cells = <1>; 804 #size-cells = <0>; 805 }; 806 }; 807 808 mcasp0: mcasp@2b00000 { 809 compatible = "ti,am33xx-mcasp-audio"; 810 reg = <0x0 0x02b00000 0x0 0x2000>, 811 <0x0 0x02b08000 0x0 0x1000>; 812 reg-names = "mpu","dat"; 813 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 815 interrupt-names = "tx", "rx"; 816 817 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 818 dma-names = "tx", "rx"; 819 820 clocks = <&k3_clks 174 1>; 821 clock-names = "fck"; 822 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 823 824 status = "disabled"; 825 }; 826 827 mcasp1: mcasp@2b10000 { 828 compatible = "ti,am33xx-mcasp-audio"; 829 reg = <0x0 0x02b10000 0x0 0x2000>, 830 <0x0 0x02b18000 0x0 0x1000>; 831 reg-names = "mpu","dat"; 832 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 834 interrupt-names = "tx", "rx"; 835 836 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 837 dma-names = "tx", "rx"; 838 839 clocks = <&k3_clks 175 1>; 840 clock-names = "fck"; 841 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 842 843 status = "disabled"; 844 }; 845 846 mcasp2: mcasp@2b20000 { 847 compatible = "ti,am33xx-mcasp-audio"; 848 reg = <0x0 0x02b20000 0x0 0x2000>, 849 <0x0 0x02b28000 0x0 0x1000>; 850 reg-names = "mpu","dat"; 851 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 853 interrupt-names = "tx", "rx"; 854 855 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 856 dma-names = "tx", "rx"; 857 858 clocks = <&k3_clks 176 1>; 859 clock-names = "fck"; 860 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 861 862 status = "disabled"; 863 }; 864 865 mcasp3: mcasp@2b30000 { 866 compatible = "ti,am33xx-mcasp-audio"; 867 reg = <0x0 0x02b30000 0x0 0x2000>, 868 <0x0 0x02b38000 0x0 0x1000>; 869 reg-names = "mpu","dat"; 870 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 872 interrupt-names = "tx", "rx"; 873 874 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 875 dma-names = "tx", "rx"; 876 877 clocks = <&k3_clks 177 1>; 878 clock-names = "fck"; 879 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 880 881 status = "disabled"; 882 }; 883 884 mcasp4: mcasp@2b40000 { 885 compatible = "ti,am33xx-mcasp-audio"; 886 reg = <0x0 0x02b40000 0x0 0x2000>, 887 <0x0 0x02b48000 0x0 0x1000>; 888 reg-names = "mpu","dat"; 889 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 891 interrupt-names = "tx", "rx"; 892 893 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 894 dma-names = "tx", "rx"; 895 896 clocks = <&k3_clks 178 1>; 897 clock-names = "fck"; 898 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 899 900 status = "disabled"; 901 }; 902 903 mcasp5: mcasp@2b50000 { 904 compatible = "ti,am33xx-mcasp-audio"; 905 reg = <0x0 0x02b50000 0x0 0x2000>, 906 <0x0 0x02b58000 0x0 0x1000>; 907 reg-names = "mpu","dat"; 908 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 910 interrupt-names = "tx", "rx"; 911 912 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 913 dma-names = "tx", "rx"; 914 915 clocks = <&k3_clks 179 1>; 916 clock-names = "fck"; 917 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 918 919 status = "disabled"; 920 }; 921 922 mcasp6: mcasp@2b60000 { 923 compatible = "ti,am33xx-mcasp-audio"; 924 reg = <0x0 0x02b60000 0x0 0x2000>, 925 <0x0 0x02b68000 0x0 0x1000>; 926 reg-names = "mpu","dat"; 927 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 929 interrupt-names = "tx", "rx"; 930 931 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 932 dma-names = "tx", "rx"; 933 934 clocks = <&k3_clks 180 1>; 935 clock-names = "fck"; 936 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 937 938 status = "disabled"; 939 }; 940 941 mcasp7: mcasp@2b70000 { 942 compatible = "ti,am33xx-mcasp-audio"; 943 reg = <0x0 0x02b70000 0x0 0x2000>, 944 <0x0 0x02b78000 0x0 0x1000>; 945 reg-names = "mpu","dat"; 946 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 948 interrupt-names = "tx", "rx"; 949 950 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 951 dma-names = "tx", "rx"; 952 953 clocks = <&k3_clks 181 1>; 954 clock-names = "fck"; 955 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 956 957 status = "disabled"; 958 }; 959 960 mcasp8: mcasp@2b80000 { 961 compatible = "ti,am33xx-mcasp-audio"; 962 reg = <0x0 0x02b80000 0x0 0x2000>, 963 <0x0 0x02b88000 0x0 0x1000>; 964 reg-names = "mpu","dat"; 965 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 967 interrupt-names = "tx", "rx"; 968 969 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 970 dma-names = "tx", "rx"; 971 972 clocks = <&k3_clks 182 1>; 973 clock-names = "fck"; 974 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 975 976 status = "disabled"; 977 }; 978 979 mcasp9: mcasp@2b90000 { 980 compatible = "ti,am33xx-mcasp-audio"; 981 reg = <0x0 0x02b90000 0x0 0x2000>, 982 <0x0 0x02b98000 0x0 0x1000>; 983 reg-names = "mpu","dat"; 984 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 986 interrupt-names = "tx", "rx"; 987 988 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 989 dma-names = "tx", "rx"; 990 991 clocks = <&k3_clks 183 1>; 992 clock-names = "fck"; 993 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 994 995 status = "disabled"; 996 }; 997 998 mcasp10: mcasp@2ba0000 { 999 compatible = "ti,am33xx-mcasp-audio"; 1000 reg = <0x0 0x02ba0000 0x0 0x2000>, 1001 <0x0 0x02ba8000 0x0 0x1000>; 1002 reg-names = "mpu","dat"; 1003 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1005 interrupt-names = "tx", "rx"; 1006 1007 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1008 dma-names = "tx", "rx"; 1009 1010 clocks = <&k3_clks 184 1>; 1011 clock-names = "fck"; 1012 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1013 1014 status = "disabled"; 1015 }; 1016 1017 mcasp11: mcasp@2bb0000 { 1018 compatible = "ti,am33xx-mcasp-audio"; 1019 reg = <0x0 0x02bb0000 0x0 0x2000>, 1020 <0x0 0x02bb8000 0x0 0x1000>; 1021 reg-names = "mpu","dat"; 1022 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1024 interrupt-names = "tx", "rx"; 1025 1026 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1027 dma-names = "tx", "rx"; 1028 1029 clocks = <&k3_clks 185 1>; 1030 clock-names = "fck"; 1031 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1032 1033 status = "disabled"; 1034 }; 1035 1036 watchdog0: watchdog@2200000 { 1037 compatible = "ti,j7-rti-wdt"; 1038 reg = <0x0 0x2200000 0x0 0x100>; 1039 clocks = <&k3_clks 252 1>; 1040 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1041 assigned-clocks = <&k3_clks 252 1>; 1042 assigned-clock-parents = <&k3_clks 252 5>; 1043 }; 1044 1045 watchdog1: watchdog@2210000 { 1046 compatible = "ti,j7-rti-wdt"; 1047 reg = <0x0 0x2210000 0x0 0x100>; 1048 clocks = <&k3_clks 253 1>; 1049 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1050 assigned-clocks = <&k3_clks 253 1>; 1051 assigned-clock-parents = <&k3_clks 253 5>; 1052 }; 1053}; 1054