1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_POWER_H__ 7 #define __INTEL_DISPLAY_POWER_H__ 8 9 #include "intel_display.h" 10 #include "intel_runtime_pm.h" 11 #include "i915_reg.h" 12 13 struct drm_i915_private; 14 struct intel_encoder; 15 16 enum intel_display_power_domain { 17 POWER_DOMAIN_DISPLAY_CORE, 18 POWER_DOMAIN_PIPE_A, 19 POWER_DOMAIN_PIPE_B, 20 POWER_DOMAIN_PIPE_C, 21 POWER_DOMAIN_PIPE_D, 22 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 23 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 24 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 25 POWER_DOMAIN_PIPE_D_PANEL_FITTER, 26 POWER_DOMAIN_TRANSCODER_A, 27 POWER_DOMAIN_TRANSCODER_B, 28 POWER_DOMAIN_TRANSCODER_C, 29 POWER_DOMAIN_TRANSCODER_D, 30 POWER_DOMAIN_TRANSCODER_EDP, 31 /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */ 32 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 33 POWER_DOMAIN_TRANSCODER_DSI_A, 34 POWER_DOMAIN_TRANSCODER_DSI_C, 35 POWER_DOMAIN_PORT_DDI_A_LANES, 36 POWER_DOMAIN_PORT_DDI_B_LANES, 37 POWER_DOMAIN_PORT_DDI_C_LANES, 38 POWER_DOMAIN_PORT_DDI_D_LANES, 39 POWER_DOMAIN_PORT_DDI_E_LANES, 40 POWER_DOMAIN_PORT_DDI_F_LANES, 41 POWER_DOMAIN_PORT_DDI_G_LANES, 42 POWER_DOMAIN_PORT_DDI_H_LANES, 43 POWER_DOMAIN_PORT_DDI_I_LANES, 44 POWER_DOMAIN_PORT_DDI_A_IO, 45 POWER_DOMAIN_PORT_DDI_B_IO, 46 POWER_DOMAIN_PORT_DDI_C_IO, 47 POWER_DOMAIN_PORT_DDI_D_IO, 48 POWER_DOMAIN_PORT_DDI_E_IO, 49 POWER_DOMAIN_PORT_DDI_F_IO, 50 POWER_DOMAIN_PORT_DDI_G_IO, 51 POWER_DOMAIN_PORT_DDI_H_IO, 52 POWER_DOMAIN_PORT_DDI_I_IO, 53 POWER_DOMAIN_PORT_DSI, 54 POWER_DOMAIN_PORT_CRT, 55 POWER_DOMAIN_PORT_OTHER, 56 POWER_DOMAIN_VGA, 57 POWER_DOMAIN_AUDIO, 58 POWER_DOMAIN_AUX_A, 59 POWER_DOMAIN_AUX_B, 60 POWER_DOMAIN_AUX_C, 61 POWER_DOMAIN_AUX_D, 62 POWER_DOMAIN_AUX_E, 63 POWER_DOMAIN_AUX_F, 64 POWER_DOMAIN_AUX_G, 65 POWER_DOMAIN_AUX_H, 66 POWER_DOMAIN_AUX_I, 67 POWER_DOMAIN_AUX_IO_A, 68 POWER_DOMAIN_AUX_C_TBT, 69 POWER_DOMAIN_AUX_D_TBT, 70 POWER_DOMAIN_AUX_E_TBT, 71 POWER_DOMAIN_AUX_F_TBT, 72 POWER_DOMAIN_AUX_G_TBT, 73 POWER_DOMAIN_AUX_H_TBT, 74 POWER_DOMAIN_AUX_I_TBT, 75 POWER_DOMAIN_GMBUS, 76 POWER_DOMAIN_MODESET, 77 POWER_DOMAIN_GT_IRQ, 78 POWER_DOMAIN_DPLL_DC_OFF, 79 POWER_DOMAIN_INIT, 80 81 POWER_DOMAIN_NUM, 82 }; 83 84 /* 85 * i915_power_well_id: 86 * 87 * IDs used to look up power wells. Power wells accessed directly bypassing 88 * the power domains framework must be assigned a unique ID. The rest of power 89 * wells must be assigned DISP_PW_ID_NONE. 90 */ 91 enum i915_power_well_id { 92 DISP_PW_ID_NONE, 93 94 VLV_DISP_PW_DISP2D, 95 BXT_DISP_PW_DPIO_CMN_A, 96 VLV_DISP_PW_DPIO_CMN_BC, 97 GLK_DISP_PW_DPIO_CMN_C, 98 CHV_DISP_PW_DPIO_CMN_D, 99 HSW_DISP_PW_GLOBAL, 100 SKL_DISP_PW_MISC_IO, 101 SKL_DISP_PW_1, 102 SKL_DISP_PW_2, 103 TGL_DISP_PW_3, 104 SKL_DISP_DC_OFF, 105 }; 106 107 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 108 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 109 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 110 #define POWER_DOMAIN_TRANSCODER(tran) \ 111 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 112 (tran) + POWER_DOMAIN_TRANSCODER_A) 113 114 struct i915_power_well; 115 116 struct i915_power_well_ops { 117 /* 118 * Synchronize the well's hw state to match the current sw state, for 119 * example enable/disable it based on the current refcount. Called 120 * during driver init and resume time, possibly after first calling 121 * the enable/disable handlers. 122 */ 123 void (*sync_hw)(struct drm_i915_private *dev_priv, 124 struct i915_power_well *power_well); 125 /* 126 * Enable the well and resources that depend on it (for example 127 * interrupts located on the well). Called after the 0->1 refcount 128 * transition. 129 */ 130 void (*enable)(struct drm_i915_private *dev_priv, 131 struct i915_power_well *power_well); 132 /* 133 * Disable the well and resources that depend on it. Called after 134 * the 1->0 refcount transition. 135 */ 136 void (*disable)(struct drm_i915_private *dev_priv, 137 struct i915_power_well *power_well); 138 /* Returns the hw enabled state. */ 139 bool (*is_enabled)(struct drm_i915_private *dev_priv, 140 struct i915_power_well *power_well); 141 }; 142 143 struct i915_power_well_regs { 144 i915_reg_t bios; 145 i915_reg_t driver; 146 i915_reg_t kvmr; 147 i915_reg_t debug; 148 }; 149 150 /* Power well structure for haswell */ 151 struct i915_power_well_desc { 152 const char *name; 153 bool always_on; 154 u64 domains; 155 /* unique identifier for this power well */ 156 enum i915_power_well_id id; 157 /* 158 * Arbitraty data associated with this power well. Platform and power 159 * well specific. 160 */ 161 union { 162 struct { 163 /* 164 * request/status flag index in the PUNIT power well 165 * control/status registers. 166 */ 167 u8 idx; 168 } vlv; 169 struct { 170 enum dpio_phy phy; 171 } bxt; 172 struct { 173 const struct i915_power_well_regs *regs; 174 /* 175 * request/status flag index in the power well 176 * constrol/status registers. 177 */ 178 u8 idx; 179 /* Mask of pipes whose IRQ logic is backed by the pw */ 180 u8 irq_pipe_mask; 181 /* The pw is backing the VGA functionality */ 182 bool has_vga:1; 183 bool has_fuses:1; 184 /* 185 * The pw is for an ICL+ TypeC PHY port in 186 * Thunderbolt mode. 187 */ 188 bool is_tc_tbt:1; 189 } hsw; 190 }; 191 const struct i915_power_well_ops *ops; 192 }; 193 194 struct i915_power_well { 195 const struct i915_power_well_desc *desc; 196 /* power well enable/disable usage count */ 197 int count; 198 /* cached hw enabled state */ 199 bool hw_enabled; 200 }; 201 202 struct i915_power_domains { 203 /* 204 * Power wells needed for initialization at driver init and suspend 205 * time are on. They are kept on until after the first modeset. 206 */ 207 bool initializing; 208 bool display_core_suspended; 209 int power_well_count; 210 211 intel_wakeref_t wakeref; 212 213 struct mutex lock; 214 int domain_use_count[POWER_DOMAIN_NUM]; 215 216 struct delayed_work async_put_work; 217 intel_wakeref_t async_put_wakeref; 218 u64 async_put_domains[2]; 219 220 struct i915_power_well *power_wells; 221 }; 222 223 #define for_each_power_domain(domain, mask) \ 224 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 225 for_each_if(BIT_ULL(domain) & (mask)) 226 227 #define for_each_power_well(__dev_priv, __power_well) \ 228 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ 229 (__power_well) - (__dev_priv)->power_domains.power_wells < \ 230 (__dev_priv)->power_domains.power_well_count; \ 231 (__power_well)++) 232 233 #define for_each_power_well_reverse(__dev_priv, __power_well) \ 234 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ 235 (__dev_priv)->power_domains.power_well_count - 1; \ 236 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ 237 (__power_well)--) 238 239 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ 240 for_each_power_well(__dev_priv, __power_well) \ 241 for_each_if((__power_well)->desc->domains & (__domain_mask)) 242 243 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ 244 for_each_power_well_reverse(__dev_priv, __power_well) \ 245 for_each_if((__power_well)->desc->domains & (__domain_mask)) 246 247 int intel_power_domains_init(struct drm_i915_private *dev_priv); 248 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 249 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 250 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 251 void intel_power_domains_enable(struct drm_i915_private *dev_priv); 252 void intel_power_domains_disable(struct drm_i915_private *dev_priv); 253 void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 254 enum i915_drm_suspend_mode); 255 void intel_power_domains_resume(struct drm_i915_private *dev_priv); 256 257 void intel_display_power_suspend_late(struct drm_i915_private *i915); 258 void intel_display_power_resume_early(struct drm_i915_private *i915); 259 void intel_display_power_suspend(struct drm_i915_private *i915); 260 void intel_display_power_resume(struct drm_i915_private *i915); 261 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 262 u32 state); 263 264 const char * 265 intel_display_power_domain_str(enum intel_display_power_domain domain); 266 267 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 268 enum intel_display_power_domain domain); 269 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 270 enum intel_display_power_domain domain); 271 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 272 enum intel_display_power_domain domain); 273 intel_wakeref_t 274 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 275 enum intel_display_power_domain domain); 276 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 277 enum intel_display_power_domain domain); 278 void __intel_display_power_put_async(struct drm_i915_private *i915, 279 enum intel_display_power_domain domain, 280 intel_wakeref_t wakeref); 281 void intel_display_power_flush_work(struct drm_i915_private *i915); 282 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 283 void intel_display_power_put(struct drm_i915_private *dev_priv, 284 enum intel_display_power_domain domain, 285 intel_wakeref_t wakeref); 286 static inline void 287 intel_display_power_put_async(struct drm_i915_private *i915, 288 enum intel_display_power_domain domain, 289 intel_wakeref_t wakeref) 290 { 291 __intel_display_power_put_async(i915, domain, wakeref); 292 } 293 #else 294 static inline void 295 intel_display_power_put(struct drm_i915_private *i915, 296 enum intel_display_power_domain domain, 297 intel_wakeref_t wakeref) 298 { 299 intel_display_power_put_unchecked(i915, domain); 300 } 301 302 static inline void 303 intel_display_power_put_async(struct drm_i915_private *i915, 304 enum intel_display_power_domain domain, 305 intel_wakeref_t wakeref) 306 { 307 __intel_display_power_put_async(i915, domain, -1); 308 } 309 #endif 310 311 enum dbuf_slice { 312 DBUF_S1, 313 DBUF_S2, 314 }; 315 316 #define with_intel_display_power(i915, domain, wf) \ 317 for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ 318 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) 319 320 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, 321 u8 req_slices); 322 323 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 324 bool override, unsigned int mask); 325 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 326 enum dpio_channel ch, bool override); 327 328 #endif /* __INTEL_DISPLAY_POWER_H__ */ 329