1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_HAL_H 7 #define ATH11K_HAL_H 8 9 #include "hal_desc.h" 10 #include "rx_desc.h" 11 12 struct ath11k_base; 13 14 #define HAL_LINK_DESC_SIZE (32 << 2) 15 #define HAL_LINK_DESC_ALIGN 128 16 #define HAL_NUM_MPDUS_PER_LINK_DESC 6 17 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7 18 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6 19 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12 20 #define HAL_MAX_AVAIL_BLK_RES 3 21 22 #define HAL_RING_BASE_ALIGN 8 23 24 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704 25 /* TODO: Check with hw team on the supported scatter buf size */ 26 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8 27 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \ 28 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE) 29 30 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 48 31 #define HAL_DSCP_TID_TBL_SIZE 24 32 33 /* calculate the register address from bar0 of shadow register x */ 34 #define SHADOW_BASE_ADDRESS 0x00003024 35 #define SHADOW_NUM_REGISTERS 36 36 37 /* WCSS Relative address */ 38 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 39 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 40 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG 0x00a00000 41 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG 0x00a01000 42 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG 0x00a02000 43 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG 0x00a03000 44 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 45 46 /* SW2TCL(x) R0 ring configuration address */ 47 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014 48 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c 49 #define HAL_TCL1_RING_BASE_LSB 0x00000510 50 #define HAL_TCL1_RING_BASE_MSB 0x00000514 51 #define HAL_TCL1_RING_ID 0x00000518 52 #define HAL_TCL1_RING_MISC 0x00000520 53 #define HAL_TCL1_RING_TP_ADDR_LSB 0x0000052c 54 #define HAL_TCL1_RING_TP_ADDR_MSB 0x00000530 55 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0 0x00000540 56 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1 0x00000544 57 #define HAL_TCL1_RING_MSI1_BASE_LSB 0x00000558 58 #define HAL_TCL1_RING_MSI1_BASE_MSB 0x0000055c 59 #define HAL_TCL1_RING_MSI1_DATA 0x00000560 60 #define HAL_TCL2_RING_BASE_LSB 0x00000568 61 #define HAL_TCL_RING_BASE_LSB 0x00000618 62 63 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET \ 64 (HAL_TCL1_RING_MSI1_BASE_LSB - HAL_TCL1_RING_BASE_LSB) 65 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET \ 66 (HAL_TCL1_RING_MSI1_BASE_MSB - HAL_TCL1_RING_BASE_LSB) 67 #define HAL_TCL1_RING_MSI1_DATA_OFFSET \ 68 (HAL_TCL1_RING_MSI1_DATA - HAL_TCL1_RING_BASE_LSB) 69 #define HAL_TCL1_RING_BASE_MSB_OFFSET \ 70 (HAL_TCL1_RING_BASE_MSB - HAL_TCL1_RING_BASE_LSB) 71 #define HAL_TCL1_RING_ID_OFFSET \ 72 (HAL_TCL1_RING_ID - HAL_TCL1_RING_BASE_LSB) 73 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET \ 74 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0 - HAL_TCL1_RING_BASE_LSB) 75 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET \ 76 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1 - HAL_TCL1_RING_BASE_LSB) 77 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET \ 78 (HAL_TCL1_RING_TP_ADDR_LSB - HAL_TCL1_RING_BASE_LSB) 79 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET \ 80 (HAL_TCL1_RING_TP_ADDR_MSB - HAL_TCL1_RING_BASE_LSB) 81 #define HAL_TCL1_RING_MISC_OFFSET \ 82 (HAL_TCL1_RING_MISC - HAL_TCL1_RING_BASE_LSB) 83 84 /* SW2TCL(x) R2 ring pointers (head/tail) address */ 85 #define HAL_TCL1_RING_HP 0x00002000 86 #define HAL_TCL1_RING_TP 0x00002004 87 #define HAL_TCL2_RING_HP 0x00002008 88 #define HAL_TCL_RING_HP 0x00002018 89 90 #define HAL_TCL1_RING_TP_OFFSET \ 91 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP) 92 93 /* TCL STATUS ring address */ 94 #define HAL_TCL_STATUS_RING_BASE_LSB 0x00000720 95 #define HAL_TCL_STATUS_RING_HP 0x00002030 96 97 /* REO2SW(x) R0 ring configuration address */ 98 #define HAL_REO1_GEN_ENABLE 0x00000000 99 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c 100 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010 101 #define HAL_REO1_RING_BASE_LSB 0x0000029c 102 #define HAL_REO1_RING_BASE_MSB 0x000002a0 103 #define HAL_REO1_RING_ID 0x000002a4 104 #define HAL_REO1_RING_MISC 0x000002ac 105 #define HAL_REO1_RING_HP_ADDR_LSB 0x000002b0 106 #define HAL_REO1_RING_HP_ADDR_MSB 0x000002b4 107 #define HAL_REO1_RING_PRODUCER_INT_SETUP 0x000002c0 108 #define HAL_REO1_RING_MSI1_BASE_LSB 0x000002e4 109 #define HAL_REO1_RING_MSI1_BASE_MSB 0x000002e8 110 #define HAL_REO1_RING_MSI1_DATA 0x000002ec 111 #define HAL_REO2_RING_BASE_LSB 0x000002f4 112 #define HAL_REO1_AGING_THRESH_IX_0 0x00000564 113 #define HAL_REO1_AGING_THRESH_IX_1 0x00000568 114 #define HAL_REO1_AGING_THRESH_IX_2 0x0000056c 115 #define HAL_REO1_AGING_THRESH_IX_3 0x00000570 116 117 #define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET \ 118 (HAL_REO1_RING_MSI1_BASE_LSB - HAL_REO1_RING_BASE_LSB) 119 #define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET \ 120 (HAL_REO1_RING_MSI1_BASE_MSB - HAL_REO1_RING_BASE_LSB) 121 #define HAL_REO1_RING_MSI1_DATA_OFFSET \ 122 (HAL_REO1_RING_MSI1_DATA - HAL_REO1_RING_BASE_LSB) 123 #define HAL_REO1_RING_BASE_MSB_OFFSET \ 124 (HAL_REO1_RING_BASE_MSB - HAL_REO1_RING_BASE_LSB) 125 #define HAL_REO1_RING_ID_OFFSET (HAL_REO1_RING_ID - HAL_REO1_RING_BASE_LSB) 126 #define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET \ 127 (HAL_REO1_RING_PRODUCER_INT_SETUP - HAL_REO1_RING_BASE_LSB) 128 #define HAL_REO1_RING_HP_ADDR_LSB_OFFSET \ 129 (HAL_REO1_RING_HP_ADDR_LSB - HAL_REO1_RING_BASE_LSB) 130 #define HAL_REO1_RING_HP_ADDR_MSB_OFFSET \ 131 (HAL_REO1_RING_HP_ADDR_MSB - HAL_REO1_RING_BASE_LSB) 132 #define HAL_REO1_RING_MISC_OFFSET (HAL_REO1_RING_MISC - HAL_REO1_RING_BASE_LSB) 133 134 /* REO2SW(x) R2 ring pointers (head/tail) address */ 135 #define HAL_REO1_RING_HP 0x00003038 136 #define HAL_REO1_RING_TP 0x0000303c 137 #define HAL_REO2_RING_HP 0x00003040 138 139 #define HAL_REO1_RING_TP_OFFSET (HAL_REO1_RING_TP - HAL_REO1_RING_HP) 140 141 /* REO2TCL R0 ring configuration address */ 142 #define HAL_REO_TCL_RING_BASE_LSB 0x000003fc 143 144 /* REO2TCL R2 ring pointer (head/tail) address */ 145 #define HAL_REO_TCL_RING_HP 0x00003058 146 147 /* REO CMD R0 address */ 148 #define HAL_REO_CMD_RING_BASE_LSB 0x00000194 149 150 /* REO CMD R2 address */ 151 #define HAL_REO_CMD_HP 0x00003020 152 153 /* SW2REO R0 address */ 154 #define HAL_SW2REO_RING_BASE_LSB 0x000001ec 155 156 /* SW2REO R2 address */ 157 #define HAL_SW2REO_RING_HP 0x00003028 158 159 /* CE ring R0 address */ 160 #define HAL_CE_DST_RING_BASE_LSB 0x00000000 161 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058 162 #define HAL_CE_DST_RING_CTRL 0x000000b0 163 164 /* CE ring R2 address */ 165 #define HAL_CE_DST_RING_HP 0x00000400 166 #define HAL_CE_DST_STATUS_RING_HP 0x00000408 167 168 /* REO status address */ 169 #define HAL_REO_STATUS_RING_BASE_LSB 0x00000504 170 #define HAL_REO_STATUS_HP 0x00003070 171 172 /* WBM Idle R0 address */ 173 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB 0x00000860 174 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR 0x00000870 175 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR 0x00000048 176 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR 0x0000004c 177 #define HAL_WBM_SCATTERED_RING_BASE_LSB 0x00000058 178 #define HAL_WBM_SCATTERED_RING_BASE_MSB 0x0000005c 179 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 0x00000068 180 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 0x0000006c 181 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 0x00000078 182 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 0x0000007c 183 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR 0x00000084 184 185 /* WBM Idle R2 address */ 186 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b0 187 188 /* SW2WBM R0 release address */ 189 #define HAL_WBM_RELEASE_RING_BASE_LSB 0x000001d8 190 191 /* SW2WBM R2 release address */ 192 #define HAL_WBM_RELEASE_RING_HP 0x00003018 193 194 /* WBM2SW R0 release address */ 195 #define HAL_WBM0_RELEASE_RING_BASE_LSB 0x00000910 196 #define HAL_WBM1_RELEASE_RING_BASE_LSB 0x00000968 197 198 /* WBM2SW R2 release address */ 199 #define HAL_WBM0_RELEASE_RING_HP 0x000030c0 200 #define HAL_WBM1_RELEASE_RING_HP 0x000030c8 201 202 /* TCL ring feild mask and offset */ 203 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 204 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 205 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 206 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1) 207 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3) 208 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4) 209 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5) 210 #define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6) 211 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16) 212 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0) 213 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0) 214 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 215 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 216 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(17) 217 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0) 218 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0) 219 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3) 220 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6) 221 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9) 222 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12) 223 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15) 224 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18) 225 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21) 226 227 /* REO ring feild mask and offset */ 228 #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 229 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 230 #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8) 231 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 232 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3) 233 #define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4) 234 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5) 235 #define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6) 236 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16) 237 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0) 238 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 239 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 240 #define HAL_REO1_GEN_ENABLE_FRAG_DST_RING GENMASK(25, 23) 241 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2) 242 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3) 243 244 /* CE ring bit field mask and shift */ 245 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0) 246 247 #define HAL_ADDR_LSB_REG_MASK 0xffffffff 248 249 #define HAL_ADDR_MSB_REG_SHIFT 32 250 251 /* WBM ring bit field mask and shift */ 252 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1) 253 #define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2) 254 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16) 255 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0) 256 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8) 257 258 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8) 259 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8) 260 261 #define BASE_ADDR_MATCH_TAG_VAL 0x5 262 263 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff 264 #define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE 0x000fffff 265 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff 266 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff 267 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 268 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff 269 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff 270 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 271 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff 272 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff 273 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 274 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x0000ffff 275 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff 276 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 277 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff 278 279 #define HAL_RX_DESC_SIZE (sizeof(struct hal_rx_desc)) 280 281 /* Add any other errors here and return them in 282 * ath11k_hal_rx_desc_get_err(). 283 */ 284 285 enum hal_srng_ring_id { 286 HAL_SRNG_RING_ID_REO2SW1 = 0, 287 HAL_SRNG_RING_ID_REO2SW2, 288 HAL_SRNG_RING_ID_REO2SW3, 289 HAL_SRNG_RING_ID_REO2SW4, 290 HAL_SRNG_RING_ID_REO2TCL, 291 HAL_SRNG_RING_ID_SW2REO, 292 293 HAL_SRNG_RING_ID_REO_CMD = 8, 294 HAL_SRNG_RING_ID_REO_STATUS, 295 296 HAL_SRNG_RING_ID_SW2TCL1 = 16, 297 HAL_SRNG_RING_ID_SW2TCL2, 298 HAL_SRNG_RING_ID_SW2TCL3, 299 HAL_SRNG_RING_ID_SW2TCL4, 300 301 HAL_SRNG_RING_ID_SW2TCL_CMD = 24, 302 HAL_SRNG_RING_ID_TCL_STATUS, 303 304 HAL_SRNG_RING_ID_CE0_SRC = 32, 305 HAL_SRNG_RING_ID_CE1_SRC, 306 HAL_SRNG_RING_ID_CE2_SRC, 307 HAL_SRNG_RING_ID_CE3_SRC, 308 HAL_SRNG_RING_ID_CE4_SRC, 309 HAL_SRNG_RING_ID_CE5_SRC, 310 HAL_SRNG_RING_ID_CE6_SRC, 311 HAL_SRNG_RING_ID_CE7_SRC, 312 HAL_SRNG_RING_ID_CE8_SRC, 313 HAL_SRNG_RING_ID_CE9_SRC, 314 HAL_SRNG_RING_ID_CE10_SRC, 315 HAL_SRNG_RING_ID_CE11_SRC, 316 317 HAL_SRNG_RING_ID_CE0_DST = 56, 318 HAL_SRNG_RING_ID_CE1_DST, 319 HAL_SRNG_RING_ID_CE2_DST, 320 HAL_SRNG_RING_ID_CE3_DST, 321 HAL_SRNG_RING_ID_CE4_DST, 322 HAL_SRNG_RING_ID_CE5_DST, 323 HAL_SRNG_RING_ID_CE6_DST, 324 HAL_SRNG_RING_ID_CE7_DST, 325 HAL_SRNG_RING_ID_CE8_DST, 326 HAL_SRNG_RING_ID_CE9_DST, 327 HAL_SRNG_RING_ID_CE10_DST, 328 HAL_SRNG_RING_ID_CE11_DST, 329 330 HAL_SRNG_RING_ID_CE0_DST_STATUS = 80, 331 HAL_SRNG_RING_ID_CE1_DST_STATUS, 332 HAL_SRNG_RING_ID_CE2_DST_STATUS, 333 HAL_SRNG_RING_ID_CE3_DST_STATUS, 334 HAL_SRNG_RING_ID_CE4_DST_STATUS, 335 HAL_SRNG_RING_ID_CE5_DST_STATUS, 336 HAL_SRNG_RING_ID_CE6_DST_STATUS, 337 HAL_SRNG_RING_ID_CE7_DST_STATUS, 338 HAL_SRNG_RING_ID_CE8_DST_STATUS, 339 HAL_SRNG_RING_ID_CE9_DST_STATUS, 340 HAL_SRNG_RING_ID_CE10_DST_STATUS, 341 HAL_SRNG_RING_ID_CE11_DST_STATUS, 342 343 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 104, 344 HAL_SRNG_RING_ID_WBM_SW_RELEASE, 345 HAL_SRNG_RING_ID_WBM2SW0_RELEASE, 346 HAL_SRNG_RING_ID_WBM2SW1_RELEASE, 347 HAL_SRNG_RING_ID_WBM2SW2_RELEASE, 348 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, 349 350 HAL_SRNG_RING_ID_UMAC_ID_END = 127, 351 HAL_SRNG_RING_ID_LMAC1_ID_START, 352 353 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF = HAL_SRNG_RING_ID_LMAC1_ID_START, 354 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF, 355 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA2_BUF, 356 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_STATBUF, 357 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 358 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 359 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 360 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 361 HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 362 363 HAL_SRNG_RING_ID_LMAC1_ID_END = 143 364 }; 365 366 /* SRNG registers are split into two groups R0 and R2 */ 367 #define HAL_SRNG_REG_GRP_R0 0 368 #define HAL_SRNG_REG_GRP_R2 1 369 #define HAL_SRNG_NUM_REG_GRP 2 370 371 #define HAL_SRNG_NUM_LMACS 3 372 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_RING_ID_REO2SW1 373 #define HAL_SRNG_RINGS_PER_LMAC (HAL_SRNG_RING_ID_LMAC1_ID_END - \ 374 HAL_SRNG_RING_ID_LMAC1_ID_START) 375 #define HAL_SRNG_NUM_LMAC_RINGS (HAL_SRNG_NUM_LMACS * HAL_SRNG_RINGS_PER_LMAC) 376 #define HAL_SRNG_RING_ID_MAX (HAL_SRNG_RING_ID_UMAC_ID_END + \ 377 HAL_SRNG_NUM_LMAC_RINGS) 378 379 enum hal_ring_type { 380 HAL_REO_DST, 381 HAL_REO_EXCEPTION, 382 HAL_REO_REINJECT, 383 HAL_REO_CMD, 384 HAL_REO_STATUS, 385 HAL_TCL_DATA, 386 HAL_TCL_CMD, 387 HAL_TCL_STATUS, 388 HAL_CE_SRC, 389 HAL_CE_DST, 390 HAL_CE_DST_STATUS, 391 HAL_WBM_IDLE_LINK, 392 HAL_SW2WBM_RELEASE, 393 HAL_WBM2SW_RELEASE, 394 HAL_RXDMA_BUF, 395 HAL_RXDMA_DST, 396 HAL_RXDMA_MONITOR_BUF, 397 HAL_RXDMA_MONITOR_STATUS, 398 HAL_RXDMA_MONITOR_DST, 399 HAL_RXDMA_MONITOR_DESC, 400 HAL_RXDMA_DIR_BUF, 401 HAL_MAX_RING_TYPES, 402 }; 403 404 #define HAL_RX_MAX_BA_WINDOW 256 405 406 #define HAL_DEFAULT_REO_TIMEOUT_USEC (40 * 1000) 407 408 /** 409 * enum hal_reo_cmd_type: Enum for REO command type 410 * @CMD_GET_QUEUE_STATS: Get REO queue status/stats 411 * @CMD_FLUSH_QUEUE: Flush all frames in REO queue 412 * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache 413 * @CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked 414 * earlier with a 'REO_FLUSH_CACHE' command 415 * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 416 * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings 417 */ 418 enum hal_reo_cmd_type { 419 HAL_REO_CMD_GET_QUEUE_STATS = 0, 420 HAL_REO_CMD_FLUSH_QUEUE = 1, 421 HAL_REO_CMD_FLUSH_CACHE = 2, 422 HAL_REO_CMD_UNBLOCK_CACHE = 3, 423 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4, 424 HAL_REO_CMD_UPDATE_RX_QUEUE = 5, 425 }; 426 427 /** 428 * enum hal_reo_cmd_status: Enum for execution status of REO command 429 * @HAL_REO_CMD_SUCCESS: Command has successfully executed 430 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue 431 * or cache was blocked 432 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to 433 * invalid queue desc 434 * @HAL_REO_CMD_RESOURCE_BLOCKED: 435 * @HAL_REO_CMD_DRAIN: 436 */ 437 enum hal_reo_cmd_status { 438 HAL_REO_CMD_SUCCESS = 0, 439 HAL_REO_CMD_BLOCKED = 1, 440 HAL_REO_CMD_FAILED = 2, 441 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 442 HAL_REO_CMD_DRAIN = 0xff, 443 }; 444 445 struct hal_wbm_idle_scatter_list { 446 dma_addr_t paddr; 447 struct hal_wbm_link_desc *vaddr; 448 }; 449 450 struct hal_srng_params { 451 dma_addr_t ring_base_paddr; 452 u32 *ring_base_vaddr; 453 int num_entries; 454 u32 intr_batch_cntr_thres_entries; 455 u32 intr_timer_thres_us; 456 u32 flags; 457 u32 max_buffer_len; 458 u32 low_threshold; 459 460 /* Add more params as needed */ 461 }; 462 463 enum hal_srng_dir { 464 HAL_SRNG_DIR_SRC, 465 HAL_SRNG_DIR_DST 466 }; 467 468 /* srng flags */ 469 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008 470 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010 471 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020 472 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000 473 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000 474 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000 475 476 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1) 477 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10) 478 479 /* Common SRNG ring structure for source and destination rings */ 480 struct hal_srng { 481 /* Unique SRNG ring ID */ 482 u8 ring_id; 483 484 /* Ring initialization done */ 485 u8 initialized; 486 487 /* Interrupt/MSI value assigned to this ring */ 488 int irq; 489 490 /* Physical base address of the ring */ 491 dma_addr_t ring_base_paddr; 492 493 /* Virtual base address of the ring */ 494 u32 *ring_base_vaddr; 495 496 /* Number of entries in ring */ 497 u32 num_entries; 498 499 /* Ring size */ 500 u32 ring_size; 501 502 /* Ring size mask */ 503 u32 ring_size_mask; 504 505 /* Size of ring entry */ 506 u32 entry_size; 507 508 /* Interrupt timer threshold - in micro seconds */ 509 u32 intr_timer_thres_us; 510 511 /* Interrupt batch counter threshold - in number of ring entries */ 512 u32 intr_batch_cntr_thres_entries; 513 514 /* MSI Address */ 515 dma_addr_t msi_addr; 516 517 /* MSI data */ 518 u32 msi_data; 519 520 /* Misc flags */ 521 u32 flags; 522 523 /* Lock for serializing ring index updates */ 524 spinlock_t lock; 525 526 /* Start offset of SRNG register groups for this ring 527 * TBD: See if this is required - register address can be derived 528 * from ring ID 529 */ 530 u32 hwreg_base[HAL_SRNG_NUM_REG_GRP]; 531 532 /* Source or Destination ring */ 533 enum hal_srng_dir ring_dir; 534 535 union { 536 struct { 537 /* SW tail pointer */ 538 u32 tp; 539 540 /* Shadow head pointer location to be updated by HW */ 541 volatile u32 *hp_addr; 542 543 /* Cached head pointer */ 544 u32 cached_hp; 545 546 /* Tail pointer location to be updated by SW - This 547 * will be a register address and need not be 548 * accessed through SW structure 549 */ 550 u32 *tp_addr; 551 552 /* Current SW loop cnt */ 553 u32 loop_cnt; 554 555 /* max transfer size */ 556 u16 max_buffer_length; 557 } dst_ring; 558 559 struct { 560 /* SW head pointer */ 561 u32 hp; 562 563 /* SW reap head pointer */ 564 u32 reap_hp; 565 566 /* Shadow tail pointer location to be updated by HW */ 567 u32 *tp_addr; 568 569 /* Cached tail pointer */ 570 u32 cached_tp; 571 572 /* Head pointer location to be updated by SW - This 573 * will be a register address and need not be accessed 574 * through SW structure 575 */ 576 u32 *hp_addr; 577 578 /* Low threshold - in number of ring entries */ 579 u32 low_threshold; 580 } src_ring; 581 } u; 582 }; 583 584 /* Interrupt mitigation - Batch threshold in terms of numer of frames */ 585 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 586 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 587 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 588 589 /* Interrupt mitigation - timer threshold in us */ 590 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000 591 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500 592 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 1000 593 594 /* HW SRNG configuration table */ 595 struct hal_srng_config { 596 int start_ring_id; 597 u16 max_rings; 598 u16 entry_size; 599 u32 reg_start[HAL_SRNG_NUM_REG_GRP]; 600 u16 reg_size[HAL_SRNG_NUM_REG_GRP]; 601 u8 lmac_ring; 602 enum hal_srng_dir ring_dir; 603 u32 max_size; 604 }; 605 606 /** 607 * enum hal_rx_buf_return_buf_manager 608 * 609 * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 610 * @HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 611 * descriptor list. 612 * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 613 * @HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 614 * @HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 615 * @HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 616 * @HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 617 */ 618 619 enum hal_rx_buf_return_buf_manager { 620 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST, 621 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST, 622 HAL_RX_BUF_RBM_FW_BM, 623 HAL_RX_BUF_RBM_SW0_BM, 624 HAL_RX_BUF_RBM_SW1_BM, 625 HAL_RX_BUF_RBM_SW2_BM, 626 HAL_RX_BUF_RBM_SW3_BM, 627 }; 628 629 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000 630 631 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0) 632 #define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1) 633 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2) 634 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3) 635 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4) 636 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5) 637 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6) 638 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7) 639 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8) 640 641 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* feilds */ 642 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8) 643 #define HAL_REO_CMD_UPD0_VLD BIT(9) 644 #define HAL_REO_CMD_UPD0_ALDC BIT(10) 645 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11) 646 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12) 647 #define HAL_REO_CMD_UPD0_AC BIT(13) 648 #define HAL_REO_CMD_UPD0_BAR BIT(14) 649 #define HAL_REO_CMD_UPD0_RETRY BIT(15) 650 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16) 651 #define HAL_REO_CMD_UPD0_OOR_MODE BIT(17) 652 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18) 653 #define HAL_REO_CMD_UPD0_PN_CHECK BIT(19) 654 #define HAL_REO_CMD_UPD0_EVEN_PN BIT(20) 655 #define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21) 656 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22) 657 #define HAL_REO_CMD_UPD0_PN_SIZE BIT(23) 658 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24) 659 #define HAL_REO_CMD_UPD0_SVLD BIT(25) 660 #define HAL_REO_CMD_UPD0_SSN BIT(26) 661 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27) 662 #define HAL_REO_CMD_UPD0_PN_ERR BIT(28) 663 #define HAL_REO_CMD_UPD0_PN_VALID BIT(29) 664 #define HAL_REO_CMD_UPD0_PN BIT(30) 665 666 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* feilds */ 667 #define HAL_REO_CMD_UPD1_VLD BIT(16) 668 #define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17) 669 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19) 670 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20) 671 #define HAL_REO_CMD_UPD1_AC GENMASK(22, 21) 672 #define HAL_REO_CMD_UPD1_BAR BIT(23) 673 #define HAL_REO_CMD_UPD1_RETRY BIT(24) 674 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25) 675 #define HAL_REO_CMD_UPD1_OOR_MODE BIT(26) 676 #define HAL_REO_CMD_UPD1_PN_CHECK BIT(27) 677 #define HAL_REO_CMD_UPD1_EVEN_PN BIT(28) 678 #define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29) 679 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30) 680 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31) 681 682 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* feilds */ 683 #define HAL_REO_CMD_UPD2_SVLD BIT(10) 684 #define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11) 685 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23) 686 #define HAL_REO_CMD_UPD2_PN_ERR BIT(24) 687 688 #define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP GENMASK(31, 8) 689 690 struct ath11k_hal_reo_cmd { 691 u32 addr_lo; 692 u32 flag; 693 u32 upd0; 694 u32 upd1; 695 u32 upd2; 696 u32 pn[4]; 697 u16 rx_queue_num; 698 u16 min_rel; 699 u16 min_fwd; 700 u8 addr_hi; 701 u8 ac_list; 702 u8 blocking_idx; 703 u16 ba_window_size; 704 u8 pn_size; 705 }; 706 707 enum hal_pn_type { 708 HAL_PN_TYPE_NONE, 709 HAL_PN_TYPE_WPA, 710 HAL_PN_TYPE_WAPI_EVEN, 711 HAL_PN_TYPE_WAPI_UNEVEN, 712 }; 713 714 enum hal_ce_desc { 715 HAL_CE_DESC_SRC, 716 HAL_CE_DESC_DST, 717 HAL_CE_DESC_DST_STATUS, 718 }; 719 720 struct hal_reo_status_header { 721 u16 cmd_num; 722 enum hal_reo_cmd_status cmd_status; 723 u16 cmd_exe_time; 724 u32 timestamp; 725 }; 726 727 struct hal_reo_status_queue_stats { 728 u16 ssn; 729 u16 curr_idx; 730 u32 pn[4]; 731 u32 last_rx_queue_ts; 732 u32 last_rx_dequeue_ts; 733 u32 rx_bitmap[8]; /* Bitmap from 0-255 */ 734 u32 curr_mpdu_cnt; 735 u32 curr_msdu_cnt; 736 u16 fwd_due_to_bar_cnt; 737 u16 dup_cnt; 738 u32 frames_in_order_cnt; 739 u32 num_mpdu_processed_cnt; 740 u32 num_msdu_processed_cnt; 741 u32 total_num_processed_byte_cnt; 742 u32 late_rx_mpdu_cnt; 743 u32 reorder_hole_cnt; 744 u8 timeout_cnt; 745 u8 bar_rx_cnt; 746 u8 num_window_2k_jump_cnt; 747 }; 748 749 struct hal_reo_status_flush_queue { 750 bool err_detected; 751 }; 752 753 enum hal_reo_status_flush_cache_err_code { 754 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS, 755 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE, 756 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND, 757 }; 758 759 struct hal_reo_status_flush_cache { 760 bool err_detected; 761 enum hal_reo_status_flush_cache_err_code err_code; 762 bool cache_controller_flush_status_hit; 763 u8 cache_controller_flush_status_desc_type; 764 u8 cache_controller_flush_status_client_id; 765 u8 cache_controller_flush_status_err; 766 u8 cache_controller_flush_status_cnt; 767 }; 768 769 enum hal_reo_status_unblock_cache_type { 770 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE, 771 HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE, 772 }; 773 774 struct hal_reo_status_unblock_cache { 775 bool err_detected; 776 enum hal_reo_status_unblock_cache_type unblock_type; 777 }; 778 779 struct hal_reo_status_flush_timeout_list { 780 bool err_detected; 781 bool list_empty; 782 u16 release_desc_cnt; 783 u16 fwd_buf_cnt; 784 }; 785 786 enum hal_reo_threshold_idx { 787 HAL_REO_THRESHOLD_IDX_DESC_COUNTER0, 788 HAL_REO_THRESHOLD_IDX_DESC_COUNTER1, 789 HAL_REO_THRESHOLD_IDX_DESC_COUNTER2, 790 HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM, 791 }; 792 793 struct hal_reo_status_desc_thresh_reached { 794 enum hal_reo_threshold_idx threshold_idx; 795 u32 link_desc_counter0; 796 u32 link_desc_counter1; 797 u32 link_desc_counter2; 798 u32 link_desc_counter_sum; 799 }; 800 801 struct hal_reo_status { 802 struct hal_reo_status_header uniform_hdr; 803 u8 loop_cnt; 804 union { 805 struct hal_reo_status_queue_stats queue_stats; 806 struct hal_reo_status_flush_queue flush_queue; 807 struct hal_reo_status_flush_cache flush_cache; 808 struct hal_reo_status_unblock_cache unblock_cache; 809 struct hal_reo_status_flush_timeout_list timeout_list; 810 struct hal_reo_status_desc_thresh_reached desc_thresh_reached; 811 } u; 812 }; 813 814 /** 815 * HAL context to be used to access SRNG APIs (currently used by data path 816 * and transport (CE) modules) 817 */ 818 struct ath11k_hal { 819 /* HAL internal state for all SRNG rings. 820 */ 821 struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX]; 822 823 /* SRNG configuration table */ 824 const struct hal_srng_config *srng_config; 825 826 /* Remote pointer memory for HW/FW updates */ 827 struct { 828 u32 *vaddr; 829 dma_addr_t paddr; 830 } rdp; 831 832 /* Shared memory for ring pointer updates from host to FW */ 833 struct { 834 u32 *vaddr; 835 dma_addr_t paddr; 836 } wrp; 837 838 /* Available REO blocking resources bitmap */ 839 u8 avail_blk_resource; 840 841 u8 current_blk_index; 842 843 /* shadow register configuration */ 844 u32 shadow_reg_addr[SHADOW_NUM_REGISTERS]; 845 int num_shadow_reg_configured; 846 }; 847 848 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid); 849 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size, 850 u32 start_seqtype); 851 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab, 852 struct hal_srng *srng); 853 void ath11k_hal_reo_hw_setup(struct ath11k_base *ab); 854 void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab, 855 struct hal_wbm_idle_scatter_list *sbuf, 856 u32 nsbufs, u32 tot_link_desc, 857 u32 end_offset); 858 859 dma_addr_t ath11k_hal_srng_get_tp_addr(struct ath11k_base *ab, 860 struct hal_srng *srng); 861 dma_addr_t ath11k_hal_srng_get_hp_addr(struct ath11k_base *ab, 862 struct hal_srng *srng); 863 void ath11k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie, 864 dma_addr_t paddr); 865 u32 ath11k_hal_ce_get_desc_size(enum hal_ce_desc type); 866 void ath11k_hal_ce_src_set_desc(void *buf, dma_addr_t paddr, u32 len, u32 id, 867 u8 byte_swap_data); 868 void ath11k_hal_ce_dst_set_desc(void *buf, dma_addr_t paddr); 869 u32 ath11k_hal_ce_dst_status_get_length(void *buf); 870 int ath11k_hal_srng_get_entrysize(u32 ring_type); 871 int ath11k_hal_srng_get_max_entries(u32 ring_type); 872 void ath11k_hal_srng_get_params(struct ath11k_base *ab, struct hal_srng *srng, 873 struct hal_srng_params *params); 874 u32 *ath11k_hal_srng_dst_get_next_entry(struct ath11k_base *ab, 875 struct hal_srng *srng); 876 u32 *ath11k_hal_srng_dst_peek(struct ath11k_base *ab, struct hal_srng *srng); 877 int ath11k_hal_srng_dst_num_free(struct ath11k_base *ab, struct hal_srng *srng, 878 bool sync_hw_ptr); 879 u32 *ath11k_hal_srng_src_peek(struct ath11k_base *ab, struct hal_srng *srng); 880 u32 *ath11k_hal_srng_src_get_next_reaped(struct ath11k_base *ab, 881 struct hal_srng *srng); 882 u32 *ath11k_hal_srng_src_reap_next(struct ath11k_base *ab, 883 struct hal_srng *srng); 884 u32 *ath11k_hal_srng_src_get_next_entry(struct ath11k_base *ab, 885 struct hal_srng *srng); 886 int ath11k_hal_srng_src_num_free(struct ath11k_base *ab, struct hal_srng *srng, 887 bool sync_hw_ptr); 888 void ath11k_hal_srng_access_begin(struct ath11k_base *ab, 889 struct hal_srng *srng); 890 void ath11k_hal_srng_access_end(struct ath11k_base *ab, struct hal_srng *srng); 891 int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type, 892 int ring_num, int mac_id, 893 struct hal_srng_params *params); 894 int ath11k_hal_srng_init(struct ath11k_base *ath11k); 895 void ath11k_hal_srng_deinit(struct ath11k_base *ath11k); 896 897 #endif 898