1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Ingenic SoCs NAND controller devicetree bindings
8
9maintainers:
10  - Paul Cercueil <paul@crapouillou.net>
11
12allOf:
13  - $ref: nand-controller.yaml#
14
15properties:
16  compatible:
17    enum:
18      - ingenic,jz4740-nand
19      - ingenic,jz4725b-nand
20      - ingenic,jz4780-nand
21
22  reg:
23    items:
24      - description: Bank number, offset and size of first attached NAND chip
25      - description: Bank number, offset and size of second attached NAND chip
26      - description: Bank number, offset and size of third attached NAND chip
27      - description: Bank number, offset and size of fourth attached NAND chip
28    minItems: 1
29
30  ecc-engine: true
31
32  partitions:
33    type: object
34    description:
35      Node containing description of fixed partitions.
36      See Documentation/devicetree/bindings/mtd/partition.txt
37
38patternProperties:
39  "^nand@[a-f0-9]$":
40    type: object
41    properties:
42      rb-gpios:
43        description: GPIO specifier for the busy pin.
44        maxItems: 1
45
46      wp-gpios:
47        description: GPIO specifier for the write-protect pin.
48        maxItems: 1
49
50required:
51  - compatible
52  - reg
53
54examples:
55  - |
56    #include <dt-bindings/clock/jz4780-cgu.h>
57    memory-controller@13410000 {
58      compatible = "ingenic,jz4780-nemc";
59      reg = <0x13410000 0x10000>;
60      #address-cells = <2>;
61      #size-cells = <1>;
62      ranges = <1 0 0x1b000000 0x1000000>,
63         <2 0 0x1a000000 0x1000000>,
64         <3 0 0x19000000 0x1000000>,
65         <4 0 0x18000000 0x1000000>,
66         <5 0 0x17000000 0x1000000>,
67         <6 0 0x16000000 0x1000000>;
68
69      clocks = <&cgu JZ4780_CLK_NEMC>;
70
71      nand-controller@1 {
72        compatible = "ingenic,jz4780-nand";
73        reg = <1 0 0x1000000>;
74
75        #address-cells = <1>;
76        #size-cells = <0>;
77
78        ecc-engine = <&bch>;
79
80        ingenic,nemc-tAS = <10>;
81        ingenic,nemc-tAH = <5>;
82        ingenic,nemc-tBP = <10>;
83        ingenic,nemc-tAW = <15>;
84        ingenic,nemc-tSTRV = <100>;
85
86        pinctrl-names = "default";
87        pinctrl-0 = <&pins_nemc>;
88
89        nand@1 {
90          reg = <1>;
91
92          nand-ecc-step-size = <1024>;
93          nand-ecc-strength = <24>;
94          nand-ecc-mode = "hw";
95          nand-on-flash-bbt;
96
97          pinctrl-names = "default";
98          pinctrl-0 = <&pins_nemc_cs1>;
99
100          partitions {
101            compatible = "fixed-partitions";
102            #address-cells = <2>;
103            #size-cells = <2>;
104
105            partition@0 {
106              label = "u-boot-spl";
107              reg = <0x0 0x0 0x0 0x800000>;
108            };
109
110            partition@800000 {
111              label = "u-boot";
112              reg = <0x0 0x800000 0x0 0x200000>;
113            };
114
115            partition@a00000 {
116              label = "u-boot-env";
117              reg = <0x0 0xa00000 0x0 0x200000>;
118            };
119
120            partition@c00000 {
121              label = "boot";
122              reg = <0x0 0xc00000 0x0 0x4000000>;
123            };
124
125            partition@4c00000 {
126              label = "system";
127              reg = <0x0 0x4c00000 0x1 0xfb400000>;
128            };
129          };
130        };
131      };
132    };
133