1# SPDX-License-Identifier: (GPL-2.0)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra30 SoC External Memory Controller
8
9maintainers:
10  - Dmitry Osipenko <digetx@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12  - Thierry Reding <thierry.reding@gmail.com>
13
14description: |
15  The EMC interfaces with the off-chip SDRAM to service the request stream
16  sent from Memory Controller. The EMC also has various performance-affecting
17  settings beyond the obvious SDRAM configuration parameters and initialization
18  settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
19  LPDDR3, and DDR3.
20
21properties:
22  compatible:
23    const: nvidia,tegra30-emc
24
25  reg:
26    maxItems: 1
27
28  clocks:
29    maxItems: 1
30
31  interrupts:
32    maxItems: 1
33
34  nvidia,memory-controller:
35    $ref: /schemas/types.yaml#/definitions/phandle
36    description:
37      Phandle of the Memory Controller node.
38
39patternProperties:
40  "^emc-timings-[0-9]+$":
41    type: object
42    properties:
43      nvidia,ram-code:
44        $ref: /schemas/types.yaml#/definitions/uint32
45        description:
46          Value of RAM_CODE this timing set is used for.
47
48    patternProperties:
49      "^timing-[0-9]+$":
50        type: object
51        properties:
52          clock-frequency:
53            description:
54              Memory clock rate in Hz.
55            minimum: 1000000
56            maximum: 900000000
57
58          nvidia,emc-auto-cal-interval:
59            description:
60              Pad calibration interval in microseconds.
61            $ref: /schemas/types.yaml#/definitions/uint32
62            minimum: 0
63            maximum: 2097151
64
65          nvidia,emc-mode-1:
66            $ref: /schemas/types.yaml#/definitions/uint32
67            description:
68              Mode Register 1.
69
70          nvidia,emc-mode-2:
71            $ref: /schemas/types.yaml#/definitions/uint32
72            description:
73              Mode Register 2.
74
75          nvidia,emc-mode-reset:
76            $ref: /schemas/types.yaml#/definitions/uint32
77            description:
78              Mode Register 0.
79
80          nvidia,emc-zcal-cnt-long:
81            description:
82              Number of EMC clocks to wait before issuing any commands after
83              sending ZCAL_MRW_CMD.
84            $ref: /schemas/types.yaml#/definitions/uint32
85            minimum: 0
86            maximum: 1023
87
88          nvidia,emc-cfg-dyn-self-ref:
89            type: boolean
90            description:
91              Dynamic self-refresh enabled.
92
93          nvidia,emc-cfg-periodic-qrst:
94            type: boolean
95            description:
96              FBIO "read" FIFO periodic resetting enabled.
97
98          nvidia,emc-configuration:
99            description:
100              EMC timing characterization data. These are the registers
101              (see section "18.13.2 EMC Registers" in the TRM) whose values
102              need to be specified, according to the board documentation.
103            $ref: /schemas/types.yaml#/definitions/uint32-array
104            items:
105              - description: EMC_RC
106              - description: EMC_RFC
107              - description: EMC_RAS
108              - description: EMC_RP
109              - description: EMC_R2W
110              - description: EMC_W2R
111              - description: EMC_R2P
112              - description: EMC_W2P
113              - description: EMC_RD_RCD
114              - description: EMC_WR_RCD
115              - description: EMC_RRD
116              - description: EMC_REXT
117              - description: EMC_WEXT
118              - description: EMC_WDV
119              - description: EMC_QUSE
120              - description: EMC_QRST
121              - description: EMC_QSAFE
122              - description: EMC_RDV
123              - description: EMC_REFRESH
124              - description: EMC_BURST_REFRESH_NUM
125              - description: EMC_PRE_REFRESH_REQ_CNT
126              - description: EMC_PDEX2WR
127              - description: EMC_PDEX2RD
128              - description: EMC_PCHG2PDEN
129              - description: EMC_ACT2PDEN
130              - description: EMC_AR2PDEN
131              - description: EMC_RW2PDEN
132              - description: EMC_TXSR
133              - description: EMC_TXSRDLL
134              - description: EMC_TCKE
135              - description: EMC_TFAW
136              - description: EMC_TRPAB
137              - description: EMC_TCLKSTABLE
138              - description: EMC_TCLKSTOP
139              - description: EMC_TREFBW
140              - description: EMC_QUSE_EXTRA
141              - description: EMC_FBIO_CFG6
142              - description: EMC_ODT_WRITE
143              - description: EMC_ODT_READ
144              - description: EMC_FBIO_CFG5
145              - description: EMC_CFG_DIG_DLL
146              - description: EMC_CFG_DIG_DLL_PERIOD
147              - description: EMC_DLL_XFORM_DQS0
148              - description: EMC_DLL_XFORM_DQS1
149              - description: EMC_DLL_XFORM_DQS2
150              - description: EMC_DLL_XFORM_DQS3
151              - description: EMC_DLL_XFORM_DQS4
152              - description: EMC_DLL_XFORM_DQS5
153              - description: EMC_DLL_XFORM_DQS6
154              - description: EMC_DLL_XFORM_DQS7
155              - description: EMC_DLL_XFORM_QUSE0
156              - description: EMC_DLL_XFORM_QUSE1
157              - description: EMC_DLL_XFORM_QUSE2
158              - description: EMC_DLL_XFORM_QUSE3
159              - description: EMC_DLL_XFORM_QUSE4
160              - description: EMC_DLL_XFORM_QUSE5
161              - description: EMC_DLL_XFORM_QUSE6
162              - description: EMC_DLL_XFORM_QUSE7
163              - description: EMC_DLI_TRIM_TXDQS0
164              - description: EMC_DLI_TRIM_TXDQS1
165              - description: EMC_DLI_TRIM_TXDQS2
166              - description: EMC_DLI_TRIM_TXDQS3
167              - description: EMC_DLI_TRIM_TXDQS4
168              - description: EMC_DLI_TRIM_TXDQS5
169              - description: EMC_DLI_TRIM_TXDQS6
170              - description: EMC_DLI_TRIM_TXDQS7
171              - description: EMC_DLL_XFORM_DQ0
172              - description: EMC_DLL_XFORM_DQ1
173              - description: EMC_DLL_XFORM_DQ2
174              - description: EMC_DLL_XFORM_DQ3
175              - description: EMC_XM2CMDPADCTRL
176              - description: EMC_XM2DQSPADCTRL2
177              - description: EMC_XM2DQPADCTRL2
178              - description: EMC_XM2CLKPADCTRL
179              - description: EMC_XM2COMPPADCTRL
180              - description: EMC_XM2VTTGENPADCTRL
181              - description: EMC_XM2VTTGENPADCTRL2
182              - description: EMC_XM2QUSEPADCTRL
183              - description: EMC_XM2DQSPADCTRL3
184              - description: EMC_CTT_TERM_CTRL
185              - description: EMC_ZCAL_INTERVAL
186              - description: EMC_ZCAL_WAIT_CNT
187              - description: EMC_MRS_WAIT_CNT
188              - description: EMC_AUTO_CAL_CONFIG
189              - description: EMC_CTT
190              - description: EMC_CTT_DURATION
191              - description: EMC_DYN_SELF_REF_CONTROL
192              - description: EMC_FBIO_SPARE
193              - description: EMC_CFG_RSV
194
195        required:
196          - clock-frequency
197          - nvidia,emc-auto-cal-interval
198          - nvidia,emc-mode-1
199          - nvidia,emc-mode-2
200          - nvidia,emc-mode-reset
201          - nvidia,emc-zcal-cnt-long
202          - nvidia,emc-configuration
203
204        additionalProperties: false
205
206    required:
207      - nvidia,ram-code
208
209    additionalProperties: false
210
211required:
212  - compatible
213  - reg
214  - interrupts
215  - clocks
216  - nvidia,memory-controller
217
218additionalProperties: false
219
220examples:
221  - |
222    external-memory-controller@7000f400 {
223        compatible = "nvidia,tegra30-emc";
224        reg = <0x7000f400 0x400>;
225        interrupts = <0 78 4>;
226        clocks = <&tegra_car 57>;
227
228        nvidia,memory-controller = <&mc>;
229
230        emc-timings-1 {
231            nvidia,ram-code = <1>;
232
233            timing-667000000 {
234                clock-frequency = <667000000>;
235
236                nvidia,emc-auto-cal-interval = <0x001fffff>;
237                nvidia,emc-mode-1 = <0x80100002>;
238                nvidia,emc-mode-2 = <0x80200018>;
239                nvidia,emc-mode-reset = <0x80000b71>;
240                nvidia,emc-zcal-cnt-long = <0x00000040>;
241                nvidia,emc-cfg-periodic-qrst;
242
243                nvidia,emc-configuration = <
244                    0x00000020 /* EMC_RC */
245                    0x0000006a /* EMC_RFC */
246                    0x00000017 /* EMC_RAS */
247                    0x00000007 /* EMC_RP */
248                    0x00000005 /* EMC_R2W */
249                    0x0000000c /* EMC_W2R */
250                    0x00000003 /* EMC_R2P */
251                    0x00000011 /* EMC_W2P */
252                    0x00000007 /* EMC_RD_RCD */
253                    0x00000007 /* EMC_WR_RCD */
254                    0x00000002 /* EMC_RRD */
255                    0x00000001 /* EMC_REXT */
256                    0x00000000 /* EMC_WEXT */
257                    0x00000007 /* EMC_WDV */
258                    0x0000000a /* EMC_QUSE */
259                    0x00000009 /* EMC_QRST */
260                    0x0000000b /* EMC_QSAFE */
261                    0x00000011 /* EMC_RDV */
262                    0x00001412 /* EMC_REFRESH */
263                    0x00000000 /* EMC_BURST_REFRESH_NUM */
264                    0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
265                    0x00000002 /* EMC_PDEX2WR */
266                    0x0000000e /* EMC_PDEX2RD */
267                    0x00000001 /* EMC_PCHG2PDEN */
268                    0x00000000 /* EMC_ACT2PDEN */
269                    0x0000000c /* EMC_AR2PDEN */
270                    0x00000016 /* EMC_RW2PDEN */
271                    0x00000072 /* EMC_TXSR */
272                    0x00000200 /* EMC_TXSRDLL */
273                    0x00000005 /* EMC_TCKE */
274                    0x00000015 /* EMC_TFAW */
275                    0x00000000 /* EMC_TRPAB */
276                    0x00000006 /* EMC_TCLKSTABLE */
277                    0x00000007 /* EMC_TCLKSTOP */
278                    0x00001453 /* EMC_TREFBW */
279                    0x0000000b /* EMC_QUSE_EXTRA */
280                    0x00000006 /* EMC_FBIO_CFG6 */
281                    0x00000000 /* EMC_ODT_WRITE */
282                    0x00000000 /* EMC_ODT_READ */
283                    0x00005088 /* EMC_FBIO_CFG5 */
284                    0xf00b0191 /* EMC_CFG_DIG_DLL */
285                    0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
286                    0x00000008 /* EMC_DLL_XFORM_DQS0 */
287                    0x00000008 /* EMC_DLL_XFORM_DQS1 */
288                    0x00000008 /* EMC_DLL_XFORM_DQS2 */
289                    0x00000008 /* EMC_DLL_XFORM_DQS3 */
290                    0x0000000a /* EMC_DLL_XFORM_DQS4 */
291                    0x0000000a /* EMC_DLL_XFORM_DQS5 */
292                    0x0000000a /* EMC_DLL_XFORM_DQS6 */
293                    0x0000000a /* EMC_DLL_XFORM_DQS7 */
294                    0x00018000 /* EMC_DLL_XFORM_QUSE0 */
295                    0x00018000 /* EMC_DLL_XFORM_QUSE1 */
296                    0x00018000 /* EMC_DLL_XFORM_QUSE2 */
297                    0x00018000 /* EMC_DLL_XFORM_QUSE3 */
298                    0x00000000 /* EMC_DLL_XFORM_QUSE4 */
299                    0x00000000 /* EMC_DLL_XFORM_QUSE5 */
300                    0x00000000 /* EMC_DLL_XFORM_QUSE6 */
301                    0x00000000 /* EMC_DLL_XFORM_QUSE7 */
302                    0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
303                    0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
304                    0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
305                    0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
306                    0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
307                    0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
308                    0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
309                    0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
310                    0x0000000a /* EMC_DLL_XFORM_DQ0 */
311                    0x0000000a /* EMC_DLL_XFORM_DQ1 */
312                    0x0000000a /* EMC_DLL_XFORM_DQ2 */
313                    0x0000000a /* EMC_DLL_XFORM_DQ3 */
314                    0x000002a0 /* EMC_XM2CMDPADCTRL */
315                    0x0800013d /* EMC_XM2DQSPADCTRL2 */
316                    0x22220000 /* EMC_XM2DQPADCTRL2 */
317                    0x77fff884 /* EMC_XM2CLKPADCTRL */
318                    0x01f1f501 /* EMC_XM2COMPPADCTRL */
319                    0x07077404 /* EMC_XM2VTTGENPADCTRL */
320                    0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
321                    0x080001e8 /* EMC_XM2QUSEPADCTRL */
322                    0x0c000021 /* EMC_XM2DQSPADCTRL3 */
323                    0x00000802 /* EMC_CTT_TERM_CTRL */
324                    0x00020000 /* EMC_ZCAL_INTERVAL */
325                    0x00000100 /* EMC_ZCAL_WAIT_CNT */
326                    0x0155000c /* EMC_MRS_WAIT_CNT */
327                    0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
328                    0x00000000 /* EMC_CTT */
329                    0x00000000 /* EMC_CTT_DURATION */
330                    0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
331                    0xe8000000 /* EMC_FBIO_SPARE */
332                    0xff00ff49 /* EMC_CFG_RSV */
333                >;
334            };
335        };
336    };
337