1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * nct7904.c - driver for Nuvoton NCT7904D. 4 * 5 * Copyright (c) 2015 Kontron 6 * Author: Vadim V. Vlasov <vvlasov@dev.rtsoft.ru> 7 * 8 * Copyright (c) 2019 Advantech 9 * Author: Amy.Shih <amy.shih@advantech.com.tw> 10 * 11 * Supports the following chips: 12 * 13 * Chip #vin #fan #pwm #temp #dts chip ID 14 * nct7904d 20 12 4 5 8 0xc5 15 */ 16 17 #include <linux/module.h> 18 #include <linux/device.h> 19 #include <linux/init.h> 20 #include <linux/i2c.h> 21 #include <linux/mutex.h> 22 #include <linux/hwmon.h> 23 24 #define VENDOR_ID_REG 0x7A /* Any bank */ 25 #define NUVOTON_ID 0x50 26 #define CHIP_ID_REG 0x7B /* Any bank */ 27 #define NCT7904_ID 0xC5 28 #define DEVICE_ID_REG 0x7C /* Any bank */ 29 30 #define BANK_SEL_REG 0xFF 31 #define BANK_0 0x00 32 #define BANK_1 0x01 33 #define BANK_2 0x02 34 #define BANK_3 0x03 35 #define BANK_4 0x04 36 #define BANK_MAX 0x04 37 38 #define FANIN_MAX 12 /* Counted from 1 */ 39 #define VSEN_MAX 21 /* VSEN1..14, 3VDD, VBAT, V3VSB, 40 LTD (not a voltage), VSEN17..19 */ 41 #define FANCTL_MAX 4 /* Counted from 1 */ 42 #define TCPU_MAX 8 /* Counted from 1 */ 43 #define TEMP_MAX 4 /* Counted from 1 */ 44 45 #define VT_ADC_CTRL0_REG 0x20 /* Bank 0 */ 46 #define VT_ADC_CTRL1_REG 0x21 /* Bank 0 */ 47 #define VT_ADC_CTRL2_REG 0x22 /* Bank 0 */ 48 #define FANIN_CTRL0_REG 0x24 49 #define FANIN_CTRL1_REG 0x25 50 #define DTS_T_CTRL0_REG 0x26 51 #define DTS_T_CTRL1_REG 0x27 52 #define VT_ADC_MD_REG 0x2E 53 54 #define VSEN1_HV_LL_REG 0x02 /* Bank 1; 2 regs (HV/LV) per sensor */ 55 #define VSEN1_LV_LL_REG 0x03 /* Bank 1; 2 regs (HV/LV) per sensor */ 56 #define VSEN1_HV_HL_REG 0x00 /* Bank 1; 2 regs (HV/LV) per sensor */ 57 #define VSEN1_LV_HL_REG 0x01 /* Bank 1; 2 regs (HV/LV) per sensor */ 58 #define SMI_STS1_REG 0xC1 /* Bank 0; SMI Status Register */ 59 #define SMI_STS3_REG 0xC3 /* Bank 0; SMI Status Register */ 60 #define SMI_STS5_REG 0xC5 /* Bank 0; SMI Status Register */ 61 #define SMI_STS7_REG 0xC7 /* Bank 0; SMI Status Register */ 62 #define SMI_STS8_REG 0xC8 /* Bank 0; SMI Status Register */ 63 64 #define VSEN1_HV_REG 0x40 /* Bank 0; 2 regs (HV/LV) per sensor */ 65 #define TEMP_CH1_HV_REG 0x42 /* Bank 0; same as VSEN2_HV */ 66 #define LTD_HV_REG 0x62 /* Bank 0; 2 regs in VSEN range */ 67 #define LTD_HV_HL_REG 0x44 /* Bank 1; 1 reg for LTD */ 68 #define LTD_LV_HL_REG 0x45 /* Bank 1; 1 reg for LTD */ 69 #define LTD_HV_LL_REG 0x46 /* Bank 1; 1 reg for LTD */ 70 #define LTD_LV_LL_REG 0x47 /* Bank 1; 1 reg for LTD */ 71 #define TEMP_CH1_CH_REG 0x05 /* Bank 1; 1 reg for LTD */ 72 #define TEMP_CH1_W_REG 0x06 /* Bank 1; 1 reg for LTD */ 73 #define TEMP_CH1_WH_REG 0x07 /* Bank 1; 1 reg for LTD */ 74 #define TEMP_CH1_C_REG 0x04 /* Bank 1; 1 reg per sensor */ 75 #define DTS_T_CPU1_C_REG 0x90 /* Bank 1; 1 reg per sensor */ 76 #define DTS_T_CPU1_CH_REG 0x91 /* Bank 1; 1 reg per sensor */ 77 #define DTS_T_CPU1_W_REG 0x92 /* Bank 1; 1 reg per sensor */ 78 #define DTS_T_CPU1_WH_REG 0x93 /* Bank 1; 1 reg per sensor */ 79 #define FANIN1_HV_REG 0x80 /* Bank 0; 2 regs (HV/LV) per sensor */ 80 #define FANIN1_HV_HL_REG 0x60 /* Bank 1; 2 regs (HV/LV) per sensor */ 81 #define FANIN1_LV_HL_REG 0x61 /* Bank 1; 2 regs (HV/LV) per sensor */ 82 #define T_CPU1_HV_REG 0xA0 /* Bank 0; 2 regs (HV/LV) per sensor */ 83 84 #define PRTS_REG 0x03 /* Bank 2 */ 85 #define PFE_REG 0x00 /* Bank 2; PECI Function Enable */ 86 #define TSI_CTRL_REG 0x50 /* Bank 2; TSI Control Register */ 87 #define FANCTL1_FMR_REG 0x00 /* Bank 3; 1 reg per channel */ 88 #define FANCTL1_OUT_REG 0x10 /* Bank 3; 1 reg per channel */ 89 90 #define VOLT_MONITOR_MODE 0x0 91 #define THERMAL_DIODE_MODE 0x1 92 #define THERMISTOR_MODE 0x3 93 94 #define ENABLE_TSI BIT(1) 95 96 static const unsigned short normal_i2c[] = { 97 0x2d, 0x2e, I2C_CLIENT_END 98 }; 99 100 struct nct7904_data { 101 struct i2c_client *client; 102 struct mutex bank_lock; 103 int bank_sel; 104 u32 fanin_mask; 105 u32 vsen_mask; 106 u32 tcpu_mask; 107 u8 fan_mode[FANCTL_MAX]; 108 u8 enable_dts; 109 u8 has_dts; 110 u8 temp_mode; /* 0: TR mode, 1: TD mode */ 111 u8 fan_alarm[2]; 112 u8 vsen_alarm[3]; 113 }; 114 115 /* Access functions */ 116 static int nct7904_bank_lock(struct nct7904_data *data, unsigned int bank) 117 { 118 int ret; 119 120 mutex_lock(&data->bank_lock); 121 if (data->bank_sel == bank) 122 return 0; 123 ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank); 124 if (ret == 0) 125 data->bank_sel = bank; 126 else 127 data->bank_sel = -1; 128 return ret; 129 } 130 131 static inline void nct7904_bank_release(struct nct7904_data *data) 132 { 133 mutex_unlock(&data->bank_lock); 134 } 135 136 /* Read 1-byte register. Returns unsigned reg or -ERRNO on error. */ 137 static int nct7904_read_reg(struct nct7904_data *data, 138 unsigned int bank, unsigned int reg) 139 { 140 struct i2c_client *client = data->client; 141 int ret; 142 143 ret = nct7904_bank_lock(data, bank); 144 if (ret == 0) 145 ret = i2c_smbus_read_byte_data(client, reg); 146 147 nct7904_bank_release(data); 148 return ret; 149 } 150 151 /* 152 * Read 2-byte register. Returns register in big-endian format or 153 * -ERRNO on error. 154 */ 155 static int nct7904_read_reg16(struct nct7904_data *data, 156 unsigned int bank, unsigned int reg) 157 { 158 struct i2c_client *client = data->client; 159 int ret, hi; 160 161 ret = nct7904_bank_lock(data, bank); 162 if (ret == 0) { 163 ret = i2c_smbus_read_byte_data(client, reg); 164 if (ret >= 0) { 165 hi = ret; 166 ret = i2c_smbus_read_byte_data(client, reg + 1); 167 if (ret >= 0) 168 ret |= hi << 8; 169 } 170 } 171 172 nct7904_bank_release(data); 173 return ret; 174 } 175 176 /* Write 1-byte register. Returns 0 or -ERRNO on error. */ 177 static int nct7904_write_reg(struct nct7904_data *data, 178 unsigned int bank, unsigned int reg, u8 val) 179 { 180 struct i2c_client *client = data->client; 181 int ret; 182 183 ret = nct7904_bank_lock(data, bank); 184 if (ret == 0) 185 ret = i2c_smbus_write_byte_data(client, reg, val); 186 187 nct7904_bank_release(data); 188 return ret; 189 } 190 191 static int nct7904_read_fan(struct device *dev, u32 attr, int channel, 192 long *val) 193 { 194 struct nct7904_data *data = dev_get_drvdata(dev); 195 unsigned int cnt, rpm; 196 int ret; 197 198 switch (attr) { 199 case hwmon_fan_input: 200 ret = nct7904_read_reg16(data, BANK_0, 201 FANIN1_HV_REG + channel * 2); 202 if (ret < 0) 203 return ret; 204 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f); 205 if (cnt == 0x1fff) 206 rpm = 0; 207 else 208 rpm = 1350000 / cnt; 209 *val = rpm; 210 return 0; 211 case hwmon_fan_min: 212 ret = nct7904_read_reg16(data, BANK_1, 213 FANIN1_HV_HL_REG + channel * 2); 214 if (ret < 0) 215 return ret; 216 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f); 217 if (cnt == 0x1fff) 218 rpm = 0; 219 else 220 rpm = 1350000 / cnt; 221 *val = rpm; 222 return 0; 223 case hwmon_fan_alarm: 224 ret = nct7904_read_reg(data, BANK_0, 225 SMI_STS5_REG + (channel >> 3)); 226 if (ret < 0) 227 return ret; 228 if (!data->fan_alarm[channel >> 3]) 229 data->fan_alarm[channel >> 3] = ret & 0xff; 230 else 231 /* If there is new alarm showing up */ 232 data->fan_alarm[channel >> 3] |= (ret & 0xff); 233 *val = (data->fan_alarm[channel >> 3] >> (channel & 0x07)) & 1; 234 /* Needs to clean the alarm if alarm existing */ 235 if (*val) 236 data->fan_alarm[channel >> 3] ^= 1 << (channel & 0x07); 237 return 0; 238 default: 239 return -EOPNOTSUPP; 240 } 241 } 242 243 static umode_t nct7904_fan_is_visible(const void *_data, u32 attr, int channel) 244 { 245 const struct nct7904_data *data = _data; 246 247 switch (attr) { 248 case hwmon_fan_input: 249 case hwmon_fan_alarm: 250 if (data->fanin_mask & (1 << channel)) 251 return 0444; 252 break; 253 case hwmon_fan_min: 254 if (data->fanin_mask & (1 << channel)) 255 return 0644; 256 break; 257 default: 258 break; 259 } 260 261 return 0; 262 } 263 264 static u8 nct7904_chan_to_index[] = { 265 0, /* Not used */ 266 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 267 18, 19, 20, 16 268 }; 269 270 static int nct7904_read_in(struct device *dev, u32 attr, int channel, 271 long *val) 272 { 273 struct nct7904_data *data = dev_get_drvdata(dev); 274 int ret, volt, index; 275 276 index = nct7904_chan_to_index[channel]; 277 278 switch (attr) { 279 case hwmon_in_input: 280 ret = nct7904_read_reg16(data, BANK_0, 281 VSEN1_HV_REG + index * 2); 282 if (ret < 0) 283 return ret; 284 volt = ((ret & 0xff00) >> 5) | (ret & 0x7); 285 if (index < 14) 286 volt *= 2; /* 0.002V scale */ 287 else 288 volt *= 6; /* 0.006V scale */ 289 *val = volt; 290 return 0; 291 case hwmon_in_min: 292 ret = nct7904_read_reg16(data, BANK_1, 293 VSEN1_HV_LL_REG + index * 4); 294 if (ret < 0) 295 return ret; 296 volt = ((ret & 0xff00) >> 5) | (ret & 0x7); 297 if (index < 14) 298 volt *= 2; /* 0.002V scale */ 299 else 300 volt *= 6; /* 0.006V scale */ 301 *val = volt; 302 return 0; 303 case hwmon_in_max: 304 ret = nct7904_read_reg16(data, BANK_1, 305 VSEN1_HV_HL_REG + index * 4); 306 if (ret < 0) 307 return ret; 308 volt = ((ret & 0xff00) >> 5) | (ret & 0x7); 309 if (index < 14) 310 volt *= 2; /* 0.002V scale */ 311 else 312 volt *= 6; /* 0.006V scale */ 313 *val = volt; 314 return 0; 315 case hwmon_in_alarm: 316 ret = nct7904_read_reg(data, BANK_0, 317 SMI_STS1_REG + (index >> 3)); 318 if (ret < 0) 319 return ret; 320 if (!data->vsen_alarm[index >> 3]) 321 data->vsen_alarm[index >> 3] = ret & 0xff; 322 else 323 /* If there is new alarm showing up */ 324 data->vsen_alarm[index >> 3] |= (ret & 0xff); 325 *val = (data->vsen_alarm[index >> 3] >> (index & 0x07)) & 1; 326 /* Needs to clean the alarm if alarm existing */ 327 if (*val) 328 data->vsen_alarm[index >> 3] ^= 1 << (index & 0x07); 329 return 0; 330 default: 331 return -EOPNOTSUPP; 332 } 333 } 334 335 static umode_t nct7904_in_is_visible(const void *_data, u32 attr, int channel) 336 { 337 const struct nct7904_data *data = _data; 338 int index = nct7904_chan_to_index[channel]; 339 340 switch (attr) { 341 case hwmon_in_input: 342 case hwmon_in_alarm: 343 if (channel > 0 && (data->vsen_mask & BIT(index))) 344 return 0444; 345 break; 346 case hwmon_in_min: 347 case hwmon_in_max: 348 if (channel > 0 && (data->vsen_mask & BIT(index))) 349 return 0644; 350 break; 351 default: 352 break; 353 } 354 355 return 0; 356 } 357 358 static int nct7904_read_temp(struct device *dev, u32 attr, int channel, 359 long *val) 360 { 361 struct nct7904_data *data = dev_get_drvdata(dev); 362 int ret, temp; 363 unsigned int reg1, reg2, reg3; 364 365 switch (attr) { 366 case hwmon_temp_input: 367 if (channel == 4) 368 ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG); 369 else if (channel < 5) 370 ret = nct7904_read_reg16(data, BANK_0, 371 TEMP_CH1_HV_REG + channel * 4); 372 else 373 ret = nct7904_read_reg16(data, BANK_0, 374 T_CPU1_HV_REG + (channel - 5) 375 * 2); 376 if (ret < 0) 377 return ret; 378 temp = ((ret & 0xff00) >> 5) | (ret & 0x7); 379 *val = sign_extend32(temp, 10) * 125; 380 return 0; 381 case hwmon_temp_alarm: 382 if (channel == 4) { 383 ret = nct7904_read_reg(data, BANK_0, 384 SMI_STS3_REG); 385 if (ret < 0) 386 return ret; 387 *val = (ret >> 1) & 1; 388 } else if (channel < 4) { 389 ret = nct7904_read_reg(data, BANK_0, 390 SMI_STS1_REG); 391 if (ret < 0) 392 return ret; 393 *val = (ret >> (((channel * 2) + 1) & 0x07)) & 1; 394 } else { 395 if ((channel - 5) < 4) { 396 ret = nct7904_read_reg(data, BANK_0, 397 SMI_STS7_REG + 398 ((channel - 5) >> 3)); 399 if (ret < 0) 400 return ret; 401 *val = (ret >> ((channel - 5) & 0x07)) & 1; 402 } else { 403 ret = nct7904_read_reg(data, BANK_0, 404 SMI_STS8_REG + 405 ((channel - 5) >> 3)); 406 if (ret < 0) 407 return ret; 408 *val = (ret >> (((channel - 5) & 0x07) - 4)) 409 & 1; 410 } 411 } 412 return 0; 413 case hwmon_temp_type: 414 if (channel < 5) { 415 if ((data->tcpu_mask >> channel) & 0x01) { 416 if ((data->temp_mode >> channel) & 0x01) 417 *val = 3; /* TD */ 418 else 419 *val = 4; /* TR */ 420 } else { 421 *val = 0; 422 } 423 } else { 424 if ((data->has_dts >> (channel - 5)) & 0x01) { 425 if (data->enable_dts & ENABLE_TSI) 426 *val = 5; /* TSI */ 427 else 428 *val = 6; /* PECI */ 429 } else { 430 *val = 0; 431 } 432 } 433 return 0; 434 case hwmon_temp_max: 435 reg1 = LTD_HV_LL_REG; 436 reg2 = TEMP_CH1_W_REG; 437 reg3 = DTS_T_CPU1_W_REG; 438 break; 439 case hwmon_temp_max_hyst: 440 reg1 = LTD_LV_LL_REG; 441 reg2 = TEMP_CH1_WH_REG; 442 reg3 = DTS_T_CPU1_WH_REG; 443 break; 444 case hwmon_temp_crit: 445 reg1 = LTD_HV_HL_REG; 446 reg2 = TEMP_CH1_C_REG; 447 reg3 = DTS_T_CPU1_C_REG; 448 break; 449 case hwmon_temp_crit_hyst: 450 reg1 = LTD_LV_HL_REG; 451 reg2 = TEMP_CH1_CH_REG; 452 reg3 = DTS_T_CPU1_CH_REG; 453 break; 454 default: 455 return -EOPNOTSUPP; 456 } 457 458 if (channel == 4) 459 ret = nct7904_read_reg(data, BANK_1, reg1); 460 else if (channel < 5) 461 ret = nct7904_read_reg(data, BANK_1, 462 reg2 + channel * 8); 463 else 464 ret = nct7904_read_reg(data, BANK_1, 465 reg3 + (channel - 5) * 4); 466 467 if (ret < 0) 468 return ret; 469 *val = ret * 1000; 470 return 0; 471 } 472 473 static umode_t nct7904_temp_is_visible(const void *_data, u32 attr, int channel) 474 { 475 const struct nct7904_data *data = _data; 476 477 switch (attr) { 478 case hwmon_temp_input: 479 case hwmon_temp_alarm: 480 case hwmon_temp_type: 481 if (channel < 5) { 482 if (data->tcpu_mask & BIT(channel)) 483 return 0444; 484 } else { 485 if (data->has_dts & BIT(channel - 5)) 486 return 0444; 487 } 488 break; 489 case hwmon_temp_max: 490 case hwmon_temp_max_hyst: 491 case hwmon_temp_crit: 492 case hwmon_temp_crit_hyst: 493 if (channel < 5) { 494 if (data->tcpu_mask & BIT(channel)) 495 return 0644; 496 } else { 497 if (data->has_dts & BIT(channel - 5)) 498 return 0644; 499 } 500 break; 501 default: 502 break; 503 } 504 505 return 0; 506 } 507 508 static int nct7904_read_pwm(struct device *dev, u32 attr, int channel, 509 long *val) 510 { 511 struct nct7904_data *data = dev_get_drvdata(dev); 512 int ret; 513 514 switch (attr) { 515 case hwmon_pwm_input: 516 ret = nct7904_read_reg(data, BANK_3, FANCTL1_OUT_REG + channel); 517 if (ret < 0) 518 return ret; 519 *val = ret; 520 return 0; 521 case hwmon_pwm_enable: 522 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + channel); 523 if (ret < 0) 524 return ret; 525 526 *val = ret ? 2 : 1; 527 return 0; 528 default: 529 return -EOPNOTSUPP; 530 } 531 } 532 533 static int nct7904_write_temp(struct device *dev, u32 attr, int channel, 534 long val) 535 { 536 struct nct7904_data *data = dev_get_drvdata(dev); 537 int ret; 538 unsigned int reg1, reg2, reg3; 539 540 val = clamp_val(val / 1000, -128, 127); 541 542 switch (attr) { 543 case hwmon_temp_max: 544 reg1 = LTD_HV_LL_REG; 545 reg2 = TEMP_CH1_W_REG; 546 reg3 = DTS_T_CPU1_W_REG; 547 break; 548 case hwmon_temp_max_hyst: 549 reg1 = LTD_LV_LL_REG; 550 reg2 = TEMP_CH1_WH_REG; 551 reg3 = DTS_T_CPU1_WH_REG; 552 break; 553 case hwmon_temp_crit: 554 reg1 = LTD_HV_HL_REG; 555 reg2 = TEMP_CH1_C_REG; 556 reg3 = DTS_T_CPU1_C_REG; 557 break; 558 case hwmon_temp_crit_hyst: 559 reg1 = LTD_LV_HL_REG; 560 reg2 = TEMP_CH1_CH_REG; 561 reg3 = DTS_T_CPU1_CH_REG; 562 break; 563 default: 564 return -EOPNOTSUPP; 565 } 566 if (channel == 4) 567 ret = nct7904_write_reg(data, BANK_1, reg1, val); 568 else if (channel < 5) 569 ret = nct7904_write_reg(data, BANK_1, 570 reg2 + channel * 8, val); 571 else 572 ret = nct7904_write_reg(data, BANK_1, 573 reg3 + (channel - 5) * 4, val); 574 575 return ret; 576 } 577 578 static int nct7904_write_fan(struct device *dev, u32 attr, int channel, 579 long val) 580 { 581 struct nct7904_data *data = dev_get_drvdata(dev); 582 int ret; 583 u8 tmp; 584 585 switch (attr) { 586 case hwmon_fan_min: 587 if (val <= 0) 588 return -EINVAL; 589 590 val = clamp_val(DIV_ROUND_CLOSEST(1350000, val), 1, 0x1fff); 591 tmp = (val >> 5) & 0xff; 592 ret = nct7904_write_reg(data, BANK_1, 593 FANIN1_HV_HL_REG + channel * 2, tmp); 594 if (ret < 0) 595 return ret; 596 tmp = val & 0x1f; 597 ret = nct7904_write_reg(data, BANK_1, 598 FANIN1_LV_HL_REG + channel * 2, tmp); 599 return ret; 600 default: 601 return -EOPNOTSUPP; 602 } 603 } 604 605 static int nct7904_write_in(struct device *dev, u32 attr, int channel, 606 long val) 607 { 608 struct nct7904_data *data = dev_get_drvdata(dev); 609 int ret, index, tmp; 610 611 index = nct7904_chan_to_index[channel]; 612 613 if (index < 14) 614 val = val / 2; /* 0.002V scale */ 615 else 616 val = val / 6; /* 0.006V scale */ 617 618 val = clamp_val(val, 0, 0x7ff); 619 620 switch (attr) { 621 case hwmon_in_min: 622 tmp = nct7904_read_reg(data, BANK_1, 623 VSEN1_LV_LL_REG + index * 4); 624 if (tmp < 0) 625 return tmp; 626 tmp &= ~0x7; 627 tmp |= val & 0x7; 628 ret = nct7904_write_reg(data, BANK_1, 629 VSEN1_LV_LL_REG + index * 4, tmp); 630 if (ret < 0) 631 return ret; 632 tmp = nct7904_read_reg(data, BANK_1, 633 VSEN1_HV_LL_REG + index * 4); 634 if (tmp < 0) 635 return tmp; 636 tmp = (val >> 3) & 0xff; 637 ret = nct7904_write_reg(data, BANK_1, 638 VSEN1_HV_LL_REG + index * 4, tmp); 639 return ret; 640 case hwmon_in_max: 641 tmp = nct7904_read_reg(data, BANK_1, 642 VSEN1_LV_HL_REG + index * 4); 643 if (tmp < 0) 644 return tmp; 645 tmp &= ~0x7; 646 tmp |= val & 0x7; 647 ret = nct7904_write_reg(data, BANK_1, 648 VSEN1_LV_HL_REG + index * 4, tmp); 649 if (ret < 0) 650 return ret; 651 tmp = nct7904_read_reg(data, BANK_1, 652 VSEN1_HV_HL_REG + index * 4); 653 if (tmp < 0) 654 return tmp; 655 tmp = (val >> 3) & 0xff; 656 ret = nct7904_write_reg(data, BANK_1, 657 VSEN1_HV_HL_REG + index * 4, tmp); 658 return ret; 659 default: 660 return -EOPNOTSUPP; 661 } 662 } 663 664 static int nct7904_write_pwm(struct device *dev, u32 attr, int channel, 665 long val) 666 { 667 struct nct7904_data *data = dev_get_drvdata(dev); 668 int ret; 669 670 switch (attr) { 671 case hwmon_pwm_input: 672 if (val < 0 || val > 255) 673 return -EINVAL; 674 ret = nct7904_write_reg(data, BANK_3, FANCTL1_OUT_REG + channel, 675 val); 676 return ret; 677 case hwmon_pwm_enable: 678 if (val < 1 || val > 2 || 679 (val == 2 && !data->fan_mode[channel])) 680 return -EINVAL; 681 ret = nct7904_write_reg(data, BANK_3, FANCTL1_FMR_REG + channel, 682 val == 2 ? data->fan_mode[channel] : 0); 683 return ret; 684 default: 685 return -EOPNOTSUPP; 686 } 687 } 688 689 static umode_t nct7904_pwm_is_visible(const void *_data, u32 attr, int channel) 690 { 691 switch (attr) { 692 case hwmon_pwm_input: 693 case hwmon_pwm_enable: 694 return 0644; 695 default: 696 return 0; 697 } 698 } 699 700 static int nct7904_read(struct device *dev, enum hwmon_sensor_types type, 701 u32 attr, int channel, long *val) 702 { 703 switch (type) { 704 case hwmon_in: 705 return nct7904_read_in(dev, attr, channel, val); 706 case hwmon_fan: 707 return nct7904_read_fan(dev, attr, channel, val); 708 case hwmon_pwm: 709 return nct7904_read_pwm(dev, attr, channel, val); 710 case hwmon_temp: 711 return nct7904_read_temp(dev, attr, channel, val); 712 default: 713 return -EOPNOTSUPP; 714 } 715 } 716 717 static int nct7904_write(struct device *dev, enum hwmon_sensor_types type, 718 u32 attr, int channel, long val) 719 { 720 switch (type) { 721 case hwmon_in: 722 return nct7904_write_in(dev, attr, channel, val); 723 case hwmon_fan: 724 return nct7904_write_fan(dev, attr, channel, val); 725 case hwmon_pwm: 726 return nct7904_write_pwm(dev, attr, channel, val); 727 case hwmon_temp: 728 return nct7904_write_temp(dev, attr, channel, val); 729 default: 730 return -EOPNOTSUPP; 731 } 732 } 733 734 static umode_t nct7904_is_visible(const void *data, 735 enum hwmon_sensor_types type, 736 u32 attr, int channel) 737 { 738 switch (type) { 739 case hwmon_in: 740 return nct7904_in_is_visible(data, attr, channel); 741 case hwmon_fan: 742 return nct7904_fan_is_visible(data, attr, channel); 743 case hwmon_pwm: 744 return nct7904_pwm_is_visible(data, attr, channel); 745 case hwmon_temp: 746 return nct7904_temp_is_visible(data, attr, channel); 747 default: 748 return 0; 749 } 750 } 751 752 /* Return 0 if detection is successful, -ENODEV otherwise */ 753 static int nct7904_detect(struct i2c_client *client, 754 struct i2c_board_info *info) 755 { 756 struct i2c_adapter *adapter = client->adapter; 757 758 if (!i2c_check_functionality(adapter, 759 I2C_FUNC_SMBUS_READ_BYTE | 760 I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) 761 return -ENODEV; 762 763 /* Determine the chip type. */ 764 if (i2c_smbus_read_byte_data(client, VENDOR_ID_REG) != NUVOTON_ID || 765 i2c_smbus_read_byte_data(client, CHIP_ID_REG) != NCT7904_ID || 766 (i2c_smbus_read_byte_data(client, DEVICE_ID_REG) & 0xf0) != 0x50 || 767 (i2c_smbus_read_byte_data(client, BANK_SEL_REG) & 0xf8) != 0x00) 768 return -ENODEV; 769 770 strlcpy(info->type, "nct7904", I2C_NAME_SIZE); 771 772 return 0; 773 } 774 775 static const struct hwmon_channel_info *nct7904_info[] = { 776 HWMON_CHANNEL_INFO(in, 777 /* dummy, skipped in is_visible */ 778 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 779 HWMON_I_ALARM, 780 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 781 HWMON_I_ALARM, 782 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 783 HWMON_I_ALARM, 784 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 785 HWMON_I_ALARM, 786 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 787 HWMON_I_ALARM, 788 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 789 HWMON_I_ALARM, 790 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 791 HWMON_I_ALARM, 792 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 793 HWMON_I_ALARM, 794 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 795 HWMON_I_ALARM, 796 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 797 HWMON_I_ALARM, 798 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 799 HWMON_I_ALARM, 800 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 801 HWMON_I_ALARM, 802 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 803 HWMON_I_ALARM, 804 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 805 HWMON_I_ALARM, 806 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 807 HWMON_I_ALARM, 808 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 809 HWMON_I_ALARM, 810 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 811 HWMON_I_ALARM, 812 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 813 HWMON_I_ALARM, 814 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 815 HWMON_I_ALARM, 816 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 817 HWMON_I_ALARM, 818 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 819 HWMON_I_ALARM), 820 HWMON_CHANNEL_INFO(fan, 821 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 822 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 823 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 824 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 825 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 826 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 827 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 828 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 829 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 830 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 831 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 832 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM), 833 HWMON_CHANNEL_INFO(pwm, 834 HWMON_PWM_INPUT | HWMON_PWM_ENABLE, 835 HWMON_PWM_INPUT | HWMON_PWM_ENABLE, 836 HWMON_PWM_INPUT | HWMON_PWM_ENABLE, 837 HWMON_PWM_INPUT | HWMON_PWM_ENABLE), 838 HWMON_CHANNEL_INFO(temp, 839 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 840 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 841 HWMON_T_CRIT_HYST, 842 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 843 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 844 HWMON_T_CRIT_HYST, 845 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 846 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 847 HWMON_T_CRIT_HYST, 848 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 849 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 850 HWMON_T_CRIT_HYST, 851 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 852 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 853 HWMON_T_CRIT_HYST, 854 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 855 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 856 HWMON_T_CRIT_HYST, 857 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 858 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 859 HWMON_T_CRIT_HYST, 860 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 861 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 862 HWMON_T_CRIT_HYST, 863 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 864 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 865 HWMON_T_CRIT_HYST, 866 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 867 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 868 HWMON_T_CRIT_HYST, 869 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 870 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 871 HWMON_T_CRIT_HYST, 872 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 873 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 874 HWMON_T_CRIT_HYST, 875 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 876 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 877 HWMON_T_CRIT_HYST), 878 NULL 879 }; 880 881 static const struct hwmon_ops nct7904_hwmon_ops = { 882 .is_visible = nct7904_is_visible, 883 .read = nct7904_read, 884 .write = nct7904_write, 885 }; 886 887 static const struct hwmon_chip_info nct7904_chip_info = { 888 .ops = &nct7904_hwmon_ops, 889 .info = nct7904_info, 890 }; 891 892 static int nct7904_probe(struct i2c_client *client, 893 const struct i2c_device_id *id) 894 { 895 struct nct7904_data *data; 896 struct device *hwmon_dev; 897 struct device *dev = &client->dev; 898 int ret, i; 899 u32 mask; 900 u8 val, bit; 901 902 data = devm_kzalloc(dev, sizeof(struct nct7904_data), GFP_KERNEL); 903 if (!data) 904 return -ENOMEM; 905 906 data->client = client; 907 mutex_init(&data->bank_lock); 908 data->bank_sel = -1; 909 910 /* Setup sensor groups. */ 911 /* FANIN attributes */ 912 ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG); 913 if (ret < 0) 914 return ret; 915 data->fanin_mask = (ret >> 8) | ((ret & 0xff) << 8); 916 917 /* 918 * VSEN attributes 919 * 920 * Note: voltage sensors overlap with external temperature 921 * sensors. So, if we ever decide to support the latter 922 * we will have to adjust 'vsen_mask' accordingly. 923 */ 924 mask = 0; 925 ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG); 926 if (ret >= 0) 927 mask = (ret >> 8) | ((ret & 0xff) << 8); 928 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG); 929 if (ret >= 0) 930 mask |= (ret << 16); 931 data->vsen_mask = mask; 932 933 /* CPU_TEMP attributes */ 934 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG); 935 if (ret < 0) 936 return ret; 937 938 if ((ret & 0x6) == 0x6) 939 data->tcpu_mask |= 1; /* TR1 */ 940 if ((ret & 0x18) == 0x18) 941 data->tcpu_mask |= 2; /* TR2 */ 942 if ((ret & 0x20) == 0x20) 943 data->tcpu_mask |= 4; /* TR3 */ 944 if ((ret & 0x80) == 0x80) 945 data->tcpu_mask |= 8; /* TR4 */ 946 947 /* LTD */ 948 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG); 949 if (ret < 0) 950 return ret; 951 if ((ret & 0x02) == 0x02) 952 data->tcpu_mask |= 0x10; 953 954 /* Multi-Function detecting for Volt and TR/TD */ 955 ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG); 956 if (ret < 0) 957 return ret; 958 959 data->temp_mode = 0; 960 for (i = 0; i < 4; i++) { 961 val = (ret >> (i * 2)) & 0x03; 962 bit = (1 << i); 963 if (val == VOLT_MONITOR_MODE) { 964 data->tcpu_mask &= ~bit; 965 } else if (val == THERMAL_DIODE_MODE && i < 2) { 966 data->temp_mode |= bit; 967 data->vsen_mask &= ~(0x06 << (i * 2)); 968 } else if (val == THERMISTOR_MODE) { 969 data->vsen_mask &= ~(0x02 << (i * 2)); 970 } else { 971 /* Reserved */ 972 data->tcpu_mask &= ~bit; 973 data->vsen_mask &= ~(0x06 << (i * 2)); 974 } 975 } 976 977 /* PECI */ 978 ret = nct7904_read_reg(data, BANK_2, PFE_REG); 979 if (ret < 0) 980 return ret; 981 if (ret & 0x80) { 982 data->enable_dts = 1; /* Enable DTS & PECI */ 983 } else { 984 ret = nct7904_read_reg(data, BANK_2, TSI_CTRL_REG); 985 if (ret < 0) 986 return ret; 987 if (ret & 0x80) 988 data->enable_dts = 0x3; /* Enable DTS & TSI */ 989 } 990 991 /* Check DTS enable status */ 992 if (data->enable_dts) { 993 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG); 994 if (ret < 0) 995 return ret; 996 data->has_dts = ret & 0xF; 997 if (data->enable_dts & ENABLE_TSI) { 998 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG); 999 if (ret < 0) 1000 return ret; 1001 data->has_dts |= (ret & 0xF) << 4; 1002 } 1003 } 1004 1005 for (i = 0; i < FANCTL_MAX; i++) { 1006 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + i); 1007 if (ret < 0) 1008 return ret; 1009 data->fan_mode[i] = ret; 1010 } 1011 1012 hwmon_dev = 1013 devm_hwmon_device_register_with_info(dev, client->name, data, 1014 &nct7904_chip_info, NULL); 1015 return PTR_ERR_OR_ZERO(hwmon_dev); 1016 } 1017 1018 static const struct i2c_device_id nct7904_id[] = { 1019 {"nct7904", 0}, 1020 {} 1021 }; 1022 MODULE_DEVICE_TABLE(i2c, nct7904_id); 1023 1024 static struct i2c_driver nct7904_driver = { 1025 .class = I2C_CLASS_HWMON, 1026 .driver = { 1027 .name = "nct7904", 1028 }, 1029 .probe = nct7904_probe, 1030 .id_table = nct7904_id, 1031 .detect = nct7904_detect, 1032 .address_list = normal_i2c, 1033 }; 1034 1035 module_i2c_driver(nct7904_driver); 1036 1037 MODULE_AUTHOR("Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>"); 1038 MODULE_DESCRIPTION("Hwmon driver for NUVOTON NCT7904"); 1039 MODULE_LICENSE("GPL"); 1040