1 /* 2 * Copyright © 2006-2019 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DISPLAY_H_ 26 #define _INTEL_DISPLAY_H_ 27 28 #include <drm/drm_util.h> 29 30 enum link_m_n_set; 31 struct dpll; 32 struct drm_connector; 33 struct drm_device; 34 struct drm_display_mode; 35 struct drm_encoder; 36 struct drm_file; 37 struct drm_format_info; 38 struct drm_framebuffer; 39 struct drm_i915_error_state_buf; 40 struct drm_i915_gem_object; 41 struct drm_i915_private; 42 struct drm_mode_fb_cmd2; 43 struct drm_modeset_acquire_ctx; 44 struct drm_plane; 45 struct drm_plane_state; 46 struct i915_ggtt_view; 47 struct intel_atomic_state; 48 struct intel_crtc; 49 struct intel_crtc_state; 50 struct intel_crtc_state; 51 struct intel_digital_port; 52 struct intel_dp; 53 struct intel_encoder; 54 struct intel_load_detect_pipe; 55 struct intel_plane; 56 struct intel_plane_state; 57 struct intel_remapped_info; 58 struct intel_rotation_info; 59 60 enum i915_gpio { 61 GPIOA, 62 GPIOB, 63 GPIOC, 64 GPIOD, 65 GPIOE, 66 GPIOF, 67 GPIOG, 68 GPIOH, 69 __GPIOI_UNUSED, 70 GPIOJ, 71 GPIOK, 72 GPIOL, 73 GPIOM, 74 GPION, 75 GPIOO, 76 }; 77 78 /* 79 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the 80 * rest have consecutive values and match the enum values of transcoders 81 * with a 1:1 transcoder -> pipe mapping. 82 */ 83 enum pipe { 84 INVALID_PIPE = -1, 85 86 PIPE_A = 0, 87 PIPE_B, 88 PIPE_C, 89 PIPE_D, 90 _PIPE_EDP, 91 92 I915_MAX_PIPES = _PIPE_EDP 93 }; 94 95 #define pipe_name(p) ((p) + 'A') 96 97 enum transcoder { 98 INVALID_TRANSCODER = -1, 99 /* 100 * The following transcoders have a 1:1 transcoder -> pipe mapping, 101 * keep their values fixed: the code assumes that TRANSCODER_A=0, the 102 * rest have consecutive values and match the enum values of the pipes 103 * they map to. 104 */ 105 TRANSCODER_A = PIPE_A, 106 TRANSCODER_B = PIPE_B, 107 TRANSCODER_C = PIPE_C, 108 TRANSCODER_D = PIPE_D, 109 110 /* 111 * The following transcoders can map to any pipe, their enum value 112 * doesn't need to stay fixed. 113 */ 114 TRANSCODER_EDP, 115 TRANSCODER_DSI_0, 116 TRANSCODER_DSI_1, 117 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ 118 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ 119 120 I915_MAX_TRANSCODERS 121 }; 122 123 static inline const char *transcoder_name(enum transcoder transcoder) 124 { 125 switch (transcoder) { 126 case TRANSCODER_A: 127 return "A"; 128 case TRANSCODER_B: 129 return "B"; 130 case TRANSCODER_C: 131 return "C"; 132 case TRANSCODER_D: 133 return "D"; 134 case TRANSCODER_EDP: 135 return "EDP"; 136 case TRANSCODER_DSI_A: 137 return "DSI A"; 138 case TRANSCODER_DSI_C: 139 return "DSI C"; 140 default: 141 return "<invalid>"; 142 } 143 } 144 145 static inline bool transcoder_is_dsi(enum transcoder transcoder) 146 { 147 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; 148 } 149 150 /* 151 * Global legacy plane identifier. Valid only for primary/sprite 152 * planes on pre-g4x, and only for primary planes on g4x-bdw. 153 */ 154 enum i9xx_plane_id { 155 PLANE_A, 156 PLANE_B, 157 PLANE_C, 158 }; 159 160 #define plane_name(p) ((p) + 'A') 161 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') 162 163 /* 164 * Per-pipe plane identifier. 165 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 166 * number of planes per CRTC. Not all platforms really have this many planes, 167 * which means some arrays of size I915_MAX_PLANES may have unused entries 168 * between the topmost sprite plane and the cursor plane. 169 * 170 * This is expected to be passed to various register macros 171 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. 172 */ 173 enum plane_id { 174 PLANE_PRIMARY, 175 PLANE_SPRITE0, 176 PLANE_SPRITE1, 177 PLANE_SPRITE2, 178 PLANE_SPRITE3, 179 PLANE_SPRITE4, 180 PLANE_SPRITE5, 181 PLANE_CURSOR, 182 183 I915_MAX_PLANES, 184 }; 185 186 #define for_each_plane_id_on_crtc(__crtc, __p) \ 187 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ 188 for_each_if((__crtc)->plane_ids_mask & BIT(__p)) 189 190 enum port { 191 PORT_NONE = -1, 192 193 PORT_A = 0, 194 PORT_B, 195 PORT_C, 196 PORT_D, 197 PORT_E, 198 PORT_F, 199 PORT_G, 200 PORT_H, 201 PORT_I, 202 203 I915_MAX_PORTS 204 }; 205 206 #define port_name(p) ((p) + 'A') 207 208 /* 209 * Ports identifier referenced from other drivers. 210 * Expected to remain stable over time 211 */ 212 static inline const char *port_identifier(enum port port) 213 { 214 switch (port) { 215 case PORT_A: 216 return "Port A"; 217 case PORT_B: 218 return "Port B"; 219 case PORT_C: 220 return "Port C"; 221 case PORT_D: 222 return "Port D"; 223 case PORT_E: 224 return "Port E"; 225 case PORT_F: 226 return "Port F"; 227 case PORT_G: 228 return "Port G"; 229 case PORT_H: 230 return "Port H"; 231 case PORT_I: 232 return "Port I"; 233 default: 234 return "<invalid>"; 235 } 236 } 237 238 enum tc_port { 239 PORT_TC_NONE = -1, 240 241 PORT_TC1 = 0, 242 PORT_TC2, 243 PORT_TC3, 244 PORT_TC4, 245 PORT_TC5, 246 PORT_TC6, 247 248 I915_MAX_TC_PORTS 249 }; 250 251 enum tc_port_mode { 252 TC_PORT_TBT_ALT, 253 TC_PORT_DP_ALT, 254 TC_PORT_LEGACY, 255 }; 256 257 enum dpio_channel { 258 DPIO_CH0, 259 DPIO_CH1 260 }; 261 262 enum dpio_phy { 263 DPIO_PHY0, 264 DPIO_PHY1, 265 DPIO_PHY2, 266 }; 267 268 #define I915_NUM_PHYS_VLV 2 269 270 enum aux_ch { 271 AUX_CH_A, 272 AUX_CH_B, 273 AUX_CH_C, 274 AUX_CH_D, 275 AUX_CH_E, /* ICL+ */ 276 AUX_CH_F, 277 AUX_CH_G, 278 }; 279 280 #define aux_ch_name(a) ((a) + 'A') 281 282 /* Used by dp and fdi links */ 283 struct intel_link_m_n { 284 u32 tu; 285 u32 gmch_m; 286 u32 gmch_n; 287 u32 link_m; 288 u32 link_n; 289 }; 290 291 enum phy { 292 PHY_NONE = -1, 293 294 PHY_A = 0, 295 PHY_B, 296 PHY_C, 297 PHY_D, 298 PHY_E, 299 PHY_F, 300 PHY_G, 301 PHY_H, 302 PHY_I, 303 304 I915_MAX_PHYS 305 }; 306 307 #define phy_name(a) ((a) + 'A') 308 309 enum phy_fia { 310 FIA1, 311 FIA2, 312 FIA3, 313 }; 314 315 #define for_each_pipe(__dev_priv, __p) \ 316 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ 317 for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p)) 318 319 #define for_each_pipe_masked(__dev_priv, __p, __mask) \ 320 for_each_pipe(__dev_priv, __p) \ 321 for_each_if((__mask) & BIT(__p)) 322 323 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ 324 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ 325 for_each_if ((__mask) & (1 << (__t))) 326 327 #define for_each_universal_plane(__dev_priv, __pipe, __p) \ 328 for ((__p) = 0; \ 329 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ 330 (__p)++) 331 332 #define for_each_sprite(__dev_priv, __p, __s) \ 333 for ((__s) = 0; \ 334 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ 335 (__s)++) 336 337 #define for_each_port(__port) \ 338 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) 339 340 #define for_each_port_masked(__port, __ports_mask) \ 341 for_each_port(__port) \ 342 for_each_if((__ports_mask) & BIT(__port)) 343 344 #define for_each_phy_masked(__phy, __phys_mask) \ 345 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 346 for_each_if((__phys_mask) & BIT(__phy)) 347 348 #define for_each_crtc(dev, crtc) \ 349 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 350 351 #define for_each_intel_plane(dev, intel_plane) \ 352 list_for_each_entry(intel_plane, \ 353 &(dev)->mode_config.plane_list, \ 354 base.head) 355 356 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ 357 list_for_each_entry(intel_plane, \ 358 &(dev)->mode_config.plane_list, \ 359 base.head) \ 360 for_each_if((plane_mask) & \ 361 drm_plane_mask(&intel_plane->base)) 362 363 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 364 list_for_each_entry(intel_plane, \ 365 &(dev)->mode_config.plane_list, \ 366 base.head) \ 367 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 368 369 #define for_each_intel_crtc(dev, intel_crtc) \ 370 list_for_each_entry(intel_crtc, \ 371 &(dev)->mode_config.crtc_list, \ 372 base.head) 373 374 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ 375 list_for_each_entry(intel_crtc, \ 376 &(dev)->mode_config.crtc_list, \ 377 base.head) \ 378 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base)) 379 380 #define for_each_intel_encoder(dev, intel_encoder) \ 381 list_for_each_entry(intel_encoder, \ 382 &(dev)->mode_config.encoder_list, \ 383 base.head) 384 385 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ 386 list_for_each_entry(intel_encoder, \ 387 &(dev)->mode_config.encoder_list, \ 388 base.head) \ 389 for_each_if((encoder_mask) & \ 390 drm_encoder_mask(&intel_encoder->base)) 391 392 #define for_each_intel_dp(dev, intel_encoder) \ 393 for_each_intel_encoder(dev, intel_encoder) \ 394 for_each_if(intel_encoder_is_dp(intel_encoder)) 395 396 #define for_each_intel_connector_iter(intel_connector, iter) \ 397 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) 398 399 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 400 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 401 for_each_if((intel_encoder)->base.crtc == (__crtc)) 402 403 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 404 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 405 for_each_if((intel_connector)->base.encoder == (__encoder)) 406 407 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ 408 for ((__i) = 0; \ 409 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 410 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 411 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ 412 (__i)++) \ 413 for_each_if(plane) 414 415 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 416 for ((__i) = 0; \ 417 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 418 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 419 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 420 (__i)++) \ 421 for_each_if(plane) 422 423 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 424 for ((__i) = 0; \ 425 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 426 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 427 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 428 (__i)++) \ 429 for_each_if(crtc) 430 431 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 432 for ((__i) = 0; \ 433 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ 434 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ 435 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ 436 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 437 (__i)++) \ 438 for_each_if(plane) 439 440 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 441 for ((__i) = 0; \ 442 (__i) < (__state)->base.dev->mode_config.num_crtc && \ 443 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 444 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 445 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 446 (__i)++) \ 447 for_each_if(crtc) 448 449 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 450 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 451 (__i) >= 0 && \ 452 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 453 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 454 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 455 (__i)--) \ 456 for_each_if(crtc) 457 458 #define intel_atomic_crtc_state_for_each_plane_state( \ 459 plane, plane_state, \ 460 crtc_state) \ 461 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ 462 ((crtc_state)->uapi.plane_mask)) \ 463 for_each_if ((plane_state = \ 464 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) 465 466 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ 467 for ((__i) = 0; \ 468 (__i) < (__state)->base.num_connector; \ 469 (__i)++) \ 470 for_each_if ((__state)->base.connectors[__i].ptr && \ 471 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ 472 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) 473 474 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 475 u8 active_pipes); 476 void intel_link_compute_m_n(u16 bpp, int nlanes, 477 int pixel_clock, int link_clock, 478 struct intel_link_m_n *m_n, 479 bool constant_n, bool fec_enable); 480 bool is_ccs_modifier(u64 modifier); 481 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane); 482 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); 483 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, 484 u32 pixel_format, u64 modifier); 485 bool intel_plane_can_remap(const struct intel_plane_state *plane_state); 486 enum drm_mode_status 487 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, 488 const struct drm_display_mode *mode); 489 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); 490 bool is_trans_port_sync_mode(const struct intel_crtc_state *state); 491 492 void intel_plane_destroy(struct drm_plane *plane); 493 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state); 494 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state); 495 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 496 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); 497 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); 498 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); 499 int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 500 const char *name, u32 reg, int ref_freq); 501 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, 502 const char *name, u32 reg); 503 void lpt_pch_enable(const struct intel_crtc_state *crtc_state); 504 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); 505 void lpt_disable_iclkip(struct drm_i915_private *dev_priv); 506 void intel_init_display_hooks(struct drm_i915_private *dev_priv); 507 unsigned int intel_fb_xy_to_linear(int x, int y, 508 const struct intel_plane_state *state, 509 int plane); 510 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, 511 int color_plane, unsigned int height); 512 void intel_add_fb_offsets(int *x, int *y, 513 const struct intel_plane_state *state, int plane); 514 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); 515 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); 516 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); 517 int intel_display_suspend(struct drm_device *dev); 518 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); 519 void intel_encoder_destroy(struct drm_encoder *encoder); 520 struct drm_display_mode * 521 intel_encoder_current_mode(struct intel_encoder *encoder); 522 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); 523 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); 524 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, 525 enum port port); 526 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 527 struct drm_file *file_priv); 528 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); 529 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state); 530 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state); 531 532 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); 533 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 534 struct intel_digital_port *dport, 535 unsigned int expected_mask); 536 int intel_get_load_detect_pipe(struct drm_connector *connector, 537 struct intel_load_detect_pipe *old, 538 struct drm_modeset_acquire_ctx *ctx); 539 void intel_release_load_detect_pipe(struct drm_connector *connector, 540 struct intel_load_detect_pipe *old, 541 struct drm_modeset_acquire_ctx *ctx); 542 struct i915_vma * 543 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, 544 const struct i915_ggtt_view *view, 545 bool uses_fence, 546 unsigned long *out_flags); 547 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags); 548 struct drm_framebuffer * 549 intel_framebuffer_create(struct drm_i915_gem_object *obj, 550 struct drm_mode_fb_cmd2 *mode_cmd); 551 int intel_prepare_plane_fb(struct drm_plane *plane, 552 struct drm_plane_state *new_state); 553 void intel_cleanup_plane_fb(struct drm_plane *plane, 554 struct drm_plane_state *old_state); 555 556 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, 557 enum pipe pipe); 558 559 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 560 const struct dpll *dpll); 561 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); 562 int lpt_get_iclkip(struct drm_i915_private *dev_priv); 563 bool intel_fuzzy_clock_check(int clock1, int clock2); 564 565 void intel_prepare_reset(struct drm_i915_private *dev_priv); 566 void intel_finish_reset(struct drm_i915_private *dev_priv); 567 void intel_dp_get_m_n(struct intel_crtc *crtc, 568 struct intel_crtc_state *pipe_config); 569 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, 570 enum link_m_n_set m_n); 571 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 572 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 573 struct dpll *best_clock); 574 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); 575 576 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); 577 void hsw_enable_ips(const struct intel_crtc_state *crtc_state); 578 void hsw_disable_ips(const struct intel_crtc_state *crtc_state); 579 enum intel_display_power_domain intel_port_to_power_domain(enum port port); 580 enum intel_display_power_domain 581 intel_aux_power_domain(struct intel_digital_port *dig_port); 582 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 583 struct intel_crtc_state *pipe_config); 584 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 585 struct intel_crtc_state *crtc_state); 586 587 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center); 588 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); 589 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); 590 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); 591 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, 592 const struct intel_plane_state *plane_state); 593 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state); 594 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 595 const struct intel_plane_state *plane_state); 596 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state); 597 u32 skl_plane_stride(const struct intel_plane_state *plane_state, 598 int plane); 599 int skl_check_plane_surface(struct intel_plane_state *plane_state); 600 int i9xx_check_plane_surface(struct intel_plane_state *plane_state); 601 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); 602 unsigned int i9xx_plane_max_stride(struct intel_plane *plane, 603 u32 pixel_format, u64 modifier, 604 unsigned int rotation); 605 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); 606 607 struct intel_display_error_state * 608 intel_display_capture_error_state(struct drm_i915_private *dev_priv); 609 void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 610 struct intel_display_error_state *error); 611 612 bool 613 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, 614 uint64_t modifier); 615 616 /* modesetting */ 617 void intel_modeset_init_hw(struct drm_i915_private *i915); 618 int intel_modeset_init_noirq(struct drm_i915_private *i915); 619 int intel_modeset_init(struct drm_i915_private *i915); 620 void intel_modeset_driver_remove(struct drm_i915_private *i915); 621 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915); 622 void intel_display_resume(struct drm_device *dev); 623 void intel_init_pch_refclk(struct drm_i915_private *dev_priv); 624 625 /* modesetting asserts */ 626 void assert_panel_unlocked(struct drm_i915_private *dev_priv, 627 enum pipe pipe); 628 void assert_pll(struct drm_i915_private *dev_priv, 629 enum pipe pipe, bool state); 630 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 631 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 632 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); 633 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) 634 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) 635 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 636 enum pipe pipe, bool state); 637 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) 638 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) 639 void assert_pipe(struct drm_i915_private *dev_priv, 640 enum transcoder cpu_transcoder, bool state); 641 #define assert_pipe_enabled(d, t) assert_pipe(d, t, true) 642 #define assert_pipe_disabled(d, t) assert_pipe(d, t, false) 643 644 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 645 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 646 * which may not necessarily be a user visible problem. This will either 647 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 648 * enable distros and users to tailor their preferred amount of i915 abrt 649 * spam. 650 */ 651 #define I915_STATE_WARN(condition, format...) ({ \ 652 int __ret_warn_on = !!(condition); \ 653 if (unlikely(__ret_warn_on)) \ 654 if (!WARN(i915_modparams.verbose_state_checks, format)) \ 655 DRM_ERROR(format); \ 656 unlikely(__ret_warn_on); \ 657 }) 658 659 #define I915_STATE_WARN_ON(x) \ 660 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") 661 662 #endif 663