1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12/ { 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie@1003000 { 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 22 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 23 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 38 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 39 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 40 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 41 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <4>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <1>; 85 }; 86 }; 87 88 host1x@50000000 { 89 compatible = "nvidia,tegra210-host1x", "simple-bus"; 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 94 clock-names = "host1x"; 95 resets = <&tegra_car 28>; 96 reset-names = "host1x"; 97 98 #address-cells = <2>; 99 #size-cells = <2>; 100 101 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 102 103 iommus = <&mc TEGRA_SWGROUP_HC>; 104 105 dpaux1: dpaux@54040000 { 106 compatible = "nvidia,tegra210-dpaux"; 107 reg = <0x0 0x54040000 0x0 0x00040000>; 108 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 109 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 110 <&tegra_car TEGRA210_CLK_PLL_DP>; 111 clock-names = "dpaux", "parent"; 112 resets = <&tegra_car 207>; 113 reset-names = "dpaux"; 114 power-domains = <&pd_sor>; 115 status = "disabled"; 116 117 state_dpaux1_aux: pinmux-aux { 118 groups = "dpaux-io"; 119 function = "aux"; 120 }; 121 122 state_dpaux1_i2c: pinmux-i2c { 123 groups = "dpaux-io"; 124 function = "i2c"; 125 }; 126 127 state_dpaux1_off: pinmux-off { 128 groups = "dpaux-io"; 129 function = "off"; 130 }; 131 132 i2c-bus { 133 #address-cells = <1>; 134 #size-cells = <0>; 135 }; 136 }; 137 138 vi@54080000 { 139 compatible = "nvidia,tegra210-vi"; 140 reg = <0x0 0x54080000 0x0 0x700>; 141 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 142 status = "disabled"; 143 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 144 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 145 146 clocks = <&tegra_car TEGRA210_CLK_VI>; 147 power-domains = <&pd_venc>; 148 149 #address-cells = <1>; 150 #size-cells = <1>; 151 152 ranges = <0x0 0x0 0x54080000 0x2000>; 153 154 csi@838 { 155 compatible = "nvidia,tegra210-csi"; 156 reg = <0x838 0x1300>; 157 status = "disabled"; 158 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 159 <&tegra_car TEGRA210_CLK_CILCD>, 160 <&tegra_car TEGRA210_CLK_CILE>, 161 <&tegra_car TEGRA210_CLK_CSI_TPG>; 162 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 163 <&tegra_car TEGRA210_CLK_PLL_P>, 164 <&tegra_car TEGRA210_CLK_PLL_P>; 165 assigned-clock-rates = <102000000>, 166 <102000000>, 167 <102000000>, 168 <972000000>; 169 170 clocks = <&tegra_car TEGRA210_CLK_CSI>, 171 <&tegra_car TEGRA210_CLK_CILAB>, 172 <&tegra_car TEGRA210_CLK_CILCD>, 173 <&tegra_car TEGRA210_CLK_CILE>, 174 <&tegra_car TEGRA210_CLK_CSI_TPG>; 175 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 176 power-domains = <&pd_sor>; 177 }; 178 }; 179 180 tsec@54100000 { 181 compatible = "nvidia,tegra210-tsec"; 182 reg = <0x0 0x54100000 0x0 0x00040000>; 183 }; 184 185 dc@54200000 { 186 compatible = "nvidia,tegra210-dc"; 187 reg = <0x0 0x54200000 0x0 0x00040000>; 188 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&tegra_car TEGRA210_CLK_DISP1>, 190 <&tegra_car TEGRA210_CLK_PLL_P>; 191 clock-names = "dc", "parent"; 192 resets = <&tegra_car 27>; 193 reset-names = "dc"; 194 195 iommus = <&mc TEGRA_SWGROUP_DC>; 196 197 nvidia,head = <0>; 198 }; 199 200 dc@54240000 { 201 compatible = "nvidia,tegra210-dc"; 202 reg = <0x0 0x54240000 0x0 0x00040000>; 203 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&tegra_car TEGRA210_CLK_DISP2>, 205 <&tegra_car TEGRA210_CLK_PLL_P>; 206 clock-names = "dc", "parent"; 207 resets = <&tegra_car 26>; 208 reset-names = "dc"; 209 210 iommus = <&mc TEGRA_SWGROUP_DCB>; 211 212 nvidia,head = <1>; 213 }; 214 215 dsi@54300000 { 216 compatible = "nvidia,tegra210-dsi"; 217 reg = <0x0 0x54300000 0x0 0x00040000>; 218 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 219 <&tegra_car TEGRA210_CLK_DSIALP>, 220 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 221 clock-names = "dsi", "lp", "parent"; 222 resets = <&tegra_car 48>; 223 reset-names = "dsi"; 224 power-domains = <&pd_sor>; 225 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 226 227 status = "disabled"; 228 229 #address-cells = <1>; 230 #size-cells = <0>; 231 }; 232 233 vic@54340000 { 234 compatible = "nvidia,tegra210-vic"; 235 reg = <0x0 0x54340000 0x0 0x00040000>; 236 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 238 clock-names = "vic"; 239 resets = <&tegra_car 178>; 240 reset-names = "vic"; 241 242 iommus = <&mc TEGRA_SWGROUP_VIC>; 243 power-domains = <&pd_vic>; 244 }; 245 246 nvjpg@54380000 { 247 compatible = "nvidia,tegra210-nvjpg"; 248 reg = <0x0 0x54380000 0x0 0x00040000>; 249 status = "disabled"; 250 }; 251 252 dsi@54400000 { 253 compatible = "nvidia,tegra210-dsi"; 254 reg = <0x0 0x54400000 0x0 0x00040000>; 255 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 256 <&tegra_car TEGRA210_CLK_DSIBLP>, 257 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 258 clock-names = "dsi", "lp", "parent"; 259 resets = <&tegra_car 82>; 260 reset-names = "dsi"; 261 power-domains = <&pd_sor>; 262 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 263 264 status = "disabled"; 265 266 #address-cells = <1>; 267 #size-cells = <0>; 268 }; 269 270 nvdec@54480000 { 271 compatible = "nvidia,tegra210-nvdec"; 272 reg = <0x0 0x54480000 0x0 0x00040000>; 273 status = "disabled"; 274 }; 275 276 nvenc@544c0000 { 277 compatible = "nvidia,tegra210-nvenc"; 278 reg = <0x0 0x544c0000 0x0 0x00040000>; 279 status = "disabled"; 280 }; 281 282 tsec@54500000 { 283 compatible = "nvidia,tegra210-tsec"; 284 reg = <0x0 0x54500000 0x0 0x00040000>; 285 status = "disabled"; 286 }; 287 288 sor@54540000 { 289 compatible = "nvidia,tegra210-sor"; 290 reg = <0x0 0x54540000 0x0 0x00040000>; 291 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 293 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 294 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 295 <&tegra_car TEGRA210_CLK_PLL_DP>, 296 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 297 clock-names = "sor", "out", "parent", "dp", "safe"; 298 resets = <&tegra_car 182>; 299 reset-names = "sor"; 300 pinctrl-0 = <&state_dpaux_aux>; 301 pinctrl-1 = <&state_dpaux_i2c>; 302 pinctrl-2 = <&state_dpaux_off>; 303 pinctrl-names = "aux", "i2c", "off"; 304 power-domains = <&pd_sor>; 305 status = "disabled"; 306 }; 307 308 sor@54580000 { 309 compatible = "nvidia,tegra210-sor1"; 310 reg = <0x0 0x54580000 0x0 0x00040000>; 311 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 313 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 314 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 315 <&tegra_car TEGRA210_CLK_PLL_DP>, 316 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 317 clock-names = "sor", "out", "parent", "dp", "safe"; 318 resets = <&tegra_car 183>; 319 reset-names = "sor"; 320 pinctrl-0 = <&state_dpaux1_aux>; 321 pinctrl-1 = <&state_dpaux1_i2c>; 322 pinctrl-2 = <&state_dpaux1_off>; 323 pinctrl-names = "aux", "i2c", "off"; 324 power-domains = <&pd_sor>; 325 status = "disabled"; 326 }; 327 328 dpaux: dpaux@545c0000 { 329 compatible = "nvidia,tegra124-dpaux"; 330 reg = <0x0 0x545c0000 0x0 0x00040000>; 331 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 333 <&tegra_car TEGRA210_CLK_PLL_DP>; 334 clock-names = "dpaux", "parent"; 335 resets = <&tegra_car 181>; 336 reset-names = "dpaux"; 337 power-domains = <&pd_sor>; 338 status = "disabled"; 339 340 state_dpaux_aux: pinmux-aux { 341 groups = "dpaux-io"; 342 function = "aux"; 343 }; 344 345 state_dpaux_i2c: pinmux-i2c { 346 groups = "dpaux-io"; 347 function = "i2c"; 348 }; 349 350 state_dpaux_off: pinmux-off { 351 groups = "dpaux-io"; 352 function = "off"; 353 }; 354 355 i2c-bus { 356 #address-cells = <1>; 357 #size-cells = <0>; 358 }; 359 }; 360 361 isp@54600000 { 362 compatible = "nvidia,tegra210-isp"; 363 reg = <0x0 0x54600000 0x0 0x00040000>; 364 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 365 status = "disabled"; 366 }; 367 368 isp@54680000 { 369 compatible = "nvidia,tegra210-isp"; 370 reg = <0x0 0x54680000 0x0 0x00040000>; 371 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 372 status = "disabled"; 373 }; 374 375 i2c@546c0000 { 376 compatible = "nvidia,tegra210-i2c-vi"; 377 reg = <0x0 0x546c0000 0x0 0x00040000>; 378 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 379 status = "disabled"; 380 }; 381 }; 382 383 gic: interrupt-controller@50041000 { 384 compatible = "arm,gic-400"; 385 #interrupt-cells = <3>; 386 interrupt-controller; 387 reg = <0x0 0x50041000 0x0 0x1000>, 388 <0x0 0x50042000 0x0 0x2000>, 389 <0x0 0x50044000 0x0 0x2000>, 390 <0x0 0x50046000 0x0 0x2000>; 391 interrupts = <GIC_PPI 9 392 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 393 interrupt-parent = <&gic>; 394 }; 395 396 gpu@57000000 { 397 compatible = "nvidia,gm20b"; 398 reg = <0x0 0x57000000 0x0 0x01000000>, 399 <0x0 0x58000000 0x0 0x01000000>; 400 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 402 interrupt-names = "stall", "nonstall"; 403 clocks = <&tegra_car TEGRA210_CLK_GPU>, 404 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 405 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 406 clock-names = "gpu", "pwr", "ref"; 407 resets = <&tegra_car 184>; 408 reset-names = "gpu"; 409 410 iommus = <&mc TEGRA_SWGROUP_GPU>; 411 412 status = "disabled"; 413 }; 414 415 lic: interrupt-controller@60004000 { 416 compatible = "nvidia,tegra210-ictlr"; 417 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 418 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 419 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 420 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 421 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 422 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 423 interrupt-controller; 424 #interrupt-cells = <3>; 425 interrupt-parent = <&gic>; 426 }; 427 428 timer@60005000 { 429 compatible = "nvidia,tegra210-timer"; 430 reg = <0x0 0x60005000 0x0 0x400>; 431 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 446 clock-names = "timer"; 447 }; 448 449 tegra_car: clock@60006000 { 450 compatible = "nvidia,tegra210-car"; 451 reg = <0x0 0x60006000 0x0 0x1000>; 452 #clock-cells = <1>; 453 #reset-cells = <1>; 454 }; 455 456 flow-controller@60007000 { 457 compatible = "nvidia,tegra210-flowctrl"; 458 reg = <0x0 0x60007000 0x0 0x1000>; 459 }; 460 461 gpio: gpio@6000d000 { 462 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 463 reg = <0x0 0x6000d000 0x0 0x1000>; 464 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 472 #gpio-cells = <2>; 473 gpio-controller; 474 #interrupt-cells = <2>; 475 interrupt-controller; 476 }; 477 478 apbdma: dma@60020000 { 479 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 480 reg = <0x0 0x60020000 0x0 0x1400>; 481 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 514 clock-names = "dma"; 515 resets = <&tegra_car 34>; 516 reset-names = "dma"; 517 #dma-cells = <1>; 518 }; 519 520 apbmisc@70000800 { 521 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 522 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 523 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 524 }; 525 526 pinmux: pinmux@700008d4 { 527 compatible = "nvidia,tegra210-pinmux"; 528 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 529 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 530 sdmmc1_3v3_drv: sdmmc1-3v3-drv { 531 sdmmc1 { 532 nvidia,pins = "drive_sdmmc1"; 533 nvidia,pull-down-strength = <0x8>; 534 nvidia,pull-up-strength = <0x8>; 535 }; 536 }; 537 sdmmc1_1v8_drv: sdmmc1-1v8-drv { 538 sdmmc1 { 539 nvidia,pins = "drive_sdmmc1"; 540 nvidia,pull-down-strength = <0x4>; 541 nvidia,pull-up-strength = <0x3>; 542 }; 543 }; 544 sdmmc2_1v8_drv: sdmmc2-1v8-drv { 545 sdmmc2 { 546 nvidia,pins = "drive_sdmmc2"; 547 nvidia,pull-down-strength = <0x10>; 548 nvidia,pull-up-strength = <0x10>; 549 }; 550 }; 551 sdmmc3_3v3_drv: sdmmc3-3v3-drv { 552 sdmmc3 { 553 nvidia,pins = "drive_sdmmc3"; 554 nvidia,pull-down-strength = <0x8>; 555 nvidia,pull-up-strength = <0x8>; 556 }; 557 }; 558 sdmmc3_1v8_drv: sdmmc3-1v8-drv { 559 sdmmc3 { 560 nvidia,pins = "drive_sdmmc3"; 561 nvidia,pull-down-strength = <0x4>; 562 nvidia,pull-up-strength = <0x3>; 563 }; 564 }; 565 sdmmc4_1v8_drv: sdmmc4-1v8-drv { 566 sdmmc4 { 567 nvidia,pins = "drive_sdmmc4"; 568 nvidia,pull-down-strength = <0x10>; 569 nvidia,pull-up-strength = <0x10>; 570 }; 571 }; 572 }; 573 574 /* 575 * There are two serial driver i.e. 8250 based simple serial 576 * driver and APB DMA based serial driver for higher baudrate 577 * and performance. To enable the 8250 based driver, the compatible 578 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 579 * the APB DMA based serial driver, the compatible is 580 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 581 */ 582 uarta: serial@70006000 { 583 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 584 reg = <0x0 0x70006000 0x0 0x40>; 585 reg-shift = <2>; 586 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 588 clock-names = "serial"; 589 resets = <&tegra_car 6>; 590 reset-names = "serial"; 591 dmas = <&apbdma 8>, <&apbdma 8>; 592 dma-names = "rx", "tx"; 593 status = "disabled"; 594 }; 595 596 uartb: serial@70006040 { 597 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 598 reg = <0x0 0x70006040 0x0 0x40>; 599 reg-shift = <2>; 600 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 602 clock-names = "serial"; 603 resets = <&tegra_car 7>; 604 reset-names = "serial"; 605 dmas = <&apbdma 9>, <&apbdma 9>; 606 dma-names = "rx", "tx"; 607 status = "disabled"; 608 }; 609 610 uartc: serial@70006200 { 611 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 612 reg = <0x0 0x70006200 0x0 0x40>; 613 reg-shift = <2>; 614 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 616 clock-names = "serial"; 617 resets = <&tegra_car 55>; 618 reset-names = "serial"; 619 dmas = <&apbdma 10>, <&apbdma 10>; 620 dma-names = "rx", "tx"; 621 status = "disabled"; 622 }; 623 624 uartd: serial@70006300 { 625 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 626 reg = <0x0 0x70006300 0x0 0x40>; 627 reg-shift = <2>; 628 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 630 clock-names = "serial"; 631 resets = <&tegra_car 65>; 632 reset-names = "serial"; 633 dmas = <&apbdma 19>, <&apbdma 19>; 634 dma-names = "rx", "tx"; 635 status = "disabled"; 636 }; 637 638 pwm: pwm@7000a000 { 639 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 640 reg = <0x0 0x7000a000 0x0 0x100>; 641 #pwm-cells = <2>; 642 clocks = <&tegra_car TEGRA210_CLK_PWM>; 643 clock-names = "pwm"; 644 resets = <&tegra_car 17>; 645 reset-names = "pwm"; 646 status = "disabled"; 647 }; 648 649 i2c@7000c000 { 650 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 651 reg = <0x0 0x7000c000 0x0 0x100>; 652 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 656 clock-names = "div-clk"; 657 resets = <&tegra_car 12>; 658 reset-names = "i2c"; 659 dmas = <&apbdma 21>, <&apbdma 21>; 660 dma-names = "rx", "tx"; 661 status = "disabled"; 662 }; 663 664 i2c@7000c400 { 665 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 666 reg = <0x0 0x7000c400 0x0 0x100>; 667 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 671 clock-names = "div-clk"; 672 resets = <&tegra_car 54>; 673 reset-names = "i2c"; 674 dmas = <&apbdma 22>, <&apbdma 22>; 675 dma-names = "rx", "tx"; 676 status = "disabled"; 677 }; 678 679 i2c@7000c500 { 680 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 681 reg = <0x0 0x7000c500 0x0 0x100>; 682 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 686 clock-names = "div-clk"; 687 resets = <&tegra_car 67>; 688 reset-names = "i2c"; 689 dmas = <&apbdma 23>, <&apbdma 23>; 690 dma-names = "rx", "tx"; 691 status = "disabled"; 692 }; 693 694 i2c@7000c700 { 695 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 696 reg = <0x0 0x7000c700 0x0 0x100>; 697 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 701 clock-names = "div-clk"; 702 resets = <&tegra_car 103>; 703 reset-names = "i2c"; 704 dmas = <&apbdma 26>, <&apbdma 26>; 705 dma-names = "rx", "tx"; 706 pinctrl-0 = <&state_dpaux1_i2c>; 707 pinctrl-1 = <&state_dpaux1_off>; 708 pinctrl-names = "default", "idle"; 709 status = "disabled"; 710 }; 711 712 i2c@7000d000 { 713 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 714 reg = <0x0 0x7000d000 0x0 0x100>; 715 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 719 clock-names = "div-clk"; 720 resets = <&tegra_car 47>; 721 reset-names = "i2c"; 722 dmas = <&apbdma 24>, <&apbdma 24>; 723 dma-names = "rx", "tx"; 724 status = "disabled"; 725 }; 726 727 i2c@7000d100 { 728 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 729 reg = <0x0 0x7000d100 0x0 0x100>; 730 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 734 clock-names = "div-clk"; 735 resets = <&tegra_car 166>; 736 reset-names = "i2c"; 737 dmas = <&apbdma 30>, <&apbdma 30>; 738 dma-names = "rx", "tx"; 739 pinctrl-0 = <&state_dpaux_i2c>; 740 pinctrl-1 = <&state_dpaux_off>; 741 pinctrl-names = "default", "idle"; 742 status = "disabled"; 743 }; 744 745 spi@7000d400 { 746 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 747 reg = <0x0 0x7000d400 0x0 0x200>; 748 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 752 clock-names = "spi"; 753 resets = <&tegra_car 41>; 754 reset-names = "spi"; 755 dmas = <&apbdma 15>, <&apbdma 15>; 756 dma-names = "rx", "tx"; 757 status = "disabled"; 758 }; 759 760 spi@7000d600 { 761 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 762 reg = <0x0 0x7000d600 0x0 0x200>; 763 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 767 clock-names = "spi"; 768 resets = <&tegra_car 44>; 769 reset-names = "spi"; 770 dmas = <&apbdma 16>, <&apbdma 16>; 771 dma-names = "rx", "tx"; 772 status = "disabled"; 773 }; 774 775 spi@7000d800 { 776 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 777 reg = <0x0 0x7000d800 0x0 0x200>; 778 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 782 clock-names = "spi"; 783 resets = <&tegra_car 46>; 784 reset-names = "spi"; 785 dmas = <&apbdma 17>, <&apbdma 17>; 786 dma-names = "rx", "tx"; 787 status = "disabled"; 788 }; 789 790 spi@7000da00 { 791 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 792 reg = <0x0 0x7000da00 0x0 0x200>; 793 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 797 clock-names = "spi"; 798 resets = <&tegra_car 68>; 799 reset-names = "spi"; 800 dmas = <&apbdma 18>, <&apbdma 18>; 801 dma-names = "rx", "tx"; 802 status = "disabled"; 803 }; 804 805 rtc@7000e000 { 806 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 807 reg = <0x0 0x7000e000 0x0 0x100>; 808 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 809 interrupt-parent = <&tegra_pmc>; 810 clocks = <&tegra_car TEGRA210_CLK_RTC>; 811 clock-names = "rtc"; 812 }; 813 814 tegra_pmc: pmc@7000e400 { 815 compatible = "nvidia,tegra210-pmc"; 816 reg = <0x0 0x7000e400 0x0 0x400>; 817 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 818 clock-names = "pclk", "clk32k_in"; 819 #clock-cells = <1>; 820 #interrupt-cells = <2>; 821 interrupt-controller; 822 823 powergates { 824 pd_audio: aud { 825 clocks = <&tegra_car TEGRA210_CLK_APE>, 826 <&tegra_car TEGRA210_CLK_APB2APE>; 827 resets = <&tegra_car 198>; 828 #power-domain-cells = <0>; 829 }; 830 831 pd_sor: sor { 832 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 833 <&tegra_car TEGRA210_CLK_SOR1>, 834 <&tegra_car TEGRA210_CLK_CILAB>, 835 <&tegra_car TEGRA210_CLK_CILCD>, 836 <&tegra_car TEGRA210_CLK_CILE>, 837 <&tegra_car TEGRA210_CLK_DSIA>, 838 <&tegra_car TEGRA210_CLK_DSIB>, 839 <&tegra_car TEGRA210_CLK_DPAUX>, 840 <&tegra_car TEGRA210_CLK_DPAUX1>, 841 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 842 resets = <&tegra_car TEGRA210_CLK_SOR0>, 843 <&tegra_car TEGRA210_CLK_SOR1>, 844 <&tegra_car TEGRA210_CLK_DSIA>, 845 <&tegra_car TEGRA210_CLK_DSIB>, 846 <&tegra_car TEGRA210_CLK_DPAUX>, 847 <&tegra_car TEGRA210_CLK_DPAUX1>, 848 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 849 #power-domain-cells = <0>; 850 }; 851 852 pd_xusbss: xusba { 853 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 854 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 855 #power-domain-cells = <0>; 856 }; 857 858 pd_xusbdev: xusbb { 859 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 860 resets = <&tegra_car 95>; 861 #power-domain-cells = <0>; 862 }; 863 864 pd_xusbhost: xusbc { 865 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 866 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 867 #power-domain-cells = <0>; 868 }; 869 870 pd_vic: vic { 871 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 872 clock-names = "vic"; 873 resets = <&tegra_car 178>; 874 reset-names = "vic"; 875 #power-domain-cells = <0>; 876 }; 877 878 pd_venc: venc { 879 clocks = <&tegra_car TEGRA210_CLK_VI>, 880 <&tegra_car TEGRA210_CLK_CSI>; 881 resets = <&mc TEGRA210_MC_RESET_VI>, 882 <&tegra_car 20>, 883 <&tegra_car 52>; 884 #power-domain-cells = <0>; 885 }; 886 }; 887 888 sdmmc1_3v3: sdmmc1-3v3 { 889 pins = "sdmmc1"; 890 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 891 }; 892 893 sdmmc1_1v8: sdmmc1-1v8 { 894 pins = "sdmmc1"; 895 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 896 }; 897 898 sdmmc3_3v3: sdmmc3-3v3 { 899 pins = "sdmmc3"; 900 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 901 }; 902 903 sdmmc3_1v8: sdmmc3-1v8 { 904 pins = "sdmmc3"; 905 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 906 }; 907 908 pex_dpd_disable: pex_en { 909 pex-dpd-disable { 910 pins = "pex-bias", "pex-clk1", "pex-clk2"; 911 low-power-disable; 912 }; 913 }; 914 915 pex_dpd_enable: pex_dis { 916 pex-dpd-enable { 917 pins = "pex-bias", "pex-clk1", "pex-clk2"; 918 low-power-enable; 919 }; 920 }; 921 }; 922 923 fuse@7000f800 { 924 compatible = "nvidia,tegra210-efuse"; 925 reg = <0x0 0x7000f800 0x0 0x400>; 926 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 927 clock-names = "fuse"; 928 resets = <&tegra_car 39>; 929 reset-names = "fuse"; 930 }; 931 932 mc: memory-controller@70019000 { 933 compatible = "nvidia,tegra210-mc"; 934 reg = <0x0 0x70019000 0x0 0x1000>; 935 clocks = <&tegra_car TEGRA210_CLK_MC>; 936 clock-names = "mc"; 937 938 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 939 940 #iommu-cells = <1>; 941 #reset-cells = <1>; 942 }; 943 944 emc: external-memory-controller@7001b000 { 945 compatible = "nvidia,tegra210-emc"; 946 reg = <0x0 0x7001b000 0x0 0x1000>, 947 <0x0 0x7001e000 0x0 0x1000>, 948 <0x0 0x7001f000 0x0 0x1000>; 949 clocks = <&tegra_car TEGRA210_CLK_EMC>; 950 clock-names = "emc"; 951 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 952 nvidia,memory-controller = <&mc>; 953 #cooling-cells = <2>; 954 }; 955 956 sata@70020000 { 957 compatible = "nvidia,tegra210-ahci"; 958 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 959 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 960 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 961 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&tegra_car TEGRA210_CLK_SATA>, 963 <&tegra_car TEGRA210_CLK_SATA_OOB>; 964 clock-names = "sata", "sata-oob"; 965 resets = <&tegra_car 124>, 966 <&tegra_car 123>, 967 <&tegra_car 129>; 968 reset-names = "sata", "sata-oob", "sata-cold"; 969 status = "disabled"; 970 }; 971 972 hda@70030000 { 973 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 974 reg = <0x0 0x70030000 0x0 0x10000>; 975 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&tegra_car TEGRA210_CLK_HDA>, 977 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 978 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 979 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 980 resets = <&tegra_car 125>, /* hda */ 981 <&tegra_car 128>, /* hda2hdmi */ 982 <&tegra_car 111>; /* hda2codec_2x */ 983 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 984 status = "disabled"; 985 }; 986 987 usb@70090000 { 988 compatible = "nvidia,tegra210-xusb"; 989 reg = <0x0 0x70090000 0x0 0x8000>, 990 <0x0 0x70098000 0x0 0x1000>, 991 <0x0 0x70099000 0x0 0x1000>; 992 reg-names = "hcd", "fpci", "ipfs"; 993 994 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 996 997 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 998 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 999 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1000 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1001 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1002 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1003 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1004 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1005 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1006 <&tegra_car TEGRA210_CLK_CLK_M>, 1007 <&tegra_car TEGRA210_CLK_PLL_E>; 1008 clock-names = "xusb_host", "xusb_host_src", 1009 "xusb_falcon_src", "xusb_ss", 1010 "xusb_ss_div2", "xusb_ss_src", 1011 "xusb_hs_src", "xusb_fs_src", 1012 "pll_u_480m", "clk_m", "pll_e"; 1013 resets = <&tegra_car 89>, <&tegra_car 156>, 1014 <&tegra_car 143>; 1015 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1016 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1017 power-domain-names = "xusb_host", "xusb_ss"; 1018 1019 nvidia,xusb-padctl = <&padctl>; 1020 1021 status = "disabled"; 1022 }; 1023 1024 padctl: padctl@7009f000 { 1025 compatible = "nvidia,tegra210-xusb-padctl"; 1026 reg = <0x0 0x7009f000 0x0 0x1000>; 1027 resets = <&tegra_car 142>; 1028 reset-names = "padctl"; 1029 1030 status = "disabled"; 1031 1032 pads { 1033 usb2 { 1034 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1035 clock-names = "trk"; 1036 status = "disabled"; 1037 1038 lanes { 1039 usb2-0 { 1040 status = "disabled"; 1041 #phy-cells = <0>; 1042 }; 1043 1044 usb2-1 { 1045 status = "disabled"; 1046 #phy-cells = <0>; 1047 }; 1048 1049 usb2-2 { 1050 status = "disabled"; 1051 #phy-cells = <0>; 1052 }; 1053 1054 usb2-3 { 1055 status = "disabled"; 1056 #phy-cells = <0>; 1057 }; 1058 }; 1059 }; 1060 1061 hsic { 1062 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1063 clock-names = "trk"; 1064 status = "disabled"; 1065 1066 lanes { 1067 hsic-0 { 1068 status = "disabled"; 1069 #phy-cells = <0>; 1070 }; 1071 1072 hsic-1 { 1073 status = "disabled"; 1074 #phy-cells = <0>; 1075 }; 1076 }; 1077 }; 1078 1079 pcie { 1080 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1081 clock-names = "pll"; 1082 resets = <&tegra_car 205>; 1083 reset-names = "phy"; 1084 status = "disabled"; 1085 1086 lanes { 1087 pcie-0 { 1088 status = "disabled"; 1089 #phy-cells = <0>; 1090 }; 1091 1092 pcie-1 { 1093 status = "disabled"; 1094 #phy-cells = <0>; 1095 }; 1096 1097 pcie-2 { 1098 status = "disabled"; 1099 #phy-cells = <0>; 1100 }; 1101 1102 pcie-3 { 1103 status = "disabled"; 1104 #phy-cells = <0>; 1105 }; 1106 1107 pcie-4 { 1108 status = "disabled"; 1109 #phy-cells = <0>; 1110 }; 1111 1112 pcie-5 { 1113 status = "disabled"; 1114 #phy-cells = <0>; 1115 }; 1116 1117 pcie-6 { 1118 status = "disabled"; 1119 #phy-cells = <0>; 1120 }; 1121 }; 1122 }; 1123 1124 sata { 1125 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1126 clock-names = "pll"; 1127 resets = <&tegra_car 204>; 1128 reset-names = "phy"; 1129 status = "disabled"; 1130 1131 lanes { 1132 sata-0 { 1133 status = "disabled"; 1134 #phy-cells = <0>; 1135 }; 1136 }; 1137 }; 1138 }; 1139 1140 ports { 1141 usb2-0 { 1142 status = "disabled"; 1143 }; 1144 1145 usb2-1 { 1146 status = "disabled"; 1147 }; 1148 1149 usb2-2 { 1150 status = "disabled"; 1151 }; 1152 1153 usb2-3 { 1154 status = "disabled"; 1155 }; 1156 1157 hsic-0 { 1158 status = "disabled"; 1159 }; 1160 1161 usb3-0 { 1162 status = "disabled"; 1163 }; 1164 1165 usb3-1 { 1166 status = "disabled"; 1167 }; 1168 1169 usb3-2 { 1170 status = "disabled"; 1171 }; 1172 1173 usb3-3 { 1174 status = "disabled"; 1175 }; 1176 }; 1177 }; 1178 1179 sdhci@700b0000 { 1180 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1181 reg = <0x0 0x700b0000 0x0 0x200>; 1182 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1183 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; 1184 clock-names = "sdhci"; 1185 resets = <&tegra_car 14>; 1186 reset-names = "sdhci"; 1187 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1188 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1189 pinctrl-0 = <&sdmmc1_3v3>; 1190 pinctrl-1 = <&sdmmc1_1v8>; 1191 pinctrl-2 = <&sdmmc1_3v3_drv>; 1192 pinctrl-3 = <&sdmmc1_1v8_drv>; 1193 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1194 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1195 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1196 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1197 nvidia,default-tap = <0x2>; 1198 nvidia,default-trim = <0x4>; 1199 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1200 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1201 <&tegra_car TEGRA210_CLK_PLL_C4>; 1202 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1203 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1204 status = "disabled"; 1205 }; 1206 1207 sdhci@700b0200 { 1208 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1209 reg = <0x0 0x700b0200 0x0 0x200>; 1210 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1211 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; 1212 clock-names = "sdhci"; 1213 resets = <&tegra_car 9>; 1214 reset-names = "sdhci"; 1215 pinctrl-names = "sdmmc-1v8-drv"; 1216 pinctrl-0 = <&sdmmc2_1v8_drv>; 1217 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1218 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1219 nvidia,default-tap = <0x8>; 1220 nvidia,default-trim = <0x0>; 1221 status = "disabled"; 1222 }; 1223 1224 sdhci@700b0400 { 1225 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1226 reg = <0x0 0x700b0400 0x0 0x200>; 1227 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; 1229 clock-names = "sdhci"; 1230 resets = <&tegra_car 69>; 1231 reset-names = "sdhci"; 1232 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1233 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1234 pinctrl-0 = <&sdmmc3_3v3>; 1235 pinctrl-1 = <&sdmmc3_1v8>; 1236 pinctrl-2 = <&sdmmc3_3v3_drv>; 1237 pinctrl-3 = <&sdmmc3_1v8_drv>; 1238 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1239 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1240 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1241 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1242 nvidia,default-tap = <0x3>; 1243 nvidia,default-trim = <0x3>; 1244 status = "disabled"; 1245 }; 1246 1247 sdhci@700b0600 { 1248 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; 1249 reg = <0x0 0x700b0600 0x0 0x200>; 1250 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1251 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; 1252 clock-names = "sdhci"; 1253 resets = <&tegra_car 15>; 1254 reset-names = "sdhci"; 1255 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1256 pinctrl-0 = <&sdmmc4_1v8_drv>; 1257 pinctrl-1 = <&sdmmc4_1v8_drv>; 1258 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1259 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1260 nvidia,default-tap = <0x8>; 1261 nvidia,default-trim = <0x0>; 1262 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1263 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1264 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1265 nvidia,dqs-trim = <40>; 1266 mmc-hs400-1_8v; 1267 status = "disabled"; 1268 }; 1269 1270 usb@700d0000 { 1271 compatible = "nvidia,tegra210-xudc"; 1272 reg = <0x0 0x700d0000 0x0 0x8000>, 1273 <0x0 0x700d8000 0x0 0x1000>, 1274 <0x0 0x700d9000 0x0 0x1000>; 1275 reg-names = "base", "fpci", "ipfs"; 1276 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1277 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1278 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1279 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1280 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1281 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1282 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1283 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1284 power-domain-names = "dev", "ss"; 1285 nvidia,xusb-padctl = <&padctl>; 1286 status = "disabled"; 1287 }; 1288 1289 mipi: mipi@700e3000 { 1290 compatible = "nvidia,tegra210-mipi"; 1291 reg = <0x0 0x700e3000 0x0 0x100>; 1292 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1293 clock-names = "mipi-cal"; 1294 power-domains = <&pd_sor>; 1295 #nvidia,mipi-calibrate-cells = <1>; 1296 }; 1297 1298 dfll: clock@70110000 { 1299 compatible = "nvidia,tegra210-dfll"; 1300 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1301 <0 0x70110000 0 0x100>, /* I2C output control */ 1302 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1303 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1304 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1305 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1306 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1307 <&tegra_car TEGRA210_CLK_I2C5>; 1308 clock-names = "soc", "ref", "i2c"; 1309 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; 1310 reset-names = "dvco"; 1311 #clock-cells = <0>; 1312 clock-output-names = "dfllCPU_out"; 1313 status = "disabled"; 1314 }; 1315 1316 aconnect@702c0000 { 1317 compatible = "nvidia,tegra210-aconnect"; 1318 clocks = <&tegra_car TEGRA210_CLK_APE>, 1319 <&tegra_car TEGRA210_CLK_APB2APE>; 1320 clock-names = "ape", "apb2ape"; 1321 power-domains = <&pd_audio>; 1322 #address-cells = <1>; 1323 #size-cells = <1>; 1324 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1325 status = "disabled"; 1326 1327 adma: dma@702e2000 { 1328 compatible = "nvidia,tegra210-adma"; 1329 reg = <0x702e2000 0x2000>; 1330 interrupt-parent = <&agic>; 1331 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1353 #dma-cells = <1>; 1354 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1355 clock-names = "d_audio"; 1356 status = "disabled"; 1357 }; 1358 1359 agic: agic@702f9000 { 1360 compatible = "nvidia,tegra210-agic"; 1361 #interrupt-cells = <3>; 1362 interrupt-controller; 1363 reg = <0x702f9000 0x1000>, 1364 <0x702fa000 0x2000>; 1365 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1366 clocks = <&tegra_car TEGRA210_CLK_APE>; 1367 clock-names = "clk"; 1368 status = "disabled"; 1369 }; 1370 }; 1371 1372 spi@70410000 { 1373 compatible = "nvidia,tegra210-qspi"; 1374 reg = <0x0 0x70410000 0x0 0x1000>; 1375 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1376 #address-cells = <1>; 1377 #size-cells = <0>; 1378 clocks = <&tegra_car TEGRA210_CLK_QSPI>; 1379 clock-names = "qspi"; 1380 resets = <&tegra_car 211>; 1381 reset-names = "qspi"; 1382 dmas = <&apbdma 5>, <&apbdma 5>; 1383 dma-names = "rx", "tx"; 1384 status = "disabled"; 1385 }; 1386 1387 usb@7d000000 { 1388 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1389 reg = <0x0 0x7d000000 0x0 0x4000>; 1390 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1391 phy_type = "utmi"; 1392 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1393 clock-names = "usb"; 1394 resets = <&tegra_car 22>; 1395 reset-names = "usb"; 1396 nvidia,phy = <&phy1>; 1397 status = "disabled"; 1398 }; 1399 1400 phy1: usb-phy@7d000000 { 1401 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1402 reg = <0x0 0x7d000000 0x0 0x4000>, 1403 <0x0 0x7d000000 0x0 0x4000>; 1404 phy_type = "utmi"; 1405 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1406 <&tegra_car TEGRA210_CLK_PLL_U>, 1407 <&tegra_car TEGRA210_CLK_USBD>; 1408 clock-names = "reg", "pll_u", "utmi-pads"; 1409 resets = <&tegra_car 22>, <&tegra_car 22>; 1410 reset-names = "usb", "utmi-pads"; 1411 nvidia,hssync-start-delay = <0>; 1412 nvidia,idle-wait-delay = <17>; 1413 nvidia,elastic-limit = <16>; 1414 nvidia,term-range-adj = <6>; 1415 nvidia,xcvr-setup = <9>; 1416 nvidia,xcvr-lsfslew = <0>; 1417 nvidia,xcvr-lsrslew = <3>; 1418 nvidia,hssquelch-level = <2>; 1419 nvidia,hsdiscon-level = <5>; 1420 nvidia,xcvr-hsslew = <12>; 1421 nvidia,has-utmi-pad-registers; 1422 status = "disabled"; 1423 }; 1424 1425 usb@7d004000 { 1426 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1427 reg = <0x0 0x7d004000 0x0 0x4000>; 1428 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1429 phy_type = "utmi"; 1430 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1431 clock-names = "usb"; 1432 resets = <&tegra_car 58>; 1433 reset-names = "usb"; 1434 nvidia,phy = <&phy2>; 1435 status = "disabled"; 1436 }; 1437 1438 phy2: usb-phy@7d004000 { 1439 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1440 reg = <0x0 0x7d004000 0x0 0x4000>, 1441 <0x0 0x7d000000 0x0 0x4000>; 1442 phy_type = "utmi"; 1443 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1444 <&tegra_car TEGRA210_CLK_PLL_U>, 1445 <&tegra_car TEGRA210_CLK_USBD>; 1446 clock-names = "reg", "pll_u", "utmi-pads"; 1447 resets = <&tegra_car 58>, <&tegra_car 22>; 1448 reset-names = "usb", "utmi-pads"; 1449 nvidia,hssync-start-delay = <0>; 1450 nvidia,idle-wait-delay = <17>; 1451 nvidia,elastic-limit = <16>; 1452 nvidia,term-range-adj = <6>; 1453 nvidia,xcvr-setup = <9>; 1454 nvidia,xcvr-lsfslew = <0>; 1455 nvidia,xcvr-lsrslew = <3>; 1456 nvidia,hssquelch-level = <2>; 1457 nvidia,hsdiscon-level = <5>; 1458 nvidia,xcvr-hsslew = <12>; 1459 status = "disabled"; 1460 }; 1461 1462 cpus { 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 1466 cpu@0 { 1467 device_type = "cpu"; 1468 compatible = "arm,cortex-a57"; 1469 reg = <0>; 1470 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1471 <&tegra_car TEGRA210_CLK_PLL_X>, 1472 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1473 <&dfll>; 1474 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1475 clock-latency = <300000>; 1476 cpu-idle-states = <&CPU_SLEEP>; 1477 next-level-cache = <&L2>; 1478 }; 1479 1480 cpu@1 { 1481 device_type = "cpu"; 1482 compatible = "arm,cortex-a57"; 1483 reg = <1>; 1484 cpu-idle-states = <&CPU_SLEEP>; 1485 next-level-cache = <&L2>; 1486 }; 1487 1488 cpu@2 { 1489 device_type = "cpu"; 1490 compatible = "arm,cortex-a57"; 1491 reg = <2>; 1492 cpu-idle-states = <&CPU_SLEEP>; 1493 next-level-cache = <&L2>; 1494 }; 1495 1496 cpu@3 { 1497 device_type = "cpu"; 1498 compatible = "arm,cortex-a57"; 1499 reg = <3>; 1500 cpu-idle-states = <&CPU_SLEEP>; 1501 next-level-cache = <&L2>; 1502 }; 1503 1504 idle-states { 1505 entry-method = "psci"; 1506 1507 CPU_SLEEP: cpu-sleep { 1508 compatible = "arm,idle-state"; 1509 arm,psci-suspend-param = <0x40000007>; 1510 entry-latency-us = <100>; 1511 exit-latency-us = <30>; 1512 min-residency-us = <1000>; 1513 wakeup-latency-us = <130>; 1514 idle-state-name = "cpu-sleep"; 1515 status = "disabled"; 1516 }; 1517 }; 1518 1519 L2: l2-cache { 1520 compatible = "cache"; 1521 }; 1522 }; 1523 1524 pmu { 1525 compatible = "arm,armv8-pmuv3"; 1526 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1530 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 1531 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 1532 }; 1533 1534 timer { 1535 compatible = "arm,armv8-timer"; 1536 interrupts = <GIC_PPI 13 1537 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1538 <GIC_PPI 14 1539 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1540 <GIC_PPI 11 1541 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1542 <GIC_PPI 10 1543 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1544 interrupt-parent = <&gic>; 1545 arm,no-tick-in-suspend; 1546 }; 1547 1548 soctherm: thermal-sensor@700e2000 { 1549 compatible = "nvidia,tegra210-soctherm"; 1550 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 1551 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1552 reg-names = "soctherm-reg", "car-reg"; 1553 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1555 interrupt-names = "thermal", "edp"; 1556 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1557 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1558 clock-names = "tsensor", "soctherm"; 1559 resets = <&tegra_car 78>; 1560 reset-names = "soctherm"; 1561 #thermal-sensor-cells = <1>; 1562 1563 throttle-cfgs { 1564 throttle_heavy: heavy { 1565 nvidia,priority = <100>; 1566 nvidia,cpu-throt-percent = <85>; 1567 1568 #cooling-cells = <2>; 1569 }; 1570 }; 1571 }; 1572 1573 thermal-zones { 1574 cpu { 1575 polling-delay-passive = <1000>; 1576 polling-delay = <0>; 1577 1578 thermal-sensors = 1579 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1580 1581 trips { 1582 cpu-shutdown-trip { 1583 temperature = <102500>; 1584 hysteresis = <0>; 1585 type = "critical"; 1586 }; 1587 1588 cpu_throttle_trip: throttle-trip { 1589 temperature = <98500>; 1590 hysteresis = <1000>; 1591 type = "hot"; 1592 }; 1593 }; 1594 1595 cooling-maps { 1596 map0 { 1597 trip = <&cpu_throttle_trip>; 1598 cooling-device = <&throttle_heavy 1 1>; 1599 }; 1600 }; 1601 }; 1602 1603 mem { 1604 polling-delay-passive = <0>; 1605 polling-delay = <0>; 1606 1607 thermal-sensors = 1608 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1609 1610 trips { 1611 dram_nominal: mem-nominal-trip { 1612 temperature = <50000>; 1613 hysteresis = <1000>; 1614 type = "passive"; 1615 }; 1616 1617 dram_throttle: mem-throttle-trip { 1618 temperature = <70000>; 1619 hysteresis = <1000>; 1620 type = "active"; 1621 }; 1622 1623 mem-shutdown-trip { 1624 temperature = <103000>; 1625 hysteresis = <0>; 1626 type = "critical"; 1627 }; 1628 }; 1629 1630 cooling-maps { 1631 dram-passive { 1632 cooling-device = <&emc 0 0>; 1633 trip = <&dram_nominal>; 1634 }; 1635 1636 dram-active { 1637 cooling-device = <&emc 1 1>; 1638 trip = <&dram_throttle>; 1639 }; 1640 }; 1641 }; 1642 1643 gpu { 1644 polling-delay-passive = <1000>; 1645 polling-delay = <0>; 1646 1647 thermal-sensors = 1648 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1649 1650 trips { 1651 gpu-shutdown-trip { 1652 temperature = <103000>; 1653 hysteresis = <0>; 1654 type = "critical"; 1655 }; 1656 1657 gpu_throttle_trip: throttle-trip { 1658 temperature = <100000>; 1659 hysteresis = <1000>; 1660 type = "hot"; 1661 }; 1662 }; 1663 1664 cooling-maps { 1665 map0 { 1666 trip = <&gpu_throttle_trip>; 1667 cooling-device = <&throttle_heavy 1 1>; 1668 }; 1669 }; 1670 }; 1671 1672 pllx { 1673 polling-delay-passive = <0>; 1674 polling-delay = <0>; 1675 1676 thermal-sensors = 1677 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1678 1679 trips { 1680 pllx-shutdown-trip { 1681 temperature = <103000>; 1682 hysteresis = <0>; 1683 type = "critical"; 1684 }; 1685 }; 1686 1687 cooling-maps { 1688 /* 1689 * There are currently no cooling maps, 1690 * because there are no cooling devices. 1691 */ 1692 }; 1693 }; 1694 }; 1695}; 1696