1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/renesas,rcar-dmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas R-Car and RZ/G DMA Controller
8
9maintainers:
10  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
11
12allOf:
13  - $ref: "dma-controller.yaml#"
14
15properties:
16  compatible:
17    items:
18      - enum:
19          - renesas,dmac-r8a7743  # RZ/G1M
20          - renesas,dmac-r8a7744  # RZ/G1N
21          - renesas,dmac-r8a7745  # RZ/G1E
22          - renesas,dmac-r8a77470 # RZ/G1C
23          - renesas,dmac-r8a774a1 # RZ/G2M
24          - renesas,dmac-r8a774b1 # RZ/G2N
25          - renesas,dmac-r8a774c0 # RZ/G2E
26          - renesas,dmac-r8a7790  # R-Car H2
27          - renesas,dmac-r8a7791  # R-Car M2-W
28          - renesas,dmac-r8a7792  # R-Car V2H
29          - renesas,dmac-r8a7793  # R-Car M2-N
30          - renesas,dmac-r8a7794  # R-Car E2
31          - renesas,dmac-r8a7795  # R-Car H3
32          - renesas,dmac-r8a7796  # R-Car M3-W
33          - renesas,dmac-r8a77961 # R-Car M3-W+
34          - renesas,dmac-r8a77965 # R-Car M3-N
35          - renesas,dmac-r8a77970 # R-Car V3M
36          - renesas,dmac-r8a77980 # R-Car V3H
37          - renesas,dmac-r8a77990 # R-Car E3
38          - renesas,dmac-r8a77995 # R-Car D3
39      - const: renesas,rcar-dmac
40
41  reg:
42    maxItems: 1
43
44  interrupts:
45    minItems: 9
46    maxItems: 17
47
48  interrupt-names:
49    minItems: 9
50    maxItems: 17
51    items:
52      - const: error
53      - pattern: "^ch([0-9]|1[0-5])$"
54      - pattern: "^ch([0-9]|1[0-5])$"
55      - pattern: "^ch([0-9]|1[0-5])$"
56      - pattern: "^ch([0-9]|1[0-5])$"
57      - pattern: "^ch([0-9]|1[0-5])$"
58      - pattern: "^ch([0-9]|1[0-5])$"
59      - pattern: "^ch([0-9]|1[0-5])$"
60      - pattern: "^ch([0-9]|1[0-5])$"
61      - pattern: "^ch([0-9]|1[0-5])$"
62      - pattern: "^ch([0-9]|1[0-5])$"
63      - pattern: "^ch([0-9]|1[0-5])$"
64      - pattern: "^ch([0-9]|1[0-5])$"
65      - pattern: "^ch([0-9]|1[0-5])$"
66      - pattern: "^ch([0-9]|1[0-5])$"
67      - pattern: "^ch([0-9]|1[0-5])$"
68      - pattern: "^ch([0-9]|1[0-5])$"
69
70  clocks:
71    maxItems: 1
72
73  clock-names:
74    maxItems: 1
75    items:
76      - const: fck
77
78  '#dma-cells':
79    const: 1
80    description:
81      The cell specifies the MID/RID of the DMAC port connected to
82      the DMA client.
83
84  dma-channels:
85    minimum: 8
86    maximum: 16
87
88  dma-channel-mask: true
89
90  iommus:
91    minItems: 8
92    maxItems: 16
93
94  power-domains:
95    maxItems: 1
96
97  resets:
98    maxItems: 1
99
100required:
101  - compatible
102  - reg
103  - interrupts
104  - interrupt-names
105  - clocks
106  - clock-names
107  - '#dma-cells'
108  - dma-channels
109  - power-domains
110  - resets
111
112additionalProperties: false
113
114examples:
115  - |
116    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
117    #include <dt-bindings/interrupt-controller/arm-gic.h>
118    #include <dt-bindings/power/r8a7790-sysc.h>
119
120    dmac0: dma-controller@e6700000 {
121        compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
122        reg = <0xe6700000 0x20000>;
123        interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
124                     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
125                     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
126                     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
127                     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
128                     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
129                     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
130                     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
131                     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
132                     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
133                     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
134                     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
135                     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
136                     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
137                     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
138                     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
139        interrupt-names = "error",
140                          "ch0", "ch1", "ch2", "ch3",
141                          "ch4", "ch5", "ch6", "ch7",
142                          "ch8", "ch9", "ch10", "ch11",
143                          "ch12", "ch13", "ch14";
144        clocks = <&cpg CPG_MOD 219>;
145        clock-names = "fck";
146        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
147        resets = <&cpg 219>;
148        #dma-cells = <1>;
149        dma-channels = <15>;
150    };
151