1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This header defines architecture specific interfaces, x86 version 6 */ 7 8 #ifndef _ASM_X86_KVM_HOST_H 9 #define _ASM_X86_KVM_HOST_H 10 11 #include <linux/types.h> 12 #include <linux/mm.h> 13 #include <linux/mmu_notifier.h> 14 #include <linux/tracepoint.h> 15 #include <linux/cpumask.h> 16 #include <linux/irq_work.h> 17 #include <linux/irq.h> 18 19 #include <linux/kvm.h> 20 #include <linux/kvm_para.h> 21 #include <linux/kvm_types.h> 22 #include <linux/perf_event.h> 23 #include <linux/pvclock_gtod.h> 24 #include <linux/clocksource.h> 25 #include <linux/irqbypass.h> 26 #include <linux/hyperv.h> 27 28 #include <asm/apic.h> 29 #include <asm/pvclock-abi.h> 30 #include <asm/desc.h> 31 #include <asm/mtrr.h> 32 #include <asm/msr-index.h> 33 #include <asm/asm.h> 34 #include <asm/kvm_page_track.h> 35 #include <asm/kvm_vcpu_regs.h> 36 #include <asm/hyperv-tlfs.h> 37 38 #define __KVM_HAVE_ARCH_VCPU_DEBUGFS 39 40 #define KVM_MAX_VCPUS 288 41 #define KVM_SOFT_MAX_VCPUS 240 42 #define KVM_MAX_VCPU_ID 1023 43 #define KVM_USER_MEM_SLOTS 509 44 /* memory slots that are not exposed to userspace */ 45 #define KVM_PRIVATE_MEM_SLOTS 3 46 #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) 47 48 #define KVM_HALT_POLL_NS_DEFAULT 200000 49 50 #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS 51 52 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 53 KVM_DIRTY_LOG_INITIALLY_SET) 54 55 /* x86-specific vcpu->requests bit members */ 56 #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0) 57 #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1) 58 #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2) 59 #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3) 60 #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4) 61 #define KVM_REQ_LOAD_MMU_PGD KVM_ARCH_REQ(5) 62 #define KVM_REQ_EVENT KVM_ARCH_REQ(6) 63 #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7) 64 #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8) 65 #define KVM_REQ_NMI KVM_ARCH_REQ(9) 66 #define KVM_REQ_PMU KVM_ARCH_REQ(10) 67 #define KVM_REQ_PMI KVM_ARCH_REQ(11) 68 #define KVM_REQ_SMI KVM_ARCH_REQ(12) 69 #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13) 70 #define KVM_REQ_MCLOCK_INPROGRESS \ 71 KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 72 #define KVM_REQ_SCAN_IOAPIC \ 73 KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 74 #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16) 75 #define KVM_REQ_APIC_PAGE_RELOAD \ 76 KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 77 #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18) 78 #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19) 79 #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20) 80 #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21) 81 #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22) 82 #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23) 83 #define KVM_REQ_GET_VMCS12_PAGES KVM_ARCH_REQ(24) 84 #define KVM_REQ_APICV_UPDATE \ 85 KVM_ARCH_REQ_FLAGS(25, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 86 #define KVM_REQ_TLB_FLUSH_CURRENT KVM_ARCH_REQ(26) 87 #define KVM_REQ_HV_TLB_FLUSH \ 88 KVM_ARCH_REQ_FLAGS(27, KVM_REQUEST_NO_WAKEUP) 89 #define KVM_REQ_APF_READY KVM_ARCH_REQ(28) 90 91 #define CR0_RESERVED_BITS \ 92 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ 93 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ 94 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) 95 96 #define CR4_RESERVED_BITS \ 97 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ 98 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ 99 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ 100 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ 101 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ 102 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) 103 104 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) 105 106 107 108 #define INVALID_PAGE (~(hpa_t)0) 109 #define VALID_PAGE(x) ((x) != INVALID_PAGE) 110 111 #define UNMAPPED_GVA (~(gpa_t)0) 112 113 /* KVM Hugepage definitions for x86 */ 114 #define KVM_MAX_HUGEPAGE_LEVEL PG_LEVEL_1G 115 #define KVM_NR_PAGE_SIZES (KVM_MAX_HUGEPAGE_LEVEL - PG_LEVEL_4K + 1) 116 #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) 117 #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) 118 #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) 119 #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) 120 #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) 121 122 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) 123 { 124 /* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */ 125 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - 126 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); 127 } 128 129 #define KVM_PERMILLE_MMU_PAGES 20 130 #define KVM_MIN_ALLOC_MMU_PAGES 64UL 131 #define KVM_MMU_HASH_SHIFT 12 132 #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) 133 #define KVM_MIN_FREE_MMU_PAGES 5 134 #define KVM_REFILL_PAGES 25 135 #define KVM_MAX_CPUID_ENTRIES 80 136 #define KVM_NR_FIXED_MTRR_REGION 88 137 #define KVM_NR_VAR_MTRR 8 138 139 #define ASYNC_PF_PER_VCPU 64 140 141 enum kvm_reg { 142 VCPU_REGS_RAX = __VCPU_REGS_RAX, 143 VCPU_REGS_RCX = __VCPU_REGS_RCX, 144 VCPU_REGS_RDX = __VCPU_REGS_RDX, 145 VCPU_REGS_RBX = __VCPU_REGS_RBX, 146 VCPU_REGS_RSP = __VCPU_REGS_RSP, 147 VCPU_REGS_RBP = __VCPU_REGS_RBP, 148 VCPU_REGS_RSI = __VCPU_REGS_RSI, 149 VCPU_REGS_RDI = __VCPU_REGS_RDI, 150 #ifdef CONFIG_X86_64 151 VCPU_REGS_R8 = __VCPU_REGS_R8, 152 VCPU_REGS_R9 = __VCPU_REGS_R9, 153 VCPU_REGS_R10 = __VCPU_REGS_R10, 154 VCPU_REGS_R11 = __VCPU_REGS_R11, 155 VCPU_REGS_R12 = __VCPU_REGS_R12, 156 VCPU_REGS_R13 = __VCPU_REGS_R13, 157 VCPU_REGS_R14 = __VCPU_REGS_R14, 158 VCPU_REGS_R15 = __VCPU_REGS_R15, 159 #endif 160 VCPU_REGS_RIP, 161 NR_VCPU_REGS, 162 163 VCPU_EXREG_PDPTR = NR_VCPU_REGS, 164 VCPU_EXREG_CR0, 165 VCPU_EXREG_CR3, 166 VCPU_EXREG_CR4, 167 VCPU_EXREG_RFLAGS, 168 VCPU_EXREG_SEGMENTS, 169 VCPU_EXREG_EXIT_INFO_1, 170 VCPU_EXREG_EXIT_INFO_2, 171 }; 172 173 enum { 174 VCPU_SREG_ES, 175 VCPU_SREG_CS, 176 VCPU_SREG_SS, 177 VCPU_SREG_DS, 178 VCPU_SREG_FS, 179 VCPU_SREG_GS, 180 VCPU_SREG_TR, 181 VCPU_SREG_LDTR, 182 }; 183 184 enum exit_fastpath_completion { 185 EXIT_FASTPATH_NONE, 186 EXIT_FASTPATH_REENTER_GUEST, 187 EXIT_FASTPATH_EXIT_HANDLED, 188 }; 189 typedef enum exit_fastpath_completion fastpath_t; 190 191 struct x86_emulate_ctxt; 192 struct x86_exception; 193 enum x86_intercept; 194 enum x86_intercept_stage; 195 196 #define KVM_NR_MEM_OBJS 40 197 198 #define KVM_NR_DB_REGS 4 199 200 #define DR6_BD (1 << 13) 201 #define DR6_BS (1 << 14) 202 #define DR6_BT (1 << 15) 203 #define DR6_RTM (1 << 16) 204 #define DR6_FIXED_1 0xfffe0ff0 205 #define DR6_INIT 0xffff0ff0 206 #define DR6_VOLATILE 0x0001e00f 207 208 #define DR7_BP_EN_MASK 0x000000ff 209 #define DR7_GE (1 << 9) 210 #define DR7_GD (1 << 13) 211 #define DR7_FIXED_1 0x00000400 212 #define DR7_VOLATILE 0xffff2bff 213 214 #define PFERR_PRESENT_BIT 0 215 #define PFERR_WRITE_BIT 1 216 #define PFERR_USER_BIT 2 217 #define PFERR_RSVD_BIT 3 218 #define PFERR_FETCH_BIT 4 219 #define PFERR_PK_BIT 5 220 #define PFERR_GUEST_FINAL_BIT 32 221 #define PFERR_GUEST_PAGE_BIT 33 222 223 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) 224 #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) 225 #define PFERR_USER_MASK (1U << PFERR_USER_BIT) 226 #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) 227 #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) 228 #define PFERR_PK_MASK (1U << PFERR_PK_BIT) 229 #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) 230 #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) 231 232 #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ 233 PFERR_WRITE_MASK | \ 234 PFERR_PRESENT_MASK) 235 236 /* apic attention bits */ 237 #define KVM_APIC_CHECK_VAPIC 0 238 /* 239 * The following bit is set with PV-EOI, unset on EOI. 240 * We detect PV-EOI changes by guest by comparing 241 * this bit with PV-EOI in guest memory. 242 * See the implementation in apic_update_pv_eoi. 243 */ 244 #define KVM_APIC_PV_EOI_PENDING 1 245 246 struct kvm_kernel_irq_routing_entry; 247 248 /* 249 * We don't want allocation failures within the mmu code, so we preallocate 250 * enough memory for a single page fault in a cache. 251 */ 252 struct kvm_mmu_memory_cache { 253 int nobjs; 254 void *objects[KVM_NR_MEM_OBJS]; 255 }; 256 257 /* 258 * the pages used as guest page table on soft mmu are tracked by 259 * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used 260 * by indirect shadow page can not be more than 15 bits. 261 * 262 * Currently, we used 14 bits that are @level, @gpte_is_8_bytes, @quadrant, @access, 263 * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp. 264 */ 265 union kvm_mmu_page_role { 266 u32 word; 267 struct { 268 unsigned level:4; 269 unsigned gpte_is_8_bytes:1; 270 unsigned quadrant:2; 271 unsigned direct:1; 272 unsigned access:3; 273 unsigned invalid:1; 274 unsigned nxe:1; 275 unsigned cr0_wp:1; 276 unsigned smep_andnot_wp:1; 277 unsigned smap_andnot_wp:1; 278 unsigned ad_disabled:1; 279 unsigned guest_mode:1; 280 unsigned :6; 281 282 /* 283 * This is left at the top of the word so that 284 * kvm_memslots_for_spte_role can extract it with a 285 * simple shift. While there is room, give it a whole 286 * byte so it is also faster to load it from memory. 287 */ 288 unsigned smm:8; 289 }; 290 }; 291 292 union kvm_mmu_extended_role { 293 /* 294 * This structure complements kvm_mmu_page_role caching everything needed for 295 * MMU configuration. If nothing in both these structures changed, MMU 296 * re-configuration can be skipped. @valid bit is set on first usage so we don't 297 * treat all-zero structure as valid data. 298 */ 299 u32 word; 300 struct { 301 unsigned int valid:1; 302 unsigned int execonly:1; 303 unsigned int cr0_pg:1; 304 unsigned int cr4_pae:1; 305 unsigned int cr4_pse:1; 306 unsigned int cr4_pke:1; 307 unsigned int cr4_smap:1; 308 unsigned int cr4_smep:1; 309 unsigned int maxphyaddr:6; 310 }; 311 }; 312 313 union kvm_mmu_role { 314 u64 as_u64; 315 struct { 316 union kvm_mmu_page_role base; 317 union kvm_mmu_extended_role ext; 318 }; 319 }; 320 321 struct kvm_rmap_head { 322 unsigned long val; 323 }; 324 325 struct kvm_mmu_page { 326 struct list_head link; 327 struct hlist_node hash_link; 328 struct list_head lpage_disallowed_link; 329 330 bool unsync; 331 u8 mmu_valid_gen; 332 bool mmio_cached; 333 bool lpage_disallowed; /* Can't be replaced by an equiv large page */ 334 335 /* 336 * The following two entries are used to key the shadow page in the 337 * hash table. 338 */ 339 union kvm_mmu_page_role role; 340 gfn_t gfn; 341 342 u64 *spt; 343 /* hold the gfn of each spte inside spt */ 344 gfn_t *gfns; 345 int root_count; /* Currently serving as active root */ 346 unsigned int unsync_children; 347 struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */ 348 DECLARE_BITMAP(unsync_child_bitmap, 512); 349 350 #ifdef CONFIG_X86_32 351 /* 352 * Used out of the mmu-lock to avoid reading spte values while an 353 * update is in progress; see the comments in __get_spte_lockless(). 354 */ 355 int clear_spte_count; 356 #endif 357 358 /* Number of writes since the last time traversal visited this page. */ 359 atomic_t write_flooding_count; 360 }; 361 362 struct kvm_pio_request { 363 unsigned long linear_rip; 364 unsigned long count; 365 int in; 366 int port; 367 int size; 368 }; 369 370 #define PT64_ROOT_MAX_LEVEL 5 371 372 struct rsvd_bits_validate { 373 u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL]; 374 u64 bad_mt_xwr; 375 }; 376 377 struct kvm_mmu_root_info { 378 gpa_t pgd; 379 hpa_t hpa; 380 }; 381 382 #define KVM_MMU_ROOT_INFO_INVALID \ 383 ((struct kvm_mmu_root_info) { .pgd = INVALID_PAGE, .hpa = INVALID_PAGE }) 384 385 #define KVM_MMU_NUM_PREV_ROOTS 3 386 387 /* 388 * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit, 389 * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the 390 * current mmu mode. 391 */ 392 struct kvm_mmu { 393 unsigned long (*get_guest_pgd)(struct kvm_vcpu *vcpu); 394 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); 395 int (*page_fault)(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u32 err, 396 bool prefault); 397 void (*inject_page_fault)(struct kvm_vcpu *vcpu, 398 struct x86_exception *fault); 399 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t gva_or_gpa, 400 u32 access, struct x86_exception *exception); 401 gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 402 struct x86_exception *exception); 403 int (*sync_page)(struct kvm_vcpu *vcpu, 404 struct kvm_mmu_page *sp); 405 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa); 406 void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, 407 u64 *spte, const void *pte); 408 hpa_t root_hpa; 409 gpa_t root_pgd; 410 union kvm_mmu_role mmu_role; 411 u8 root_level; 412 u8 shadow_root_level; 413 u8 ept_ad; 414 bool direct_map; 415 struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS]; 416 417 /* 418 * Bitmap; bit set = permission fault 419 * Byte index: page fault error code [4:1] 420 * Bit index: pte permissions in ACC_* format 421 */ 422 u8 permissions[16]; 423 424 /* 425 * The pkru_mask indicates if protection key checks are needed. It 426 * consists of 16 domains indexed by page fault error code bits [4:1], 427 * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. 428 * Each domain has 2 bits which are ANDed with AD and WD from PKRU. 429 */ 430 u32 pkru_mask; 431 432 u64 *pae_root; 433 u64 *lm_root; 434 435 /* 436 * check zero bits on shadow page table entries, these 437 * bits include not only hardware reserved bits but also 438 * the bits spte never used. 439 */ 440 struct rsvd_bits_validate shadow_zero_check; 441 442 struct rsvd_bits_validate guest_rsvd_check; 443 444 /* Can have large pages at levels 2..last_nonleaf_level-1. */ 445 u8 last_nonleaf_level; 446 447 bool nx; 448 449 u64 pdptrs[4]; /* pae */ 450 }; 451 452 struct kvm_tlb_range { 453 u64 start_gfn; 454 u64 pages; 455 }; 456 457 enum pmc_type { 458 KVM_PMC_GP = 0, 459 KVM_PMC_FIXED, 460 }; 461 462 struct kvm_pmc { 463 enum pmc_type type; 464 u8 idx; 465 u64 counter; 466 u64 eventsel; 467 struct perf_event *perf_event; 468 struct kvm_vcpu *vcpu; 469 /* 470 * eventsel value for general purpose counters, 471 * ctrl value for fixed counters. 472 */ 473 u64 current_config; 474 }; 475 476 struct kvm_pmu { 477 unsigned nr_arch_gp_counters; 478 unsigned nr_arch_fixed_counters; 479 unsigned available_event_types; 480 u64 fixed_ctr_ctrl; 481 u64 global_ctrl; 482 u64 global_status; 483 u64 global_ovf_ctrl; 484 u64 counter_bitmask[2]; 485 u64 global_ctrl_mask; 486 u64 global_ovf_ctrl_mask; 487 u64 reserved_bits; 488 u8 version; 489 struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; 490 struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; 491 struct irq_work irq_work; 492 DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX); 493 DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX); 494 DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX); 495 496 /* 497 * The gate to release perf_events not marked in 498 * pmc_in_use only once in a vcpu time slice. 499 */ 500 bool need_cleanup; 501 502 /* 503 * The total number of programmed perf_events and it helps to avoid 504 * redundant check before cleanup if guest don't use vPMU at all. 505 */ 506 u8 event_count; 507 }; 508 509 struct kvm_pmu_ops; 510 511 enum { 512 KVM_DEBUGREG_BP_ENABLED = 1, 513 KVM_DEBUGREG_WONT_EXIT = 2, 514 KVM_DEBUGREG_RELOAD = 4, 515 }; 516 517 struct kvm_mtrr_range { 518 u64 base; 519 u64 mask; 520 struct list_head node; 521 }; 522 523 struct kvm_mtrr { 524 struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; 525 mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; 526 u64 deftype; 527 528 struct list_head head; 529 }; 530 531 /* Hyper-V SynIC timer */ 532 struct kvm_vcpu_hv_stimer { 533 struct hrtimer timer; 534 int index; 535 union hv_stimer_config config; 536 u64 count; 537 u64 exp_time; 538 struct hv_message msg; 539 bool msg_pending; 540 }; 541 542 /* Hyper-V synthetic interrupt controller (SynIC)*/ 543 struct kvm_vcpu_hv_synic { 544 u64 version; 545 u64 control; 546 u64 msg_page; 547 u64 evt_page; 548 atomic64_t sint[HV_SYNIC_SINT_COUNT]; 549 atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; 550 DECLARE_BITMAP(auto_eoi_bitmap, 256); 551 DECLARE_BITMAP(vec_bitmap, 256); 552 bool active; 553 bool dont_zero_synic_pages; 554 }; 555 556 /* Hyper-V per vcpu emulation context */ 557 struct kvm_vcpu_hv { 558 u32 vp_index; 559 u64 hv_vapic; 560 s64 runtime_offset; 561 struct kvm_vcpu_hv_synic synic; 562 struct kvm_hyperv_exit exit; 563 struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; 564 DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); 565 cpumask_t tlb_flush; 566 }; 567 568 struct kvm_vcpu_arch { 569 /* 570 * rip and regs accesses must go through 571 * kvm_{register,rip}_{read,write} functions. 572 */ 573 unsigned long regs[NR_VCPU_REGS]; 574 u32 regs_avail; 575 u32 regs_dirty; 576 577 unsigned long cr0; 578 unsigned long cr0_guest_owned_bits; 579 unsigned long cr2; 580 unsigned long cr3; 581 unsigned long cr4; 582 unsigned long cr4_guest_owned_bits; 583 unsigned long cr8; 584 u32 host_pkru; 585 u32 pkru; 586 u32 hflags; 587 u64 efer; 588 u64 apic_base; 589 struct kvm_lapic *apic; /* kernel irqchip context */ 590 bool apicv_active; 591 bool load_eoi_exitmap_pending; 592 DECLARE_BITMAP(ioapic_handled_vectors, 256); 593 unsigned long apic_attention; 594 int32_t apic_arb_prio; 595 int mp_state; 596 u64 ia32_misc_enable_msr; 597 u64 smbase; 598 u64 smi_count; 599 bool tpr_access_reporting; 600 bool xsaves_enabled; 601 u64 ia32_xss; 602 u64 microcode_version; 603 u64 arch_capabilities; 604 u64 perf_capabilities; 605 606 /* 607 * Paging state of the vcpu 608 * 609 * If the vcpu runs in guest mode with two level paging this still saves 610 * the paging mode of the l1 guest. This context is always used to 611 * handle faults. 612 */ 613 struct kvm_mmu *mmu; 614 615 /* Non-nested MMU for L1 */ 616 struct kvm_mmu root_mmu; 617 618 /* L1 MMU when running nested */ 619 struct kvm_mmu guest_mmu; 620 621 /* 622 * Paging state of an L2 guest (used for nested npt) 623 * 624 * This context will save all necessary information to walk page tables 625 * of an L2 guest. This context is only initialized for page table 626 * walking and not for faulting since we never handle l2 page faults on 627 * the host. 628 */ 629 struct kvm_mmu nested_mmu; 630 631 /* 632 * Pointer to the mmu context currently used for 633 * gva_to_gpa translations. 634 */ 635 struct kvm_mmu *walk_mmu; 636 637 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; 638 struct kvm_mmu_memory_cache mmu_page_cache; 639 struct kvm_mmu_memory_cache mmu_page_header_cache; 640 641 /* 642 * QEMU userspace and the guest each have their own FPU state. 643 * In vcpu_run, we switch between the user and guest FPU contexts. 644 * While running a VCPU, the VCPU thread will have the guest FPU 645 * context. 646 * 647 * Note that while the PKRU state lives inside the fpu registers, 648 * it is switched out separately at VMENTER and VMEXIT time. The 649 * "guest_fpu" state here contains the guest FPU context, with the 650 * host PRKU bits. 651 */ 652 struct fpu *user_fpu; 653 struct fpu *guest_fpu; 654 655 u64 xcr0; 656 u64 guest_supported_xcr0; 657 658 struct kvm_pio_request pio; 659 void *pio_data; 660 661 u8 event_exit_inst_len; 662 663 struct kvm_queued_exception { 664 bool pending; 665 bool injected; 666 bool has_error_code; 667 u8 nr; 668 u32 error_code; 669 unsigned long payload; 670 bool has_payload; 671 u8 nested_apf; 672 } exception; 673 674 struct kvm_queued_interrupt { 675 bool injected; 676 bool soft; 677 u8 nr; 678 } interrupt; 679 680 int halt_request; /* real mode on Intel only */ 681 682 int cpuid_nent; 683 struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; 684 685 int maxphyaddr; 686 int tdp_level; 687 688 /* emulate context */ 689 690 struct x86_emulate_ctxt *emulate_ctxt; 691 bool emulate_regs_need_sync_to_vcpu; 692 bool emulate_regs_need_sync_from_vcpu; 693 int (*complete_userspace_io)(struct kvm_vcpu *vcpu); 694 695 gpa_t time; 696 struct pvclock_vcpu_time_info hv_clock; 697 unsigned int hw_tsc_khz; 698 struct gfn_to_hva_cache pv_time; 699 bool pv_time_enabled; 700 /* set guest stopped flag in pvclock flags field */ 701 bool pvclock_set_guest_stopped_request; 702 703 struct { 704 u8 preempted; 705 u64 msr_val; 706 u64 last_steal; 707 struct gfn_to_pfn_cache cache; 708 } st; 709 710 u64 l1_tsc_offset; 711 u64 tsc_offset; 712 u64 last_guest_tsc; 713 u64 last_host_tsc; 714 u64 tsc_offset_adjustment; 715 u64 this_tsc_nsec; 716 u64 this_tsc_write; 717 u64 this_tsc_generation; 718 bool tsc_catchup; 719 bool tsc_always_catchup; 720 s8 virtual_tsc_shift; 721 u32 virtual_tsc_mult; 722 u32 virtual_tsc_khz; 723 s64 ia32_tsc_adjust_msr; 724 u64 msr_ia32_power_ctl; 725 u64 tsc_scaling_ratio; 726 727 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ 728 unsigned nmi_pending; /* NMI queued after currently running handler */ 729 bool nmi_injected; /* Trying to inject an NMI this entry */ 730 bool smi_pending; /* SMI queued after currently running handler */ 731 732 struct kvm_mtrr mtrr_state; 733 u64 pat; 734 735 unsigned switch_db_regs; 736 unsigned long db[KVM_NR_DB_REGS]; 737 unsigned long dr6; 738 unsigned long dr7; 739 unsigned long eff_db[KVM_NR_DB_REGS]; 740 unsigned long guest_debug_dr7; 741 u64 msr_platform_info; 742 u64 msr_misc_features_enables; 743 744 u64 mcg_cap; 745 u64 mcg_status; 746 u64 mcg_ctl; 747 u64 mcg_ext_ctl; 748 u64 *mce_banks; 749 750 /* Cache MMIO info */ 751 u64 mmio_gva; 752 unsigned mmio_access; 753 gfn_t mmio_gfn; 754 u64 mmio_gen; 755 756 struct kvm_pmu pmu; 757 758 /* used for guest single stepping over the given code position */ 759 unsigned long singlestep_rip; 760 761 struct kvm_vcpu_hv hyperv; 762 763 cpumask_var_t wbinvd_dirty_mask; 764 765 unsigned long last_retry_eip; 766 unsigned long last_retry_addr; 767 768 struct { 769 bool halted; 770 gfn_t gfns[ASYNC_PF_PER_VCPU]; 771 struct gfn_to_hva_cache data; 772 u64 msr_en_val; /* MSR_KVM_ASYNC_PF_EN */ 773 u64 msr_int_val; /* MSR_KVM_ASYNC_PF_INT */ 774 u16 vec; 775 u32 id; 776 bool send_user_only; 777 u32 host_apf_flags; 778 unsigned long nested_apf_token; 779 bool delivery_as_pf_vmexit; 780 bool pageready_pending; 781 } apf; 782 783 /* OSVW MSRs (AMD only) */ 784 struct { 785 u64 length; 786 u64 status; 787 } osvw; 788 789 struct { 790 u64 msr_val; 791 struct gfn_to_hva_cache data; 792 } pv_eoi; 793 794 u64 msr_kvm_poll_control; 795 796 /* 797 * Indicates the guest is trying to write a gfn that contains one or 798 * more of the PTEs used to translate the write itself, i.e. the access 799 * is changing its own translation in the guest page tables. KVM exits 800 * to userspace if emulation of the faulting instruction fails and this 801 * flag is set, as KVM cannot make forward progress. 802 * 803 * If emulation fails for a write to guest page tables, KVM unprotects 804 * (zaps) the shadow page for the target gfn and resumes the guest to 805 * retry the non-emulatable instruction (on hardware). Unprotecting the 806 * gfn doesn't allow forward progress for a self-changing access because 807 * doing so also zaps the translation for the gfn, i.e. retrying the 808 * instruction will hit a !PRESENT fault, which results in a new shadow 809 * page and sends KVM back to square one. 810 */ 811 bool write_fault_to_shadow_pgtable; 812 813 /* set at EPT violation at this point */ 814 unsigned long exit_qualification; 815 816 /* pv related host specific info */ 817 struct { 818 bool pv_unhalted; 819 } pv; 820 821 int pending_ioapic_eoi; 822 int pending_external_vector; 823 824 /* be preempted when it's in kernel-mode(cpl=0) */ 825 bool preempted_in_kernel; 826 827 /* Flush the L1 Data cache for L1TF mitigation on VMENTER */ 828 bool l1tf_flush_l1d; 829 830 /* AMD MSRC001_0015 Hardware Configuration */ 831 u64 msr_hwcr; 832 }; 833 834 struct kvm_lpage_info { 835 int disallow_lpage; 836 }; 837 838 struct kvm_arch_memory_slot { 839 struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; 840 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; 841 unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; 842 }; 843 844 /* 845 * We use as the mode the number of bits allocated in the LDR for the 846 * logical processor ID. It happens that these are all powers of two. 847 * This makes it is very easy to detect cases where the APICs are 848 * configured for multiple modes; in that case, we cannot use the map and 849 * hence cannot use kvm_irq_delivery_to_apic_fast either. 850 */ 851 #define KVM_APIC_MODE_XAPIC_CLUSTER 4 852 #define KVM_APIC_MODE_XAPIC_FLAT 8 853 #define KVM_APIC_MODE_X2APIC 16 854 855 struct kvm_apic_map { 856 struct rcu_head rcu; 857 u8 mode; 858 u32 max_apic_id; 859 union { 860 struct kvm_lapic *xapic_flat_map[8]; 861 struct kvm_lapic *xapic_cluster_map[16][4]; 862 }; 863 struct kvm_lapic *phys_map[]; 864 }; 865 866 /* Hyper-V synthetic debugger (SynDbg)*/ 867 struct kvm_hv_syndbg { 868 struct { 869 u64 control; 870 u64 status; 871 u64 send_page; 872 u64 recv_page; 873 u64 pending_page; 874 } control; 875 u64 options; 876 }; 877 878 /* Hyper-V emulation context */ 879 struct kvm_hv { 880 struct mutex hv_lock; 881 u64 hv_guest_os_id; 882 u64 hv_hypercall; 883 u64 hv_tsc_page; 884 885 /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ 886 u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; 887 u64 hv_crash_ctl; 888 889 struct ms_hyperv_tsc_page tsc_ref; 890 891 struct idr conn_to_evt; 892 893 u64 hv_reenlightenment_control; 894 u64 hv_tsc_emulation_control; 895 u64 hv_tsc_emulation_status; 896 897 /* How many vCPUs have VP index != vCPU index */ 898 atomic_t num_mismatched_vp_indexes; 899 900 struct hv_partition_assist_pg *hv_pa_pg; 901 struct kvm_hv_syndbg hv_syndbg; 902 }; 903 904 enum kvm_irqchip_mode { 905 KVM_IRQCHIP_NONE, 906 KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ 907 KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ 908 }; 909 910 #define APICV_INHIBIT_REASON_DISABLE 0 911 #define APICV_INHIBIT_REASON_HYPERV 1 912 #define APICV_INHIBIT_REASON_NESTED 2 913 #define APICV_INHIBIT_REASON_IRQWIN 3 914 #define APICV_INHIBIT_REASON_PIT_REINJ 4 915 #define APICV_INHIBIT_REASON_X2APIC 5 916 917 struct kvm_arch { 918 unsigned long n_used_mmu_pages; 919 unsigned long n_requested_mmu_pages; 920 unsigned long n_max_mmu_pages; 921 unsigned int indirect_shadow_pages; 922 u8 mmu_valid_gen; 923 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; 924 /* 925 * Hash table of struct kvm_mmu_page. 926 */ 927 struct list_head active_mmu_pages; 928 struct list_head zapped_obsolete_pages; 929 struct list_head lpage_disallowed_mmu_pages; 930 struct kvm_page_track_notifier_node mmu_sp_tracker; 931 struct kvm_page_track_notifier_head track_notifier_head; 932 933 struct list_head assigned_dev_head; 934 struct iommu_domain *iommu_domain; 935 bool iommu_noncoherent; 936 #define __KVM_HAVE_ARCH_NONCOHERENT_DMA 937 atomic_t noncoherent_dma_count; 938 #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE 939 atomic_t assigned_device_count; 940 struct kvm_pic *vpic; 941 struct kvm_ioapic *vioapic; 942 struct kvm_pit *vpit; 943 atomic_t vapics_in_nmi_mode; 944 struct mutex apic_map_lock; 945 struct kvm_apic_map *apic_map; 946 bool apic_map_dirty; 947 948 bool apic_access_page_done; 949 unsigned long apicv_inhibit_reasons; 950 951 gpa_t wall_clock; 952 953 bool mwait_in_guest; 954 bool hlt_in_guest; 955 bool pause_in_guest; 956 bool cstate_in_guest; 957 958 unsigned long irq_sources_bitmap; 959 s64 kvmclock_offset; 960 raw_spinlock_t tsc_write_lock; 961 u64 last_tsc_nsec; 962 u64 last_tsc_write; 963 u32 last_tsc_khz; 964 u64 cur_tsc_nsec; 965 u64 cur_tsc_write; 966 u64 cur_tsc_offset; 967 u64 cur_tsc_generation; 968 int nr_vcpus_matched_tsc; 969 970 spinlock_t pvclock_gtod_sync_lock; 971 bool use_master_clock; 972 u64 master_kernel_ns; 973 u64 master_cycle_now; 974 struct delayed_work kvmclock_update_work; 975 struct delayed_work kvmclock_sync_work; 976 977 struct kvm_xen_hvm_config xen_hvm_config; 978 979 /* reads protected by irq_srcu, writes by irq_lock */ 980 struct hlist_head mask_notifier_list; 981 982 struct kvm_hv hyperv; 983 984 #ifdef CONFIG_KVM_MMU_AUDIT 985 int audit_point; 986 #endif 987 988 bool backwards_tsc_observed; 989 bool boot_vcpu_runs_old_kvmclock; 990 u32 bsp_vcpu_id; 991 992 u64 disabled_quirks; 993 994 enum kvm_irqchip_mode irqchip_mode; 995 u8 nr_reserved_ioapic_pins; 996 997 bool disabled_lapic_found; 998 999 bool x2apic_format; 1000 bool x2apic_broadcast_quirk_disabled; 1001 1002 bool guest_can_read_msr_platform_info; 1003 bool exception_payload_enabled; 1004 1005 struct kvm_pmu_event_filter *pmu_event_filter; 1006 struct task_struct *nx_lpage_recovery_thread; 1007 }; 1008 1009 struct kvm_vm_stat { 1010 ulong mmu_shadow_zapped; 1011 ulong mmu_pte_write; 1012 ulong mmu_pte_updated; 1013 ulong mmu_pde_zapped; 1014 ulong mmu_flooded; 1015 ulong mmu_recycled; 1016 ulong mmu_cache_miss; 1017 ulong mmu_unsync; 1018 ulong remote_tlb_flush; 1019 ulong lpages; 1020 ulong nx_lpage_splits; 1021 ulong max_mmu_page_hash_collisions; 1022 }; 1023 1024 struct kvm_vcpu_stat { 1025 u64 pf_fixed; 1026 u64 pf_guest; 1027 u64 tlb_flush; 1028 u64 invlpg; 1029 1030 u64 exits; 1031 u64 io_exits; 1032 u64 mmio_exits; 1033 u64 signal_exits; 1034 u64 irq_window_exits; 1035 u64 nmi_window_exits; 1036 u64 l1d_flush; 1037 u64 halt_exits; 1038 u64 halt_successful_poll; 1039 u64 halt_attempted_poll; 1040 u64 halt_poll_invalid; 1041 u64 halt_wakeup; 1042 u64 request_irq_exits; 1043 u64 irq_exits; 1044 u64 host_state_reload; 1045 u64 fpu_reload; 1046 u64 insn_emulation; 1047 u64 insn_emulation_fail; 1048 u64 hypercalls; 1049 u64 irq_injections; 1050 u64 nmi_injections; 1051 u64 req_event; 1052 u64 halt_poll_success_ns; 1053 u64 halt_poll_fail_ns; 1054 }; 1055 1056 struct x86_instruction_info; 1057 1058 struct msr_data { 1059 bool host_initiated; 1060 u32 index; 1061 u64 data; 1062 }; 1063 1064 struct kvm_lapic_irq { 1065 u32 vector; 1066 u16 delivery_mode; 1067 u16 dest_mode; 1068 bool level; 1069 u16 trig_mode; 1070 u32 shorthand; 1071 u32 dest_id; 1072 bool msi_redir_hint; 1073 }; 1074 1075 static inline u16 kvm_lapic_irq_dest_mode(bool dest_mode_logical) 1076 { 1077 return dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; 1078 } 1079 1080 struct kvm_x86_ops { 1081 int (*hardware_enable)(void); 1082 void (*hardware_disable)(void); 1083 void (*hardware_unsetup)(void); 1084 bool (*cpu_has_accelerated_tpr)(void); 1085 bool (*has_emulated_msr)(u32 index); 1086 void (*cpuid_update)(struct kvm_vcpu *vcpu); 1087 1088 unsigned int vm_size; 1089 int (*vm_init)(struct kvm *kvm); 1090 void (*vm_destroy)(struct kvm *kvm); 1091 1092 /* Create, but do not attach this VCPU */ 1093 int (*vcpu_create)(struct kvm_vcpu *vcpu); 1094 void (*vcpu_free)(struct kvm_vcpu *vcpu); 1095 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); 1096 1097 void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); 1098 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); 1099 void (*vcpu_put)(struct kvm_vcpu *vcpu); 1100 1101 void (*update_bp_intercept)(struct kvm_vcpu *vcpu); 1102 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 1103 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 1104 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); 1105 void (*get_segment)(struct kvm_vcpu *vcpu, 1106 struct kvm_segment *var, int seg); 1107 int (*get_cpl)(struct kvm_vcpu *vcpu); 1108 void (*set_segment)(struct kvm_vcpu *vcpu, 1109 struct kvm_segment *var, int seg); 1110 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); 1111 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); 1112 int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); 1113 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); 1114 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1115 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1116 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1117 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1118 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); 1119 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); 1120 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); 1121 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); 1122 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); 1123 1124 void (*tlb_flush_all)(struct kvm_vcpu *vcpu); 1125 void (*tlb_flush_current)(struct kvm_vcpu *vcpu); 1126 int (*tlb_remote_flush)(struct kvm *kvm); 1127 int (*tlb_remote_flush_with_range)(struct kvm *kvm, 1128 struct kvm_tlb_range *range); 1129 1130 /* 1131 * Flush any TLB entries associated with the given GVA. 1132 * Does not need to flush GPA->HPA mappings. 1133 * Can potentially get non-canonical addresses through INVLPGs, which 1134 * the implementation may choose to ignore if appropriate. 1135 */ 1136 void (*tlb_flush_gva)(struct kvm_vcpu *vcpu, gva_t addr); 1137 1138 /* 1139 * Flush any TLB entries created by the guest. Like tlb_flush_gva(), 1140 * does not need to flush GPA->HPA mappings. 1141 */ 1142 void (*tlb_flush_guest)(struct kvm_vcpu *vcpu); 1143 1144 enum exit_fastpath_completion (*run)(struct kvm_vcpu *vcpu); 1145 int (*handle_exit)(struct kvm_vcpu *vcpu, 1146 enum exit_fastpath_completion exit_fastpath); 1147 int (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); 1148 void (*update_emulated_instruction)(struct kvm_vcpu *vcpu); 1149 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); 1150 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); 1151 void (*patch_hypercall)(struct kvm_vcpu *vcpu, 1152 unsigned char *hypercall_addr); 1153 void (*set_irq)(struct kvm_vcpu *vcpu); 1154 void (*set_nmi)(struct kvm_vcpu *vcpu); 1155 void (*queue_exception)(struct kvm_vcpu *vcpu); 1156 void (*cancel_injection)(struct kvm_vcpu *vcpu); 1157 int (*interrupt_allowed)(struct kvm_vcpu *vcpu, bool for_injection); 1158 int (*nmi_allowed)(struct kvm_vcpu *vcpu, bool for_injection); 1159 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); 1160 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); 1161 void (*enable_nmi_window)(struct kvm_vcpu *vcpu); 1162 void (*enable_irq_window)(struct kvm_vcpu *vcpu); 1163 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); 1164 bool (*check_apicv_inhibit_reasons)(ulong bit); 1165 void (*pre_update_apicv_exec_ctrl)(struct kvm *kvm, bool activate); 1166 void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); 1167 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); 1168 void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr); 1169 bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu); 1170 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); 1171 void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu); 1172 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu); 1173 int (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); 1174 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); 1175 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); 1176 int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr); 1177 int (*get_tdp_level)(struct kvm_vcpu *vcpu); 1178 u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); 1179 1180 void (*load_mmu_pgd)(struct kvm_vcpu *vcpu, unsigned long cr3); 1181 1182 bool (*has_wbinvd_exit)(void); 1183 1184 /* Returns actual tsc_offset set in active VMCS */ 1185 u64 (*write_l1_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); 1186 1187 void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); 1188 1189 int (*check_intercept)(struct kvm_vcpu *vcpu, 1190 struct x86_instruction_info *info, 1191 enum x86_intercept_stage stage, 1192 struct x86_exception *exception); 1193 void (*handle_exit_irqoff)(struct kvm_vcpu *vcpu); 1194 1195 void (*request_immediate_exit)(struct kvm_vcpu *vcpu); 1196 1197 void (*sched_in)(struct kvm_vcpu *kvm, int cpu); 1198 1199 /* 1200 * Arch-specific dirty logging hooks. These hooks are only supposed to 1201 * be valid if the specific arch has hardware-accelerated dirty logging 1202 * mechanism. Currently only for PML on VMX. 1203 * 1204 * - slot_enable_log_dirty: 1205 * called when enabling log dirty mode for the slot. 1206 * - slot_disable_log_dirty: 1207 * called when disabling log dirty mode for the slot. 1208 * also called when slot is created with log dirty disabled. 1209 * - flush_log_dirty: 1210 * called before reporting dirty_bitmap to userspace. 1211 * - enable_log_dirty_pt_masked: 1212 * called when reenabling log dirty for the GFNs in the mask after 1213 * corresponding bits are cleared in slot->dirty_bitmap. 1214 */ 1215 void (*slot_enable_log_dirty)(struct kvm *kvm, 1216 struct kvm_memory_slot *slot); 1217 void (*slot_disable_log_dirty)(struct kvm *kvm, 1218 struct kvm_memory_slot *slot); 1219 void (*flush_log_dirty)(struct kvm *kvm); 1220 void (*enable_log_dirty_pt_masked)(struct kvm *kvm, 1221 struct kvm_memory_slot *slot, 1222 gfn_t offset, unsigned long mask); 1223 int (*write_log_dirty)(struct kvm_vcpu *vcpu); 1224 1225 /* pmu operations of sub-arch */ 1226 const struct kvm_pmu_ops *pmu_ops; 1227 const struct kvm_x86_nested_ops *nested_ops; 1228 1229 /* 1230 * Architecture specific hooks for vCPU blocking due to 1231 * HLT instruction. 1232 * Returns for .pre_block(): 1233 * - 0 means continue to block the vCPU. 1234 * - 1 means we cannot block the vCPU since some event 1235 * happens during this period, such as, 'ON' bit in 1236 * posted-interrupts descriptor is set. 1237 */ 1238 int (*pre_block)(struct kvm_vcpu *vcpu); 1239 void (*post_block)(struct kvm_vcpu *vcpu); 1240 1241 void (*vcpu_blocking)(struct kvm_vcpu *vcpu); 1242 void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); 1243 1244 int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, 1245 uint32_t guest_irq, bool set); 1246 void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); 1247 bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu); 1248 1249 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 1250 bool *expired); 1251 void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); 1252 1253 void (*setup_mce)(struct kvm_vcpu *vcpu); 1254 1255 int (*smi_allowed)(struct kvm_vcpu *vcpu, bool for_injection); 1256 int (*pre_enter_smm)(struct kvm_vcpu *vcpu, char *smstate); 1257 int (*pre_leave_smm)(struct kvm_vcpu *vcpu, const char *smstate); 1258 void (*enable_smi_window)(struct kvm_vcpu *vcpu); 1259 1260 int (*mem_enc_op)(struct kvm *kvm, void __user *argp); 1261 int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1262 int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1263 1264 int (*get_msr_feature)(struct kvm_msr_entry *entry); 1265 1266 bool (*need_emulation_on_page_fault)(struct kvm_vcpu *vcpu); 1267 1268 bool (*apic_init_signal_blocked)(struct kvm_vcpu *vcpu); 1269 int (*enable_direct_tlbflush)(struct kvm_vcpu *vcpu); 1270 1271 void (*migrate_timers)(struct kvm_vcpu *vcpu); 1272 }; 1273 1274 struct kvm_x86_nested_ops { 1275 int (*check_events)(struct kvm_vcpu *vcpu); 1276 bool (*hv_timer_pending)(struct kvm_vcpu *vcpu); 1277 int (*get_state)(struct kvm_vcpu *vcpu, 1278 struct kvm_nested_state __user *user_kvm_nested_state, 1279 unsigned user_data_size); 1280 int (*set_state)(struct kvm_vcpu *vcpu, 1281 struct kvm_nested_state __user *user_kvm_nested_state, 1282 struct kvm_nested_state *kvm_state); 1283 bool (*get_vmcs12_pages)(struct kvm_vcpu *vcpu); 1284 1285 int (*enable_evmcs)(struct kvm_vcpu *vcpu, 1286 uint16_t *vmcs_version); 1287 uint16_t (*get_evmcs_version)(struct kvm_vcpu *vcpu); 1288 }; 1289 1290 struct kvm_x86_init_ops { 1291 int (*cpu_has_kvm_support)(void); 1292 int (*disabled_by_bios)(void); 1293 int (*check_processor_compatibility)(void); 1294 int (*hardware_setup)(void); 1295 1296 struct kvm_x86_ops *runtime_ops; 1297 }; 1298 1299 struct kvm_arch_async_pf { 1300 u32 token; 1301 gfn_t gfn; 1302 unsigned long cr3; 1303 bool direct_map; 1304 }; 1305 1306 extern u64 __read_mostly host_efer; 1307 1308 extern struct kvm_x86_ops kvm_x86_ops; 1309 1310 #define __KVM_HAVE_ARCH_VM_ALLOC 1311 static inline struct kvm *kvm_arch_alloc_vm(void) 1312 { 1313 return __vmalloc(kvm_x86_ops.vm_size, GFP_KERNEL_ACCOUNT | __GFP_ZERO); 1314 } 1315 void kvm_arch_free_vm(struct kvm *kvm); 1316 1317 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB 1318 static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm) 1319 { 1320 if (kvm_x86_ops.tlb_remote_flush && 1321 !kvm_x86_ops.tlb_remote_flush(kvm)) 1322 return 0; 1323 else 1324 return -ENOTSUPP; 1325 } 1326 1327 int kvm_mmu_module_init(void); 1328 void kvm_mmu_module_exit(void); 1329 1330 void kvm_mmu_destroy(struct kvm_vcpu *vcpu); 1331 int kvm_mmu_create(struct kvm_vcpu *vcpu); 1332 void kvm_mmu_init_vm(struct kvm *kvm); 1333 void kvm_mmu_uninit_vm(struct kvm *kvm); 1334 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, 1335 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, 1336 u64 acc_track_mask, u64 me_mask); 1337 1338 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); 1339 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, 1340 struct kvm_memory_slot *memslot, 1341 int start_level); 1342 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, 1343 const struct kvm_memory_slot *memslot); 1344 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, 1345 struct kvm_memory_slot *memslot); 1346 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, 1347 struct kvm_memory_slot *memslot); 1348 void kvm_mmu_slot_set_dirty(struct kvm *kvm, 1349 struct kvm_memory_slot *memslot); 1350 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, 1351 struct kvm_memory_slot *slot, 1352 gfn_t gfn_offset, unsigned long mask); 1353 void kvm_mmu_zap_all(struct kvm *kvm); 1354 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen); 1355 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm); 1356 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages); 1357 1358 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); 1359 bool pdptrs_changed(struct kvm_vcpu *vcpu); 1360 1361 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 1362 const void *val, int bytes); 1363 1364 struct kvm_irq_mask_notifier { 1365 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); 1366 int irq; 1367 struct hlist_node link; 1368 }; 1369 1370 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, 1371 struct kvm_irq_mask_notifier *kimn); 1372 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, 1373 struct kvm_irq_mask_notifier *kimn); 1374 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, 1375 bool mask); 1376 1377 extern bool tdp_enabled; 1378 1379 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); 1380 1381 /* control of guest tsc rate supported? */ 1382 extern bool kvm_has_tsc_control; 1383 /* maximum supported tsc_khz for guests */ 1384 extern u32 kvm_max_guest_tsc_khz; 1385 /* number of bits of the fractional part of the TSC scaling ratio */ 1386 extern u8 kvm_tsc_scaling_ratio_frac_bits; 1387 /* maximum allowed value of TSC scaling ratio */ 1388 extern u64 kvm_max_tsc_scaling_ratio; 1389 /* 1ull << kvm_tsc_scaling_ratio_frac_bits */ 1390 extern u64 kvm_default_tsc_scaling_ratio; 1391 1392 extern u64 kvm_mce_cap_supported; 1393 1394 /* 1395 * EMULTYPE_NO_DECODE - Set when re-emulating an instruction (after completing 1396 * userspace I/O) to indicate that the emulation context 1397 * should be resued as is, i.e. skip initialization of 1398 * emulation context, instruction fetch and decode. 1399 * 1400 * EMULTYPE_TRAP_UD - Set when emulating an intercepted #UD from hardware. 1401 * Indicates that only select instructions (tagged with 1402 * EmulateOnUD) should be emulated (to minimize the emulator 1403 * attack surface). See also EMULTYPE_TRAP_UD_FORCED. 1404 * 1405 * EMULTYPE_SKIP - Set when emulating solely to skip an instruction, i.e. to 1406 * decode the instruction length. For use *only* by 1407 * kvm_x86_ops.skip_emulated_instruction() implementations. 1408 * 1409 * EMULTYPE_ALLOW_RETRY_PF - Set when the emulator should resume the guest to 1410 * retry native execution under certain conditions, 1411 * Can only be set in conjunction with EMULTYPE_PF. 1412 * 1413 * EMULTYPE_TRAP_UD_FORCED - Set when emulating an intercepted #UD that was 1414 * triggered by KVM's magic "force emulation" prefix, 1415 * which is opt in via module param (off by default). 1416 * Bypasses EmulateOnUD restriction despite emulating 1417 * due to an intercepted #UD (see EMULTYPE_TRAP_UD). 1418 * Used to test the full emulator from userspace. 1419 * 1420 * EMULTYPE_VMWARE_GP - Set when emulating an intercepted #GP for VMware 1421 * backdoor emulation, which is opt in via module param. 1422 * VMware backoor emulation handles select instructions 1423 * and reinjects the #GP for all other cases. 1424 * 1425 * EMULTYPE_PF - Set when emulating MMIO by way of an intercepted #PF, in which 1426 * case the CR2/GPA value pass on the stack is valid. 1427 */ 1428 #define EMULTYPE_NO_DECODE (1 << 0) 1429 #define EMULTYPE_TRAP_UD (1 << 1) 1430 #define EMULTYPE_SKIP (1 << 2) 1431 #define EMULTYPE_ALLOW_RETRY_PF (1 << 3) 1432 #define EMULTYPE_TRAP_UD_FORCED (1 << 4) 1433 #define EMULTYPE_VMWARE_GP (1 << 5) 1434 #define EMULTYPE_PF (1 << 6) 1435 1436 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type); 1437 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 1438 void *insn, int insn_len); 1439 1440 void kvm_enable_efer_bits(u64); 1441 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); 1442 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, bool host_initiated); 1443 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data); 1444 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data); 1445 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu); 1446 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu); 1447 1448 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in); 1449 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); 1450 int kvm_emulate_halt(struct kvm_vcpu *vcpu); 1451 int kvm_vcpu_halt(struct kvm_vcpu *vcpu); 1452 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); 1453 1454 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 1455 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); 1456 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 1457 1458 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 1459 int reason, bool has_error_code, u32 error_code); 1460 1461 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 1462 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); 1463 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 1464 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); 1465 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); 1466 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); 1467 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); 1468 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); 1469 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); 1470 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); 1471 1472 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1473 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1474 1475 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); 1476 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 1477 bool kvm_rdpmc(struct kvm_vcpu *vcpu); 1478 1479 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1480 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1481 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, unsigned long payload); 1482 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1483 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1484 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); 1485 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 1486 struct x86_exception *fault); 1487 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1488 gfn_t gfn, void *data, int offset, int len, 1489 u32 access); 1490 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); 1491 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); 1492 1493 static inline int __kvm_irq_line_state(unsigned long *irq_state, 1494 int irq_source_id, int level) 1495 { 1496 /* Logical OR for level trig interrupt */ 1497 if (level) 1498 __set_bit(irq_source_id, irq_state); 1499 else 1500 __clear_bit(irq_source_id, irq_state); 1501 1502 return !!(*irq_state); 1503 } 1504 1505 #define KVM_MMU_ROOT_CURRENT BIT(0) 1506 #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i) 1507 #define KVM_MMU_ROOTS_ALL (~0UL) 1508 1509 int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); 1510 void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); 1511 1512 void kvm_inject_nmi(struct kvm_vcpu *vcpu); 1513 1514 void kvm_update_dr7(struct kvm_vcpu *vcpu); 1515 1516 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); 1517 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); 1518 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); 1519 int kvm_mmu_load(struct kvm_vcpu *vcpu); 1520 void kvm_mmu_unload(struct kvm_vcpu *vcpu); 1521 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); 1522 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1523 ulong roots_to_free); 1524 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 1525 struct x86_exception *exception); 1526 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 1527 struct x86_exception *exception); 1528 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 1529 struct x86_exception *exception); 1530 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 1531 struct x86_exception *exception); 1532 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 1533 struct x86_exception *exception); 1534 1535 bool kvm_apicv_activated(struct kvm *kvm); 1536 void kvm_apicv_init(struct kvm *kvm, bool enable); 1537 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu); 1538 void kvm_request_apicv_update(struct kvm *kvm, bool activate, 1539 unsigned long bit); 1540 1541 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); 1542 1543 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, 1544 void *insn, int insn_len); 1545 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); 1546 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1547 gva_t gva, hpa_t root_hpa); 1548 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid); 1549 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush, 1550 bool skip_mmu_sync); 1551 1552 void kvm_configure_mmu(bool enable_tdp, int tdp_page_level); 1553 1554 static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 1555 struct x86_exception *exception) 1556 { 1557 return gpa; 1558 } 1559 1560 static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) 1561 { 1562 struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); 1563 1564 return (struct kvm_mmu_page *)page_private(page); 1565 } 1566 1567 static inline u16 kvm_read_ldt(void) 1568 { 1569 u16 ldt; 1570 asm("sldt %0" : "=g"(ldt)); 1571 return ldt; 1572 } 1573 1574 static inline void kvm_load_ldt(u16 sel) 1575 { 1576 asm("lldt %0" : : "rm"(sel)); 1577 } 1578 1579 #ifdef CONFIG_X86_64 1580 static inline unsigned long read_msr(unsigned long msr) 1581 { 1582 u64 value; 1583 1584 rdmsrl(msr, value); 1585 return value; 1586 } 1587 #endif 1588 1589 static inline u32 get_rdx_init_val(void) 1590 { 1591 return 0x600; /* P6 family */ 1592 } 1593 1594 static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) 1595 { 1596 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 1597 } 1598 1599 #define TSS_IOPB_BASE_OFFSET 0x66 1600 #define TSS_BASE_SIZE 0x68 1601 #define TSS_IOPB_SIZE (65536 / 8) 1602 #define TSS_REDIRECTION_SIZE (256 / 8) 1603 #define RMODE_TSS_SIZE \ 1604 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) 1605 1606 enum { 1607 TASK_SWITCH_CALL = 0, 1608 TASK_SWITCH_IRET = 1, 1609 TASK_SWITCH_JMP = 2, 1610 TASK_SWITCH_GATE = 3, 1611 }; 1612 1613 #define HF_GIF_MASK (1 << 0) 1614 #define HF_NMI_MASK (1 << 3) 1615 #define HF_IRET_MASK (1 << 4) 1616 #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ 1617 #define HF_SMM_MASK (1 << 6) 1618 #define HF_SMM_INSIDE_NMI_MASK (1 << 7) 1619 1620 #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE 1621 #define KVM_ADDRESS_SPACE_NUM 2 1622 1623 #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) 1624 #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) 1625 1626 asmlinkage void kvm_spurious_fault(void); 1627 1628 /* 1629 * Hardware virtualization extension instructions may fault if a 1630 * reboot turns off virtualization while processes are running. 1631 * Usually after catching the fault we just panic; during reboot 1632 * instead the instruction is ignored. 1633 */ 1634 #define __kvm_handle_fault_on_reboot(insn) \ 1635 "666: \n\t" \ 1636 insn "\n\t" \ 1637 "jmp 668f \n\t" \ 1638 "667: \n\t" \ 1639 "call kvm_spurious_fault \n\t" \ 1640 "668: \n\t" \ 1641 _ASM_EXTABLE(666b, 667b) 1642 1643 #define KVM_ARCH_WANT_MMU_NOTIFIER 1644 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); 1645 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 1646 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 1647 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 1648 int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); 1649 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); 1650 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); 1651 int kvm_cpu_get_interrupt(struct kvm_vcpu *v); 1652 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); 1653 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); 1654 1655 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, 1656 unsigned long ipi_bitmap_high, u32 min, 1657 unsigned long icr, int op_64_bit); 1658 1659 void kvm_define_shared_msr(unsigned index, u32 msr); 1660 int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); 1661 1662 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); 1663 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); 1664 1665 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); 1666 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); 1667 1668 void kvm_make_mclock_inprogress_request(struct kvm *kvm); 1669 void kvm_make_scan_ioapic_request(struct kvm *kvm); 1670 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 1671 unsigned long *vcpu_bitmap); 1672 1673 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 1674 struct kvm_async_pf *work); 1675 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 1676 struct kvm_async_pf *work); 1677 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, 1678 struct kvm_async_pf *work); 1679 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu); 1680 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu); 1681 extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); 1682 1683 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); 1684 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); 1685 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu); 1686 1687 int kvm_is_in_guest(void); 1688 1689 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); 1690 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); 1691 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); 1692 1693 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, 1694 struct kvm_vcpu **dest_vcpu); 1695 1696 void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, 1697 struct kvm_lapic_irq *irq); 1698 1699 static inline bool kvm_irq_is_postable(struct kvm_lapic_irq *irq) 1700 { 1701 /* We can only post Fixed and LowPrio IRQs */ 1702 return (irq->delivery_mode == APIC_DM_FIXED || 1703 irq->delivery_mode == APIC_DM_LOWEST); 1704 } 1705 1706 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) 1707 { 1708 if (kvm_x86_ops.vcpu_blocking) 1709 kvm_x86_ops.vcpu_blocking(vcpu); 1710 } 1711 1712 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) 1713 { 1714 if (kvm_x86_ops.vcpu_unblocking) 1715 kvm_x86_ops.vcpu_unblocking(vcpu); 1716 } 1717 1718 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 1719 1720 static inline int kvm_cpu_get_apicid(int mps_cpu) 1721 { 1722 #ifdef CONFIG_X86_LOCAL_APIC 1723 return default_cpu_present_to_apicid(mps_cpu); 1724 #else 1725 WARN_ON_ONCE(1); 1726 return BAD_APICID; 1727 #endif 1728 } 1729 1730 #define put_smstate(type, buf, offset, val) \ 1731 *(type *)((buf) + (offset) - 0x7e00) = val 1732 1733 #define GET_SMSTATE(type, buf, offset) \ 1734 (*(type *)((buf) + (offset) - 0x7e00)) 1735 1736 #endif /* _ASM_X86_KVM_HOST_H */ 1737