1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Global Clock & Reset Controller Binding for MSM8998 8 9maintainers: 10 - Stephen Boyd <sboyd@kernel.org> 11 - Taniya Das <tdas@codeaurora.org> 12 13description: | 14 Qualcomm global clock control module which supports the clocks, resets and 15 power domains on MSM8998. 16 17 See also: 18 - dt-bindings/clock/qcom,gcc-msm8998.h 19 20properties: 21 compatible: 22 const: qcom,gcc-msm8998 23 24 clocks: 25 items: 26 - description: Board XO source 27 - description: Sleep clock source 28 - description: USB 3.0 phy pipe clock 29 - description: UFS phy rx symbol clock for pipe 0 30 - description: UFS phy rx symbol clock for pipe 1 31 - description: UFS phy tx symbol clock 32 - description: PCIE phy pipe clock 33 34 clock-names: 35 items: 36 - const: xo 37 - const: sleep_clk 38 - const: usb3_pipe 39 - const: ufs_rx_symbol0 40 - const: ufs_rx_symbol1 41 - const: ufs_tx_symbol0 42 - const: pcie0_pipe 43 44 '#clock-cells': 45 const: 1 46 47 '#reset-cells': 48 const: 1 49 50 '#power-domain-cells': 51 const: 1 52 53 reg: 54 maxItems: 1 55 56 protected-clocks: 57 description: 58 Protected clock specifier list as per common clock binding. 59 60required: 61 - compatible 62 - clocks 63 - clock-names 64 - reg 65 - '#clock-cells' 66 - '#reset-cells' 67 - '#power-domain-cells' 68 69examples: 70 - | 71 #include <dt-bindings/clock/qcom,rpmcc.h> 72 clock-controller@100000 { 73 compatible = "qcom,gcc-msm8998"; 74 #clock-cells = <1>; 75 #reset-cells = <1>; 76 #power-domain-cells = <1>; 77 reg = <0x00100000 0xb0000>; 78 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 79 <&sleep>, 80 <0>, 81 <0>, 82 <0>, 83 <0>, 84 <0>; 85 clock-names = "xo", 86 "sleep_clk", 87 "usb3_pipe", 88 "ufs_rx_symbol0", 89 "ufs_rx_symbol1", 90 "ufs_tx_symbol0", 91 "pcie0_pipe"; 92 }; 93... 94